Method and device for generating linear frequency modulation signal based on multi-channel parallel real-time calculation

Abstract

The present invention provides a method and device for generating a linear frequency modulation signal based on multi-channel parallel real-time calculation, relating to the field of synthetic aperture radar technology. The method comprises: determining a starting frequency control word and a frequency modulation slope control word based on preset linear frequency modulation signal parameters; generating k parallel frequency control words based on a constructed virtual serial frequency control word, a starting frequency control word, and a frequency modulation slope control word, where k is an integer greater than 1; inputting the k parallel frequency control words into k phase accumulators to synchronously generate k phase-continuous linear frequency modulation signals; and combining the k signals via a digital-to-analog converter to output a broadband linear frequency modulation signal. The method utilizes the arithmetic progression characteristics of the virtual serial frequency control words to eliminate the phase compensation terms of all parallel branches, and then ensures phase continuity between the multiple signals through synchronous recursion of the multiple phase accumulators.

Description

Technical Field

[0001] The present invention relates to the technical field of synthetic aperture radar, and in particular to a method and device for generating a linear frequency modulation signal based on multi-path parallel real-time calculation. Background Art

[0002] Due to its characteristic of linear frequency modulation (LFM) signals, whose frequency varies linearly with time, they are widely used in radar, communications, medical imaging, and other fields. In particular, in Synthetic Aperture Radar (SAR) systems, LFM signals effectively balance detection range and resolution while offering strong anti-interference capabilities and high adaptability, making them a key technology in modern electronic systems.

[0003] Early linear frequency modulation (LFM) signal generation relied primarily on analog devices. However, these methods suffered from low linearity, poor stability, and high phase noise, making them incapable of meeting the signal bandwidth and phase accuracy requirements of modern electronic systems. With the advancement of digital technology, methods based on direct digital synthesis (DDS) have gradually become mainstream. DDS generates signals directly in the digital domain, offering higher accuracy and flexibility, and enabling easy adjustment of signal parameters (such as bandwidth and pulse width). On field-programmable gate array (FPGA) hardware platforms, DDS technology is typically implemented using a phase accumulator and waveform memory, employing both serial and parallel computation methods.

[0004] Digital linear frequency modulation signal generation methods based on serial computing gradually generate frequency control words through a phase accumulator and output the signal using a waveform memory. However, due to the limitations of the FPGA's operating clock frequency (generally no higher than 300 MHz), serial methods cannot generate higher-frequency broadband signals (e.g., bandwidths above 1 GHz) in real time. Furthermore, they have low resource utilization and cannot fully utilize the FPGA's parallel computing capabilities.

[0005] To overcome clock frequency limitations, existing methods for generating digital linear frequency modulation signals based on parallel computing and phase compensation employ a multi-channel parallel DDS structure, using phase compensation to ensure phase continuity after the combined signals are combined. However, this method produces discontinuities between the phases of the multiple channels, necessitating phase compensation in separate channels. Furthermore, the compensation value is time-dependent, meaning that the phase value at a given moment is correlated with the phase values ​​at all previous moments, resulting in a significant time complexity. This requires dynamic calculations using a large number of adders and multipliers, significantly increasing computational complexity and resource consumption. Summary of the Invention

[0006] The present invention provides a method and device for generating linear frequency modulation signals based on multi-channel parallel real-time computing, which is used to address the defects of the existing technology such as complex phase compensation and high computing resource consumption, and achieves low-complexity computing and efficient FPGA resource utilization. The technical solutions proposed by the present invention are as follows:

[0007] In a first aspect, the present invention provides a method for generating a linear frequency modulation signal based on multi-channel parallel real-time calculation, comprising:

[0008] Determine the starting frequency control word and the frequency modulation slope control word according to the preset linear frequency modulation signal parameters;

[0009] Constructing a virtual serial frequency control word, and generating k parallel frequency control words based on the virtual serial frequency control word, the starting frequency control word, and the frequency modulation slope control word, where k is an integer greater than 1;

[0010] Inputting the k parallel frequency control words into k phase accumulators respectively to synchronously generate k phase-continuous linear frequency modulation signals;

[0011] The k phase-continuous linear frequency modulation signals are combined and output as a broadband linear frequency modulation signal through a digital-to-analog converter.

[0012] Optionally, the preset linear frequency modulation signal parameters include a center frequency, a phase accumulator bit width, a sampling frequency, a sampling point number control word, and a signal bandwidth; and determining a starting frequency control word and a frequency modulation slope control word according to the preset linear frequency modulation signal parameters includes:

[0013] Determine the frequency modulation slope control word according to the phase accumulator bit width, sampling frequency, sampling point number control word and signal bandwidth;

[0014] A frequency control word corresponding to the center frequency is obtained, and the starting frequency control word is determined according to the frequency control word corresponding to the center frequency, the sampling point number control word, and the frequency modulation slope control word.

[0015] Optionally, the constructing of the virtual serial frequency control word, generating k parallel frequency control words based on the virtual serial frequency control word, the starting frequency control word, and the frequency modulation slope control word, includes:

[0016] Calculating the initial value of the frequency control word of each channel in parallel according to the starting frequency control word;

[0017] Constructing a virtual serial frequency control word; wherein the difference between the serial frequency control word of the current serial point and the serial frequency control word of the previous serial point is the frequency modulation slope control word;

[0018] Based on the virtual serial frequency control word, the j-th parallel frequency control word is calculated using an arithmetic progression summation formula; j=1, 2, ..., k-1.

[0019] Optionally, the initial phase offsets of the k parallel phase accumulators are determined by:

[0020] Determine the center phase offset according to the frequency control word corresponding to the center frequency, the starting frequency control word, and the sampling point number control word:

[0021] Using the center phase offset as the initial phase offset of the 0th path in parallel;

[0022] The initial phase offset of the i+1th path in parallel is determined according to the initial value of the frequency control word of the i+1th path in parallel and the initial phase offset of the ith path in parallel; wherein i=1,2,…,k-1.

[0023] Optionally, the frequency control word of each adjacent point in parallel is the sum of the frequency control words of the first k points in serial.

[0024] Optionally, the phase accumulator adopts a DDS IP core.

[0025] In a second aspect, the present invention further provides a device for generating a linear frequency modulation signal based on multi-channel parallel real-time computing, comprising the following modules:

[0026] An initial phase generating module is used to determine the starting frequency control word and the frequency modulation slope control word according to the preset linear frequency modulation signal parameters;

[0027] a control word generation module, configured to construct a virtual serial frequency control word, and generate k parallel frequency control words based on the virtual serial frequency control word, the starting frequency control word, and the frequency modulation slope control word, where k is an integer greater than 1;

[0028] A phase accumulation module inputs the k-channel parallel frequency control words into k phase accumulators respectively to synchronously generate k-channel phase-continuous linear frequency modulation signals;

[0029] The digital-to-analog conversion module is used to combine the k phase-continuous linear frequency modulation signals through a digital-to-analog converter and output them as a broadband linear frequency modulation signal.

[0030] In a third aspect, the present invention further provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein when the processor executes the computer program, the linear frequency modulation signal generation method based on multi-channel parallel real-time calculation as described in the first aspect above is implemented.

[0031] In a fourth aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the linear frequency modulation signal generation method based on multi-channel parallel real-time calculation as described in the first aspect above.

[0032] In a fifth aspect, the present invention further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the linear frequency modulation signal generation method based on multi-channel parallel real-time calculation as described in the first aspect above.

[0033] Based on the above technical solution, the present invention has the following beneficial effects compared with the prior art:

[0034] The present invention provides a method and device for generating linear frequency modulation (LFM) signals based on multi-channel parallel real-time computation. By determining the starting frequency control word and the frequency modulation slope control word based on preset LFM signal parameters, the analog signal parameters are converted into high-precision digital control words, making computations in digital systems more efficient while ensuring accuracy and avoiding the resource consumption of floating-point operations. K-channel parallel frequency control words are generated based on the starting frequency control word, the frequency modulation slope control word, and a constructed virtual serial frequency control word, distributing the signal generation task among k parallel channels. Using virtual serial signal reconstruction technology, the complex multi-channel phase continuity problem is transformed into a simple arithmetic sequence summation problem. The O(k²) complexity nonlinear compensation required for real-time computation in traditional parallel computing methods is simplified to addition and shift operations. Each channel independently generates its own frequency control word sequence based on the starting frequency control word and the frequency modulation slope control word. Each channel only needs to handle a portion of the frequency control word generation task. This parallel generation method fully utilizes the parallel processing capabilities of hardware platforms such as FPGAs, significantly improving signal generation speed while reducing the computational complexity of a single channel. K parallel frequency control words are input into k phase accumulators, generating k phase-continuous linear frequency modulation signals synchronously. In a parallel processing architecture, the k phase accumulators operate simultaneously, each accumulating the input frequency control words at a fixed clock frequency. Because the k frequency control words have the same starting frequency and frequency modulation slope, the generated k phase sequences are synchronized in time and phase-continuous, eliminating the need for dynamic phase compensation. The phase accumulator's operation is simple, requiring only addition, further reducing computational complexity and improving signal generation efficiency. The k signals are combined and output as a wideband linear frequency modulation signal via a digital-to-analog converter. Because the k signals have the same frequency variation characteristics, combining the outputs yields a wider bandwidth and higher signal power, enabling the generation of a wideband linear frequency modulation signal.

[0035] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0036] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 This is the basic principle diagram of serial DDS technology generating linear frequency modulation signals.

[0039] Figure 2 This is the schematic diagram of the i-th DDS when the number of parallel paths is 16.

[0040] Figure 3 The present invention provides a flow chart of a method for generating a linear frequency modulation signal based on multi-channel parallel real-time calculation.

[0041] Figure 4 This is a state machine control flow chart provided by the present invention.

[0042] Figure 5 This is a schematic diagram of the calculation principle of the j-th path when the number of parallel paths provided by the present invention is k=16.

[0043] Figure 6 It is a structural diagram of a linear frequency modulation signal generating device based on multi-channel parallel real-time calculation provided by the present invention.

[0044] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0045] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0046] Figure 1 This is the basic principle diagram of serial DDS technology to generate linear frequency modulation signal. Figure 1 , the process of generating linear frequency modulation signals using serial DDS technology is explained:

[0047] The mathematical expression of linear frequency modulation signal is:

[0048] (1)

[0049] Where, It represents the instantaneous amplitude of the linear frequency modulation signal at time t; f0 is the center frequency; K=B / T is the linear frequency modulation slope, B is the signal bandwidth, and T is the pulse width. It is a rectangular window function, which is used to limit the pulse width of the signal.

[0050] Linear frequency modulation signals are primarily generated in the digital domain using DDS technology. The DDS signal generation principle is to sample an analog signal. Once the sampling process has occurred and the sampled values ​​have been quantized, the original analog signal is reconstructed from the quantized values. The basic serial DDS structure consists of a frequency accumulator, a phase accumulator, a waveform memory (ROM), and a D / A converter.

[0051] For linear frequency modulation signals, the input control word of DDS generally has the starting frequency control word f word0 , FM slope control word K word , sampling point number control word N word , and their calculation formulas are as follows:

[0052] (2)

[0053] (3)

[0054] (4)

[0055] Where, is the phase accumulator bit width; f s is the sampling frequency.

[0056] Figure 1 In the frequency accumulator, the frequency accumulator is actually based on the starting frequency control word f word0 and the frequency modulation slope control word K word Calculate the phase increment of each step and get the frequency control word f word The phase accumulator performs phase accumulation in each clock cycle according to the frequency control word to obtain a phase value P addr , this value also represents the lookup table address in the waveform memory; the waveform memory stores the sine wave amplitude of one cycle in the ROM, and reads the sine wave amplitude according to P in the continuous clock cycle. addrOutput the corresponding amplitude to obtain the orthogonal IQ two-way signal, which is converted by the D / A converter to output the linear frequency modulation signal, that is, Figure 1 The output frequency f out In the above process, the work before DA conversion can be implemented in the FPGA by digital domain calculation. The phase accumulator and waveform memory modules are usually completed using FPGA IP cores (FPGA IP cores are reusable modules that can implement specific functions in the FPGA, similar to callable functions in programming languages. The relevant IP core in Xilinx FPGAs is called Vivado DDS IP core) to simplify the design work.

[0057] Figure 1 The DDS structure in this paper is serial and can only generate linear frequency modulation signals that are lower than the FPGA operating clock frequency. With the development of synthetic aperture radar, there is a need to generate broadband linear frequency modulation signals to improve radar range resolution. However, the operating clock frequency of FPGAs is generally low, typically no higher than 300 MHz. To generate broadband signals, such as 1 GHz or 1.2 GHz bandwidth, a DDS method based on parallel computing must be used.

[0058] The following describes a method for generating a digital linear frequency modulation signal based on parallel computing and phase compensation (hereinafter referred to as the traditional parallel computing method):

[0059] Parallel computing means outputting multiple signals simultaneously on the FPGA side, and completing parallel-to-serial conversion and digital-to-analog conversion at a higher clock frequency on the DA side. Taking 16-channel parallel output as an example, in order to keep the phase of the 16-channel signals continuous after merging, the traditional parallel computing method starts from the generation principle of linear frequency modulation signals and splits the frequency control word generation module into two modules: the initial phase generation module and the phase accumulation and compensation module. Taking 16-channel parallel as an example, the specific working process of this method is as follows: Figure 2 shown.

[0060] ① Initial phase generation module:

[0061] From formula (1), we can see that the phase consists of two parts: the first term and the second term. So the first term initial phase control word if of the 16-channel signal is word0 0, f word0 , 2 f word0 ,… ,15 f word0 ; 16-way signal secondary initial phase control word i 2 K word 0, K word , 4K word ,… ,15 2 K word , some of which need to be passed through K wordThe single-channel initial phase control word is obtained by adding the primary phase control word and the secondary phase control word. word0 +i 2 K word .

[0062] ②Phase accumulation and compensation module:

[0063] The step of the accumulation of the linear terms is 16 f word0 , and the step calculation of the quadratic accumulation is very complicated. When the step is 1, the cumulative amount of the quadratic accumulation at time n is 1+2+…+n=(n 2 +n) / 2; and when the step is 2×16 2 ×K word When the cumulative amount of the second accumulation at time n is (n 2 +n)×16 2 ×K word So it is necessary to use a step size of 2×16 2 ×K word Phase compensation is performed on each signal based on the phase compensation of 16 2 n 2 +i×32n, the specific compensation method is shown in Table 1:

[0064] Table 1 Quadratic phase compensation rules

[0065]

[0066] It can be seen that the amount of phase compensation is updated according to time, and only when each signal is phase compensated according to a specific rule can the phase continuity of the 16 signals after merging be guaranteed.

[0067] Since n is not a fixed value, this method requires a large number of adders and multipliers when performing phase compensation, which has high computational complexity and consumes a lot of FPGA resources. In addition, the compensation for each channel is different, and the compensation value is time-dependent, which has a certain time complexity and leads to difficulties in actual implementation.

[0068] To address these technical deficiencies, the present invention designs a novel method for generating linear frequency modulation signals based on multi-channel parallel real-time computation. This method decouples the real-time phase calculation from the signal duration, significantly reducing computational and time complexity. This method eliminates the need for multipliers during frequency generation and maintains the same code within each parallel module, significantly reducing the resources required for real-time computation within the FPGA.

[0069] Refer to the following Figure 3 , the linear frequency modulation signal generation method based on multi-channel parallel real-time calculation provided by the present invention is described.

[0070] The core of multi-channel parallel DDS is how to generate parallel frequency control words. Existing parallel DDS technology is mainly based on the generation principle of linear frequency modulation signals in formula (1), which accumulates and compensates the phase from the first and second terms, but does not fully utilize the timing phase relationship in the frequency control word generation process when multiple channels are parallel. In fact, linear frequency modulation signals have the characteristic of increasing frequency. The present invention does not start from formula (1), but from the parallel frequency control word f at the previous moment in each channel. word_par(n) Infer the parallel frequency control word f at the next moment word_par(n+1) , thus obtaining the phase of each parallel signal closely arranged at the next moment. The subscripts (n) and (n+1) represent the position of the point in the time series.

[0071] According to the characteristic of linear frequency modulation signal outputting frequency linearly over time, the output frequency can be expressed as:

[0072] (5)

[0073] Where, It represents the actual frequency value of the linear frequency modulation signal at time t; f0 is the center frequency; K is the linear frequency modulation slope.

[0074] Its serial corresponding frequency control word f word_ser It also has the characteristic of linear change and can be expressed as:

[0075] (6)

[0076] Where, is the serial frequency control word of the nth point, f word0 is the starting frequency control word, K word It is the frequency modulation slope control word.

[0077] Further express f word_ser(n+1) With f word_ser(n) The time relationship is as follows:

[0078] (7)

[0079] Where, f word_ser(n+1) is the serial frequency control word of the n+1th point, is the serial frequency control word of the nth point, Δf word It is the increment of the frequency control word at the current moment.

[0080] Formula (7) shows that in the serial DDS, the increment of the frequency control word at the current moment is Δf word That is the frequency modulation slope control word K word , serial frequency control word f word_serHowever, in a k-way parallel DDS (k>1), the phases of adjacent points in each way are no longer closely arranged, and the corresponding parallel frequency control word f word_par It also no longer has the characteristic of linear growth.

[0081] In addition, in the 16-way parallel process, the corresponding relationship between the Nth point in the jth parallel branch and the nth point in the assumed parallel to serial conversion is summarized in the following table:

[0082] Table 2 Correspondence between the number of points of parallel and serial calculations

[0083]

[0084] That is, in a k-way parallel system, the relationship between the serial point n and the parallel point N can be derived from the following formula:

[0085] (8)

[0086] Based on the above prerequisites, the present invention proposes a k-way parallel frequency control word f word_par The expression method is expressed as follows:

[0087] (9)

[0088] In the formula, the superscript [j] represents the jth parallel path, (N+1) represents the N+1th point in the parallel path, and (n+1) represents the n+1th point in the serial path. This formula means that because the frequency control word must ultimately be fed into the phase accumulator and accumulated on a clock basis, the frequency control word for each adjacent point in the parallel path is equivalent to the sum of the frequency control words for the previous k points in the serial path.

[0089] The meaning of each parameter in the formula is: is the parallel frequency control word of the j-th path at the N+1-th point. (i=1,2,…,k) is the serial frequency control word of the virtual serial signal at the n+i-th point, and k is the number of parallel paths.

[0090] According to formula (6) and formula (8), f word_ser It increases linearly with time, meeting the requirements of an arithmetic sequence, and the arithmetic sequence summation formula can be used to calculate f word_par :

[0091] (10)

[0092] Where, f word_ser(n+1) is the first term, f word_ser(n+k) is the last term. k is the number of parallel paths, which also represents the number of terms in the arithmetic progression.

[0093] Formula (9) is the core principle of the present invention, that is, in solving the k-way parallel frequency control word f [j] word_par(N+1) In the process of constructing the virtual serial frequency control word f word_ser(n+1) With f word_ser(n+k) , calculate f by the arithmetic progression summation formula [j] word_par(N+1) .f word_ser(n+1) is the serial frequency control word of the n+1th point, f word_ser(n+k) is the serial frequency control word of the n+kth point. Taking 16 channels as an example, refer to Figure 5 As shown, the constructed virtual serial frequency control word is f word_ser(n+1) With f word_ser(n+16) .

[0094] In addition, f in formula (9) word_ser(n+1) With f word_ser(n+k) The recursive method can be used to solve:

[0095] (11)

[0096] Where, f word_ser(n-k) It is the serial frequency control word of the nkth point.

[0097] Among them, f word_ser(n-k) and f word_ser(n) That is to solve The corresponding serial frequency control word. In the formula, n≥k. When n<k, it is the initial value. Please refer to formula (7) for the calculation method. Formula (7)(10)(11) represents the serial frequency control word f at the current moment. word_ser(n+1) Only depends on the serial frequency control word f at the previous moment word_ser(n) , and the parallel frequency control word of each branch at the current moment can be deduced It can only rely on the parallel frequency control word of each branch at the previous moment .

[0098] The linear frequency modulation signal generation method based on multi-channel parallel real-time calculation provided by the present invention refers to Figure 3 As shown, including the following:

[0099] S110, determining the starting frequency control word f according to the preset linear frequency modulation signal parameters word0 and FM slope control word K word ;

[0100] The frequency of a linear frequency modulation signal changes linearly over time, and its mathematical expression is shown in the above formula (1). The starting frequency control word and the frequency modulation slope control word are the core parameters for generating a linear frequency modulation signal, directly determining the signal's starting frequency and the frequency change rate. For example, in a radar system, the starting frequency determines the starting distance for detecting a target, and the frequency modulation slope affects the range resolution. By precalculating the control word, the subsequent frequency generation and phase accumulation steps only require simple calculations based on these parameters, reducing computational complexity and improving real-time performance.

[0101] S120 , construct a virtual serial frequency control word, and generate k parallel frequency control words based on the virtual serial frequency control word, the starting frequency control word, and the frequency modulation slope control word, where k is an integer greater than 1.

[0102] By distributing control words to k parallel channels, each channel independently generates a frequency control word sequence, fully utilizing hardware resources and significantly improving signal generation speed. For example, when k = 4, signal generation speed can theoretically increase by a factor of four. The parallel-generated frequency control words have the same starting frequency and frequency modulation slope, ensuring phase continuity across all channel signals.

[0103] The present invention adopts an arithmetic progression summation method, based on a virtual serial frequency control word (such as Figure 5 f in word_ser(n+1) With f word_ser(n+16) ) Use formula (9) to calculate the parallel frequency control word for each channel , using recursive relations to optimize calculations, avoiding multiplication operations, and only requiring addition + shifting to complete real-time updates. By superimposing and summing virtual serial signals, namely formulas (9) and (10), the phase continuity of multiple signals is guaranteed without the need for dynamic compensation. Traditional parallel computing methods require independent compensation for each channel, with a complexity of O(k 2 ), for example, 16 channels require 256 multiplications. This invention uses arithmetic progression summation to require only one addition and one shift. For example, when k = 16, the sum is optimized to (first term + last term) × 8. Furthermore, by eliminating multipliers and using only adders and shifters, FPGA resource usage is reduced by over 70%. It also supports flexible expansion of the number of parallel channels, with resource consumption increasing only linearly.

[0104] S130 , inputting the k parallel frequency control words into k phase accumulators respectively to synchronously generate k phase-continuous linear frequency modulation signals.

[0105] Input k parallel frequency control words into k phase accumulators (such as the Vivado DDS IP core of FPGA), refer to Figure 5As shown, quadrature IQ signals are synchronously generated. The phase accumulator accumulates the frequency control word to generate the corresponding phase sequence. Each phase accumulator accumulates the input frequency control word at a fixed clock frequency. The output phase value serves as the address of the sine lookup table, thereby obtaining the corresponding sine wave amplitude value. Because the k phase accumulators use the same starting frequency control word and frequency modulation slope control word, with only minor phase differences, the k linear frequency modulation signals they generate have the same frequency variation characteristics, but their phases are continuous and correlated.

[0106] The signals generated by the parallel phase accumulator are superimposed in the frequency domain, effectively expanding the signal bandwidth. For example, the signal bandwidth B of the generated baseband signal is affected by the sampling frequency f s Limitation. The sampling frequency of a single channel is f s When generating a linear frequency modulation signal with a signal bandwidth of B, it is necessary to satisfy the Nyquist sampling theorem f s ≥2B. k parallel signals increase the sampling rate to kf s , extending the maximum bandwidth that can be generated by a factor of k. Phase continuity ensures smooth signal transitions, avoids spectrum leakage caused by phase jumps, and improves the signal's spectral purity. The superposition of parallel signals enhances signal power, enabling the system to maintain good performance even in high-noise environments.

[0107] S140 , combining the k phase-continuous linear frequency modulation signals through a digital-to-analog converter and outputting them as a broadband linear frequency modulation signal.

[0108] In the digital domain, k digital signals are processed and superimposed, using methods such as weighted summation and digital filtering, to improve signal quality and performance. The combined digital signal is then input into a DAC, which converts it into an analog signal. Because the k signals have the same frequency variation characteristics, combining the outputs can achieve wider bandwidth and higher signal power, thereby enabling the generation of wideband linear frequency modulation signals.

[0109] The present invention provides a multi-channel parallel real-time computation-based linear frequency modulation signal generation method. The method determines the starting frequency control word and frequency modulation slope control word based on preset linear frequency modulation signal parameters, converting the analog signal parameters into high-precision digital control words. This makes computation in a digital system more efficient, ensuring accuracy while avoiding the resource consumption of floating-point operations. K-channel parallel frequency control words are generated based on the starting frequency control word, frequency modulation slope control word, and a constructed virtual serial frequency control word, distributing the signal generation task among k parallel channels. Virtual serial signal reconstruction technology is employed to transform the complex multi-channel phase continuity problem into a simple arithmetic sequence summation problem. Through mathematical transformation, the O(k²) complexity nonlinear compensation required for real-time computation in traditional parallel computing methods is simplified to a low-complexity addition-shift operation. Each channel independently generates its own frequency control word sequence based on the starting frequency control word and frequency modulation slope control word. Each channel only needs to handle a portion of the frequency control word generation task. This parallel generation method fully utilizes the parallel processing capabilities of hardware platforms such as FPGAs, significantly improving signal generation speed while reducing the computational complexity of a single channel. K parallel frequency control words are fed into k phase accumulators to synchronously generate k phase-continuous linear frequency modulation signals. In a parallel processing architecture, the k phase accumulators operate simultaneously, each accumulating the input frequency control words at a fixed clock frequency. Because the k frequency control words have the same starting frequency and frequency modulation slope, the generated k phase sequences are time-synchronized and phase-continuous, eliminating the need for dynamic phase compensation. The phase accumulator's operation is simple, requiring only addition, further reducing computational complexity and improving signal generation efficiency. The k signals are combined and output as a wideband linear frequency modulation signal using a digital-to-analog converter (DAC). Because the k signals have the same frequency variation characteristics, combining the outputs yields a wider bandwidth and higher signal power, enabling the generation of a wideband linear frequency modulation signal.

[0110] Compared to traditional single-channel signal generation methods, multi-channel signal merging eliminates the need for complex phase compensation algorithms to adjust the signal's phase, as the parallel generation process already ensures phase continuity. In the DAC, the combined digital signal is converted to an analog signal. Due to the superposition of k signals, the signal power is enhanced, thereby improving the signal-to-noise ratio. Furthermore, this combined output method fully utilizes the resources of hardware platforms such as FPGAs, centrally processing signals from multiple parallel channels, reducing hardware resource waste and improving FPGA resource utilization efficiency.

[0111] The present invention uses an FPGA chip as the hardware carrier and uses the Verilog language to write the code module. The implementation is divided into a state machine control module, an initial phase generation module, and a phase accumulation module. The specific functions are as follows:

[0112] The state machine control module is a working module in the FPGA software. Its main work can be represented and controlled by the state machine. Taking k=16 parallel channels as an example, the specific process is as follows: Figure 4 As shown:

[0113] Initial state after power-on: INITIALON: The initial state of the FPGA after power-on, which also serves as the initial state after reset. After counting multiple clock cycles, it enters the wait-for-trigger state IDLE1.

[0114] Waiting for trigger state IDLE1: In this state, the pulse repetition frequency (PRF) trigger signal from other working modules of the FPGA is waited for. After the high level signal is detected, the state enters the parameter acquisition state GET_PARA.

[0115] Parameter acquisition state GET_PARA: In this state, the transmission bandwidth code and pulse width code transmitted by other working modules are latched, and then the state enters the waiting calculation state WAITING.

[0116] Waiting for calculation state WAITING: In this state, calculation begins after counting a certain number of clock cycles. Since the initial calculation takes a certain amount of time, it enters the LFM_calculate_initial state after the counting is completed.

[0117] Initial phase generation state LFM_calculate_initial: In this state, the 16-bit frequency modulation slope K and the 32-bit total sampling points N are calculated based on the transmission bandwidth, actual pulse width, and sampling rate. Then, the initial phase and phase control word of the k-channel parallel signal are calculated. After the calculation is completed, the state enters the LFM_calculate_tx state.

[0118] Phase accumulation state LFM_calculate_tx: Based on the initial phase and phase control word, it calculates the real-time phase of each signal at each clock cycle and outputs it to the Vivado DDS IP core to generate sine and cosine waveforms. The IP core outputs the IQ waveforms to subsequent submodules and ultimately to the DAC. Calculation stops when the calculation clock cycle equals N / k, and the system enters the HOLDON state.

[0119] Hold state HOLDON: After entering this state, it counts multiple clock cycles and then enters the IDLE1 state to wait for the calculation trigger again.

[0120] Optionally, the preset linear frequency modulation signal parameters include center frequency, phase accumulator bit width, sampling frequency, sampling point number control word and signal bandwidth.

[0121] Among them, the center frequency (f0) is the center frequency of the signal spectrum (Hz). Phase accumulator bit width ( ) determines the frequency resolution. Sampling frequency (f s ) is the digital system working clock (such as 100MHz). Sampling point number control word (N word ) is the number of sampling points corresponding to the signal duration (N word =T×f s ), T is the pulse width. The signal bandwidth (B) is the sweep frequency range of the linear frequency modulation (Hz).

[0122] The step S110 of determining the starting frequency control word and the frequency modulation slope control word according to the preset linear frequency modulation signal parameters includes:

[0123] According to the phase accumulator bit width , sampling frequency f s , sampling point number control word N word Sum signal bandwidth B, use the above formula (4) to determine the frequency modulation slope control word K word ;

[0124] Get the frequency control word f corresponding to the center frequency center , according to the frequency control word f corresponding to the center frequency center , the sampling point number control word N word and the frequency modulation slope control word K word , determine the starting frequency control word f word0 .

[0125] The present invention uses the following formula to calculate the starting frequency control word f word0 :

[0126] (12)

[0127] Where, f center Is the frequency control word corresponding to the center frequency. Since the DDS module generates a baseband signal, f center =0.

[0128] Optionally, the step of constructing a virtual serial frequency control word in S120, generating k parallel frequency control words based on the virtual serial frequency control word, the starting frequency control word, and the frequency modulation slope control word, includes:

[0129] According to the starting frequency control word f word0 , calculate the initial value of the frequency control word of each channel in parallel:

[0130] Assume that there are k parallel branches, and the initial value of the frequency control word of each branch is based on f word0 Evenly distribute. For example:

[0131]

[0132]

[0133] Among them, f (0) word_par(0) Indicates the initial value of the frequency control word of parallel channel 0, f (1) word_par(0) Indicates the initial value of the frequency control word of the first parallel branch. The subsequent branches are deduced in the same way to form an arithmetic progression. The initial value of the frequency control word of each branch is generated by linear recursion, that is:

[0134] (13)

[0135] Where j represents the jth parallel path. It can be obtained by timing logic before real-time waveform generation. (0) word_par(0) Indicates the initial value of the frequency control word of parallel channel 0, Indicates the initial value of the frequency control word of the parallel j-th path, Indicates the initial value of the frequency control word of the j+1th parallel channel.

[0136] Construct virtual serial frequency control word f word_ser(n+1) With f word_ser(n+k) Among them, the virtual serial frequency control word satisfies the linear relationship: That is, the difference between the serial frequency control word of the current serial point and the serial frequency control word of the previous serial point is the frequency modulation slope control word K word .

[0137] For example:

[0138]

[0139] Among them, f word_ser(n) is the serial frequency control word of the nth point, f word_ser(n+1) is the serial frequency control word of the n+1th point, f word_ser(n+2) is the serial frequency control word of the n+2th point, f word_ser(n+k) It is the serial frequency control word of the n+kth point.

[0140] The frequency control word of each adjacent point in parallel is the sum of the frequency control words of the first k points in serial. For example, referring to formula (9), the parallel frequency control word of the jth path at point N+1 is , which is equivalent to k consecutive points in the virtual serial signal The sum of the serial frequency control words.

[0141] Based on the virtual serial frequency control word, the j-th parallel frequency control word is calculated using the arithmetic progression summation formula (i.e., the above formula 10); j=1,2,...,k-1. The hardware implementation is:

[0142] Calculate the sum of the first and last terms (addition) and when k is a power of 2 (such as 16-way), the k / 2 operation is converted to a right shift of log2k-1 bits, that is, only one addition and one shift are required.

[0143] After each clock cycle is completed, the first and last items of the virtual serial point are updated, the control words of all parallel branches are calculated and output, the state register is shifted, and preparation is made for the next clock cycle calculation.

[0144] Traditional parallel computing methods require the design of dynamic phase compensation terms for each signal to maintain phase continuity. However, the present invention eliminates the phase compensation terms of all parallel branches based on the arithmetic progression characteristics of the virtual serial frequency control word, and then naturally ensures the phase continuity between multiple signals through the synchronous recursion of multiple phase accumulators.

[0145] Unlike traditional parallel computing methods, the structure of each parallel branch in this invention is identical; only the starting frequency control word is dependent on the branch position; the frequency control word used during real-time calculation is independent of that location. In an FPGA implementation, each parallel branch only needs to store the accumulated results of one parallel frequency control word and two virtual serial control words from the previous clock cycle. A combination of addition and shift operations replaces all multipliers used in the real-time frequency control word calculation process. Furthermore, resource consumption increases linearly with the number of parallel paths, significantly improving the system's real-time performance and scalability.

[0146] This invention innovatively equates the multi-channel parallel phase accumulation problem to the superposition of virtual serial signals. By introducing a virtual serial frequency control word, the previously strongly time-dependent parallel computation is transformed into a time-independent arithmetic progression summation. Through mathematical reconstruction, the complex global nonlinear problem is transformed into a simple nonlinear problem that depends only on local states, providing a simple and efficient solution for linear frequency modulation signal generation.

[0147] The present invention can be applied to radar systems by adjusting the frequency modulation slope control word K word Control bandwidth and use parallel frequency control words to achieve synchronous output of multi-channel linear frequency modulation signals to improve radar resolution.

[0148] Optionally, the phase accumulator of the present invention utilizes a DDS IP core. In direct digital frequency synthesis (DDS), multiple phase signals are generated using multiple parallel phase accumulators. The DDS IP core implements frequency switching by updating the frequency control word, eliminating the need for hardware reconfiguration. To ensure phase continuity and synchronization of each signal path, a reasonable initial phase offset must be set for each accumulator, i.e., the phase offset input of the DDS IP core. The initial phase offsets of each of the k parallel phase accumulators are determined as follows:

[0149] According to the frequency control word corresponding to the center frequency , the starting frequency control word and the sampling point number control word , determine the center phase offset .

[0150] The center phase offset As the initial phase offset of the 0th path in parallel .

[0151] Starting from channel 0, the initial phase offset is calculated for each channel. The initial phase offset of each channel is the sum of the initial phase offset of the previous channel and the initial value of the frequency control word of the current channel, ensuring phase continuity when multiple channels are combined.

[0152] Specifically, according to the initial value of the frequency control word of the i+1th path in parallel The initial phase offset of the i-th path when and in parallel , determine the initial phase offset of the i+1th path in parallel ; where i=1, 2, ..., k-1. The present invention uses the following formula for calculation:

[0153] (14)

[0154] Where, This represents the initial phase offset for each parallel path. It also needs to be input to the phase accumulation module once, at the start of the calculation, and remains unchanged thereafter. This can be implemented in an FPGA using only sequential logic.

[0155] The present invention realizes phase initialization by constructing a double-layer architecture of center phase offset and recursive multi-path distribution. Based on the principle of signal spectrum symmetry, the phase initialization is realized by modular operation. A global reference phase is constructed to ensure that all parallel branches have a unified phase reference origin, fundamentally eliminating the phase reference drift problem caused by independent branch calculations in traditional parallel computing methods. A forward recursive strategy is adopted to define the initial phase of each path as the superposition of the phase of the previous path and its own frequency control word. This design allows multi-channel signals to naturally form a phase-continuous waveform in the time domain, meeting strict synchronization requirements without the need for post-stage correction. By replacing hardware compensation with mathematical construction, the phase alignment accuracy reaches the sub-milliradian level, significantly improving the spectral purity of the synthesized broadband signal, and suppressing the spurious components to a level close to the background noise. Moreover, the multi-dimensional cross-calculation in the traditional parallel computing method is simplified to a linear recursive relationship. The calculation process only requires cascaded adders, forming a minimalist data flow path in the FPGA, achieving a linear scaling characteristic of resource consumption and the increase in the number of paths.

[0156] Furthermore, phase offset calculations directly reuse the generated frequency control word, maintaining parameter consistency across the entire link. Recursive calculations and frequency control word updates share a common clock domain, avoiding cross-clock domain synchronization issues. Modulo arithmetic automatically handles accumulation overflows, ensuring system stability under extreme parameter conditions. In practical systems, this phase initialization scheme enables radar systems to obtain clearer target micro-motion signatures.

[0157] Taking 16 parallel paths as an example, the parallel process of the jth path in the phase accumulation module is shown as follows: Figure 5 As shown. The “<<” symbol represents a left shift. The “k / 2” part in formula (10) is equivalent to multiplying by 8, that is, a left shift of three bits. Figure 2 and Figure 5 It can be seen that at the same time, the phase accumulation module of the present invention only performs 5 addition operations and 2 shift operations, and does not use any multipliers at all, which greatly reduces the amount of calculation and resource usage of the entire real-time calculation module.

[0158] By dynamically adjusting the FPGA clock frequency and parameter bit width, the method of the present invention can accurately control the bandwidth, pulse width and center frequency of the linear frequency modulation signal. For example, through the 32-bit bit width frequency control word and the high-precision phase accumulator provided by the IP core, the phase resolution can reach 1 / 2 32 , significantly improving the consistency of the signal's time-frequency characteristics. Combined with a multi-channel parallel architecture, it can generate linear frequency modulation signals with a bandwidth exceeding 1.2GHz at a 100MHz main frequency, meeting the high-resolution imaging requirements of synthetic aperture radars while supporting dynamic parameter reconstruction to adapt to different scenarios.

[0159] Compared to traditional parallel computing methods that rely on a large number of multipliers and adders for phase compensation, this method replaces nonlinear calculations with an arithmetic progression summation formula. Furthermore, in FPGAs, the number of parallel paths, k, is often a power of 2. When calculating the frequency control word, this method optimizes the multiplication operations associated with k into shift operations. For example, with 16 parallel paths, a single path requires only five additions and two shifts, eliminating the need for multipliers and significantly reducing power consumption.

[0160] This method does not require pre-storage of any special signal waveforms, significantly reducing storage consumption. (In the Vivado DDS IP core, only one cycle of the sine wave needs to be stored, which is included with the IP core.)

[0161] This method utilizes a modular design, with consistent code structure across all parallel branches. Through state machine control and standardized IP core invocation, it can be expanded to 32 or higher parallel paths simply by adjusting the number of parallel paths. Furthermore, the algorithm is decoupled from the hardware platform, enabling seamless portability to different FPGA or ASIC chips, providing a technical foundation for the rapid deployment and upgrade of synthetic aperture radar systems.

[0162] The following describes a linear frequency modulation signal generation device based on multi-channel parallel real-time calculation provided by the present invention. The linear frequency modulation signal generation device based on multi-channel parallel real-time calculation described below and the linear frequency modulation signal generation method based on multi-channel parallel real-time calculation described above can be referred to in correspondence with each other.

[0163] The linear frequency modulation signal generating device based on multi-channel parallel real-time calculation provided by the present invention refers to Figure 6 As shown, including:

[0164] The initial phase generating module 210 is used to determine the starting frequency control word and the frequency modulation slope control word according to the preset linear frequency modulation signal parameters;

[0165] A control word generation module 220 is configured to construct a virtual serial frequency control word, and generate k parallel frequency control words based on the virtual serial frequency control word, the starting frequency control word, and the frequency modulation slope control word, where k is an integer greater than 1;

[0166] The phase accumulation module 230 inputs the k parallel frequency control words into k phase accumulators respectively to synchronously generate k phase-continuous linear frequency modulation signals;

[0167] The digital-to-analog conversion module 240 is configured to combine the k phase-continuous linear frequency modulation signals through a digital-to-analog converter and output the combined signals as a broadband linear frequency modulation signal.

[0168] Figure 7 An example of a physical structure diagram of an electronic device is shown below. Figure 7As shown, the electronic device may include: a processor 310, a communications interface 320, a memory 330, and a communication bus 340. The processor 310, the communications interface 320, and the memory 330 communicate with each other via the communication bus 340. The processor 310 may call logic instructions in the memory 330 to execute a linear frequency modulation signal generation method based on multi-path parallel real-time computing.

[0169] Furthermore, the logic instructions in the aforementioned memory 330 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product, stored in a storage medium, includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0170] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the linear frequency modulation signal generation method based on multi-channel parallel real-time calculation provided by the above methods.

[0171] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the linear frequency modulation signal generation method based on multi-channel parallel real-time calculation provided by the above methods.

[0172] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0173] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0174] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for generating a linear frequency modulation signal based on multi-channel parallel real-time calculation, characterized in that: include: Determine the starting frequency control word and the frequency modulation slope control word according to the preset linear frequency modulation signal parameters; Constructing virtual serial frequency control words and , generating k parallel frequency control words based on the virtual serial frequency control word, the starting frequency control word, and the frequency modulation slope control word, where k is an integer greater than 1; the parallel frequency control words are determined by the following formula: ； In the formula, the superscript [j] represents the jth parallel path, (N+1) represents the N+1th point in the parallel branch, and (n+1) represents the n+1th point in the serial path. is the parallel frequency control word of the j-th path at the N+1th point, is the serial frequency control word of the virtual serial signal at the n+ith point, and k is the number of parallel paths; ； Where, is the serial frequency control word of the n+1th point, is the serial frequency control word of the nth point; f word0 is the starting frequency control word, K word is the frequency modulation slope control word; Inputting the k parallel frequency control words into k phase accumulators respectively to synchronously generate k phase-continuous linear frequency modulation signals; The k phase-continuous linear frequency modulation signals are combined and output as a broadband linear frequency modulation signal through a digital-to-analog converter.

2. The method for generating a linear frequency modulation signal based on multi-channel parallel real-time calculation according to claim 1, characterized in that: The preset linear frequency modulation signal parameters include center frequency, phase accumulator bit width, sampling frequency, sampling point number control word and signal bandwidth; The step of determining the starting frequency control word and the frequency modulation slope control word according to the preset linear frequency modulation signal parameters includes: Determine the frequency modulation slope control word according to the phase accumulator bit width, sampling frequency, sampling point number control word and signal bandwidth; A frequency control word corresponding to the center frequency is obtained, and the starting frequency control word is determined according to the frequency control word corresponding to the center frequency, the sampling point number control word, and the frequency modulation slope control word.

3. The method for generating a linear frequency modulation signal based on multi-channel parallel real-time calculation according to claim 1, characterized in that: The constructing of a virtual serial frequency control word, generating k parallel frequency control words based on the virtual serial frequency control word, the starting frequency control word and the frequency modulation slope control word, comprises: Calculating the initial value of the frequency control word of each channel in parallel according to the starting frequency control word; Constructing a virtual serial frequency control word; wherein the difference between the serial frequency control word of the current serial point and the serial frequency control word of the previous serial point is the frequency modulation slope control word; Based on the virtual serial frequency control word, the j-th parallel frequency control word is calculated using an arithmetic progression summation formula; j=1, 2, ..., k-1.

4. The method for generating a linear frequency modulation signal based on multi-channel parallel real-time calculation according to claim 2, characterized in that: The initial phase offsets of the k parallel phase accumulators are determined by: Determine the center phase offset according to the frequency control word corresponding to the center frequency, the starting frequency control word, and the sampling point number control word: Using the center phase offset as the initial phase offset of the 0th path in parallel; The initial phase offset of the i+1th path in parallel is determined according to the initial value of the frequency control word of the i+1th path in parallel and the initial phase offset of the ith path in parallel; wherein i=1,2,…,k-1.

5. The method for generating a linear frequency modulation signal based on multi-channel parallel real-time calculation according to claim 1, characterized in that: The frequency control word of each adjacent point in parallel is the sum of the frequency control words of the first k points in serial.

6. The method for generating a linear frequency modulation signal based on multi-channel parallel real-time computing according to claim 1, wherein: The phase accumulator adopts a DDS IP core.

7. A linear frequency modulation signal generation device based on multi-channel parallel real-time calculation, characterized in that: include: An initial phase generating module is used to determine the starting frequency control word and the frequency modulation slope control word according to the preset linear frequency modulation signal parameters; A control word generation module is configured to construct a virtual serial frequency control word, and generate k parallel frequency control words based on the virtual serial frequency control word, the starting frequency control word, and the frequency modulation slope control word, where k is an integer greater than 1; the parallel frequency control words are determined by the following formula: ； In the formula, the superscript [j] represents the jth parallel path, (N+1) represents the N+1th point in the parallel branch, and (n+1) represents the n+1th point in the serial path. is the parallel frequency control word of the j-th path at the N+1th point, is the serial frequency control word of the virtual serial signal at the n+ith point, and k is the number of parallel paths; ； Where, is the serial frequency control word of the n+1th point, is the serial frequency control word of the nth point; f word0 is the starting frequency control word, K word is the frequency modulation slope control word; A phase accumulation module inputs the k-channel parallel frequency control words into k phase accumulators respectively to synchronously generate k-channel phase-continuous linear frequency modulation signals; The digital-to-analog conversion module is used to combine the k phase-continuous linear frequency modulation signals through a digital-to-analog converter and output them as a broadband linear frequency modulation signal.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the method for generating a linear frequency modulation signal based on multi-channel parallel real-time calculation as claimed in any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for generating a linear frequency modulation signal based on multi-channel parallel real-time calculation as claimed in any one of claims 1 to 6 is implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method for generating a linear frequency modulation signal based on multi-channel parallel real-time calculation as claimed in any one of claims 1 to 6 is implemented.

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