Method and apparatus for self-calibrating radio frequency transmitter

Abstract

A method and apparatus for self-calibrating a radio frequency transmitter are disclosed. The apparatus includes first circuitry that receives a reference phase value and outputs a first analog signal based on the reference phase value; a second circuitry that receives a reference phase value and outputs a second analog signal based on the reference phase value; an IQ modulator coupled to receive an input signal, a first analog signal, and a second analog signal, and to provide an IQ modulator output signal based on the input signal, the first analog signal, and the second analog signal; and compensation control circuitry that receives the IQ modulator output signal and outputs at least one compensation signal indicative of a compensation value based on the IQ modulator output signal during calibration. At least one of the first circuitry and the second circuitry includes: a digital signal generation section that generates a digital signal based on a reference phase value and at least one compensation value; a sigma-delta modulator section that receives the digital signal and sigma-delta modulates the digital signal during calibration; and a digital-to-analog converter receiving the modulated digital signal provided by the sigma-delta modulator section and outputting the respective first / second analog signal during calibration.

Description

Technical Field

[0001] This specification relates to methods and apparatus for self - calibrating radio frequency (RF) transmitters. In particular, but not exclusively, this specification relates to methods and apparatus for improving the accuracy of phase error compensation in RF transmitters. Background Art

[0002] A key parameter of an RF transmitter, such as for a radar transmitter, is the phase accuracy of the transmitter.

[0003] Some radar systems, such as advanced 77 GHz multi - input multi - output (MIMO) radar solutions, use an IQ modulator (phase rotator) in the transmitter to shift the phase of the transmitter. MIMO radar is used to improve angular resolution and relies on virtual array antennas created by the combination of transmitters and receivers. When multiple transmitters are used simultaneously, it is necessary to distinguish between the multiple transmitters in radar post - processing. In the case of Doppler Division Multiple Access (DDMA) modulation, this is achieved by using an 80 GHz phase rotator within the transmitter and encoding the transmitters by rotating the phase of each transmitter. This results in small frequency shifts in the Doppler spectrum, enabling the transmitters to be distinguished in the Doppler spectrum.

[0004] Transmitter phase accuracy can be degraded due to RF impairments in the IQ modulator (phase rotator), including amplitude and phase imbalances, local oscillator (LO) feed - through. The resulting phase error can degrade radar detection, especially image rejection. For example, non - linearities in phase rotation can create clutter in the Doppler spectrum when using DDMA modulation or in the range spectrum when using FDMA modulation. These clutters can appear as ghost targets in radar processing. Compensation for non - linearities in the phase rotator can be used to reduce the level of ghost targets. Summary of the Invention

[0005] Aspects of the present disclosure are set forth in the accompanying independent claims and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims where appropriate and not merely as explicitly stated in the claims.

[0006] According to one aspect of the present disclosure, there is provided an apparatus comprising:

[0007] A first circuitry for receiving a reference phase value and configured to output a first analog signal based on the reference phase value;

[0008] A second circuitry for receiving the reference phase value and configured to output a second analog signal based on the reference phase value;

[0009] An IQ modulator, which is coupled to receive an input signal, the first analog signal, and the second analog signal, and is configured to provide an IQ modulator output signal based on the input signal, the first analog signal, and the second analog signal; and

[0010] A compensation control circuitry, which is coupled to receive the IQ modulator output signal and is configured to output at least one compensation signal indicative of a compensation value based on the IQ modulator output signal during calibration;

[0011] Wherein at least one of the first circuitry and the second circuitry includes:

[0012] A digital signal generation part, which is configured to generate a digital signal based on the reference phase value and at least one of the compensation values,

[0013] A Σ-Δ modulator part, which is coupled to receive the digital signal and is configured to apply Σ-Δ modulation to the digital signal during calibration; and

[0014] A digital-to-analog converter, which is coupled to receive the modulated digital signal provided by the Σ-Δ modulator part during calibration and is configured to output the corresponding first / second analog signal.

[0015] An IQ modulator of a phase rotator used, for example, in a radar application typically has RF defects or non-linearities, which degrade the transmit phase accuracy, thereby introducing a phase error, which in turn can result in ghost targets in the processed radar data. RF impairments in the IQ modulator can include gain / amplitude imbalance, phase imbalance, and local oscillator (LO) feedthrough. The resulting phase error is a major contributing factor to the degradation of the radar image and carrier suppression. Compensation for RF phase defects or non-linearities in the IQ modulator can be used to improve detection, specifically by reducing the level of ghost targets and improving radar image rejection. Calibration of the IQ modulator by digital predistortion of the IQ modulator baseband input can improve the linearity of the IQ modulator and reduce the probability of false targets.

[0016] The accuracy of the compensation depends on the accuracy of the mechanism used to monitor the phase error. For example, the resolution of a DAC commonly used to control the IQ modulator is typically a limiting factor in the optimization of the phase error. Although the resolution of the DAC can be increased by increasing the number of bits of the DAC, this has an impact on the die size and can result in increased cost.

[0017] Digital Δ-Σ modulation converts an n-bit digital signal into an m-bit digital signal, where m < n, and the digital signal is modulated in time such that its average value represents the input. By applying Σ-Δ modulation to the digital signal input to the DAC of a control IQ modulator during calibration, the output signal of the phase rotator can be measured with high accuracy, thereby achieving a more accurate compensation for RF impairment. In radar applications, this can increase the dynamic range of the radar Doppler spectrum. During calibration, the compensation can be performed with a higher number of bits. By improving the accuracy of the compensation, the phase error can be reduced and the image rejection can be improved, thereby improving the radar performance.

[0018] By including a digital Σ-Δ modulator in front of the DAC during calibration, the resolution of the DAC can be effectively increased without increasing the number of DAC bits, thereby achieving a more accurate compensation for RF impairment. By improving the compensation for RF impairment, the present disclosure enables the improvement of radar performance for a given DAC resolution. In the same way, the present disclosure can enable the reduction of the actual resolution of the DAC, thereby reducing the area occupied by the DAC without degrading the performance.

[0019] Although the example of a radar transmitter is used above, the present disclosure is applicable to any radio frequency transmitter including an IQ modulator or a phase rotator, and specifically any IQ system exhibiting gain or phase imbalance or LO feedthrough.

[0020] In some embodiments, the Δ-Σ modulator section includes:

[0021] a Σ-Δ modulator configured to apply Σ-Δ modulation to a second portion of the digital signal; and

[0022] a summing node for summing the modulated second portion with a first portion of the digital signal.

[0023] Applying Σ-Δ modulation only to the second portion of the digital signal can enable the maintenance of a certain signal-to-noise ratio (SNR) in the frequency band of interest.

[0024] In some embodiments, the first portion is the integer part of the digital signal and the second portion is the fractional part of the digital signal.

[0025] In some embodiments, the first portion includes the most significant bits of the digital signal, and the second portion includes the least significant bits of the digital signal. In some embodiments, the first portion includes the same number of bits as the digital-to-analog converter.

[0026] In some embodiments, the apparatus can selectively operate in the following modes:

[0027] a calibration mode, in which the Σ-Δ modulator is enabled; and

[0028] A transmission mode in which the Σ-Δ modulator is deactivated or bypassed.

[0029] Deactivating or bypassing the Σ-Δ modulator during transmission avoids adding noise to the IQ modulator output signal. The characteristic noise shaping introduced by the Σ-Δ modulator may be incompatible with the transmission signal in some applications, specifically in some radar systems.

[0030] When the device operates in the transmission mode, the digital signal generation section may be configured to generate the digital signal based on the reference phase value and the at least one compensation value output by the compensation control circuitry during calibration.

[0031] Furthermore, even when Σ-Δ modulation is deactivated or bypassed during transmission, the phase error of the transmission can still be reduced due to the improved accuracy of the compensation values obtained during calibration.

[0032] In some embodiments, the device further includes a power amplifier coupled to receive the IQ modulator output signal, the power amplifier being configured to amplify the IQ modulator output signal for output to an antenna.

[0033] During the calibration mode, the power amplifier can be deactivated.

[0034] In some embodiments, the compensation control circuitry includes a power meter coupled to receive the IQ modulator output signal and configured to output a power measurement signal indicative of the power of the IQ modulator output signal, and wherein the at least one compensation value is determined by the compensation control circuitry based on the power measurement signal.

[0035] In some embodiments, the compensation control circuitry includes a low-pass filter for removing high-frequency noise from the power measurement signal.

[0036] In some embodiments, the at least one compensation parameter corresponds to at least one of amplitude adjustment, phase offset, and dc offset of a corresponding digital signal.

[0037] In some embodiments, the compensation control circuitry is configured to determine the at least one compensation value based on the IQ modulator output signal by iteratively updating the corresponding compensation values.

[0038] In some embodiments, the compensation control circuitry is configured to determine the at least one compensation value based on the IQ modulator output signal by performing at least one corresponding binary search.

[0039] In some embodiments, the compensation control circuit system is further configured to determine, from the IQ modulator output signal, the signal component path of the IQ modulator having the highest gain, and wherein the at least one compensation value includes an amplitude adjustment of the corresponding digital signal corresponding to the signal component path having the highest gain.

[0040] The amplitude adjustment may reduce the amplitude of the corresponding digital signal relative to a predetermined initial amplitude.

[0041] For example, if a first analog signal and a second analog signal control the in-phase signal component path and the quadrature-phase signal component path of the IQ modulator, respectively, and the in-phase signal component path is determined to have the highest gain, the amplitude of the corresponding digital signal used to generate the first analog signal may be reduced relative to its initial value, while the amplitude of the digital signal used to generate the second analog signal remains its initial value, and vice versa. This can help avoid saturating the DAC.

[0042] In some embodiments, the or each compensation parameter is stored by the first and / or second circuit system or the digital controller.

[0043] For example, the compensation parameter may be stored in a digital register, a flip-flop, or other memory element.

[0044] In some embodiments, the phase error of the IQ modulator output signal is less than or equal to 1 degree.

[0045] According to another aspect of the present disclosure, there is provided a radio frequency transmitter, comprising:

[0046] The apparatus according to the first aspect as defined above; and

[0047] A transmitting antenna coupled to the output of the IQ modulator.

[0048] In some embodiments, the radio frequency transmitter is a radar transmitter.

[0049] According to another aspect of the present disclosure, there is provided a method for self-calibrating an IQ modulator, the method comprising:

[0050] Generating a first digital signal and a second digital signal based on a reference phase value and at least one compensation value;

[0051] Applying Σ-Δ modulation to each of the first digital signal and the second digital signal; and

[0052] Converting the modulated first digital signal and the modulated second digital signal into a first analog signal and a second analog signal, respectively;

[0053] The IQ modulator generates an IQ modulator output signal based on the radio frequency input signal, the first analog signal, and the second analog signal; and

[0054] Monitor the IQ modulator output signal as a function of a reference phase value; and

[0055] Update the at least one compensation value based on the monitored IQ modulator output signal.

[0056] In some embodiments, the first digital signal corresponds to A*A comp *cos(Φ + Φ comp ) + DC comp_I , where Φ is the reference phase value, A is the initial amplitude, and the at least one compensation value includes A comp , Φ comp and DC comp_I , and optionally the second digital signal corresponds to A*sin(Φ) + DC comp_Q and the at least one compensation value further includes the value DC comp_Q .

[0057] In some embodiments, the second digital signal corresponds to A*A comp *sin(Φ + Φ comp ) + DC comp_Q , where Φ is the reference phase value, A is the initial amplitude, and the at least one compensation value includes the value A comp , Φ comp and DC comp_Q , and optionally the first digital signal corresponds to A*cos(Φ) + DC comp_I and the at least one compensation value further includes the value DC comp_I .

[0058] In some embodiments, applying Σ-Δ modulation to the first / second digital signal includes:

[0059] Dividing the first / second digital signal into a first part and a second part;

[0060] Applying Δ-Σ modulation to the second part of the first / second digital signal; and

[0061] Summing the modulated second part with the first part of the first / second digital signal.

[0062] In some embodiments, determining the at least one compensation value based on the IQ modulator output signal includes determining the at least one compensation value based on a measurement of the power of the IQ modulator output signal as a function of a phase reference value.

[0063] In some embodiments, determining the at least one compensation value based on the IQ modulator output signal includes averaging measurements of the IQ modulator output signal or applying a low-pass filter.

[0064] In some embodiments, the at least one compensation value includes at least one of amplitude adjustment, phase offset, and dc offset of a first digital signal.

[0065] In some embodiments, the method further comprises:

[0066] Determining a signal component path of the IQ modulator having the highest gain from the IQ modulator output signal;

[0067] where determining the at least one compensation value based on the IQ modulator output signal includes determining a compensation value for adjusting the amplitude of the corresponding digital signal corresponding to the signal component path having the highest gain.

[0068] In some embodiments, the method further comprises storing the at least one compensation value.

[0069] In some embodiments, determining the at least one compensation value based on the IQ modulator output signal includes iteratively updating the corresponding compensation value.

[0070] In some embodiments, determining the at least one compensation value based on the IQ modulator output signal includes at least one corresponding binary search. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Figure 1 An apparatus showing example embodiments in accordance with the present disclosure;

[0072] Figure 2 Schematically showing an example IQ modulator in an apparatus for Figure 1 example embodiments; and

[0073] Figure 3 A flowchart showing a method for calibrating an IQ modulator according to example embodiments. DETAILED DESCRIPTION

[0074] Figure 1 An apparatus 100 according to example embodiments of the present disclosure is schematically shown. The apparatus 100 in the form of a radio frequency transmitter includes a first input 105 for receiving a reference phase value Φ, a phase rotator 110, a first circuitry 120, a second circuitry 130, a compensation control circuitry 150, a buffer 160, a power amplifier 170, and a radar antenna 180.

[0075] The radio frequency phase rotator 110 in the form of an IQ modulator 110 is supplied with first analog signals A for the I and Q paths respectively Iand the second analog signal A Q for control. The IQ modulator 110 also receives an input signal in the form of a local oscillator signal LO, and generates an output signal RF I based on the local oscillator signal LO, the first analog signal A Q and the second analog signal A out . The phase of the output signal RF out is controlled by the first analog signal A I and the second analog signal A Q .

[0076] Figure 2 Schematically shows an example IQ modulator 110 for use in the device 100. The input signal LO received by the IQ modulator 110 is split into an in-phase (I) component LOI and a quadrature-phase (Q) component LOQ. The in-phase component is substantially in phase with the received input signal, and the quadrature-phase component acquires a phase shift at block 112 such that it is substantially 90 degrees out of phase with the received input signal LO. The first mixer 114 receives the in-phase component LOI and the first analog signal A I , and outputs a first signal component P I that is the product of the in-phase component LOI and the first analog signal A I . The second mixer 116 receives the quadrature-phase component LOQ and the second analog signal A Q , and outputs a second signal component P Q that is the product of the quadrature-phase component LOQ and the first analog signal A Q . The adder 118 receives the first signal component P I and the second signal component P Q , and outputs the IQ modulator output signal RF I that is the sum of the first signal component P Q and the second signal component P out .

[0077] The IQ modulator output signal RF out is coupled via a buffer 160 (e.g., a series of buffers) to a power amplifier 170 to amplify the output signal RF out for output to the radar antenna 180.

[0078] The first analog signal A I is generated by a first circuitry 120 that is coupled to a first input 105 for receiving a reference phase value Φ and is configured to output the first analog signal A I based on the reference phase value Φ. The second analog signal A QGenerated by a second circuitry 130 that is coupled to a first input 105 for receiving the reference phase value Φ and is configured to output a second analog signal A based on the reference phase value Φ Q .

[0079] For an ideal IQ modulator (phase rotator), the first analog signal and the second analog signal can be represented by A I = A * cos(Φ) and A Q = A * sin(Φ), respectively, where A is a common amplitude and Φ is the reference phase value received at the first input 105, such that the phase of the IQ modulator output signal RF out corresponds to the reference phase value Φ.

[0080] However, a real IQ modulator 110 has phase and gain defects (i.e., phase and gain imbalances), and also has LO feedthrough, resulting in non - linearity in the behavior of the IQ modulator 110, which causes a phase error at the IQ modulator output signal RF out . To optimize the phase error due to the RF defects of the IQ modulator 110, a compensation control circuitry 150 is used to monitor and compensate for the phase error by providing feedback from the output of the power rotator 110 to the first circuitry 120 and / or the second circuitry 130, which generate the respective first analog signal A I and the second analog signal A Q for controlling the IQ modulator 110. The compensation control circuitry 150 is coupled to receive the IQ modulator output signal RF out and is configured to output at least one compensation signal 512 indicative of a compensation value based on the IQ modulator output signal RF out . The compensation value is used to control the analog signals A I , A Q of the IQ modulator 110, for example, by adjusting the amplitude, phase offset, and / or dc offset of one or both of them, to pre - distort the analog signals A I , A Q . In this way, the apparatus 100 compensates for the RF defects of the IQ modulator 110. Thus, the first analog signal A I and the second analog signal A Q can more generally be represented by A I = A 1 * cos(Φ + Φ 1 ) + DC 1 and A Q = A 2 * sin(Φ + Φ 2 ) + DC 2Description, where Φ is a reference phase value received at the first input 105, A 1 , Φ 1 and DC 1 are respectively the amplitude, phase offset, and dc offset of the first analog signal, and A 2 , Φ 2 and DC 2 are respectively the amplitude, phase offset, and dc offset of the second analog signal. The amplitude, phase offset, and dc offset of each signal can be determined or adjusted by compensation signals received by the first circuit system 120 and the second circuit system 130 from the compensation control circuit system 150. In this example embodiment, the compensation values indicated by the compensation signal 512 output by the compensation control circuit system 150 include the amplitude adjustment A comp and phase offset Φ comp respectively for compensating for gain imbalance and phase imbalance, and the dc offsets DC comp_I and DC comp_Q for compensating for LO feedthrough on both paths.

[0081] The first circuit system 120 includes a first digital signal generation section 210, a first Σ-Δ modulation section 220, and a first digital-to-analog converter (DAC) 230. The first digital signal generation section 210 generates a first digital signal D 1 *cos(Φ + Φ 1 ) + DC 1 corresponding to based on the reference phase value Φ and the compensation values indicated by the compensation signal 512 received from the compensation control circuit system 150. The first Σ-Δ modulation section 220 applies Σ-Δ modulation to the first digital signal D I . The first DAC 230 is coupled to the output of the Σ-Δ modulation section 220 for selectively receiving one of the modulated first digital signal or the unmodulated portion of the first digital signal, and outputs a first analog signal A I for controlling the I (in-phase) branch of the IQ modulator 110. The first analog signal A I is an analog signal having an amplitude corresponding to the first digital signal. I

[0082] Similarly, the second circuit system 130 includes a second digital signal generation section 310, a second Σ-Δ modulation section 320, and a second digital-to-analog converter (DAC) 330. The second digital signal generation section 210 generates a second digital signal D 2 *sin(Φ + Φ 2 ) + DC 2 corresponding to based on the reference phase value Φ and the compensation values indicated by the compensation signal 512 received from the compensation control circuit system 150. Q ​. The second Σ-Δ modulation section 320 is used to perform Σ-Δ modulation on the second digital signal D Q The second DAC 330 is coupled to the output of the second Σ-Δ modulation section 320 for selectively receiving one of the modulated second digital signal or the unmodulated portion of the second digital signal, and outputs a second analog signal A Q for controlling the Q (quadrature phase) branch of the IQ modulator 110. The second analog signal A Q is an analog signal having an amplitude corresponding to the second digital signal.

[0083] Each of the first digital signal generation section 210 and the second digital signal generation section 310 includes CORDICs 214, 314 for respectively generating A 1 *cos(Φ + Φ 1 ) and A 2 *sin(Φ + Φ 2 ). Each CORDIC 214, 314 is coupled to receive a reference phase value Φ and compensation signals 512 indicating compensation values A comp (gain imbalance compensation), Φ comp (phase imbalance compensation), as well as path selection control parameters I sel and Q sel as inputs, the purpose of these inputs will be described below. In other embodiments, a look-up table (LUT) or other components may be used instead of CORDIC. For each signal path, by summing the output of the CORDICs 214, 314 with a signal representing the desired offset, the corresponding dc offset DC 1 , DC 2 can be applied after the CORDIC. In this example embodiment, the first digital signal generation section 210 includes a summing node 216 arranged to receive the output of the corresponding CORDIC 214 and the compensation signal 512 indicating the compensation value DC comp_I . The second digital signal generation section 310 includes a summing node 316 arranged to receive the output of the corresponding CORDIC 314 and the compensation signal 512 indicating the compensation value DC comp_Q .

[0084] The first Δ-Σ modulation section 220 is configured to split the first digital signal D I into a first part 222 and a second part 224, and perform Δ-Σ modulation on the first digital signal D IThe second part 224 of [the signal] applies delta-sigma modulation and sums the modulated second part 224 with the first part 222 of the first digital signal. The first delta-sigma modulator section 220 includes a delay element 225, a digital sigma-delta modulator 226, a summing node 227, and a mode selector 228. The sigma-delta modulator 226 receives the first (e.g., fractional) part 224 of the first digital signal D I and applies sigma-delta modulation to this first part 224. The delay element 225 receives the first digital signal D I of the second (e.g., integer) part 222 and applies a delay equivalent to the delay of the sigma-delta modulator 226 to this second part 222. The delayed first part output by the delay element 225 is recombined at the summing node 227 with the sigma-delta modulated second part output by the sigma-delta modulator 226. The modulated first digital signal output of the sigma-delta modulation section 220 is thus a digital signal in which one or more most significant bits are not modulated in time and one or more least significant bits are modulated in time.

[0085] The mode selector 228 in the form of a multiplexer is coupled to receive the recombined sigma-delta modulated first digital signal output by the summing node 227, the unmodulated first digital signal D I of the first part 222, and the mode control signal cal. During calibration of the device, the mode control signal cal is turned on (e.g., high), and the mode selector 228 outputs the recombined sigma-delta modulated first digital signal to the first DAC 230. During transmission, the mode control signal cal is turned off (e.g., low), and the mode selector 228 outputs the unmodulated first digital signal D I of the first part 222 to the first DAC 230.

[0086] Thus, depending on the state of the mode control signal cal, the first DAC 230 selectively receives the recombined digital signal or the unmodulated first part 222 of the first digital signal D I from the first sigma-delta modulation section 220.

[0087] Similarly, the second delta-sigma modulator section 320 is configured to split a second digital signal D Q into a first part 322 and a second part 324, apply delta-sigma modulation to the second part 324 of the second digital signal D Q and sum the modulated second part 324 with the first part 322 of the second digital signal. The second delta-sigma modulator section 320 includes a delay element 325, a digital sigma-delta modulator 326, a summing node 327, and a mode selector 328. The sigma-delta modulator 326 receives the second digital signal D QThe first (e.g., fractional) part 324 of and apply Σ-Δ modulation to this first part 324. The delay element 325 receives the second digital signal D Q The second (e.g., integer) part 322 of and apply a delay equivalent to the delay of the Σ-Δ modulator 326 to this second part 322. The delayed first part output by the delay element 325 is recombined with the Σ-Δ modulated second part output by the Σ-Δ modulator 326 at the summing node 327. The mode selector 328 in the form of a multiplexer is coupled to receive the recombined Σ-Δ modulated second digital signal output by the summing node 327, the unmodulated second digital signal D Q The first part 322 of, and the mode control signal cal. During calibration, the mode control signal cal is turned on (e.g., high), and the mode selector 328 outputs the recombined Σ-Δ modulated second digital signal to the second DAC 330. During transmission, the mode control signal cal is turned off (e.g., low), and the mode selector 328 outputs the unmodulated second digital signal D Q The first part 322 of to the second DAC 330.

[0088] The second DAC 330 thus selectively receives the recombined digital signal or the second digital signal D Q The unmodulated first part 322 of from the second Σ-Δ modulation section 320.

[0089] The digital Σ-Δ modulators 226, 326 may be provided in the form of a simple multi-stage noise shaping (MASH) structure of order 3 or 4, but other architectures of Σ-Δ modulators may also be used.

[0090] In this example embodiment, the first digital signal D I And the second digital signal D Q Each of includes n1 bits, and each of the first DAC 230 and the second DAC 330 is an n2-bit DAC, where n2 < n1. In Figure 1 The example embodiment shown, the corresponding first digital signal D I And the second digital signal D Q The first parts 222, 322 of include n2 bits, and the second parts 224, 324 include n1 - n2 bits. By way of example, the first parts 222, 322 may be the integer parts of the corresponding first / second digital signals and the second parts 224, 324 may be their fractional parts. Thus, during calibration, a larger number of bits than the DAC resolution can be used to apply compensation. This in turn enables the IQ modulator output signal to be monitored with greater accuracy, thereby increasing the accuracy of compensation.

[0091] The operation of the digital Δ-Σ modulators 226, 326 increases the accuracy of compensation and thus reduces the phase error, but also introduces high-frequency noise on the IQ modulator output signal RF out To avoid degradation of the transmission due to the noise, the apparatus 100 can operate selectively in a calibration mode (cal = 1) and a transmission mode (cal = 0), in which the first Σ-Δ modulator section 220 and the second Σ-Δ modulator section 320 are enabled, and in which the first Σ-Δ modulator 226 and the second Σ-Δ modulator 326 are bypassed or otherwise deactivated in the transmission mode. That is, the digital Σ-Δ modulators 226, 326 are activated during calibration of the phase error / image rejection to improve the accuracy of compensation, but are deactivated or bypassed during transmission to avoid adding unwanted noise to the transmitted radar signal. Thus, the input signals to the DACs 230, 330 depend on the mode (calibration or transmission). Additionally, during operation in the calibration mode, the power amplifier 170 can be deactivated to make the transmission inactive. In the compensation control circuitry 150, the monitored IQ modulator output signal RF out due to the operation of the Σ-Δ modulators 226, 326 can be mitigated, for example, by digital averaging and / or by using the low-pass filter 506.

[0092] During transmission, due to the truncation or rounding of the n1-bit digital signals (D I , D Q ) to match the n2-bit resolution of the DACs (230, 330), there may be some small degradation of the IQ modulator output signal. However, due to the application of the more accurate compensation determined during calibration, there is an overall improvement (reduction) in the phase error of the transmission.

[0093] The compensation control circuitry 150 includes a detector 502, an amplifier 504, a low-pass filter 506, an analog-to-digital converter (ADC) 508, and a digital controller 510. In this example embodiment, the detector 502 is provided in the form of a power meter 502 for monitoring the power of the signal RF out output by the IQ modulator 110. For an ideal IQ modulator without defects, the output power is constant and independent of the applied phase rotation Φ. RF defects in the IQ modulator 110 cause the power of the IQ modulator output signal RF out to vary with the reference phase value Φ. That is, when different phase rotations are applied to the RF signal, a variation in the power of the output signal RF out of the IQ modulator 110 is observed. In this example embodiment, the compensation control circuitry 150 adjusts the compensation value until the variation of P out is optimized, based on the power measurement signal P outto determine the compensation value. The power meter 502 is coupled to receive the output signal RF of the IQ modulator 110 out and is configured to output a power measurement signal P indicative of the power of the IQ modulator output signal RF out . The power meter 502 may include, for example, an RMS detector or a peak power detector. For example, the power meter 502 may be configured to measure the change in the power of the IQ modulator output signal RF out . In this example embodiment, the power meter 502 is configured to measure the incremental change in the power of the IQ modulator output signal RF out as a function of the programmed phase value Φ. out

[0094] The amplifier 504 is coupled to receive the power measurement signal P output by the power meter 502 out and amplifies the power change measured by the power meter 502. The amplifier 504 may be provided in the form of a variable gain amplifier (VGA) such that by controlling the variable gain and offset of the amplifier 504, small power changes can be amplified and recentered to occupy the entire range of the ADC 508. The low pass filter 506 is coupled to the output of the amplifier 504 and is configured to remove high frequency noise resulting from the first Σ-Δ modulator 226 and the second Σ-Δ modulator 326. In an alternative embodiment, digital averaging may be used instead of the low pass filter 506 to remove this high frequency noise, but this would require a longer calibration time. The ADC 508 is coupled to receive the output of the low pass filter 506 and translates the information to the digital controller 510.

[0095] The digital controller 510 is configured to interpret the information from the ADC 508 and generate the optimal compensation for the amplitude, phase, and dc offset of the first and / or second analog signals A I 、A Q . In this example embodiment, the compensation value indicated by the compensation signal 512 output by the compensation control circuit system 150 includes an amplitude adjustment A comp and a phase offset Φ comp for compensating for gain imbalance and phase imbalance, respectively, and a dc offset DC comp_I and DC comp_Q for compensating for LO feedthrough on both paths. The compensation signal 512 also includes path selection control parameters I sel and Q sel .

[0096] During calibration, the power of the IQ modulator output signal RF out monitored as a function of the reference phase value Φ is measured. The amplitude A I of the first digital signal D 1 , the phase offset Φ 1and / or the DC offset DC 1 and / or the second digital signal D Q amplitude A 2 phase offset Φ 2 and / or the DC offset DC 2 The values are iteratively updated until the incremental change in the output power of the IQ modulator is considered to be minimal or below a desired upper limit.

[0097] In a first example, compensation is applied by modifying the amplitude A I of the first digital signal D 1 phase offset Φ 1 and the DC offset DC 1 and the DC offset DC Q of the second analog signal D 2 To compensate for LO feedthrough on each of the I and Q paths of the IQ modulator 110, compensation is applied to the corresponding DC offsets DC 1 and DC 2 Before calibration, the input offsets for both the I and Q paths are zero, i.e., DC 1 = DC 2 = 0. During calibration, the digital controller 510 iteratively updates the DC offset compensation value DC comp_I which modifies the DC offset DC I of the first digital signal D 1 to DC 1 = DC comp_I until the power meter output indicates an optimal (small) incremental change. For example, at each iteration, the output power can be measured for two different values of the reference phase Φ, and the incremental change in the measured power indicates whether the compensation needs to be increased or decreased. Next, the digital controller 510 iteratively updates the DC offset compensation DC comp_Q which modifies the DC offset DC Q of the second digital signal D 2 to DC 2 = DC comp_Q until the power meter output indicates an optimal incremental change. Before calibration, the input gains of the DACs 230, 330 are controlled by an initial amplitude A, i.e., A 1 = A 2 = A. During calibration, to compensate for gain imbalance in the IQ modulator 110, the digital controller 510 iteratively updates the gain compensation value A comp which modifies the amplitude A 1 of the first digital signal to D 1 = A * A comp, until the incremental change measured by the power meter 502 is within the desired or optimal range, i.e., the incremental change is small. Before calibration, the input phases of the DACs 230, 330 are completely controlled by the reference phase parameter Φ, which corresponds to the desired phase rotation of the LO signal. That is, the phase offset is zero, Φ 1 = Φ 2 = 0. During calibration, to compensate for the phase imbalance in the IQ modulator 110, the digital controller 510 iteratively updates the phase compensation Φ comp , which modifies the phase offset of the first digital signal D I to Φ 1 = Φ comp , until the incremental change measured by the power meter 502 is within the desired or optimal (small) range. For each of the calibrations (dc offset (path I), dc offset (path Q), amplitude adjustment, phase offset), a binary search can be used to find the corresponding optimal compensation values (DC comp_I , DC comp_Q , A comp , Φ comp ), but those skilled in the art will appreciate that other techniques can be used.

[0098] In the above example, the dc offset is calibrated first, followed by gain imbalance and phase imbalance. The order in which the above calibrations are performed can be different from the default order stated above (i.e., dc offset (path I), followed by dc offset (path Q), followed by amplitude adjustment, followed by phase offset).

[0099] In the above example, the first and second digital signals before calibration are:

[0100] I path: D I = A * cos(Φ)

[0101] Q path: D Q = A * sin(Φ).

[0102] The compensation for gain and phase imbalance can be applied to only one path (I or Q), while the dc offset compensation is applied to both the I and Q paths. In the above example where the amplitude and phase offset compensations are applied only to the first or I (in-phase) path 120, the first and second digital signals after calibration are:

[0103] I path: D I = A * A comp * cos(Φ + Φ comp ) + DC comp_I

[0104] Q path: D Q = A * sin(Φ) + DCcomp_Q 。

[0105] Alternatively, if the amplitude and phase offset compensation is only applied to the second or Q (quadrature) path 130, the calibrated first and second digital signals will be:

[0106] I path: D I = A * cos(Φ) + DC comp_I

[0107] Q path: D Q = A * A comp * sin(Φ + Φ comp ) + DC comp_Q

[0108] The digital controller 510 can be configured to determine which path (I or Q) the compensation will be applied to. For example, the digital controller 510 can be configured to determine which of the I and Q paths shows the highest gain at the output of the IQ modulator 110 and only select this path for gain compensation. By applying a negative gain adjustment to the path showing the highest gain, saturation of the DAC can be avoided. In Figure 1 the example embodiment shown, this can be implemented by using the path selection control parameters I sel , Q sel which take the value I sel = 1, Q sel = 0 when the I signal component path has the highest gain at the output of the IQ modulator, and take the value I sel = 0, Q sel = 1 when the Q signal component path has the highest gain, and configuring the CORDICs 214, 314 such that the compensated first and second digital signals are:

[0109] D I = A * (I sel * A comp + Q sel ) * cos(Φ + I sel * Φ comp ) + DC comp_I

[0110] D Q = A * (Q sel * A comp + I sel ) * sin(Φ + Q sel * Φ comp ) + DC comp_Q

[0111] The compensation values DC comp_I 、DC comp_Q 、Acomp 、Φ comp can be stored by the first circuit system 120 and / or the second circuit system 130 or by the digital controller 510. For example, the compensation values can be stored in a digital register, a flip-flop, or other memory elements within the device 100.

[0112] Calibration can be repeated before each transmission of the device 100. Whenever calibration is performed, the first digital signal and the second digital signal are re-initialized to default settings, which in this example are D I = A*cos(Φ), D Q = A*sin(Φ). This can be accomplished by setting the compensation parameters to DC comp_I = 0, DC comp_Q = 0, A comp = 1.

[0113] Figure 3 A flowchart showing a method 600 for self-calibrating an IQ modulator according to an exemplary embodiment is shown. Method 600 includes steps 602 to 608. In step 602, a first digital signal (DI, DQ) is generated based on a reference phase value (Φ) and at least one compensation value (A comp , Φ comp , DC comp_I , DC comp_I ), and a second digital signal (DI, DQ) is generated based on the reference phase value (Φ). In step 604, Σ-Δ modulation is applied to each of the first digital signal and the second digital signal (DI, DQ). In step 604, the modulated first digital signal and the modulated second digital signal are respectively converted into a first analog signal and a second analog signal. In step 606, an IQ modulator output signal (RF I ) is generated by the IQ modulator based on a radio frequency input signal (LO), the first analog signal (A Q ) and the second analog signal (A out ). In step 608, at least one compensation value (A out , Φ comp , DC comp , DC comp_I , DC comp_I ) is updated based on the IQ modulator output signal (RF out ).

[0114] In the exemplary embodiment described above, compensation for phase, gain, and / or DC offset is performed digitally. That is, the first digital signal D I and the second digital signal D Q are calculated by CORDIC (or alternatively by a LUT). A higher number of bits greater than the number of bits of the corresponding DACs 230, 330 can be used during calibration to implement the first digital signal DI and a second digital signal D Q to give a high accuracy of compensation.

[0115] In known radar systems, the DAC resolution is mainly determined by the number of DAC bits, which limits the measurement of the variation of the IQ modulator power measured by the power meter 502. The DAC resolution thus introduces an error in the measured output power of the power meter 502, which does not allow optimized compensation of the gain and phase parameters.

[0116] In the present disclosure, this limitation due to the DAC resolution is circumvented by including digital Σ-Δ modulators 226, 326 in front of each respective DAC 230, 330. This increases the effective DAC resolution during calibration, which in turn increases the accuracy with which the phase error can be estimated and thus further compensated. With the better accuracy of error measurement due to the introduction of the Σ-Δ modulators 226, 326, the apparatus 100 according to the present disclosure enables the determination of an optimal compensation. Even during transmission, bypassing the Σ-Δ modulation such that the higher resolution compensation is quantized by the lower resolution DAC, the effect of the more accurate compensation is still an improvement over the compensation that would be determined in the absence of Σ-Δ modulation.

[0117] Based on the simulation of the calibration process in the apparatus 100 described above (repeated for 10,000 different combinations of LO feedthrough values, gain imbalance, phase imbalance, and DAC mismatch / linearity), a maximum phase error of 1 degree or less can be achieved using the apparatus according to the present disclosure. This corresponds to a maximum clutter level of 40 dBc after calibration. Even in the worst case scenario, the phase error is divided by a factor of 2. The simulation also indicates that the performance of a radar system using an 8-bit DAC system without Σ-Δ modulation is equivalent to the performance of a 7-bit DAC system incorporating Σ-Δ modulation as disclosed above. Thus, the present disclosure enables a reduction in the die area of the apparatus without degrading the performance of the apparatus. For example, by reducing the resolution of the DAC from 8 bits to 7 bits and combining it with the introduction of Σ-Δ modulation as disclosed above, the die area will be reduced by a factor of 2.

[0118] Although the above refers to Figure 1The compensation control circuitry 150 of the apparatus 100 of the described example embodiments is based on monitoring and reducing variations in the power of the IQ modulator output signal, but those skilled in the art will appreciate that other compensation techniques may be used while also benefiting from the improvements provided by the Σ-Δ modulation disclosed herein. Nonlinearities in the IQ modulator output signal may be detected by techniques other than monitoring power variations as described above. As an example, the required compensation may be determined by down-converting the output signal, digitizing the down-converted signal, and analyzing the spectral content of the signal by performing a fast Fourier transform on the digitized baseband signal to identify the level of each type of RF impairment by its spectral signature. The compensation values may then be adjusted to optimize the level of each RF impairment.

[0119] Although specific example embodiments of the present disclosure have been described, it should be understood that many modifications, additions, and / or substitutions may be made within the scope of the claims.

Claims

1. A device for self-calibrating a radio frequency transmitter, characterized in that: The device comprises: a first circuit system for receiving a reference phase value and configured to output a first analog signal based on the reference phase value; a second circuit system for receiving the reference phase value and configured to output a second analog signal based on the reference phase value; an IQ modulator coupled to receive an input signal, the first analog signal, and the second analog signal, and configured to provide an IQ modulator output signal based on the input signal, the first analog signal, and the second analog signal; and compensation control circuitry coupled to receive the IQ modulator output signal and configured during calibration to output at least one compensation signal indicative of a compensation value based on the IQ modulator output signal; At least one of the first circuit system and the second circuit system comprises: a digital signal generating section for generating a digital signal based on the reference phase value and at least one of the compensation values, a sigma-delta modulator portion coupled to receive the digital signal and configured during calibration to apply sigma-delta modulation to the digital signal; and A digital-to-analog converter is coupled to receive the modulated digital signal provided by the sigma-delta modulator portion during calibration and is configured to output the respective first / second analog signals.

2. The device according to claim 1, characterized in that The delta-sigma modulator section includes: a sigma-delta modulator configured to apply sigma-delta modulation to a second portion of the digital signal; and A summing node is provided for summing the modulated second portion with the first portion of the digital signal.

3. The device according to claim 1, characterized in that The device can be selectively configured between the following modes: a calibration mode in which the sigma-delta modulator portion is enabled; and transmit mode in which the sigma-delta modulator section is disabled or bypassed.

4. The device according to claim 3, characterized in that When the apparatus operates in the transmit mode, the digital signal generation portion is configured to generate the digital signal based on the reference phase value and the at least one compensation value output by the compensation control circuitry during calibration.

5. The device according to claim 1, characterized in that The apparatus further includes a power amplifier coupled to receive the IQ modulator output signal, the power amplifier configured to amplify the IQ modulator output signal for output to an antenna.

6. The device according to claim 1, characterized in that The compensation control circuitry includes a power meter coupled to receive the IQ modulator output signal and configured to output a power measurement signal indicative of a power of the IQ modulator output signal, and wherein the at least one compensation value is determined by the compensation control circuitry based on the power measurement signal.

7. The device according to claim 1, characterized in that The compensation control circuitry is further configured to determine a signal component path of the IQ modulator having a highest gain from the IQ modulator output signal, and wherein the at least one compensation value comprises an amplitude adjustment of a respective digital signal corresponding to the signal component path having the highest gain.

8. A radio frequency transmitter, characterized in that: The radio frequency transmitter comprises: The device according to claim 1; and A radio frequency transmit antenna is coupled to the output of the IQ modulator.

9. A device for self-calibrating a radio frequency transmitter, characterized in that: The device comprises: a first circuit system for receiving a reference phase value and configured to output a first analog signal based on the reference phase value; a second circuit system for receiving the reference phase value and configured to output a second analog signal based on the reference phase value; an IQ modulator coupled to receive an input signal, the first analog signal, and the second analog signal, and configured to provide an IQ modulator output signal based on the input signal, the first analog signal, and the second analog signal; and compensation control circuitry coupled to receive the IQ modulator output signal and configured during calibration to output at least one compensation signal indicative of a compensation value based on the IQ modulator output signal; At least one of the first circuit system and the second circuit system comprises: a digital signal generating section for generating a digital signal based on the reference phase value and at least one of the compensation values, a sigma-delta modulator portion coupled to receive the digital signal and configured during calibration to apply sigma-delta modulation to the digital signal; and a digital / analog converter coupled to receive a modulated digital signal provided by the sigma-delta modulator portion during calibration and configured to output the respective first / second analog signals; wherein during transmission, the sigma-delta modulator portion is bypassed and the digital signal generation portion is configured to generate the digital signal based on the reference phase value and the at least one compensation value output by the compensation control circuit system during calibration.

10. A method for self-calibrating an IQ modulator, characterized in that: The method comprises: generating a first digital signal and a second digital signal based on a reference phase value and at least one compensation value; applying sigma-delta modulation to each of the first digital signal and the second digital signal; and converting the modulated first digital signal and the modulated second digital signal into a first analog signal and a second analog signal, respectively; generating an IQ modulator output signal at the IQ modulator based on a radio frequency input signal, the first analog signal, and the second analog signal; and The at least one compensation value is determined based on the IQ modulator output signal.

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