Printed circuit board and semiconductor package having same

Abstract

The invention provides a printed circuit board and a semiconductor package having the same. The printed circuit board includes traces disposed on respective upper and lower surfaces of a base layer and disposed on different vertical levels from a lowermost layer to an uppermost layer, and through vias connecting the traces disposed on the different vertical levels to each other and each extending in a vertical direction to pass through at least one of the base layers. The through-vias include a first through-via connecting the traces at the lowermost layer and the uppermost layer to each other and a second through-via connecting the respective traces at an adjacent intermediate layer between the lowermost layer and the uppermost layer to each other. The first through-via passes through an interior of the second through-via in a vertical direction, the first through-via being insulated from the second through-via.

Description

Technical Field

[0001] The present disclosure relates to semiconductors, and more particularly, to printed circuit boards and semiconductor packages including the same. Background Art

[0002] In the recent electronic product market, the demand for mobile or portable devices has increased rapidly. Therefore, there has been a continuous pursuit of miniaturization and weight reduction of electronic components mounted on such electronic products. For this purpose, semiconductor packages mounted on electronic products are designed to have a smaller volume and process high-capacity data. Since such packaged semiconductor chips are mounted on printed circuit boards, the electrical reliability of these chips is important. Equally important is circuit design freedom, which is the concept that engineers designing circuits should be restricted as little as possible so that they can come up with the best possible designs. Summary of the Invention

[0003] A printed circuit board in which K base layers are stacked (where K is an integer of 3 or more), the printed circuit board including K + 1 traces, the K + 1 traces being provided on corresponding upper and lower surfaces of each base layer and being provided at different vertical levels from the lowermost layer to the uppermost layer among the base layers. Through-vias connect the traces provided at different vertical levels to each other, each through-via extending vertically through at least one of the base layers. The through-vias include a first through-via connecting the traces at the lowermost and uppermost layers to each other and a second through-via connecting the corresponding traces at adjacent intermediate layers between the lowermost and uppermost layers to each other, the first through-via passing through the interior of the second through-via in the vertical direction, and the first through-via being insulated from the second through-via.

[0004] A printed circuit board includes a substrate base, a plurality of traces provided on corresponding upper and lower surfaces of each of the plurality of base layers, and a plurality of through-vias each passing through at least one of the plurality of base layers and contacting the plurality of traces, the substrate base including a plurality of base layers. One of the plurality of through-vias has a cylindrical shape, and another of the plurality of through-vias has a hollow cylindrical shape surrounding the cylindrical shape.

[0005] A semiconductor package includes a printed circuit board having a chip mounting region and a peripheral region surrounding the chip mounting region. At least one semiconductor chip has a first surface and a second surface opposite the first surface. The at least one semiconductor chip includes chip pads disposed on the first surface and is mounted in the chip mounting region such that the first surface faces the upper surface of the printed circuit board. Connection bumps are attached to the chip pads. The printed circuit board includes base layers stacked in three or more layers, traces disposed on respective upper and lower surfaces of the base layers and disposed at different vertical levels from the lowermost layer to the uppermost layer. Through-vias connect the traces disposed at different vertical levels to each other, each through-via extending in a vertical direction and passing through at least one of the base layers. The through-vias include first through-vias connecting the traces at the lowermost and uppermost layers to each other and second through-vias connecting the respective traces at adjacent intermediate layers between the lowermost and uppermost layers to each other. The first through-vias pass through the interior of the second through-vias in the vertical direction. Description of the Drawings

[0006] Embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is a schematic perspective view of a main board including a semiconductor package according to an embodiment;

[0008] Figure 2 is a perspective view of a semiconductor package including a printed circuit board according to an embodiment;

[0009] Figure 3 is a cross-sectional view of a printed circuit board according to an embodiment;

[0010] Figure 4 is Figure 3 a top view of region AA of

[0011] Figure 5 is Figure 3 a perspective view of each wiring layer of

[0012] Figure 6 is according to Figure 3 a cross-sectional view of a printed circuit board according to a derivative embodiment of

[0013] Figure 7 is a cross-sectional view of a printed circuit board according to an embodiment;

[0014] Figure 8 is Figure 7 a top view of region BB of

[0015] Figure 9 is Figure 7 a perspective view of each wiring layer of

[0016] Figure 10 is a cross-sectional view of a printed circuit board according to a derivative embodiment of Figure 7 ;

[0017] Figure 11 is a flowchart of a method of manufacturing a printed circuit board device according to an embodiment;

[0018] Figures 12 to 20 is a cross-sectional view showing a method of manufacturing a printed circuit board according to an embodiment;

[0019] Figure 21 is a block diagram of a removable storage device;

[0020] Figure 22 and Figure 23 is a diagram showing an example of defining various form factors of a printed circuit board mounted on a Figure 21 removable storage device; and

[0021] Figure 24 is a top view of a printed circuit board according to an embodiment. DETAILED DESCRIPTION

[0022] Embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings.

[0023] Figure 1 is a schematic perspective view of a main board including a semiconductor package according to an embodiment.

[0024] Referring to Figure 1 , the main board 1100 may include various hardware mounted on its upper surface.

[0025] The various hardware included in the main board 1100 may be mounted in respective dedicated areas. For example, the main board 1100 may include a dedicated area 1000R for the storage device 1000, a dedicated area 1010R for the host 1010, a dedicated area 1020R for the memory 1020, a dedicated area 1030R for the chipset 1030, a dedicated area 1040R for the graphics processing unit 1040, a dedicated area 1050R for the network module 1050, etc. These dedicated areas may be electrically connected to each other through various wires provided on the main board 1100.

[0026] According to some embodiments, the storage device 1000, the host 1010, the memory 1020, the chipset 1030, the graphics processing unit 1040, and / or the network module 1050 may be provided as ball grid array (BGA)-type semiconductor packages 10 (see Figure 2)。For example, the storage device 1000 may include solder balls 1000B as external connection terminals, and the storage device 1000 may be mounted on the main board 1100 such that the ball lands 1000BL provided in the dedicated area 1000R are bonded to the solder balls 1000B. The storage device 1000 may be mounted on the main board 1100 by using surface mounting technology.

[0027] One or more storage devices 1000 may be provided. According to some embodiments, the storage devices 1000 may be mounted on different surfaces of the main board 1100. For example, one storage device 1000 may be mounted on the upper surface of the main board 1100, and another storage device 1000 may be mounted on the bottom surface of the main board 1100.

[0028] The storage device 1000 may send program code to the host 1010 by using a sideband protocol. According to some embodiments, in addition to the communication protocol provided for normal operation, the sideband protocol may further include an additional communication protocol (such as I2C, MCTP, SMBus, etc.). A detailed description of the components included in the storage device 1000 will be described later.

[0029] Figure 2 is a perspective view of a semiconductor package including a printed circuit board according to an embodiment.

[0030] Referring to Figure 2 , the semiconductor package 10 may include a printed circuit board 100 and a semiconductor chip 200 mounted on the printed circuit board 100.

[0031] The printed circuit board 100 may be a package substrate. The printed circuit board 100 may include a substrate base 110, upper connection pads 121 on the upper surface 102 of the printed circuit board 100, and lower connection pads on the lower surface 104 of the printed circuit board 100.

[0032] The substrate base 110 may form the overall appearance of the printed circuit board 100 and may be formed of, for example, phenolic resin, epoxy resin, and / or polyimide. An internal interconnection structure (such as traces and vias) for electrically connecting the upper connection pads 121 to the lower connection pads may be provided inside the substrate base 110. The upper connection pads 121 may be connected to the conductive connection structures on the lower surface of the semiconductor chip 200, and the lower connection pads may be connected to the solder balls 300 as external connection terminals.

[0033] The printed circuit board 100 may include a mounting area 101 on which a semiconductor chip 200 is mounted. The mounting area 101 is an area where the semiconductor chip 200 is disposed, and thus the mounting area 101 and the semiconductor chip 200 may substantially overlap each other in a vertical direction (e.g., the Z direction). Since the mounting area 101 overlaps with the semiconductor chip 200 in the vertical direction (e.g., the Z direction), the mounting area 101 may have the same shape and size as the semiconductor chip 200.

[0034] When a first horizontal direction (e.g., the X direction) is defined as a direction parallel to the first end 200E1 of the semiconductor chip 200 and a second horizontal direction (e.g., the Y direction) is defined as a direction parallel to the second end 200E2 of the semiconductor chip 200, the center point C1 of the mounting area 101 and the center point C2 of the semiconductor chip 200 may coincide with each other on a plane parallel to the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction).

[0035] The width of the semiconductor chip 200 in the first horizontal direction (e.g., the X direction) may be substantially equal to the width of the mounting area 101 in the first horizontal direction (e.g., the X direction), and the width of the semiconductor chip 200 in the second horizontal direction (e.g., the Y direction) may be substantially equal to the width of the mounting area 101 in the second horizontal direction (e.g., the Y direction).

[0036] According to some embodiments, the semiconductor chip 200 may be mounted on the mounting area 101 of the printed circuit board 100 by using a flip-chip method. For example, the semiconductor chip 200 may be connected to an upper connection pad 121 of the printed circuit board 100 through a conductive connection structure (e.g., through solder bumps), but the embodiments are not necessarily limited thereto. According to an embodiment, the semiconductor chip 200 may be mounted on the mounting area 101 of the printed circuit board 100 by using bonding wires.

[0037] The semiconductor chip 200 may be a logic chip or a memory chip. The memory chip may be, for example, a volatile memory semiconductor chip (such as a dynamic random access memory (DRAM) or a static random access memory (SRAM)) or a non-volatile memory semiconductor chip (such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM)). The logic chip may be, for example, a microprocessor, an analog device, a digital signal processor, or an application processor.

[0038] In Figure 2In [the figure], semiconductor package 10 is shown as including a semiconductor chip 200. However, semiconductor package 10 may include a plurality of semiconductor chips 200. According to some embodiments, semiconductor chip 200 may be a chip stack in which a plurality of semiconductor chips 200 are vertically stacked. For example, semiconductor chip 200 may be a high bandwidth memory (HBM).

[0039] On a plane parallel to a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction), a center point C1 of printed circuit board 100 may substantially coincide with a center point C1 of mounting area 101 and / or a center point C2 of semiconductor chip 200. In this case, when one end of printed circuit board 100 adjacent to a first end 200E1 of semiconductor chip 200 is defined as a first end 100E1 of printed circuit board 100 and an end of printed circuit board 100 opposite to first end 100E1 is defined as a second end 100E2 of printed circuit board 100, center point C1 of printed circuit board 100 may be disposed at a substantially same distance from first end 100E1 of printed circuit board 100 and from second end 100E2 of printed circuit board 100.

[0040] Underfill may be interposed between printed circuit board 100 and semiconductor chip 200. For example, underfill filling a space between printed circuit board 100 and semiconductor chip 200 may be formed by an underfill process. Underfill may be filled between printed circuit board 100 and semiconductor chip 200 and may surround a connection bump, which is a conductive connection structure interposed between printed circuit board 100 and semiconductor chip 200.

[0041] Figure 3 is a cross-sectional view of a printed circuit board according to an embodiment, Figure 4 is Figure 3 a top view of region AA of Figure 5 is Figure 3 a perspective view of each wiring layer of Figure 6 is according to Figure 3 a cross-sectional view of a printed circuit board according to a derivative embodiment of

[0042] Referring together to Figures 3 to 5 , printed circuit board 100 may have a substrate base 110, signal lines 120, and ground lines 130 and may include a first wiring layer L1, a second wiring layer L2, a third wiring layer L3, and a fourth wiring layer L4.

[0043] For ease of illustration, only a part of printed circuit board 100 of the inventive concept is shown in the drawings. However, those skilled in the art will be able to fully understand the technical concept of the inventive concept.

[0044] The printed circuit board 100 may include a substrate base 110, where K (where K is an integer equal to or greater than 3) base layers 112, 114, and 116 are stacked from the lowermost layer to the uppermost layer in the vertical direction (e.g., the Z direction). The printed circuit board 100 may also include traces 122 and 132 disposed on each of the base layers 112, 114, and 116, and vias 124 and 134 each extending in the vertical direction (e.g., the Z direction) to pass through at least one of the base layers 112, 114, and 116 to electrically connect the traces 122 and 132 disposed at different vertical levels to each other.

[0045] The substrate base 110 may be formed by stacking three base layers 112, 114, and 116. Four first, second, third, and fourth wiring layers L1, L2, L3, and L4 may be disposed on the corresponding upper and lower surfaces of the three base layers 112, 114, and 116. For ease of illustration, three base layers 112, 114, and 116 and four wiring layers L1, L2, L3, and L4 are shown. However, the number of base layers in the substrate base 110 and the number of wiring layers in the substrate base 110 need not be limited thereto.

[0046] For example, when the substrate base 110 is formed by stacking a first base layer 112, a second base layer 114, and a third base layer 116, the first wiring layer L1, the second wiring layer L2, the third wiring layer L3, and the fourth wiring layer L4 may include a first wiring layer L1 disposed on the upper surface of the first base layer 112, a second wiring layer L2 disposed on the interface between the lower surface of the first base layer 112 and the upper surface of the second base layer 114, a third wiring layer L3 disposed on the interface between the lower surface of the second base layer 114 and the upper surface of the third base layer 116, and a fourth wiring layer L4 disposed on the lower surface of the third base layer 116.

[0047] Multiple traces 122 and 132 disposed in the first wiring layer L1, the second wiring layer L2, the third wiring layer L3, and the fourth wiring layer L4 may be formed on the substrate base 110. According to some embodiments, the multiple traces 122 and 132 may include signal traces 122 and ground traces 132. The multiple traces 122 and 132 may be formed of, for example, copper (Cu), nickel (Ni), and / or beryllium copper.

[0048] According to some embodiments, the signal traces 122 may be disposed on the first wiring layer L1 and the fourth wiring layer L4. The ground traces 132 may be disposed on the second wiring layer L2 and the third wiring layer L3. For example, the signal traces 122 may be disposed on the uppermost surface and the lowermost surface of the substrate base 110, and the ground traces 132 may be disposed inside the substrate base 110.

[0049] According to some embodiments, the signal traces 122 of the first wiring layer L1 and the ground traces 132 of the second wiring layer L2 may overlap each other in a vertical direction (e.g., the Z direction) and may each extend in a first horizontal direction (e.g., the X direction). The signal traces 122 of the fourth wiring layer L4 and the ground traces 132 of the third wiring layer L3 may overlap each other in a vertical direction (e.g., the Z direction) and may each extend in a first horizontal direction (e.g., the X direction). The signal traces 122 of the first wiring layer L1 and the signal traces 122 of the fourth wiring layer L4 may each extend in different horizontal directions (e.g., the +X and -X directions). Accordingly, the ground traces 132 of the second wiring layer L2 and the ground traces 132 of the third wiring layer L3 may each extend in different horizontal directions (e.g., the +X and -X directions).

[0050] A plurality of vias 124 and 134 that electrically connect the traces 122 and 132 disposed in the first wiring layer L1, the second wiring layer L2, the third wiring layer L3, and the fourth wiring layer L4 to each other may be formed in the substrate base 110. According to some embodiments, the plurality of vias 124 and 134 may include signal vias 124 and ground vias 134. The plurality of vias 124 and 134 may be formed of, for example, copper (Cu), nickel (Ni), and / or beryllium copper.

[0051] The plurality of vias 124 and 134 may include signal vias 124 that connect the signal traces 122 of the first wiring layer L1 to the signal traces 122 of the fourth wiring layer L4 and ground vias 134 that connect the ground traces 132 of the second wiring layer L2 to the ground traces 132 of the third wiring layer L3.

[0052] According to some embodiments, the signal vias 124 may be formed in a cylindrical shape that has a first length 124L in a vertical direction (e.g., the Z direction) and a first diameter 124D in a horizontal direction (e.g., the X and Y directions). In contrast, the ground vias 134 may be formed in a hollow cylindrical shape that has a second length 134L less than the first length 124L in a vertical direction (e.g., the Z direction) and a second diameter 134D greater than the first diameter 124D in a horizontal direction (e.g., the X and Y directions). For example, each of the inner diameter and the outer diameter of the ground via 134 may be designed to be greater than the first diameter 124D of the signal via 124.

[0053] According to some embodiments, the signal vias 124 may pass through the interior of the ground vias 134 in a vertical direction (e.g., the Z direction). The signal vias 124 may be insulated from the ground vias 134. For example, the substrate base 110 or an insulating material included within the substrate base 110 (e.g., phenolic resin, epoxy resin, or polyimide) may be disposed between the signal vias 124 and the ground vias 134.

[0054] A solder mask covering at least a portion of the signal traces 122 may be formed on the upper surface of the substrate base 110. A solder mask covering at least a portion of the signal traces 122 may be formed on the lower surface of the substrate base 110. The respective portions of the signal traces 122 that are exposed without being covered by the solder mask may be the signal wirings of the printed circuit board 100. An organic solderability preservative (OSP) may be applied to the upper surfaces of the signal traces 122.

[0055] The semiconductor chip 200 (see Figure 2 ) may be mounted on the upper surface 102 of the printed circuit board 100. For example, the upper surface 102 of the printed circuit board 100 may be a chip mounting surface. Solder balls 300 serving as external connection terminals may be attached to the lower surface 104 of the printed circuit board 100. For example, the lower surface 104 of the printed circuit board 100 may be a connection terminal attachment surface. The semiconductor chip 200 (see Figure 2 ) may be electrically connected to the printed circuit board 100 via connection bumps.

[0056] In the recent electronic product market, the demand for mobile or portable devices has been growing rapidly. Therefore, there is an ongoing requirement for miniaturization and weight reduction of the electronic components installed on such electronic products. For this purpose, semiconductor packages (see Figure 2 ) installed on electronic products are required to have a smaller volume and handle high-capacity data. Since the semiconductor chip 200 (see Figure 2 ) included within this semiconductor package 10 (see Figure 2 ) is mounted on the printed circuit board 100, it is important to increase the electrical reliability and circuit design freedom of the printed circuit board 100 in the semiconductor package 10 (see Figure 2 ).

[0057] In addition, since the circuit needs to be connected from the upper surface 102 to the lower surface 104 of the printed circuit board 100 in a vertical direction (e.g., the Z direction), suitable vias 124 and 134 are required. Since the printed circuit board 100 is composed of a plurality of base layers 112, 114, and 116, a plurality of vias 124 and 134 are formed between the base layers 112, 114, and 116, and the number of vias 124 and 134 is determined according to the integration of the circuit.

[0058] When the via holes 124 and 134 are arranged side by side in different horizontal directions (e.g., X and Y directions) of the printed circuit board 100, due to the increase in the via holes 124 and 134, the placement area is large. This may lead to a reduction in the space safety of the printed circuit board 100 and the degree of freedom regarding circuit design. In addition, when the signal traces 122 and the ground traces 132 extend in different horizontal directions (e.g., +X and -X directions), the shielding effect for the signal traces 122 is reduced, resulting in a reduction in electrical reliability.

[0059] To solve these problems, in the printed circuit board 100, according to the inventive concept, the signal via hole 124 can pass through the inside of the ground via hole 134 in the vertical direction (e.g., Z direction). In this case, even when the number of the via holes 124 and 134 increases, the placement area can be effectively managed, so that the space guarantee of the printed circuit board 100 and the degree of freedom regarding circuit design can be improved.

[0060] In addition, in the printed circuit board 100, according to the inventive concept, the signal traces 122 and the ground traces 132 facing each other are formed to overlap each other in the vertical direction (e.g., Z direction), and are also designed to extend in the same horizontal direction (e.g., in the +X or -X direction). In this case, since the ground traces 132 are provided around the signal traces 122, the shielding effect for the signal traces 122 can be improved, and the electrical reliability can be improved.

[0061] Finally, in the printed circuit board 100, according to the inventive concept, the signal via hole 124 is designed to pass through the inside of the ground via hole 134 in the vertical direction (e.g., Z direction), thereby ensuring electrical reliability and the degree of freedom regarding circuit design.

[0062] Referring to Figure 6 , the printed circuit board 100 may have a substrate base 110, a signal line 120A, and a ground line 130A, and may include a first wiring layer L1, a second wiring layer L2, a third wiring layer L3, and a fourth wiring layer L4.

[0063] In the printed circuit board 100A, according to the inventive concept, a plurality of via holes 124A and 134A that electrically connect the traces 122 and 132 provided in the first wiring layer L1, the second wiring layer L2, the third wiring layer L3, and the fourth wiring layer L4 to each other may be formed in the substrate base 110. According to some embodiments, the plurality of via holes 124A and 134A may include a signal via hole 124A and a ground via hole 134A.

[0064] The plurality of vias 124A and 134A may include signal vias 124A that connect signal traces 122 of a first wiring layer L1 to signal traces 122 of a fourth wiring layer L4, and ground vias 134A that connect ground traces 132 of a second wiring layer L2 to ground traces 132 of a third wiring layer L3.

[0065] In printed circuit board 100A, according to the inventive concept, the signal via 124A may be formed in a hollow cylindrical shape that has a first length in a vertical direction (e.g., the Z direction) and a first diameter in a horizontal direction (e.g., the X and Y directions). In contrast, the ground via 134A may be formed in a hollow cylindrical shape that has a second length less than the first length in a vertical direction (e.g., the Z direction) and a second diameter greater than the first diameter in a horizontal direction (e.g., the X and Y directions). For example, each of the signal via 124A and the ground via 134A may be formed in a hollow cylindrical shape.

[0066] Figure 7 is a cross-sectional view of a printed circuit board according to an embodiment, Figure 8 is Figure 7 a top view of region BB of Figure 9 is Figure 7 a perspective view of each wiring layer of Figure 10 is according to Figure 7 a cross-sectional view of a printed circuit board according to a derivative embodiment of

[0067] Most of the components included within printed circuit boards 100B and 100C (to be described below) and the materials used to form the components are substantially the same as or similar to those described above with reference to Figures 1 to 5 Accordingly, for ease of explanation, the differences between printed circuit boards 100B and 100C and the above-described printed circuit board 100 will be mainly described. In cases where an element is not described in detail in the figure, it can be understood that the element is at least similar to the corresponding element already described elsewhere within the present disclosure.

[0068] Referring together to Figures 7 to 9 , printed circuit board 100B may have a substrate base 110, signal lines 120, and ground lines 130, and may include a first wiring layer L1, a second wiring layer L2, a third wiring layer L3, and a fourth wiring layer L4.

[0069] In printed circuit board 100B, according to the inventive concept, ground traces 132 may be disposed on the first wiring layer L1 and the fourth wiring layer L4. Signal traces 122 may be disposed on the second wiring layer L2 and the third wiring layer L3. For example, ground traces 132 may be disposed on the uppermost surface and the lowermost surface of the substrate base 110, and signal traces 122 may be disposed inside the substrate base 110.

[0070] According to some embodiments, the ground trace 132 of the first wiring layer L1 and the signal trace 122 of the second wiring layer L2 may overlap each other in a vertical direction (e.g., the Z direction) and may each extend in a first horizontal direction (e.g., the X direction). The ground trace 132 of the fourth wiring layer L4 and the signal trace 122 of the third wiring layer L3 may overlap each other in a vertical direction (e.g., the Z direction) and may each extend in a first horizontal direction (e.g., the X direction). The ground traces 132 of the first wiring layer L1 and the fourth wiring layer L4 may each extend in different horizontal directions (e.g., the +X and -X directions). Accordingly, the signal traces 122 of the second wiring layer L2 and the third wiring layer L3 may each extend in different horizontal directions (e.g., the +X and -X directions).

[0071] In printed circuit board 100B, according to the inventive concept, the plurality of vias 124 and 134 may include ground vias 134 connecting the ground trace 132 of the first wiring layer L1 to the ground trace 132 of the fourth wiring layer L4 and signal vias 124 connecting the signal trace 122 of the second wiring layer L2 to the signal trace 122 of the third wiring layer L3.

[0072] According to some embodiments, the ground via 134 may be formed in a cylindrical shape having a second length 134L in a vertical direction (e.g., the Z direction) and a second diameter 134D in a horizontal direction (e.g., the X and Y directions). In contrast, the signal via 124 may be formed in a hollow cylindrical shape having a first length 124L less than the second length 134L in a vertical direction (e.g., the Z direction) and a first diameter 124D greater than the second diameter 134D in a horizontal direction (e.g., the X and Y directions). For example, each of the inner diameter and the outer diameter of the signal via 124 may be designed to be greater than the second diameter 134D of the ground via 134.

[0073] In printed circuit board 100B, according to the inventive concept, a ground via 134 may pass through the interior of a signal via 124 in a vertical direction (e.g., the Z direction). The signal via 124 may be insulated from the ground via 134. For example, a substrate base 110 or an insulating material included in the substrate base 110 (e.g., phenolic resin, epoxy resin, or polyimide) may be disposed between the signal via 124 and the ground via 134.

[0074] Referring Figure 10 , printed circuit board 100C may have a substrate base 110, signal lines 120B, and ground lines 130B, and may include a first wiring layer L1, a second wiring layer L2, a third wiring layer L3, and a fourth wiring layer L4.

[0075] In printed circuit board 100C, according to the inventive concept, a plurality of vias 124B and 134B that electrically connect traces 122 and 132 disposed in the first wiring layer L1, the second wiring layer L2, the third wiring layer L3, and the fourth wiring layer L4 to each other may be formed in the substrate base 110. According to some embodiments, the plurality of vias 124B and 134B may include signal vias 124B and ground vias 134B.

[0076] The plurality of vias 124B and 134B may include a ground via 134B that connects a ground trace 132 of the first wiring layer L1 to a ground trace 132 of the fourth wiring layer L4 and a signal via 124B that connects a signal trace 122 of the second wiring layer L2 to a signal trace 122 of the third wiring layer L3.

[0077] In printed circuit board 100C according to the inventive concept, the ground via 134B may be formed in a hollow cylindrical shape having a second length in a vertical direction (e.g., the Z direction) and a second diameter in a horizontal direction (e.g., the X and Y directions). In contrast, the signal via 124B may be formed in a hollow cylindrical shape having a first length less than the second length in a vertical direction (e.g., the Z direction) and a first diameter greater than the second diameter in a horizontal direction (e.g., the X and Y directions). For example, each of the signal via 124B and the ground via 134B may be formed in a hollow cylindrical shape.

[0078] Figure 11 is a flowchart of a method of manufacturing a printed circuit board device according to an embodiment.

[0079] Referring Figure 11 , a method S100 of manufacturing a printed circuit board device may include a first operation S110 to a ninth operation S190.

[0080] When a certain embodiment can be implemented differently, a specific process order may be executed differently from the described order. For example, two consecutively described processes may be executed substantially simultaneously or in an order opposite to the described order.

[0081] According to the inventive concept, a method S100 of manufacturing a printed circuit board may include a first operation S110 of preparing a base layer including metal thin film layers on its upper and lower surfaces. A second operation S120 of forming initial traces by patterning the metal thin film layers on the upper and lower surfaces of the base layer may be performed. A third operation S130 of forming first vias penetrating through the initial traces and the base layer may be performed. A fourth operation S140 of forming initial through-vias by filling the first vias with metal may be performed. A fifth operation S150 of forming a ground trace and a ground through-via by forming second vias penetrating through the initial through-vias may be performed. A sixth operation S160 of forming a substrate base by forming another substrate base on the upper and lower surfaces of the base layer and forming metal thin film layers on the upper and lower surfaces of the substrate base may be performed. A seventh operation S170 of forming initial traces by patterning the metal thin film layers on the upper and lower surfaces of the substrate base may be performed. An eighth operation S180 of forming third vias penetrating through the initial traces and the substrate base may be performed. A ninth operation S190 of forming signal traces and signal through-vias by filling the third vias with metal may be performed.

[0082] Reference will be made to Figures 12 to 20 describe the respective technical features of the first operation S110 to the ninth operation S190 in detail.

[0083] Figures 12 to 20 is a cross-sectional view showing a method of manufacturing a printed circuit board according to an embodiment.

[0084] Referring to Figure 12 , a second base layer 114 including metal thin film layers 130L on its upper and lower surfaces may be prepared. The second base layer 114 may be formed of at least one material selected from phenolic resin, epoxy resin, and polyimide. The metal thin film layer 130L may be formed of Cu foil, but the embodiment is not limited thereto. For ease of explanation, the second base layer 114 will be described first. However, those skilled in the art will be able to fully understand the technical idea of the inventive concept.

[0085] Referring to Figure 13 , initial traces 132P may be formed by patterning the metal thin film layers 130L on the upper and lower surfaces of the second base layer 114 (see Figure 12 ). By etching the metal thin film layer 130L (see Figure 12 ), the initial traces 132P may be formed into a desired circuit pattern.

[0086] Referring to Figure 14 , a first through-hole TH1 passing through the initial trace 132P and the second base layer 114 can be formed. The first through-hole TH1 can be formed by laser processing or by a drilling process using a CNC drilling machine.

[0087] Referring to Figure 15 , the first through-hole TH1 can be filled with metal to form an initial through-path 134P. The initial through-path 134P can be formed of the same material as the ground trace 132.

[0088] Referring to Figure 16 , a second through-hole TH2 passing through the initial through-path 134P can be formed. The second through-hole TH2 can be formed by laser processing or by a drilling process using a CNC drilling machine. In this way, the ground trace 132 and the ground through-path 134 can be formed.

[0089] Referring to Figure 17 , the second through-hole TH2 can be filled with an insulating material (see Figure 16 ), the first base layer 112 can be formed on the upper surface of the second base layer 114, and the third base layer 116 can be formed on the lower surface of the second base layer 114, thereby forming a substrate base 110. Next, a metal thin film layer 120L can be formed on the upper and lower surfaces of the substrate base 110.

[0090] Referring to Figure 18 , the initial trace 122P can be formed by patterning the metal thin film layer 120L on the upper and lower surfaces of the substrate base 110 (see Figure 17 ). By etching the metal thin film layer 120L (see Figure 17 ), the initial trace 122P can be formed into a desired circuit pattern.

[0091] Referring to Figure 19 , a third through-hole TH3 passing through the initial trace 122P and the substrate base 110 can be formed. The third through-hole TH3 can be formed by laser processing or by a drilling process using a CNC drilling machine.

[0092] Referring to Figure 20 , the third through-hole TH3 can be filled with metal (see Figure 19 ) to form a signal trace 122 and a signal through-path 124. The signal through-path 124 can be formed of the same material as the signal trace 122.

[0093] In the printed circuit board 100, according to the inventive concept (including the above manufacturing process), the signal via 124 is provided to pass through the interior of the ground via 134 in the vertical direction (e.g., the Z direction), thereby ensuring electrical reliability and freedom regarding circuit design.

[0094] Figure 21 is a block diagram of the removable storage device 1200.

[0095] Referring to Figure 21 , the removable storage device 1200 and the host 1300 can communicate with each other, and the removable storage device 1200 can include a semiconductor package 1220, a storage controller 1240, a power supply device 1260, and a first port 1280.

[0096] The semiconductor package 1220 can include a plurality of memory chips, and each memory chip includes a plurality of memory cells. The semiconductor package 1220 is a concept in the case where the memory chips are in chip-level form rather than package form, and does not necessarily refer only to a general type of semiconductor package.

[0097] With the technological development of semiconductor packaging processes, memory chips can be mounted on printed circuit boards 1400A and 1400B (see Figure 22 and Figure 23 ) in chip-level form rather than package form. For example, the entire memory chip can be protected by a housing or the like, or the memory chip can be directly encapsulated on the printed circuit boards 1400A and 1400B (see Figure 22 and Figure 23 ) by using a polymer resin instead of molding compound.

[0098] For example, the memory chip can be a memory chip including a three-dimensional (3D) memory array. The 3D memory cell array can be monolithically formed on a physical level of the memory cells, which has circuits formed on and / or in a silicon wafer as circuits related to the operation of the memory cells, and the active regions are arranged on the silicon wafer. The term "monolithic" can mean that the layers of each level constituting the memory cell array are directly stacked on the underlying layer included in the memory cell array.

[0099] According to some embodiments, the 3D memory array can include vertically structured NAND strings, where at least one memory cell is located above another memory cell and auxiliary cells are arranged above or below the memory cells, and the at least one memory cell can include a charge trapping layer.

[0100] According to an embodiment, the plurality of memory cells may be planar NAND flash memory cells having a two-dimensional (2D) horizontal structure. According to an embodiment, the plurality of memory cells may be non-volatile memory cells such as resistive random access memory (ReRAM) cells, phase change random access memory (PRAM) cells, or magnetic random access memory (MRAM) cells.

[0101] Each memory cell included in the memory cell array may store data of two or more bits. According to some embodiments, the memory cells included in the memory cell array may be multi-level cells (MLCs) that store 2-bit data. According to an embodiment, the memory cells included in the memory cell array may be triple-level cells (TLCs) that store 3-bit data. According to an embodiment, each memory cell included in the memory cell array may store data of four or more bits. The memory cells included in a string of the memory cell array may be used as single-level cells (SLCs) that store 1-bit data.

[0102] The memory chip included in the semiconductor package 1220 may be connected to the memory controller 1240 through a channel group. For example, the semiconductor package-A 1220A may be connected to the memory controller 1240 through the channel group-A CH-A, and the semiconductor package-B 1220B may be connected to the memory controller 1240 through the channel group-B CH-B.

[0103] The drawings show two semiconductor packages 1200A and 1200B and two channel groups CH-A and CH-B, but the embodiments are not necessarily limited thereto. According to the inventive concept, the detachable storage device 1200 may include one semiconductor package and one channel group, or may include three or more semiconductor packages and three or more channel groups.

[0104] The memory controller 1240 may receive a request REQ from the host 1300 through the first port 1280 and may send a response RES to the host 1300 through the first port 1280. For example, the memory controller 1240 may receive a data read request from the host 1300 through the first port 1280, and in response to the received data read request, the memory controller 1240 may read the data stored in the memory chip included in the semiconductor package 1220 and transmit the read data to the host 1300 through the first port 1280.

[0105] The power supply device 1260 may receive power PWR from the host 1300 through the first port 1280 and may supply power to the components included in the detachable storage device 1200 based on the received power PWR, such as supplying power to the semiconductor package 1220 and the memory controller 1240.

[0106] The first port 1280 may include a plurality of pins and may be connected to the second port 1380 of the host 1300. The number, size, and arrangement of the pins may be determined based on the interface protocol through which the first port 1280 and the second port 1380 communicate with the host 1300. For example, the removable storage device 1200 and the host 1300 may communicate with each other through at least one of various interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE), and the first port 1280 may include a plurality of pins according to the interface protocol.

[0107] The removable storage device 1200 may have various form factors to enable mounting of semiconductor packages 1220 having various storage capacities. The removable storage device 1200 may include package substrates such as printed circuit boards 1400A and 1400B (see Figure 22 and Figure 23 ), and the semiconductor package 1220, the storage controller 1240, and the power supply device 1260, which are components of the removable storage device 1200, may be mounted on the printed circuit boards 1400A and 1400B (see Figure 22 and Figure 23 ).

[0108] The printed circuit boards 1400A and 1400B (see Figure 22 and Figure 23 ) may include storage chip mounting areas spaced apart from each other, and depending on the environment or application in which the removable storage device 1200 is used, the storage capacity may be adjusted by mounting the semiconductor package 1220 in all of the storage chip mounting areas or by mounting the semiconductor package 1220 in only one of the storage chip mounting areas, and the removable storage device 1200 may be used flexibly.

[0109] Figure 22 and Figure 23 are diagrams showing examples of various form factors of the printed circuit board that defines the removable storage device 1200 mounted on Figure 21 .

[0110] For example, Figure 22 shows the printed circuit board 1400A in various sizes according to the M.2 standard, Figure 23 shows the printed circuit board 1400B in various sizes according to the PCI card standard.

[0111] Referring to Figure 22 , as an example of a form factor, the M.2 standard may specify the storage device 1200 (seeFigure 21 ) The thickness and the left - right width of the printed circuit board 1400A included therein.

[0112] The M.2 standard can specify the length of the printed circuit board 1400A in the first horizontal direction (e.g., the X - direction) as 60 mm, 80 mm, or 110 mm and the length of the printed circuit board 1400A in the second horizontal direction (e.g., the Y - direction) as 22 mm.

[0113] The M.2 standard can specify the port 1410. The port 1410 can be provided on one side of the printed circuit board 1400A and can include a plurality of pins for communicating with the host 1300 (see Figure 21 ) The plurality of pins can be an exposed pattern, and the exposed pattern can be connected to a socket included in the host 1300 (see Figure 21 ) The plurality of pins can include a conductive material, such as a metal, such as copper.

[0114] The M.2 standard can stipulate a recessed structure 1420 for mounting and fixing the removable storage device 1200 (see Figure 21 ) to the host 1300 (see Figure 21 ) This form factor can include a semi - circular recessed structure 1420 formed on the other side of the printed circuit board 1400A opposite to the port 1410. An exposed pattern can be formed on the edge of the recessed structure 1420 and can be connected to a conductor of the host 1300 when mounted on the host 1300. For example, the pattern formed on the edge of the recessed structure 1420 can correspond to the ground node of the removable storage device 1200 (see Figure 21 ) and can be connected to a conductor corresponding to the ground node of the host 1300 when mounted on the host 1300.

[0115] Referring to Figure 23 , as an example of a form factor, the PCI card standard can specify the length of the printed circuit board 1400B included in the storage device 1200 (see Figure 21 ) in the first horizontal direction (e.g., the X - direction) as 106.68 mm and the length of the printed circuit board 1400B in the second horizontal direction (e.g., the Y - direction) as 174 mm or 312 mm.

[0116] The length in the second horizontal direction (e.g., the Y direction) specified by the PCI card standard defines the maximum length of the printed circuit board 1400B. A length of 174 mm in the second horizontal direction (e.g., the Y direction) can be referred to as a half length, and a length of 312 mm in the second horizontal direction (e.g., the Y direction) can be referred to as a full length. For example, the half-length printed circuit board 1400B can have a length of 106.68 mm in the first horizontal direction (e.g., the X direction) and a length of 174 mm or less in the second horizontal direction (e.g., the Y direction). The ports 1410 at the half length and the full length can have the same position and the same shape.

[0117] According to the storage capacities of various motherboards included in various electronic devices and the number of semiconductor packages installed according to different specifications, the printed circuit boards 1400A and 1400B can be manufactured to have various form factors to accommodate various motherboards.

[0118] Figure 24 is a top view of a printed circuit board 1400 according to an embodiment.

[0119] Referring to Figure 24 , the printed circuit board 1400 is shown to include a plurality of channel patterns that perform write and read operations, namely, a first channel pattern CHP1, a second channel pattern CHP2, a third channel pattern CHP3, and a fourth channel pattern CHP4.

[0120] The printed circuit board 1400 (which is a board on which semiconductor packages are mounted) includes a base layer and a wiring portion. The wiring portion includes traces and vias formed in the base layer.

[0121] According to some embodiments, the semiconductor packages can be electrically connected to the first channel pattern CHP1, the second channel pattern CHP2, the third channel pattern CHP3, and the fourth channel pattern CHP4 in a first mounting area MA1, and the semiconductor packages can be electrically connected to the second channel pattern CHP2 and the third channel pattern CHP3 in a second mounting area MA2.

[0122] The printed circuit board 1400 may further include a power supply device area PA adjacent to the storage controller area CA. However, the arrangement of the power supply device area PA is not necessarily limited to this.

[0123] In an embodiment according to the inventive concept, traces and vias for electrical connection of the first channel pattern CHP1, the second channel pattern CHP2, the third channel pattern CHP3, and the fourth channel pattern CHP4 can be formed. The traces can include the signal traces 122 and the ground traces 132 described above. The vias can include the signal vias 124 and the ground vias 134 described above.

[0124] The printed circuit board 1400 may specify the length 1400X of the printed circuit board 1400 in the first horizontal direction (e.g., the X direction) as 22 mm and specify the length 1400Y of the printed circuit board 1400 in the second horizontal direction (e.g., the Y direction) as 60 mm, 80 mm, or 110 mm. For example, the printed circuit board 1400 may be formed according to the M.2 standard. However, the inventive concept is not necessarily limited thereto.

[0125] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

[0126] Cross - reference to related applications

[0127] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0180097, filed with the Korean Intellectual Property Office on December 12, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A printed circuit board in which K base layers are stacked, wherein K is an integer of 3 or greater, the printed circuit board comprising: K+1 traces disposed on the respective upper and lower surfaces of each of the base layers and disposed at different vertical levels from the lowest one of the base layers to the highest one of the base layers; as well as through vias connecting traces arranged at different vertical levels to each other and each extending in a vertical direction through at least one layer of the base layer, The through passage comprises: a first through via connecting the traces at the lowermost layer and the uppermost layer to each other; as well as a second through via connecting corresponding traces at adjacent intermediate layers between the lowermost layer and the uppermost layer to each other, and The first through via passes through an interior of the second through via in the vertical direction, and the first through via is insulated from the second through via.

2. The printed circuit board according to claim 1, wherein The first through-via includes a signal through-via connecting signal traces to each other, and The second through via includes a ground through via connecting ground traces to each other.

3. The printed circuit board according to claim 2, wherein The signal traces are disposed on the uppermost and lowermost surfaces of the base layer, and The ground trace is disposed at an interface between the base layers.

4. The printed circuit board according to claim 3, wherein The signal trace at the lowermost layer and the ground trace at the middle layer above the lowermost layer overlap each other in the vertical direction and each extend in a first horizontal direction, and The signal trace at the uppermost layer and the ground trace at the intermediate layer below the uppermost layer overlap each other in the vertical direction and each extends in a second horizontal direction different from the first horizontal direction.

5. The printed circuit board according to claim 1, wherein The first through via includes a ground through via connecting ground traces to each other, and The second through via includes a signal through via connecting signal traces to each other.

6. The printed circuit board according to claim 5, wherein The ground traces are disposed on the uppermost and lowermost surfaces of the base layer, and The signal trace is disposed at an interface between the base layers.

7. The printed circuit board according to claim 6, wherein The ground trace at the lowermost layer and the signal trace at the middle layer above the lowermost layer overlap each other in the vertical direction and each extend in a first horizontal direction, and The ground trace at the uppermost layer and the signal trace at the intermediate layer below the uppermost layer overlap each other in the vertical direction and each extends in a second horizontal direction different from the first horizontal direction.

8. The printed circuit board of claim 1, wherein an insulating material included in the base layer is disposed between the first through via and the second through via.

9. The printed circuit board according to claim 8, wherein The first through passage has a cylindrical shape having a first length in the vertical direction and a first diameter in the horizontal direction, and The second through-passage has a hollow cylindrical shape having a second length in the vertical direction that is smaller than the first length and having a second diameter in the horizontal direction that is larger than the first diameter.

10. The printed circuit board according to claim 8, wherein The first through passage has a hollow cylindrical shape having a first length in the vertical direction and a first diameter in the horizontal direction, and The second through-passage has a hollow cylindrical shape having a second length in the vertical direction that is smaller than the first length and having a second diameter in the horizontal direction that is larger than the first diameter.

11. A printed circuit board, comprising: A substrate base, comprising a plurality of base layers; a plurality of traces disposed on respective upper and lower surfaces of each of the plurality of base layers; as well as a plurality of through vias, each passing through at least one layer of the plurality of base layers and contacting the plurality of traces, One of the plurality of through passages has a cylindrical shape, and another of the plurality of through passages has a hollow cylindrical shape surrounding the cylindrical shape.

12. The printed circuit board according to claim 11, wherein The through via having a cylindrical shape includes a signal through via connecting signal traces among the plurality of traces to each other, and The through via having a hollow cylindrical shape includes a ground through via connecting ground traces among the plurality of traces to one another.

13. The printed circuit board according to claim 12, wherein The signal trace and the ground trace facing each other extend in the horizontal direction and overlap in the vertical direction, and The signal through via has a smaller diameter than the ground through via.

14. The printed circuit board according to claim 11, wherein The through via having a cylindrical shape includes a ground through via connecting ground traces among the plurality of traces to each other, and The through via having a hollow cylindrical shape includes a signal through via that connects signal traces among the plurality of traces to each other.

15. The printed circuit board according to claim 14, wherein The signal trace and the ground trace facing each other extend in the horizontal direction and overlap in the vertical direction, and The ground through via has a smaller diameter than the signal through via.

16. A semiconductor package, comprising: a printed circuit board having a chip mounting area and a peripheral area surrounding the chip mounting area; at least one semiconductor chip having a first surface and a second surface opposite to the first surface, including a chip pad disposed on the first surface, and mounted in the chip mounting region such that the first surface faces an upper surface of the printed circuit board; as well as Connecting bumps, attached to the chip pads, The printed circuit board comprises: Base layer, stacked in three or more layers; traces disposed on respective upper and lower surfaces of the base layer and disposed at different vertical levels from a lowermost layer to an uppermost layer; and through vias connecting the traces disposed at different vertical levels to each other and each extending in a vertical direction to pass through at least one layer of the base layer, The through passage comprises: a first through via connecting the traces at the lowermost layer and the uppermost layer to each other; and a second through via connecting corresponding traces at adjacent intermediate layers between the lowermost layer and the uppermost layer to each other, and The first through passage passes through an interior of the second through passage in the vertical direction.

17. The semiconductor package according to claim 16, wherein The first through-via includes a signal through-via connecting signal traces to each other, The second through via includes a ground through via connecting the ground traces to each other, The signal traces are disposed on the uppermost and lowermost surfaces of the base layer, and The ground trace is disposed at an interface between the base layers.

18. The semiconductor package according to claim 16, wherein The first through-via includes a ground through-via connecting ground traces to each other, The second through-via includes a signal through-via connecting the signal traces to each other, The ground traces are disposed on the uppermost and lowermost surfaces of the base layer, and The signal trace is disposed at an interface between the base layers.

19. The semiconductor package according to claim 16, wherein The first through passage has a cylindrical shape having a first length in the vertical direction and a first diameter in the horizontal direction, the second through-passage has a hollow cylindrical shape having a second length in the vertical direction that is smaller than the first length and having a second diameter in the horizontal direction that is larger than the first diameter, and An insulating material included in the base layer is disposed between the first through via and the second through via.

20. The semiconductor package according to claim 16, wherein The traces at the lowermost layer and the traces at the intermediate layer above the lowermost layer overlap each other in the vertical direction and each extend in a first horizontal direction, and The traces at the uppermost layer and the traces at the intermediate layer below the uppermost layer overlap each other in the vertical direction and each extend in a second horizontal direction different from the first horizontal direction.

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