Preparation method of semiconductor structure, memory and electronic equipment

Abstract

The invention relates to a preparation method of a semiconductor structure, a memory and electronic equipment. The preparation method of the semiconductor structure comprises the following steps: etching a first target region of a plurality of first semiconductor layers and a plurality of second semiconductor layers along a direction vertical to a substrate to form an etching groove; etching each first semiconductor layer exposed in the etching groove to respectively form a plurality of bit line accommodating grooves on the left side and the right side of the etching groove; forming a metal sacrificial layer filling the etching groove and the bit line accommodating groove, and performing an annealing process on an obtained structure after the metal sacrificial layer is formed so as to form a bit line contact layer on a contact interface of the first semiconductor layer and the metal sacrificial layer; removing the residual metal sacrificial layer; forming a bit line in the bit line accommodating groove, wherein the bit line is electrically connected with the bit line contact layer; and forming a bit line isolation structure in the etching groove. The yield of the bit lines can be improved, so that the performance of the memory is further improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure, a memory, and an electronic device. Background Art

[0002] With the development of communication technology and digital technology, people continuously pursue products with lower power consumption, lighter weight, and better performance. Three-dimensional dynamic random access memory (3D DRAM) has gradually become one of the important research directions of current memories due to its unique stacked structure, which can have higher integration density and larger storage capacity. However, due to the current difficulties in the preparation of bit lines in 3D DRAM, the yield of bit lines is low, which affects the further improvement of the structure and performance of 3D DRAM. Summary of the Invention

[0003] Based on this, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, a memory, and an electronic device, which is beneficial to improving the yield of bit lines to further enhance the performance of the memory.

[0004] According to some embodiments, on the one hand, the present disclosure provides a method for manufacturing a semiconductor structure, including the following steps:

[0005] Providing a substrate, and alternately forming a plurality of layers of first semiconductor layers and a plurality of layers of second semiconductor layers on the substrate along a direction perpendicular to the substrate;

[0006] Etching a first target region of the plurality of layers of first semiconductor layers and the plurality of layers of second semiconductor layers along a direction perpendicular to the substrate to form an etching groove; the etching groove extends along a first direction parallel to the substrate;

[0007] Etching each of the first semiconductor layers exposed in the etching groove along a second direction parallel to the substrate to respectively form a plurality of bit line accommodating grooves on the left and right sides of the etching groove; the second direction intersects the first direction;

[0008] Forming a metal sacrificial layer to fill the etching groove and the bit line accommodating grooves, and performing an annealing process on the obtained structure after forming the metal sacrificial layer to form a bit line contact layer at the contact interface between the first semiconductor layer and the metal sacrificial layer;

[0009] Removing the remaining metal sacrificial layer;

[0010] Forming a bit line in the bit line accommodating groove, and electrically connecting the bit line to the bit line contact layer;

[0011] Forming a bit line isolation structure in the etching groove.

[0012] According to some embodiments, before removing the remaining metal sacrificial layer, the number of times of performing the annealing process on the obtained structure after forming the metal sacrificial layer is not less than two.

[0013] According to some embodiments, forming bit lines in bit line accommodating grooves includes the following steps:

[0014] Filling the etching grooves and the bit line accommodating grooves with a metal material to form a metal conductive layer;

[0015] Removing the metal conductive layer in the etching grooves so that the metal conductive layers remaining in the bit line accommodating grooves constitute the bit lines.

[0016] According to some embodiments, the materials of the bit lines and the metal sacrificial layer are different, and the resistivity of the bit lines is less than that of the metal sacrificial layer.

[0017] According to some embodiments, the first semiconductor layer includes a silicon layer; the second semiconductor layer includes a silicon-germanium layer; and the bit line contact layer includes a metal silicide layer.

[0018] According to some embodiments, before forming the etching grooves by etching a first target region of the multiple layers of the first semiconductor layer and the multiple layers of the second semiconductor layer in a direction perpendicular to the substrate, the manufacturing method further includes the following steps:

[0019] Patterning the multiple layers of the first semiconductor layer and the multiple layers of the second semiconductor layer to form a main trunk extending in a first direction and a plurality of branch portions located on the left and right sides of the main trunk and extending in a second direction;

[0020] Forming a covering layer covering the main trunk and the branch portions on the substrate;

[0021] Etching a second target region of the covering layer in a direction perpendicular to the substrate to form two etching holes oppositely arranged in the first direction and exposing the corresponding sidewalls of the first semiconductor layer and the second semiconductor layer in the second target region, and making the portion of the first semiconductor layer located between the two etching holes constitute the channel region of the transistor;

[0022] Etching the second semiconductor layer exposed in the etching holes in the first direction to form a word line hole; the word line hole includes: two etching holes and a removed region of the second semiconductor layer between the two etching holes;

[0023] Forming a gate dielectric layer covering the channel region and covering the inner walls of the etching holes in the word line hole;

[0024] Forming a word line covering the gate dielectric layer and filling the word line hole.

[0025] According to some embodiments, after forming the bit line accommodating grooves, the portion of the first semiconductor layer located on the side of the channel region close to the bit line accommodating grooves constitutes the first pole of the transistor, and the portion of the first semiconductor layer located on the side of the channel region away from the bit line accommodating grooves constitutes the second pole of the transistor;

[0026] Wherein, the bit line contact layer is formed at the contact interface between the first pole and the metal sacrificial layer.

[0027] According to some embodiments, before etching a second target region of the cover layer along a direction perpendicular to the substrate to form two etching holes that are oppositely disposed in a first direction and expose corresponding sidewalls of the first semiconductor layer and the second semiconductor layer in the second target region, the manufacturing method further includes the following steps:

[0028] Removing each second semiconductor layer of the branch portion in a third target region, and forming isolation structures on both sidewalls of the removal region of the second semiconductor layer and the branch portion that are oppositely disposed in the first direction; wherein, the third target region is located on a side of the second target region away from the first target region; the branch portion located in the first semiconductor layer on a side of the isolation structure away from the main portion forms a first electrode of the capacitor; the second pole of the transistor is located between the first electrode and the channel region;

[0029] And, after forming the word line, etching and removing each second semiconductor layer of the branch portion located on a side of the isolation structure away from the main portion to expose each first electrode;

[0030] Forming a dielectric layer covering the exposed surface of the first electrode, and a second electrode covering the surface of the dielectric layer away from the first electrode; the capacitor further includes the dielectric layer and the second electrode.

[0031] According to some embodiments, on the other hand, the present disclosure provides a memory, including: a substrate and multiple columns of memory cells and multiple bit line structures disposed on the substrate. Wherein, one bit line structure is correspondingly connected to one column of memory cells. The memory cell includes: a first semiconductor layer. The bit line structure includes: a bit line located at one end of the first semiconductor layer, and a bit line contact layer electrically connected to the bit line.

[0032] According to some embodiments, on the other hand, the present disclosure provides an electronic device, including the memory as described in the above some embodiments.

[0033] The embodiments of the present disclosure can / at least have the following advantages:

[0034] In the embodiments of the present disclosure, the stacked region of the first semiconductor layer and the second semiconductor layer may be etched first. After forming an etching groove extending in the first direction, each of the first semiconductor layers exposed in the etching groove may be etched along the second direction based on the etching groove to form a plurality of bit line accommodating grooves. Then, by depositing a metal sacrificial layer into the etching groove and the bit line accommodating grooves, a bit line contact layer may be formed at the contact interface between the first semiconductor layer and the metal sacrificial layer after annealing. Finally, the remaining metal sacrificial layer may be removed, a bit line electrically connected to the bit line contact layer may be formed in the bit line accommodating groove, and a bit line isolation structure may be formed in the etching groove. Thus, in the embodiments of the present disclosure, the first semiconductor layer and the second semiconductor layer are alternately stacked, and by filling a metal sacrificial layer in the bit line accommodating groove formed by etching the first semiconductor layer and annealing, a bit line contact layer may be directly formed, and the bit line may be self-aligned based on the bit line accommodating groove after removing the residual metal sacrificial layer. Thus, not only can the contact resistance between the first semiconductor layer and the bit line be effectively reduced by using the bit line contact layer, but also the process difficulty of the bit line can be reduced to ensure the bit line yield, thereby improving the memory performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain the drawings of other embodiments without creative efforts.

[0036] Figure 1 It is a flowchart of a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure;

[0037] Figure 2 It is a flowchart of forming a bit line in a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure;

[0038] Figure 3 It is a flowchart of forming a word line in a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure;

[0039] Figure 4 It is a flowchart of forming a first electrode in a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure;

[0040] Figure 5 It is a flowchart of forming a dielectric layer and a second electrode in a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure;

[0041] Figure 6 It is a schematic structural diagram of the structure obtained in step S100 in a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure;

[0042] Figure 7 Schematic diagram of the structure obtained in step S141 of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0043] Figure 8 Schematic diagram of the structure obtained in step S142 of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0044] Figure 9 Schematic diagram of the structure obtained in step S151 of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0045] Figure 10 Schematic diagram of the structure obtained in step S152 of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0046] Figure 11 Schematic diagram of the structure obtained in step S153 of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0047] Figure 12(a) is a schematic diagram of the structure obtained in step S154 of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure; Figure 12(b) is a cross-sectional view of the structure shown in Figure 12(a) taken along section A1; Figure 12(c) is a cross-sectional view of the structure shown in Figure 12(a) taken along section A2;

[0048] Figure 13 Schematic diagram of the structure obtained in step S161 of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0049] Figure 14 Schematic diagram of the structure obtained after forming a dielectric layer in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0050] Figure 15 Schematic diagram of the structure obtained in step S162 of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0051] Figure 16 Schematic diagram of the structure obtained in step S200 of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0052] Figure 17 Schematic diagram of the structure obtained in step S300 of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0053] Figure 18Schematic diagram of the structure obtained after forming a metal sacrificial layer in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0054] Figure 19 Cross-sectional schematic diagram of the structure obtained in step S400 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure on the A2 cross-section;

[0055] Figure 20 Cross-sectional schematic diagram of the structure obtained in step S500 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure on the A2 cross-section;

[0056] Figure 21 Cross-sectional schematic diagram of the structure obtained in step S610 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure on the A2 cross-section;

[0057] Figure 22 Cross-sectional schematic diagram of the structure obtained in step S620 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure on the A2 cross-section;

[0058] Figure 23 Cross-sectional schematic diagram of the structure obtained in step S700 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure on the A2 cross-section.

[0059] Explanation of the reference numerals in the drawings:

[0060] 1 - Substrate, 11 - Second semiconductor layer, 12 - First semiconductor layer; 13 - First sacrificial layer; 14 - Mask layer; 15 - Second sacrificial layer; 111 - Main trunk; 112 - Branch;

[0061] 21 - Cover layer; 22 - Isolation structure; 23 - Bit line isolation structure;

[0062] 31 - Gate dielectric layer; 32 - Dielectric layer;

[0063] 41 - Metal sacrificial layer; 42 - Bit line contact layer; 43 - Metal conductive layer;

[0064] C1 - First electrode; C2 - Second electrode; Q1 - First target area; Q2 - Second target area; Q3 - Third target area; T1 - First pole;

[0065] T2 - Second pole; G1 - Channel region; K1 - Etching hole; K2 - Word line hole; K3 - Etching groove; K4 - Bit line accommodation groove; BL - Bit line, WL - Word line. Detailed implementation manners

[0066] To facilitate an understanding of the present disclosure, the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Embodiments of the present disclosure are shown in the drawings. However, the present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete.

[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein in the description of the present disclosure are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure.

[0068] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0069] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over" and the like may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" or "underneath" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0070] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "comprises / comprising" or "has / having" or the like specifies the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0071] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown are to be expected, for example, due to manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be limited to the particular shapes of regions shown herein, but include shape deviations resulting from, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0072] Due to its unique stacked structure, three-dimensional dynamic random access memory has become an important direction in the development of memory. However, it is still difficult to deposit multiple layers of bit line materials in a smaller bit line accommodation hole, and the cost of depositing bit line materials multiple times is high. Therefore, there are still difficulties in preparing the bit lines of three-dimensional dynamic random access memory, and the yield of the bit lines is low.

[0073] Please refer to Figure 1 , some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including steps S100 to S700.

[0074] S100: Provide a substrate, and alternately form multiple layers of a first semiconductor layer and multiple layers of a second semiconductor layer on the substrate along a direction perpendicular to the substrate.

[0075] S200: Etch a first target region of the multiple layers of the first semiconductor layer and the multiple layers of the second semiconductor layer along a direction perpendicular to the substrate to form an etch groove; the etch groove extends along a first direction parallel to the substrate.

[0076] S300: Etch each of the first semiconductor layers exposed in the etch groove along a second direction parallel to the substrate to form a plurality of bit line accommodation grooves on both left and right sides of the etch groove; the second direction intersects the first direction.

[0077] S400: Form a metal sacrificial layer to fill the etch groove and the bit line accommodation grooves, and perform an annealing process on the obtained structure after forming the metal sacrificial layer to form a bit line contact layer at the contact interface between the first semiconductor layer and the metal sacrificial layer.

[0078] S500: Remove the remaining metal sacrificial layer.

[0079] S600: Form bit lines in the bit line accommodation grooves, and the bit lines are electrically connected to the bit line contact layer;

[0080] S700: Form a bit line isolation structure in the etch groove.

[0081] In the embodiments of the present disclosure, the stacked region of the first semiconductor layer and the second semiconductor layer is etched first. After forming an etching groove extending in the first direction, each first semiconductor layer exposed in the etching groove can be etched along the second direction based on the etching groove to form a plurality of bit line accommodating grooves. Then, by depositing a metal sacrificial layer into the etching groove and the bit line accommodating grooves, a bit line contact layer can be formed at the contact interface between the first semiconductor layer and the metal sacrificial layer after annealing. Finally, the remaining metal sacrificial layer is removed, a bit line electrically connected to the bit line contact layer can be formed in the bit line accommodating groove, and a bit line isolation structure can be formed in the etching groove. Thus, the embodiments of the present disclosure adopt the alternating stacking of the first semiconductor layer and the second semiconductor layer, and by using the method of filling a metal sacrificial layer and annealing in the bit line accommodating groove formed by etching the first semiconductor layer, a bit line contact layer can be directly formed, and the bit line can be self-aligned based on the bit line accommodating groove after removing the residual metal sacrificial layer. In this way, not only can the contact resistance between the first semiconductor layer and the bit line be effectively reduced by using the bit line contact layer, but also the process difficulty of the bit line can be reduced to ensure the bit line yield, thereby improving the memory performance.

[0082] In some embodiments, before step S500 of removing the remaining metal sacrificial layer, in step S400, the number of times of performing the annealing process on the structure obtained after forming the metal sacrificial layer is not less than two. In this embodiment, performing the annealing process on the structure obtained after forming the metal sacrificial layer not less than two times can achieve the effect of reducing the resistance.

[0083] In some embodiments, please refer to Figure 2 , step S600 of forming a bit line in the bit line accommodating groove includes steps S610 to S620.

[0084] S610: Fill the etching groove and each bit line accommodating groove with a metal material to form a metal conductive layer.

[0085] S620: Remove the metal conductive layer in the etching groove so that the metal conductive layer remaining in each bit line accommodating groove constitutes a bit line.

[0086] In some embodiments, the materials of the bit line and the metal sacrificial layer are different, and the resistivity of the bit line is less than the resistivity of the metal sacrificial layer.

[0087] In some embodiments, the first semiconductor layer includes a silicon layer. The second semiconductor layer includes a silicon germanium layer. The bit line contact layer includes a metal silicide layer.

[0088] It should be noted that in the above embodiments, there is no strict order restriction for the execution of each step in the method. These steps may not necessarily be executed in the described order and may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily need to be completed at the same moment but can be executed at different moments, and the execution order of these sub-steps or stages is not necessarily sequential but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps. The method is limited to being able to realize the preparation of the corresponding memory.

[0089] Based on this, for the manufacturing methods provided in some of the above embodiments, some embodiments of the present disclosure illustrate some methods as some possible implementation manners of the above manufacturing methods.

[0090] In some embodiments, please refer to Figure 3 , before step S200 etches the first target region of the multiple layers of the first semiconductor layer and the multiple layers of the second semiconductor layer in the direction perpendicular to the substrate to form an etching groove, the method for preparing the semiconductor structure further includes steps S151 to S156.

[0091] S151: Pattern the multiple layers of the first semiconductor layer and the multiple layers of the second semiconductor layer to form a main trunk extending in the first direction and a plurality of branch portions located on the left and right sides of the main trunk and extending in the second direction.

[0092] S152: Form a covering layer covering the main trunk and the branch portions on the substrate.

[0093] S153: Etch the second target region of the covering layer in the direction perpendicular to the substrate to form two etching holes oppositely arranged in the first direction and exposing the corresponding sidewalls of the first semiconductor layer and the second semiconductor layer in the second target region, and make the portion of the first semiconductor layer located between the two etching holes constitute the channel region of the transistor.

[0094] S154: Etch the second semiconductor layer exposed in the etching holes in the first direction to form a word line hole; the word line hole includes: two etching holes and a removed region of the second semiconductor layer between the two etching holes.

[0095] S155: Form a gate dielectric layer covering the channel region and covering the inner walls of the etching holes in the word line hole.

[0096] S156: Form a word line covering the gate dielectric layer and filling the word line hole.

[0097] In some embodiments, after the bit line receiving grooves are formed in step S300, the portion of the first semiconductor layer on the side of the channel region close to the bit line receiving grooves constitutes the first pole of the transistor, and the portion of the first semiconductor layer on the side of the channel region away from the bit line receiving grooves constitutes the second pole of the transistor. Among them, the bit line contact layer is formed at the contact interface between the first pole and the metal sacrificial layer.

[0098] In some embodiments, before forming the covering layer covering the main portion and the branch portion on the substrate in step S152, the method for manufacturing the semiconductor structure further includes:

[0099] Removing each second semiconductor layer of the branch portion in the third target region, and forming isolation structures on the removal region of the second semiconductor layer and on the two sidewalls of the branch portion opposite to each other in the first direction. Among them, the third target region is located on the side of the second target region away from the first target region. The first semiconductor layer of the branch portion located on the side away from the main portion of the isolation structure constitutes the first electrode of the capacitor. The second pole of the transistor is located between the first electrode and the channel region.

[0100] And, please refer to Figure 4 , after forming the word line in step S156, the method for manufacturing the semiconductor structure further includes steps S161 to S162.

[0101] S161: Etch and remove each second semiconductor layer of the branch portion located on the side away from the main portion of the isolation structure to expose each first electrode.

[0102] S162: Form a dielectric layer covering the exposed surface of the first electrode, and a second electrode covering the surface of the dielectric layer away from the first electrode. The capacitor further includes the dielectric layer and the second electrode.

[0103] To more clearly illustrate the method for manufacturing the semiconductor structure provided in the above embodiments, the following combines Figures 6 to 23 to detail this manufacturing method.

[0104] In step S100, please refer to Figure 5 , provide a substrate 1, and alternately form a plurality of layers of second semiconductor layers 11 and a plurality of layers of first semiconductor layers 12 on the substrate 1 along a direction perpendicular to the substrate 1.

[0105] Exemplarily, the substrate 1 can be composed of semiconductor materials, insulating materials, conductive materials, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a substrate such as a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including a stack such as Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator, etc.

[0106] In some examples, the second semiconductor layer 11 includes a silicon-germanium layer.

[0107] In some examples, the first semiconductor layer 12 includes a silicon layer. Thus, the structure in which the second semiconductor layer 11 and the first semiconductor layer 12 are alternately stacked can effectively adjust the stress problem between the multi-layer structures, thereby further improving the memory performance.

[0108] Here, the number of stacked layers of the second semiconductor layer 11 can be set according to the number of stacked layers of the storage layer in the memory. And, the first semiconductor layer 12 is located between adjacent second semiconductor layers 11, and the number of layers of the first semiconductor layer 12 can be set to match the number of stacked layers of the second semiconductor layer 11. Each second semiconductor layer 11 and each first semiconductor layer 12 can be formed by a deposition process respectively.

[0109] In addition, after forming the multi-layer second semiconductor layer 11 and the multi-layer first semiconductor layer 12 that are alternately stacked, a mask structure can be formed on the upper surface of the top first semiconductor layer 12. For example, the mask structure includes a first sacrificial layer 13, a mask layer 14, and a second sacrificial layer 15 that are sequentially stacked on the upper surface of the top second semiconductor layer 11.

[0110] Exemplarily, the materials of the first sacrificial layer 13 and the second sacrificial layer 15 include silicon dioxide.

[0111] Exemplarily, the material of the mask layer 14 includes polysilicon.

[0112] In step S151, please refer to Figure 6 , pattern the multi-layer second semiconductor layer 11 and the multi-layer first semiconductor layer 12 to form a main trunk portion 111 extending in the first direction (e.g., the X direction), and branch portions 112 located on the left and right sides of the main trunk portion 111 and extending in the second direction (e.g., the Y direction).

[0113] In some examples, before patterning the multi-layer second semiconductor layer 11 and the multi-layer first semiconductor layer 12, the method for preparing the semiconductor structure further includes: patterning a mask structure. Correspondingly, in some examples, patterning the multi-layer second semiconductor layer 11 and the multi-layer first semiconductor layer 12 includes: etching the multi-layer second semiconductor layer 11 and the multi-layer first semiconductor layer 12 based on the patterned mask structure.

[0114] In step S152, refer to Figures 6 to 8 , a covering layer 21 covering the main portion 111 and the branch portion 112 is formed on the substrate 1.

[0115] In some examples, before forming the covering layer 21, it further includes: refer to Figure 6 and Figure 7 , remove each second semiconductor layer 11 of the branch portion 112 in the third target region Q3, and form isolation structures 22 on the removal region of the second semiconductor layer 11 and on the opposite sidewalls of the branch portion 112 in the first direction (e.g., the X direction). Among them, the first semiconductor layer 12 of the branch portion 112 located on the side of the isolation structure 22 away from the main portion 111 constitutes the first electrode C1 of the capacitor.

[0116] Exemplarily, the material of the isolation structure 22 includes a non-metallic nitride. For example: the material of the isolation structure 22 is silicon nitride.

[0117] In some examples, refer to Figure 7 , after forming the isolation structure 22, the method for preparing the semiconductor structure further includes: removing the first sacrificial layer 13 and the second sacrificial layer 15.

[0118] Exemplarily, the first sacrificial layer 13 and the second sacrificial layer 15 can be removed by a wet etching process.

[0119] In some examples, refer to Figure 8 , the covering layer 21 can be formed by a deposition process.

[0120] In some examples, the material of the covering layer 21 includes a non-metallic oxide. For example: the material of the covering layer 21 is silicon dioxide.

[0121] In step S153, refer to Figure 9 , etch the second target region Q2 of the covering layer 21 along the direction perpendicular to the substrate 1, so as to form two etching holes K1 that are oppositely arranged in the first direction (e.g., the X direction) and expose the corresponding sidewalls of the first semiconductor layer 12 and the second semiconductor layer 11 in the second target region Q2, and make the portion of the first semiconductor layer 12 located between the two etching holes K1 constitute the channel region G1 of the transistor. To form a junctionless transistor.

[0122] In some examples, a dry etching process may be employed to form the etching hole K1.

[0123] In step S154, refer to Figure 10 , etch the second semiconductor layer 11 exposed within the etching hole K1 along the first direction (e.g., the X direction) to form the word line hole K2. The word line hole K2 includes: two etching holes K1 and the removal region of the second semiconductor layer 11 between the two etching holes K1.

[0124] In some examples, a wet etching process may be used to remove the second semiconductor layer 11 exposed within the etching hole K1.

[0125] In step S155, refer to Figure 11 , Figures 12(b) and 12(c), form a gate dielectric layer 31 within the word line hole K2 that coats the channel region G1 and covers the inner wall of the etching hole K1.

[0126] In some examples, the gate dielectric layer 31 may also cover the isolation structure 22 and the surface of the cover layer 21 facing away from the substrate 1. Correspondingly, in some embodiments, after forming the word line WL, it further includes: removing the gate dielectric layer 31 on the surface of the isolation structure 22 and the cover layer 21 facing away from the substrate 1.

[0127] In some examples, a deposition process may be employed to form the gate dielectric layer 31.

[0128] In some examples, the material of the gate dielectric layer 31 includes metal oxides. For example: the material of the gate dielectric layer 31 is hafnium dioxide (HfO 2 ).

[0129] In step S156, refer to Figures 12(a) to 12(c) , form a word line WL that covers the gate dielectric layer 31 and fills the word line hole K2.

[0130] In some examples, a deposition process may be employed to form the word line WL.

[0131] In some examples, the material of the word line WL includes metal nitrides. For example: the material of the word line WL is titanium nitride.

[0132] In step S161, refer to Figure 13 , etch and remove each second semiconductor layer 11 of the branch portion 112 located on the side of the isolation structure 22 facing away from the main trunk portion 111 to expose each first electrode C1.

[0133] In step S162, refer to Figure 14 and Figure 15 , form a dielectric layer 32 that coats the exposed surface of the first electrode C1, and a second electrode C2 that covers the surface of the dielectric layer 32 facing away from the first electrode C1. The capacitor further includes the dielectric layer 32 and the second electrode C2.

[0134] In some examples, refer to Figure 15 , after forming a dielectric layer 32 covering the exposed surface of the first electrode C1 and a second electrode C2, the method for manufacturing a semiconductor structure further includes: removing the hard mask layer 14.

[0135] In some examples, a deposition process may be used to form a dielectric layer 32 covering the exposed surface of the first electrode C1, and a second electrode C2 covering the surface of the dielectric layer 32 facing away from the first electrode C1.

[0136] In some examples, the material of the dielectric layer 32 includes a metal oxide. For example: the material of the dielectric layer 32 is hafnium dioxide (HfO 2 ).

[0137] In some examples, the material of the second electrode C2 includes polysilicon.

[0138] In step S200, refer to Figure 16 , etch a first target area Q1 of the multi-layer first semiconductor layer 12 and the multi-layer second semiconductor layer 11 along a direction perpendicular to the substrate 1 to form an etch groove K3; the etch groove K3 extends along a first direction (for example, the X direction) parallel to the substrate 1. The third target area Q3 is located on a side of the second target area Q2 away from the first target area Q1.

[0139] In some examples, a dry etching process may be used to form the etch groove K3.

[0140] In step S300, refer to Figure 17 , etch each first semiconductor layer 12 exposed in the etch groove K3 along a second direction (for example, the Y direction) parallel to the substrate 1 to respectively form a plurality of bit line receiving grooves K4 on the left and right sides of the etch groove K3.

[0141] In some examples, before etching to form a plurality of bit line receiving grooves K4, it further includes: removing the second semiconductor layer 11 on the left and right sides of the etch groove K3, and filling an isolation material in the removed area of the second semiconductor layer 11.

[0142] Exemplarily, a wet etching process may be used to remove the second semiconductor layer 11.

[0143] Exemplarily, the isolation material includes silicon dioxide.

[0144] In some examples, a wet etching process may be used to remove each first semiconductor layer 12 exposed in the etch groove K3.

[0145] In step S400, refer to Figure 18 , form a metal sacrificial layer 41 filling the etch groove K3 and the bit line receiving grooves K4. Refer to Figure 19, and an annealing process is performed on the resulting structure after forming the metal sacrificial layer 41 to form a bit line contact layer 42 at the contact interface between the first semiconductor layer 12 and the metal sacrificial layer 41.

[0146] In this embodiment, forming the bit line contact layer 42 at the contact interface between the first semiconductor layer 12 and the metal sacrificial layer 41 can reduce the resistance between the first semiconductor layer 12 and the metal sacrificial layer 41.

[0147] In some examples, the portion of the first semiconductor layer 12 located on the side of the channel region G1 close to the bit line receiving groove K4 constitutes the first pole T1 of the transistor, and the portion of the first semiconductor layer 12 located on the side of the channel region G1 away from the bit line receiving groove K4 constitutes the second pole T2 of the transistor, that is, the second pole T2 of the transistor is located between the first electrode C1 and the channel region G1. Here, the transistor is a junctionless surrounding gate transistor.

[0148] In some embodiments, the number of times of performing the annealing process on the resulting structure after forming the metal sacrificial layer 41 is not less than two.

[0149] In this embodiment, performing the annealing process on the resulting structure after forming the metal sacrificial layer 41 not less than two times can achieve the effect of reducing resistance.

[0150] In some examples, the bit line contact layer 42 is formed at the contact interface between the first pole and the metal sacrificial layer 41.

[0151] In some examples, the metal sacrificial layer 41 can be formed by a deposition process.

[0152] In some examples, the material of the metal sacrificial layer 41 includes a metal. For example, the material of the metal sacrificial layer 41 is tungsten.

[0153] In some examples, the bit line contact layer 42 includes a metal silicide layer.

[0154] In step S500, please refer to Figure 20 , and the remaining metal sacrificial layer 41 is removed.

[0155] In this embodiment, since an annealing process is performed on the resulting structure after forming the metal sacrificial layer 41, the bit line contact layer 42 is formed at the contact interface between the first semiconductor layer 12 and the metal sacrificial layer 41. And the metal sacrificial layer 41 still remains on the surfaces of other structural layers. Thus, removing the metal sacrificial layer 41 can avoid the short-circuit problem caused by the coverage of the metal on the surfaces of other structural layers. In addition, after removing the remaining metal sacrificial layer 41, a metal with a smaller resistance can be filled subsequently to improve the performance.

[0156] In some examples, the metal sacrificial layer 41 can be removed by a wet etching process.

[0157] In step 610, refer to Figure 21 , fill the etching groove K3 and each bit line accommodating groove K4 with a metal material to form a metal conductive layer 43.

[0158] In some examples, the metal conductive layer 43 can be formed by a deposition process.

[0159] In some examples, the material of the metal conductive layer 43 includes a metal. For example, the material of the metal conductive layer 43 is tungsten.

[0160] In step S620, refer to Figure 22 , remove the metal conductive layer 43 in the etching groove K3 so that the metal conductive layer 43 remaining in each bit line accommodating groove K4 constitutes a bit line BL.

[0161] In some examples, the material of the bit line BL includes a metal. For example, the material of the bit line BL is tungsten.

[0162] In some examples, the metal conductive layer 43 in the etching groove K3 can be removed by a dry etching process.

[0163] In step S700, refer to Figure 23 , form a bit line isolation structure 23 in the etching groove K3.

[0164] In some examples, the bit line isolation structure 23 can be formed by a deposition process.

[0165] In some examples, the material of the bit line isolation structure 23 includes a non-metal oxide. For example, the material of the bit line isolation structure 23 is silicon dioxide.

[0166] Some embodiments of the present disclosure also provide a memory. The memory has the technical effects that the preparation method of the semiconductor structure in the foregoing embodiments can have, which will not be elaborated herein. Refer to Figure 23 , the memory includes: a substrate 1 and multiple columns of memory cells and multiple bit line structures disposed on the substrate 1. Among them, one bit line structure is correspondingly connected to one column of memory cells. The memory cell includes: a first semiconductor layer. The bit line structure includes: a bit line BL located at one end of the first semiconductor layer 12, and a bit line contact layer 42 electrically connected to the bit line BL.

[0167] In this embodiment, the bit line contact layer 42 can reduce the resistance between the first semiconductor layer 12 and the bit line BL.

[0168] In some examples, the first semiconductor layer 12 includes a silicon layer.

[0169] In some examples, the bit line contact layer 42 includes a metal silicide layer.

[0170] Exemplarily, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductive material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including a stack of, for example, Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0171] In some examples, the material of the bit line BL includes a metal. For example, the material of the bit line BL is tungsten.

[0172] In some examples, the memory cell further includes: a transistor and a capacitor. The specific settings of the transistor and the capacitor can refer to the relevant embodiments in the preparation method of the foregoing semiconductor mechanism. Among them, the portions of the first semiconductor layer 12 located in corresponding different regions can be respectively used as the first pole T1, the channel region G1, and the second pole T2 of the transistor, and the first electrode C1 of the capacitor, etc. Exemplarily, the bit line contact layer 42 is located between the first pole T1 and the bit line BL.

[0173] In some examples, the memory further includes: a gate dielectric layer 31 and a plurality of word lines WL. The gate dielectric layer 31 covers the channel region G1, and the word line WL is disposed on the surface of the gate dielectric layer 31 facing away from the channel region G1. The specific settings of the gate dielectric layer 31 and the word line WL can refer to the relevant embodiments in the preparation method of the foregoing semiconductor mechanism.

[0174] In some examples, the material of the gate dielectric layer 31 includes a metal oxide. For example, the material of the gate dielectric layer 31 is hafnium dioxide (HfO 2 )

[0175] In some examples, the material of the word line WL includes a metal nitride. For example, the material of the word line WL is titanium nitride.

[0176] Some embodiments of the present disclosure also provide an electronic device, including the memory as described in some of the foregoing embodiments. The technical effects that the memory in the foregoing embodiments can have are also possessed by this electronic device, which will not be elaborated here. For example, data storage devices, photocopiers, network devices, household appliances, instruments, mobile phones, computers, and other devices with data storage functions. The electronic device can include a housing, a circuit board disposed in the housing, and a memory integrated on the circuit board. The structure of the memory can refer to the relevant descriptions in some of the foregoing embodiments. Other necessary elements or components may also be included in the electronic device, which are not limited in the embodiments of the present disclosure.

[0177] In some embodiments, an external control device such as a processor or an actuator coupled to the memory may also be integrated on the circuit board. For example, the electronic device further includes a processor integrated on the circuit board. The processor is coupled to the memory, and the processor is capable of controlling the read and write operations of the memory.

[0178] In some embodiments, the memory is a three-dimensional dynamic random access memory.

[0179] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0180] The above-described embodiments merely represent several implementation manners of the present disclosure. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, comprising: providing a substrate, and alternately forming a plurality of first semiconductor layers and a plurality of second semiconductor layers on the substrate along a direction perpendicular to the substrate; etching a first target area of the plurality of first semiconductor layers and the plurality of second semiconductor layers along a direction perpendicular to the substrate to form an etching groove; the etching groove extends along a first direction parallel to the substrate; etching each of the first semiconductor layers exposed in the etching groove along a second direction parallel to the substrate, so as to respectively form a plurality of bit line accommodation grooves on the left and right sides of the etching groove; the second direction intersects with the first direction; forming a metal sacrificial layer filling the etching groove and the bit line accommodation grooves, and performing an annealing process on the obtained structure after forming the metal sacrificial layer, so as to form a bit line contact layer at a contact interface between the first semiconductor layer and the metal sacrificial layer; removing the remaining metal sacrificial layer; forming a bit line in the bit line accommodation groove, and the bit line is electrically connected to the bit line contact layer; forming a bit line isolation structure in the etching groove.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, before removing the remaining metal sacrificial layer, the number of times of performing the annealing process on the obtained structure after forming the metal sacrificial layer is not less than two.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, the forming a bit line in the bit line accommodation groove includes: filling a metal material in the etching groove and each of the bit line accommodation grooves to form a metal conductive layer; removing the metal conductive layer in the etching groove, so that the metal conductive layer remaining in each of the bit line accommodation grooves constitutes the bit line.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, the materials of the bit line and the metal sacrificial layer are different, and the resistivity of the bit line is less than the resistivity of the metal sacrificial layer.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, the first semiconductor layer includes a silicon layer; the second semiconductor layer includes a silicon germanium layer; the bit line contact layer includes a metal silicide layer.

6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, characterized in that, before etching the first target area of the plurality of first semiconductor layers and the plurality of second semiconductor layers along a direction perpendicular to the substrate to form an etching groove, the manufacturing method further includes: patterning the plurality of first semiconductor layers and the plurality of second semiconductor layers to form a main portion extending along the first direction, and a plurality of branch portions located on the left and right sides of the main portion and extending along the second direction; forming a covering layer on the substrate to cover the main portion and the branch portions; etching a second target area of the covering layer along a direction perpendicular to the substrate, so as to form two etching holes oppositely arranged in the first direction and exposing corresponding side walls of the first semiconductor layer and the second semiconductor layer in the second target area, and making a portion of the first semiconductor layer located between the two etching holes constitute a channel region of a transistor; Etch the second semiconductor layer exposed in the etching hole along the first direction to form a word line hole; the word line hole includes: two of the etching holes and a removal area of the second semiconductor layer between the two etching holes; Form a gate dielectric layer in the word line hole to coat the channel region and cover the inner wall of the etching hole; Form a word line that covers the gate dielectric layer and fills the word line hole.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein, After forming the bit line accommodating groove, a portion of the first semiconductor layer on the side of the channel region close to the bit line accommodating groove constitutes the first pole of the transistor, and a portion of the first semiconductor layer on the side of the channel region away from the bit line accommodating groove constitutes the second pole of the transistor; Wherein, a bit line contact layer is formed at the contact interface between the first pole and the metal sacrificial layer.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein, Before forming the covering layer covering the main part and the branch part on the substrate, the manufacturing method further includes: Removing each second semiconductor layer of the branch part in the third target area, and forming an isolation structure in the removal area of the second semiconductor layer and on the two side walls of the branch part opposite to each other in the first direction; wherein, the third target area is located on the side of the second target area away from the first target area; a portion of the first semiconductor layer of the branch part located on the side of the isolation structure away from the main part constitutes the first electrode of the capacitor; the second pole of the transistor is located between the first electrode and the channel region; And, after forming the word line, etching and removing each second semiconductor layer of the branch part located on the side of the isolation structure away from the main part to expose each first electrode; Form a dielectric layer covering the exposed surface of the first electrode, and a second electrode covering the surface of the dielectric layer away from the first electrode; the capacitor further includes the dielectric layer and the second electrode.

9. A memory, wherein, comprising: A substrate and multiple columns of memory cells and multiple bit line structures disposed on the substrate; wherein, one of the bit line structures is correspondingly connected to one column of the memory cells; The memory cell includes: a first semiconductor layer; The bit line structure includes: a bit line at one end of the first semiconductor layer, and a bit line contact layer electrically connected to the bit line.

10. An electronic device, wherein, comprises the memory according to claim 9.

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