Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a memory system and a manufacturing method of the semiconductor device. The semiconductor device includes: a bit line structure extending in a first direction; the shielding structures extend in the first direction, and the shielding structures and the bit line structures are alternately arranged in the second direction; the isolation layer is positioned between the bit line structure and the shielding structure; wherein the size of the bit line structure in the third direction is larger than that of the shielding structure in the third direction, and the first direction, the second direction and the third direction intersect with one another.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Art

[0002] In order to improve the integration of semiconductor devices, the feature size of semiconductor devices has been continuously reduced. However, as the feature size decreases, the coupling effect between adjacent components intensifies, affecting the electrical performance of semiconductor devices. Summary of the Invention

[0003] The present application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above problems or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes: a bit line structure extending in a first direction; a shielding structure extending in the first direction and alternately arranged with the bit line structure in a second direction; and an isolation layer located between the bit line structure and the shielding structure; wherein, the size of the bit line structure in a third direction is larger than the size of the shielding structure in the third direction, and the first direction, the second direction, and the third direction intersect with each other.

[0005] In an exemplary embodiment, the semiconductor device further includes: a semiconductor pillar located on one side of the bit line structure in the third direction; wherein, the bit line structure includes: a first bit line portion and a second bit line portion stacked in the third direction, and the second bit line portion is located on the side of the first bit line portion away from the semiconductor pillar.

[0006] In an exemplary embodiment, in the third direction, the distance between the surface of the second bit line portion away from the semiconductor pillar and the surface of the shielding structure close to the semiconductor pillar is greater than the size of the shielding structure.

[0007] In an exemplary embodiment, the first bit line portion is in contact with the semiconductor pillar.

[0008] In an exemplary embodiment, the first bit line portion and the semiconductor pillar are made of the same material.

[0009] In an exemplary embodiment, the materials of the first bit line portion and the semiconductor pillar include silicon, and the material of the second bit line portion includes metal silicide.

[0010] In an exemplary embodiment, the isolation layer extends to the surface of the shielding structure close to the semiconductor pillar in the third direction.

[0011] In an exemplary embodiment, a semiconductor device has a storage region and a connection region, and a shielding structure extends within the storage region and the connection region; the semiconductor device further includes: a contact structure located within the connection region and extending in a third direction to the shielding structure.

[0012] In an exemplary embodiment, the material of the shielding structure includes a metallic material.

[0013] In an exemplary embodiment, the material of the shielding structure is molybdenum.

[0014] In a second aspect, some embodiments of the present application provide a memory system. The memory system includes: a memory including a semiconductor device as mentioned in any of the above embodiments; and a controller coupled to the memory for controlling the memory to store data.

[0015] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The semiconductor device includes a plurality of first bit line portions extending in a first direction, and the plurality of first bit line portions are spaced apart in a second direction. The method includes: forming an initial isolation layer on a first surface of the first bit line portion in a third direction and a relative surface in the second direction; forming a shielding structure between the initial isolation layers; removing a part of the initial isolation structure to expose the first surface; and forming a second bit line portion on the first surface to form a bit line structure; wherein the first direction, the second direction, and the third direction intersect each other.

[0016] In an exemplary embodiment, one side of the first bit line portion in the third direction is connected to a semiconductor pillar, and there is an insulating structure between adjacent semiconductor pillars in the second direction. The adjacent first bit line portion and the insulating structure form a first trench; wherein forming the initial isolation layer on a part of the surface of the first bit line portion includes: forming the initial isolation layer on the inner wall of the first trench and the first surface.

[0017] In an exemplary embodiment, forming the shielding structure between the initial isolation layers includes: filling a metallic material in the first trench; etching a part of the metallic material close to the first surface, and using the remaining part of the metallic material as the shielding structure.

[0018] In an exemplary embodiment, the method further includes: depositing an insulating material in the space formed in the first trench after etching the metallic material and on a side of the first surface away from the semiconductor pillar; wherein removing a part of the initial isolation structure to expose the first surface includes: removing the insulating material and the part of the initial isolation layer located on the first surface through an etching process or a chemical mechanical polishing process.

[0019] In an exemplary embodiment, the material of the first bit line portion includes silicon; wherein, forming the second bit line portion on the first surface to form a bit line structure includes: forming a metal silicide on the first surface as the second bit line portion.

[0020] In an exemplary embodiment, the method further includes: forming a contact structure connected to an end of the shielding structure in a first direction, the contact structure extending in a third direction.

[0021] According to at least one embodiment of the present application, the semiconductor device, memory system, and manufacturing method of the semiconductor device provided by the present application improve the coupling effect between adjacent bit line structures by providing a shielding structure between adjacent bit line structures and providing an isolation layer between the bit line structure and the shielding structure. By making the size of the bit line structure in the third direction larger than the size of the shielding structure in the third direction, the setting position of the bit line structure is more flexible, avoiding restrictions on the process sequence for forming the bit line structure, and being conducive to improving the process flexibility of manufacturing the bit line structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other features, objects, and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Among them:

[0023] Figure 1A is a cross-sectional schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0024] Figure 1B is a top view schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0025] Figure 2 is a scanning electron microscope image of a semiconductor device provided by an exemplary embodiment of the present application;

[0026] Figure 3 is a block diagram of a system having a memory system provided by an embodiment of the present application;

[0027] Figure 4 is a flowchart schematic diagram of a manufacturing method of a semiconductor device provided by an embodiment of the present application;

[0028] Figure 5A and Figure 5B is a schematic diagram of an intermediate structure of a semiconductor device before performing the manufacturing method provided by an embodiment of the present application; and

[0029] Figures 6 to 11 is a cross-sectional schematic diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] To better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] It should be noted that in this specification, the expressions such as first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the feature, especially do not represent any order. Therefore, without departing from the teachings of the present application, the first bit line portion discussed in the present application may also be referred to as the second bit line portion, and vice versa.

[0032] In the drawings, for ease of illustration, the thickness, dimensions, and shape of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. As used herein, the terms "substantially", "about", and similar terms are used as terms indicating approximation, rather than terms indicating degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0033] It should also be understood that expressions such as "comprising", "including", "having", "containing", and / or "including having" are open-ended rather than closed-ended expressions in this specification, which mean the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, rather than just individual elements in the list. In addition, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0034] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as the ordinary understanding of a person of ordinary skill in the art to which the present application pertains. It should also be understood that unless clearly stated in the present application, words defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0035] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. In addition, unless clearly defined or in contradiction with the context, the specific steps included in the methods described in the present application do not have to be limited to the recorded order and can be executed in any order or executed in parallel.

[0036] In addition, in the present application, when using "connect" or "couple", it may indicate direct contact or indirect contact between corresponding components, unless there are clear other limitations or can be deduced from the context.

[0037] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0038] An embodiment of the present application provides a semiconductor device. Figure 1A It is a cross-sectional schematic diagram of the semiconductor device provided by the embodiment of the present application. Figure 1B It is a top view schematic diagram of the semiconductor device provided by the embodiment of the present application. For example, Figure 1A and Figure 1B the semiconductor device 100 shown may be part of a dynamic random access memory (DRAM).

[0039] It should be noted that hereinafter, the D1 direction, D2 direction, and D3 direction in each of the accompanying drawings show the spatial relationship of each component in the semiconductor device. For example, the D3 direction is the extending direction of the semiconductor column, and the D1 direction and D2 direction are two directions that intersect (e.g., are perpendicular) to each other in a plane that intersects (e.g., is perpendicular to) the extending direction. The same concept will be adopted throughout the present application to describe the spatial relationship of each component in the semiconductor device.

[0040] As Figure 1A shown, the semiconductor device 100 includes a bit line structure 111, a shielding structure 112, and an isolation layer 113. In the semiconductor device 100, both the bit line structure 111 and the shielding structure 112 extend along the D1 direction (e.g., continuously extend), and the bit line structure 111 and the shielding structure 112 are alternately arranged in the D2 direction. For example, the plurality of shielding structures 112 are not connected to each other in the D2 direction. Among them, the size d1 of the bit line structure 111 in the D3 direction is greater than the size d2 of the shielding structure 112 in the D3 direction. The isolation layer 113 is located between the bit line structure 111 and the shielding structure 112.

[0041] In some embodiments, the material of the shielding structure 112 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), polysilicon (poly-Si), amorphous silicon (α-Si), tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), or any other suitable conductive material. Exemplarily, the material of the shielding structure 112 may be one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), or any other suitable metallic material. Selecting a metallic material to manufacture the shielding structure 112 can reduce the conductivity. For example, when the material of the shielding structure 112 is molybdenum (Mo), it can make the shielding structure 112 have good electrical conductivity and is beneficial to improving the filling performance of the shielding structure 112 during the formation process, ensuring the morphology of the shielding structure 112.

[0042] In some embodiments, the material of the isolation layer 113 may include one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), high-k dielectric materials, or any other suitable insulating materials. Among them, the high-k dielectric materials may include one or more of aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 3 ), hafnium oxide (HfO 2 ).

[0043] In an exemplary embodiment, Figure 2 a scanning electron microscope image of the semiconductor device of this exemplary embodiment is shown. As Figure 2 shown, the dielectric structure 12 having a void gap 11 is located between adjacent bit line structures 13. The above structure can improve the coupling effect between adjacent bit line structures 13 (for example, reduce the equivalent capacitance value between adjacent bit line structures 13). However, in order to form a dielectric structure 12 that meets the design requirements, the morphology and spacing distance between adjacent bit line structures 13 are relatively strict. For example, in order to improve the integration of the semiconductor device, the spacing distance between adjacent bit line structures tends to decrease, which in turn causes the air gap in the dielectric structure to tend to decrease, thus being disadvantageous for reducing the equivalent capacitance value between adjacent bit line structures and difficult to meet the design requirements for improving the coupling effect. In other words, using a dielectric structure with a void gap to improve the coupling effect will limit the iterative miniaturization of the semiconductor device.

[0044] According to the semiconductor device provided by the embodiment of the present application, compared with the semiconductor device of the above exemplary embodiment, by arranging a shielding structure between adjacent bit line structures and arranging an isolation layer between the bit line structure and the shielding structure, the coupling effect between adjacent bit line structures is improved by using the shielding structure (for example, applying a ground voltage or a negative voltage to the shielding structure). By making the size of the bit line structure in the third direction larger than the size of the shielding structure in the third direction, the setting position of the bit line structure is more flexible, avoiding restrictions on the process sequence for forming the bit line structure, and being beneficial to improving the process flexibility of manufacturing the bit line structure.

[0045] In some embodiments, as Figure 1A shown, the semiconductor device 100 may further include semiconductor pillars 114. The semiconductor pillars 114 are located on one side of the bit line structure 111 in the D3 direction. For example, for a bit line structure 111, a plurality of semiconductor pillars 114 protrude from the surface of the bit line structure 114 in the D3 direction, and the plurality of semiconductor pillars 114 are spaced apart in the D1 direction. Among them, each of the plurality of semiconductor pillars 114 extends in the D3 direction. Thus, the plurality of semiconductor pillars 114 are arranged in an array in a plane perpendicular to the D3 direction. Exemplarily, the semiconductor device 100 may further include an insulating structure 115. The insulating structure 115 is located on the outer periphery of each of the plurality of semiconductor pillars 114 arranged in an array.

[0046] In some embodiments, the bit line structure 111 may include a first bit line portion 1111 and a second bit line portion 1112 stacked in the D1 direction. The second bit line portion 1112 is located on the side of the first bit line portion 1111 away from the semiconductor pillar 114. In other words, the first bit line portion 1111 is located between the second bit line portion 1112 and the semiconductor pillar 114. For example, both the first bit line portion 1111 and the second bit line portion 1112 extend in the D1 direction (for example, continuously extend).

[0047] In some embodiments, the first bit line portion 1111 is in contact with the semiconductor pillar 114. For example, before forming the first bit line portion 1111 and the semiconductor pillar 114, both the first bit line portion 1111 and the semiconductor pillar 114 are included in the same substrate, and are formed by performing semiconductor processes such as lithography and etching on the substrate. Therefore, the first bit line portion 1111 and the semiconductor pillar 114 are made of the same material, and there is no obvious boundary between them. Exemplarily, the materials of the first bit line portion 1111 and the semiconductor pillar 114 may be semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. For example, the first bit line portion 1111 and the semiconductor pillar 114 are from a silicon substrate, and their materials are both doped or undoped silicon (Si).

[0048] In some embodiments, the material of the second bit line portion 1112 includes metal silicide. For example, the metal silicide may include silicides of one or more of titanium (Ti), cobalt (Co), nickel (Ni), and platinum (Pt). As described above, when the material of the first bit line portion 1111 is silicon, the conductivity of the first bit line portion 1111 is restricted. By using the second bit line portion 1112 with the material of metal silicide and the first bit line portion 1111 together as the bit line structure 111, the overall conductivity of the bit line structure 111 can be effectively improved. Using the bit line structure 111 to transmit bit line signals can effectively improve the transmission performance and better adapt to the development trend of high bandwidth.

[0049] In some embodiments, when the bit line structure 111 includes the first bit line portion 1111 and the second bit line portion 1112, the numerical relationship between the dimension d1 of the bit line structure 111 in the D3 direction and the dimension d2 of the shielding structure 112 in the D3 direction can also be expressed as: in the D3 direction, the distance d1 between the surface of the second bit line portion 1112 away from the semiconductor pillar 114 and the surface of the shielding structure 112 close to the semiconductor pillar 114 is greater than the dimension of the shielding structure 112. The second bit line portion 1112 and the shielding structure 112 satisfy the above dimension relationship, making the setting position of the bit line structure 111 more flexible. For example, it allows the second bit line portion 1112 to be formed after the shielding structure 112 is formed, avoiding restrictions on the process sequence for forming the bit line structure 111. It can also effectively improve the overall conductivity of the bit line structure 111, effectively improve the bit line signal transmission performance of the bit line structure 111, and better adapt to the development trend of high bandwidth.

[0050] In some embodiments, in addition to being located between the bit line structure 111 and the shielding structure 112, the isolation layer 113 can also extend to the surface of the shielding structure 112 close to the semiconductor pillar 114 in the D3 direction. For example, the above-mentioned extended portion of the isolation layer 113 can be located between the shielding structure 112 and the insulating structure 115 on the outer periphery of the semiconductor pillar 114. For example, when the materials of the isolation layer 113 and the insulating structure 115 are different, from the D1 direction, the isolation layer 113 can be approximately in a "U" shape. Another example is that when the materials of the isolation layer 113 and the insulating structure 115 are the same, there is no obvious boundary between the portion of the isolation layer 113 extending to the surface of the shielding structure 112 close to the semiconductor pillar 114 in the D3 direction and the insulating structure 115.

[0051] In some embodiments, such as Figure 1BAs shown, the semiconductor device 100 may have a storage area 101 and a connection area 102. The shielding structure 112 extends (e.g., continuously extends) within the storage area 101 and the connection area 102. For example, the bit line structure 111 also extends (e.g., continuously extends) within the storage area 101 and the connection area 102. The bit line structures 111 having different extension lengths within the connection area 102 are arranged alternately along the D2 direction, and adjacent shielding structures 112 are connected to each other within the connection area 102 and surround the ends of the bit line structures 111 having shorter extension lengths. Optionally, within the connection area 102, the isolation layer 113 can also be used to separate the shielding structure 112 from other components. The semiconductor device 100 may further include a contact structure 116. Among them, the contact structure 116 can be located within the connection area 102 and extend along the D3 direction to the shielding structure 112. For example, the contact structure 116 can be generally columnar and draw out the shielding structure 112 from the D3 direction by contacting the shielding structure 112. The material of the contact structure 116 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), polysilicon (poly-Si), amorphous silicon (α-Si), tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), or any other suitable conductive material.

[0052] It should be noted that Figure 1B The shapes and arrangements of the shown bit line structure 111 and shielding structure 112 within the connection area 102, and the number of contact structures 116 are only examples. Without departing from the teachings of the present application, the bit line structure and the shielding structure may have other shapes and arrangements, and the contact structure may have other numbers. The present application does not make specific limitations in this regard. For example, the bit line structures have the same extension length within the connection area, the shielding structures are connected to each other within the connection area and surround the ends of multiple bit line structures, and one contact structure extends along the D3 direction to the mutually connected shielding structures to draw out the shielding structures from the D3 direction.

[0053] An embodiment of the present application also provides a memory system. Figure 3 It is a block diagram of a system having a memory system provided by an embodiment of the present application.

[0054] As Figure 3 shown, the system 300 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has a memory system 310 located therein). As Figure 3As shown, the system 300 may include a host 320 and a memory system 310. The memory system 310 may have one or more memories 311 and a controller 312. The host 320 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 320 may be configured to send or receive data to or from the memory 311.

[0055] In some embodiments, the controller 312 may be coupled to the memory 311 and the host 320, and be configured to control the memory 311. For example, the controller 312 may be configured to control the memory 311 to perform operations such as reading, erasing, and programming. The controller 312 may also manage the data stored in the memory 311 and communicate with the host 320. For example, the controller 312 may communicate with an external device (e.g., the host 320) according to a specific communication protocol.

[0056] An embodiment of the present application also provides a method for manufacturing a semiconductor device. Figure 4 is a schematic flowchart of the method for manufacturing a semiconductor device provided by an embodiment of the present application. As Figure 4 shown, the method 400 for manufacturing a semiconductor device (hereinafter simply referred to as the manufacturing method 400) may include the following steps.

[0057] S410, forming an initial isolation layer on a first surface in a third direction and a relative surface in a second direction of a first bit line portion.

[0058] S420, forming a shielding structure between the initial isolation layers.

[0059] S430, removing a part of the initial isolation structure to expose the first surface.

[0060] S440, forming a second bit line portion on the first surface to form a bit line structure.

[0061] According to the method for manufacturing a semiconductor device provided by this embodiment, by forming a shielding structure between adjacent bit line structures and forming an isolation layer between the bit line structure and the shielding structure, the shielding structure is used to improve the coupling effect between adjacent bit line structures (e.g., applying a ground voltage or a negative voltage to the shielding structure). In addition, the first bit line portion and the second bit line portion in the bit line structure are formed before and after forming the shielding structure respectively, avoiding restrictions on the process sequence for forming the bit line structure, which is beneficial to improving the process flexibility for manufacturing the bit line structure.

[0062] Figure 5A and Figure 5BFIG. 0 is a schematic structural diagram of an intermediate structure of a semiconductor device provided by an embodiment of the present application before performing manufacturing method 400. Among them, Figure 5B is a cross-sectional schematic diagram of the intermediate structure taken along Figure 5A line A-A' shown in FIG. Figures 6 to 11 FIG. 6 is a cross-sectional schematic diagram of a semiconductor device provided by an embodiment of the present application during the manufacturing process. Among them, Figures 6 to 11 is a cross-sectional schematic diagram of each intermediate structure during the manufacturing process taken along Figure 5A line B-B' shown in FIG. For example, Figures 6 to 11 can be used to form Figure 1A and Figure 1B the semiconductor device 100 shown in FIG.

[0063] Next, with reference to Figure 5A and Figure 5B FIGS., the intermediate structure 500a before performing the above steps S410 to S440 will be exemplarily described.

[0064] As shown in Figure 5A and Figure 5B FIGS., before performing steps S410 to S440, the intermediate structure 500a of the semiconductor device may include a plurality of first bit line portions 5111 extending in the D1 direction. The plurality of first bit line portions 5111 are arranged at intervals in the D2 direction.

[0065] In some embodiments, one side of the first bit line portion 5111 in the D3 direction is connected to the semiconductor pillar 514. As described in detail above, a plurality of semiconductor pillars 514 protrude from the surface of one first bit line portion 5111 in the D3 direction. When the intermediate structure 500a has a plurality of first bit line portions 5111, the plurality of semiconductor pillars 514 are arranged in an array in a plane perpendicular to the D3 direction. The semiconductor pillar 514 and the first bit line portion 5111 are an integral structure, and both are formed by performing photolithography and etching processes on a silicon substrate.

[0066] In some embodiments, as shown in Figure 5B FIG., the intermediate structure 500a may further include a gate dielectric layer 521 on the sidewall of the semiconductor pillar 514. Exemplarily, the material of the gate dielectric layer 521 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), a high-k material, or any other suitable insulating material, or a combination of one or more of them. For example, the material of the gate dielectric layer 521 may be silicon oxide (SiO 2 ). When the material of the gate dielectric layer 521 is silicon oxide (SiO 2) When forming the gate dielectric layer 521 on the sidewalls of the semiconductor pillar 514, an oxidation method (e.g., dry oxidation method and / or wet oxidation method) can be adopted.

[0067] In some embodiments, the intermediate structure 500a may further include a word line 522 located on the surface of the gate dielectric layer 521. The word line 522 may extend along the D2 direction (e.g., continuously). In some examples, the word line 522 may include an adhesion layer 5221 and a metal layer 5222 that are adhered to each other. Among them, the adhesion layer 5221 may be located on the surface of the gate dielectric layer 521 and extend along the D2 direction (e.g., continuously). The metal layer 5222 may be located on the surface of the adhesion layer 5221 and extend along the D2 direction (e.g., continuously). In other words, the adhesion layer 5221 may be located between the metal layer 5222 and the gate dielectric layer 521. The adhesion layer 5221 helps to improve the bonding performance between the metal layer 5222 and the gate dielectric layer 521. For example, the material of the adhesion layer 5221 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable material. For example, the material of the metal layer 5222 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), or any other suitable metal material. In some other examples, the word line 522 may not have a composite structure but be composed of a single conductive material, and the present application does not make specific limitations thereto.

[0068] In some embodiments, the intermediate structure 500a may further include a first isolation structure 523. The first isolation structure 523 may be located between semiconductor pillars 514 adjacent in the D1 direction. For two semiconductor pillars 514 adjacent in the D1 direction (within the dashed box), the gate dielectric layer 521 and the word line 522 may be located on the sidewalls of the two semiconductor pillars 514 facing each other. A group of semiconductor pillars 514 (within the dashed box), the gate dielectric layer 521, and the word line 522 structure may be arranged in the D1 direction and may be spaced apart by a second isolation structure 524. Exemplarily, the materials of the first isolation structure 523 and the second isolation structure 524 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or one or more of any other suitable insulating materials.

[0069] According to the above description, in some embodiments, a semiconductor pillar 514, and a portion of the gate dielectric layer 521 and the word line 522 covering the sidewall of the semiconductor pillar 514 can form a transistor. In this transistor, the semiconductor pillar 514 can serve as the channel, the portion of the word line 522 in contact with the gate dielectric layer 521 can serve as the gate, and both ends of the semiconductor pillar 514 in the extending direction (i.e., the D3 direction) can respectively serve as one of the source and the drain. Since the extending direction of the semiconductor pillar 514 (i.e., the D3 direction) is perpendicular to the horizontal extending direction of the substrate, this transistor can also be referred to as a vertical-channel transistor. The vertical-channel transistor can effectively reduce the planar occupation area and improve the storage density. In this case, the word line 522 extending in the D2 direction can be used to connect a column of transistors arranged in the D2 direction. Each transistor can be a part of a memory cell (e.g., a DRAM memory cell).

[0070] It should be noted that Figure 5B The relative positional relationship between the shown word line 522 and the semiconductor pillar 514 is only an example. In some other embodiments, the word line and the semiconductor pillar may also have other relative positional relationships. For example, in the case where the semiconductor pillar has four sidewalls, the word line can surround at least one sidewall of the semiconductor pillar (e.g., two, three, and four sidewalls), and the present application does not make specific limitations thereon. Additionally, any known process method in the art can be used to form the above intermediate structure 500a, and the present application does not make specific limitations thereon.

[0071] In some embodiments, the intermediate structure 500a may further include a capacitor (not shown). The capacitor can include a first electrode, an insulating layer, and a second electrode. The insulating layer can be located between the first electrode and the second electrode. Among them, one of the first electrode and the second electrode is connected to the transistor. For example, the capacitor can be implemented as a barrel capacitor, a stacked capacitor, or any other known type of capacitor in the art. The transistor and the capacitor can jointly form a memory cell (e.g., a DRAM memory cell). Placing the capacitor and the bit line structure 511 to be formed (refer to Figure 11 ) at both ends of the semiconductor pillar 514 respectively is beneficial to further reducing the planar occupation area and improving the storage density. Additionally, compared with the method of pre-embedding the formation of the bit line structure, forming the bit line structure after forming the transistor and the capacitor is beneficial to simplifying the manufacturing process and reducing the manufacturing difficulty.

[0072] The following will exemplarily illustrate the above steps S410 to S440 in conjunction with Figures 6 to 11 exemplary illustrations.

[0073] S410

[0074] In this step, Figure 6 The intermediate structure 500b after forming the initial isolation layer 513' is shown. As Figure 6As shown, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to form an initial isolation layer 513' on the first surface 525 of the first bit line portion 5111 in the D3 direction and the opposite surface 526 in the D2 direction.

[0075] In some embodiments, the insulating structure 515 can be located on the outer periphery of a plurality of semiconductor pillars 514 arranged in an array. Specifically, the insulating structure 515 can be located between adjacent semiconductor pillars 514 in the D2 direction and can also be located between adjacent semiconductor pillars 514 in the D1 direction. Since the semiconductor pillars 514 are also connected to one side of the first bit line portion 5111 in the D3 direction, the adjacent first bit line portion 5111 and the insulating structure 515 can form a first trench 527. During the formation of the initial isolation layer 513', a thin film deposition process can be used to form the initial isolation layer 513' on the inner wall of the first trench 527 and the first surface 525 of the first bit line portion 5111.

[0076] S420

[0077] In this step, Figure 7 An intermediate structure 500c after the formation of the metal material 528 is shown. Figure 8 An intermediate structure 500c after the formation of the shielding structure 512 is shown. As Figure 6 and Figure 8 shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form the shielding structure 512 between the initial isolation layers 513'. In some embodiments, first, as Figure 6 and Figure 7 shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill the first trench 527 with the metal material 528. The metal material 528 can cover the first surface 525. For example, the metal material 528 can be molybdenum (Mo). Further, as Figure 7 and Figure 8 shown, a part of the metal material 528 close to the first surface 525 can be etched, and the remaining part of the metal material 528 can be used as the shielding structure 512. For example, there is a spacing distance between the surface of the shielding structure 512 close to the first surface 525 and the first surface 525, such that a part of the first trench 527 is re-exposed. It should be noted that the formation of the Figure 7 shown intermediate structure 500b can be omitted, and the intermediate structure 500c shown in Figure 8 can be directly formed by controlling the thin film deposition process.

[0078] In some embodiments, the manufacturing method 400 may further include the following steps. Figure 9 An intermediate structure 500d after forming the insulating material 530 is shown. As Figure 8 and Figure 9 shown, after forming the shielding structure 512, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to deposit the insulating material 530 in the space formed after etching the metal material 528 (refer to Figure 7 ) in the first trench 527 and on the side of the first surface 525 away from the semiconductor pillar 514. Exemplarily, the insulating material 530 may include one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), or any other suitable insulating material. For example, the insulating material 530 may be silicon oxide (SiO 2 ).

[0079] S430

[0080] In this step, Figure 10 An intermediate structure 500e after removing a part of the initial isolation layer 513' is shown. As Figure 8 and Figure 10 shown, a part of the initial isolation structure 513' can be removed by an etching process (e.g., wet etching and / or dry etching) to expose the first surface 525. As an alternative, a chemical mechanical polishing (CMP) process can also be used to remove a part of the initial isolation layer 513' to expose the first surface 525. The initial isolation layer 513' after being removed can be referred to as the isolation layer 513.

[0081] It should be noted that when a part of the initial isolation layer 513' is removed by an etching process, a part of the relative surface 526 of the initial isolation layer 513' located in the D2 direction of the first bit line part 5111 (refer to Figure 6 ) and close to the first surface 525 will also be removed, as Figure 10 shown. When a part of the initial isolation layer 513' is removed by a CMP process, the part of the initial isolation layer 513' located on the relative surface 526 of the first bit line part 5111 in the D2 direction (refer to Figure 6 ) can be relatively completely retained (not shown).

[0082] In some embodiments, as Figure 9 and Figure 10As shown, when forming the insulating material 530, an etching process (e.g., wet etching and / or dry etching) or a CMP process can be used to remove the part of the insulating material 530 and the initial isolation layer 513' located on the first surface 525. Among them, the insulating material 530 that is not removed can protect the shielding structure 512 from being damaged.

[0083] S440

[0084] In this step, Figure 11 a semiconductor device 500 is shown. As Figure 10 and Figure 11 shown, a second bit line portion 5112 can be formed on the first bit line portion 5111 to form a bit line structure 511.

[0085] In some embodiments, when the material of the first bit line portion 5111 is silicon, a metal silicide can be formed on the first surface 525 of the first bit line portion 5111 as the second bit line portion 5112. Here, taking nickel (Ni) silicide as an example, its formation process is illustrated. For example, first, a layer of nickel (Ni) can be deposited on the first bit line portion 5111 by PVD process. Then, nickel (Ni) can react with silicon (Si) and consume a part of silicon (Si) to form NiSi 2 . Further, under heating conditions, NiSi 2 is converted to NiSi (i.e., nickel (Ni) silicide). It should be noted that when the metal silicide is one or more of titanium (Ti) silicide, cobalt (Co) silicide, platinum (Pt) silicide or other metal silicides, similar to the formation of nickel (Ni) silicide, a layer of metal can be first formed on the first bit line portion 5111, and then the metal can react with silicon (Si) and be subjected to thermal annealing treatment to form the corresponding metal silicide.

[0086] According to the manufacturing method provided by the embodiments of the present application, by forming a shielding structure between adjacent bit line structures and forming an isolation layer between the bit line structure and the shielding structure, the coupling effect between adjacent bit line structures is improved by using the shielding structure (e.g., applying a ground voltage or a negative voltage to the shielding structure). In addition, the first bit line portion and the second bit line portion in the bit line structure are formed before and after forming the shielding structure respectively, which can avoid restricting the process sequence of forming the bit line structure and is beneficial to improving the process flexibility of manufacturing the bit line structure.

[0087] In some embodiments, the manufacturing method 400 may further include the following steps. Refer to Figure 1B, an etching process (e.g., dry etching and / or wet etching) and a thin film deposition process can be used to form a contact structure 116 connected to the end of the shielding structure 112 in the D1 direction. Among them, the contact structure 116 can extend along the D3 direction to lead out the shielding structure 112 from the D3 direction.

[0088] The above description is only for the embodiments of the present application and the explanation of the technical principles applied. Those skilled in the art should understand that the protection scope involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present application.

Claims

1. A semiconductor device, characterized in that, comprising: A bit line structure extending in a first direction; A shielding structure extending in the first direction and arranged alternately with the bit line structure in a second direction; and An isolation layer located between the bit line structure and the shielding structure; wherein, the size of the bit line structure in a third direction is larger than the size of the shielding structure in the third direction, and the first direction, the second direction, and the third direction intersect with each other.

2. The semiconductor device according to claim 1, further comprising: A semiconductor pillar located on one side of the bit line structure in the third direction; wherein, the bit line structure comprises: A first bit line portion and a second bit line portion stacked in the third direction, and the second bit line portion is located on the side of the first bit line portion away from the semiconductor pillar.

3. The semiconductor device according to claim 2, wherein, in the third direction, the distance between the surface of the second bit line portion away from the semiconductor pillar and the surface of the shielding structure close to the semiconductor pillar is greater than the size of the shielding structure.

4. The semiconductor device according to claim 2, wherein, the first bit line portion is in contact with the semiconductor pillar.

5. The semiconductor device according to claim 2, wherein, the first bit line portion and the semiconductor pillar are made of the same material.

6. The semiconductor device according to claim 5, wherein, the first bit line portion and the semiconductor pillar are made of silicon, and the second bit line portion is made of metal silicide.

7. The semiconductor device according to claim 2, wherein, the isolation layer extends to the surface of the shielding structure close to the semiconductor pillar in the third direction.

8. The semiconductor device according to claim 1, wherein, the semiconductor device has a storage area and a connection area, and the shielding structure extends in the storage area and the connection area; the semiconductor device further comprises: A contact structure located in the connection area and extending in the third direction to the shielding structure.

9. The semiconductor device according to any one of claims 1 to 8, the material of the shielding structure comprises a metal material.

10. The semiconductor device according to claim 9, the material of the shielding structure is molybdenum.

11. A memory system, characterized in that, comprising: A memory including the semiconductor device according to any one of claims 1 to 10; and A controller coupled to the memory for controlling the memory to store data.

12. A method for manufacturing a semiconductor device, wherein, the semiconductor device includes a plurality of first bit line portions extending in a first direction, and the plurality of first bit line portions are spaced apart in a second direction, characterized in that the method includes: Forming an initial isolation layer on a first surface of the first bit line portion in a third direction and a relative surface in the second direction; Forming a shielding structure between the initial isolation layers; Removing a part of the initial isolation structure to expose the first surface; and Forming a second bit line portion on the first surface to form a bit line structure; Wherein, the first direction, the second direction, and the third direction intersect with each other.

13. The manufacturing method according to claim 12, wherein, one side of the first bit line portion in the third direction is connected to the semiconductor pillar, and there is an insulating structure between the adjacent semiconductor pillars in the second direction. The adjacent first bit line portion and the insulating structure form a first trench; wherein, forming an initial isolation layer on a partial surface of the first bit line portion includes: forming the initial isolation layer on the inner wall of the first trench and the first surface.

14. The manufacturing method according to claim 13, wherein, forming a shielding structure between the initial isolation layers includes: filling the first trench with a metal material; etching a part of the metal material close to the first surface, and using the remaining part of the metal material as the shielding structure.

15. The manufacturing method according to claim 14, the method further includes: depositing an insulating material in the space formed in the first trench after etching the metal material and on the side of the first surface away from the semiconductor pillar; wherein, removing a part of the initial isolation structure to expose the first surface includes: removing the insulating material and the part of the initial isolation layer located on the first surface through an etching process or a chemical mechanical polishing process.

16. The manufacturing method according to claim 12, wherein, the material of the first bit line portion includes silicon; wherein, forming a second bit line portion on the first surface to form a bit line structure includes: forming a metal silicide on the first surface as the second bit line portion.

17. The manufacturing method according to claim 12, the method further includes: forming a contact structure connected to an end portion of the shielding structure in the first direction, and the contact structure extends along the third direction.

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