Semiconductor structure and method of manufacturing the same, electronic device

Abstract

The present disclosure relates to a semiconductor structure, a preparation method thereof and an electronic device. The method comprises: alternately forming a plurality of layers of first dielectric layers and a plurality of layers of second dielectric layers on a substrate in a vertical substrate direction; etching the plurality of layers of first dielectric layers and the plurality of layers of second dielectric layers in the vertical substrate direction to form a stack structure; filling an isolation structure in etched regions of the plurality of layers of first dielectric layers and the plurality of layers of second dielectric layers; etching the stack structure to form a first etching hole; etching a sidewall of the second dielectric layer based on the first etching hole to form a first accommodation groove; forming a first electrode in the first accommodation groove; forming a sacrificial layer covering the first electrode and filling the first etching hole; etching the isolation structure to form a second etching hole; sequentially forming a first dielectric layer and a second electrode in the second etching hole; and removing the sacrificial layer to sequentially form a second dielectric layer and a third electrode in the first etching hole.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method, and an electronic device. Background Technology

[0002] With the continuous development of semiconductor technology, people are constantly pursuing products with lower power consumption, lighter weight, and better performance. Three-dimensional memory (3D memory) is easy to integrate with higher density and larger storage capacity, and has gradually become one of the important research directions in the current memory field. However, 3D memory has high process complexity, and improvements are needed in many aspects, including the precision of process control, equipment capabilities (such as etching and film filling), and the selection of device materials. Summary of the Invention

[0003] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, as well as an electronic device, which simplifies the capacitor fabrication process and effectively improves the electrical performance of the capacitor and the electronic device.

[0004] According to some embodiments, this disclosure provides a method for fabricating a semiconductor structure, including the following steps.

[0005] A substrate is provided, and multiple layers of first dielectric layers and multiple layers of second dielectric layers are alternately formed on the substrate along a direction perpendicular to the substrate.

[0006] Multiple first dielectric layers and multiple second dielectric layers are etched along a direction perpendicular to the substrate to form a stacked structure; the stacked structure includes a first portion extending along a first direction and a plurality of second portions spaced apart along the first direction and extending from the first portion along a second direction; the first direction and the second direction are parallel to the substrate and intersect each other.

[0007] An isolation structure is filled in the etched regions of the multilayer first dielectric layer and the multilayer second dielectric layer.

[0008] The etched stacked structure is used to form a first etched hole that penetrates the second part along the direction perpendicular to the substrate.

[0009] The sidewall of the second dielectric layer is etched based on the first etching hole to expose the isolation structure at least in the first direction, forming a first receiving groove.

[0010] A first electrode is formed in the first receiving groove.

[0011] A sacrificial layer is formed that covers the first electrode and fills the first etched hole.

[0012] The isolation structure is etched to form a second etched hole that penetrates the isolation structure along the direction perpendicular to the substrate and is located between adjacent first electrodes along the first direction.

[0013] A first dielectric layer covering the first electrode and a second electrode covering the first dielectric layer and filling the second etched hole are sequentially formed in the second etched hole.

[0014] Remove the sacrificial layer.

[0015] A second dielectric layer covering the first electrode and a third electrode covering the second dielectric layer and filling the first etched hole are sequentially formed in the first etched hole.

[0016] As described above, the capacitor includes: a first electrode, a second electrode located outside the first electrode, and a third electrode located inside the first electrode.

[0017] According to some embodiments, forming a first electrode in a first receiving groove includes: forming a first electrode that fills the first receiving groove; or forming a first electrode that conformally covers the inner wall of the first receiving groove.

[0018] According to some embodiments, forming a first electrode in a first receiving groove includes: depositing a first electrode material layer in a first etched hole and a first receiving groove; removing the first electrode material layer on the inner wall of the first etched hole, such that the first electrode material layer retained in the first receiving groove constitutes the first electrode.

[0019] According to some embodiments, the first receiving groove is formed by wet etching of the second dielectric layer.

[0020] According to some embodiments, the method for fabricating the semiconductor structure further includes: after forming the sacrificial layer and before forming the second etch hole, removing each of the second dielectric layers retained in the stacked structure, and forming a conductive layer in the removal region of the second dielectric layer.

[0021] According to some embodiments, the method for fabricating the semiconductor structure further includes: after forming the second etched hole and before forming the first dielectric layer, wet-removing the first dielectric layer in the target area above and below the first electrode to expose the sacrificial layer in at least a first direction and connect it to the adjacent second etched hole to form a second accommodating trench.

[0022] Accordingly, a first dielectric layer is also formed on the inner wall of the second receiving groove, and the second electrode also fills the second receiving groove.

[0023] According to some embodiments, a second dielectric layer covering the first electrode and a third electrode covering the second dielectric layer and filling the first etched hole are sequentially formed in the first etched hole, including the following steps.

[0024] A second dielectric material layer is formed on the exposed surface of the first electrode away from the first dielectric layer, the exposed surface of the first dielectric layer away from the second electrode, and the top surface of the second electrode.

[0025] A third electrode material layer is formed, covering the exposed surface of the second dielectric material layer and filling the first etched hole.

[0026] The third electrode material layer and the second dielectric material layer are ground until the top surface of the second electrode is exposed, such that the second dielectric material layer retained in the first etched hole constitutes the second dielectric layer, and the third electrode material layer retained in the first etched hole constitutes the third electrode.

[0027] Accordingly, the method for fabricating the semiconductor structure further includes: forming a contact layer on the top surface of each second electrode and each third electrode, wherein the contact layer interconnects each second electrode and each third electrode.

[0028] According to some embodiments, the first dielectric layer includes an oxide layer, the second dielectric layer includes a nitride layer, and the sacrificial layer includes a low-k dielectric layer.

[0029] According to some embodiments, this disclosure also provides a semiconductor structure that can be fabricated using the methods described in the above embodiments. The semiconductor structure includes: a substrate, a plurality of first electrodes, a plurality of first dielectric layers, a plurality of second electrodes, a plurality of second dielectric layers, and a plurality of third electrodes.

[0030] Multiple first electrodes are spaced apart along a first direction parallel to the substrate. The first electrodes are in a ring-like structure, with the axis of the ring-like structure perpendicular to the substrate. A first dielectric layer covers the inner sidewalls of the first electrodes and extends along a direction perpendicular to the substrate to the substrate surface in a cup-shaped structure. A second electrode covers the surface of the corresponding first dielectric layer opposite to the first electrode and fills the cup-shaped region of the first dielectric layer. A second dielectric layer is located between two adjacent first electrodes along the first direction, covers the outer sidewalls of the corresponding first electrodes, and extends along a direction perpendicular to the substrate, covering the surface of the first dielectric layer opposite to the second electrode and extending to the substrate surface in a cup-shaped structure. A third electrode covers the surface of the corresponding second dielectric layer opposite to the first electrode and fills the cup-shaped region of the second dielectric layer.

[0031] According to some embodiments, the semiconductor structure further includes a contact layer. The contact layer is located on the top surface of each second electrode and each third electrode, and interconnects the second electrodes and the third electrodes.

[0032] According to some embodiments, both the first dielectric layer and the second dielectric layer include a high-k dielectric layer; the first electrode includes a titanium nitride layer; and both the second electrode and the third electrode include a titanium nitride layer and a polysilicon layer stacked along a direction away from the corresponding dielectric layer.

[0033] According to some embodiments, this disclosure also provides an electronic device, including: a semiconductor structure as described in the foregoing embodiments.

[0034] The embodiments disclosed herein may have, or at least have, the following advantages:

[0035] In this embodiment, based on alternating layers of first dielectric layers and second dielectric layers, a stacked structure can be patterned and filled with an isolation structure. Then, by forming a first etching hole and etching the second dielectric layer to form a first receiving trench, a first electrode can be directly formed within the first receiving trench. Compared to the high aspect ratio etching process for metal thin films, this effectively reduces process difficulty and production costs.

[0036] Based on this, in this embodiment, after forming a sacrificial layer within the first etched hole, a second etched hole can be formed by etching the isolation structure between adjacent first electrodes, thereby sequentially forming a first dielectric layer and a second electrode within the second etched hole. Furthermore, after removing the sacrificial layer, a second dielectric layer and a third electrode can be sequentially formed within the first etched hole. Thus, the capacitor includes a first electrode, a second electrode located outside the first electrode, and a third electrode located inside the first electrode. This not only simplifies the capacitor fabrication process but also increases the effective electrode area in the capacitor, thereby increasing the capacitance value and improving the electrical performance of the capacitor and the electronic device. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure provided in some embodiments of this disclosure;

[0039] Figure 2 This is a flowchart of a method for fabricating another semiconductor structure provided in some embodiments of this disclosure;

[0040] Figure 3 This is a schematic diagram of a structure obtained by alternately stacking multiple first dielectric layers and multiple second dielectric layers according to some embodiments of this disclosure; wherein, Figure 3 Figure (a) is a top view of the structure shown. Figure 3 Figure (b) is a schematic cross-sectional view of the structure shown along the AA direction;

[0041] Figure 4 This is a schematic diagram of a structure obtained after forming a laminated structure and an isolation structure, provided in some embodiments of this disclosure; wherein, Figure 4 Figure (a) is a top view of the structure shown. Figure 4 Figure (b) is a schematic cross-sectional view of the structure shown along the AA direction;

[0042] Figure 5 This is a schematic diagram of a structure obtained after forming a first etched hole, provided in some embodiments of this disclosure; wherein, Figure 5 Figure (a) is a top view of the structure shown. Figure 5 Figure (b) is a schematic cross-sectional view of the structure shown along the AA direction;

[0043] Figure 6 This is a schematic diagram of the structure obtained after forming the first receiving groove, provided in some embodiments of this disclosure; wherein, Figure 6 Figure (a) is a top view of the structure shown. Figure 6 Figure (b) is a schematic cross-sectional view of the structure shown along the AA direction. Figure 6 Figure (c) in the diagram is a cross-sectional view of the structure shown along the BB direction;

[0044] Figure 7 This is a schematic diagram of a structure obtained after forming a first electrode material layer, provided in some embodiments of this disclosure; wherein, Figure 7 Figure (a) is a schematic cross-sectional view of the structure shown along the AA direction. Figure 7 Figure (b) in the diagram is a cross-sectional view of the structure shown along the BB direction;

[0045] Figure 8 This is a schematic diagram of a structure obtained after forming a first electrode, provided in some embodiments of this disclosure; wherein, Figure 8 Figure (a) is a schematic cross-sectional view of the structure shown along the AA direction. Figure 8 Figure (b) in the diagram is a cross-sectional view of the structure shown along the BB direction;

[0046] Figure 9 This is a schematic diagram of a structure obtained after forming a sacrificial layer, provided in some embodiments of this disclosure; wherein, Figure 9 Figure (a) is a schematic cross-sectional view of the structure shown along the AA direction. Figure 9 Figure (b) in the diagram is a cross-sectional view of the structure shown along the BB direction;

[0047] Figure 10 This is a schematic diagram of a structure obtained after forming a second etched hole and a second receiving groove, provided in some embodiments of this disclosure; wherein... Figure 10 Figure (a) is a top view of the structure shown. Figure 10 Figure (b) in the diagram is a cross-sectional view of the structure shown along the BB direction;

[0048] Figure 11This is a schematic diagram of a structure obtained after forming a first dielectric layer and a second electrode, provided in some embodiments of this disclosure; wherein, Figure 11 Figure (a) is a top view of the structure shown. Figure 11 Figure (b) in the diagram is a cross-sectional view of the structure shown along the BB direction;

[0049] Figure 12 This is a schematic diagram of the structure obtained after removing the sacrificial layer according to some embodiments of this disclosure; wherein, Figure 12 Figure (a) is a top view of the structure shown. Figure 12 Figure (b) in the diagram is a cross-sectional view of the structure shown along the BB direction;

[0050] Figure 13 This is a schematic cross-sectional view along the BB direction of a structure obtained after forming a second dielectric material layer and a third electrode material layer, as provided in some embodiments of this disclosure.

[0051] Figure 14 This is a schematic diagram of a structure obtained after forming a second dielectric layer and a third electrode, provided in some embodiments of this disclosure; wherein, Figure 14 Figure (a) is a top view of the structure shown. Figure 14 Figure (b) in the diagram is a cross-sectional view of the structure shown along the BB direction;

[0052] Figure 15 This is a schematic cross-sectional view along the BB direction of a structure obtained after forming a contact layer, as provided in some embodiments of this disclosure;

[0053] Figure 16 This is a schematic diagram of a structure obtained after forming a first electrode material layer, provided in some embodiments of this disclosure; wherein, Figure 16 Figure (a) is a schematic cross-sectional view of the structure shown along the AA direction. Figure 16 Figure (b) in the diagram is a cross-sectional view of the structure shown along the BB direction;

[0054] Figure 17 This is a schematic diagram of a structure obtained after forming a first electrode, provided in some embodiments of this disclosure; wherein, Figure 17 Figure (a) is a schematic cross-sectional view of the structure shown along the AA direction. Figure 17 Figure (b) in the diagram is a cross-sectional view of the structure shown along the BB direction;

[0055] Figure 18 This is a schematic diagram of a structure obtained after forming a sacrificial layer and a conductive layer, provided in some embodiments of this disclosure; wherein, Figure 18 Figure (a) is a schematic cross-sectional view of the structure shown along the AA direction. Figure 18 Figure (b) in the diagram is a cross-sectional view of the structure shown along the BB direction;

[0056] Figure 19 This is a schematic diagram of a structure obtained after forming a first dielectric layer and a second electrode, provided in some embodiments of this disclosure; wherein, Figure 19 Figure (a) is a schematic cross-sectional view of the structure shown along the AA direction. Figure 19 Figure (b) in the diagram is a cross-sectional view of the structure shown along the BB direction;

[0057] Figure 20 This is a schematic diagram of a structure obtained after forming a second dielectric layer and a third electrode, provided in some embodiments of this disclosure; wherein, Figure 20 Figure (a) is a schematic cross-sectional view of the structure shown along the AA direction. Figure 20 Figure (b) is a schematic cross-sectional view of the structure shown along the BB direction.

[0058] Figure label:

[0059] 1-Substrate, N-Layered structure, N1-First part, N2-Second part, L1-First dielectric layer, L2-Second dielectric layer, L3-Conductive layer, H1-First etched hole, H2-Second etched hole, G1-First accommodating trench, G2-Second accommodating trench, 2-Isolation structure, 3-Capacitor, 31-First electrode, 310-First electrode material layer, 32-First dielectric layer, 33-Second electrode, 34-Second dielectric layer, 340-Second dielectric material layer, 35-Third electrode, 36-Contact layer, 331 and 351-Titanium nitride layer, 3510-Titanium nitride material layer, 332 and 352-Polysilicon layer, 3520-Polysilicon material layer, 4-Sacrificial layer. Detailed Implementation

[0060] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0062] The term "embodiment" in this document means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0063] It is understood that the terms "first," "second," "third," "fourth," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first transistor may be referred to as a second transistor, and similarly, a second transistor may be referred to as a first transistor. Both the first transistor and the second transistor are transistors, but they are not the same transistor.

[0064] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0065] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0066] Please see Figure 1 This disclosure provides a method for fabricating a semiconductor structure, including steps S100 to S1100.

[0067] S100 provides a substrate on which multiple layers of first dielectric layers and multiple layers of second dielectric layers are alternately formed along a direction perpendicular to the substrate.

[0068] For example, the first dielectric layer includes, but is not limited to, an oxide layer, such as a silicon oxide layer. The second dielectric layer includes, but is not limited to, a nitride layer, such as a silicon nitride layer.

[0069] S200, etching multiple first dielectric layers and multiple second dielectric layers along the direction perpendicular to the substrate to form a stacked structure; the stacked structure includes a first portion extending along a first direction and a plurality of second portions spaced apart along the first direction and extending from the first portion along a second direction; the first direction and the second direction are parallel to the substrate and intersect each other.

[0070] S300, filling the etched regions of the multilayer first dielectric layer and the multilayer second dielectric layer with an isolation structure.

[0071] For example, the material of the isolation structure can be the same as the material of the first dielectric layer to facilitate subsequent synchronous etching.

[0072] S400, etching stack structure, forming a first etched hole that penetrates the second part along the direction perpendicular to the substrate.

[0073] S500, based on the first etching hole, the sidewall of the second dielectric layer is etched to expose the isolation structure at least in the first direction, forming a first receiving groove.

[0074] S600, a first electrode is formed in the first receiving groove.

[0075] For example, the first electrode includes, but is not limited to, a titanium nitride layer.

[0076] S700, a sacrificial layer is formed to cover the first electrode and fill the first etched hole.

[0077] For example, the sacrificial layer includes, but is not limited to, a low-K dielectric layer.

[0078] Here, K is the dielectric constant, used to measure the ability of a material to store charge. Materials are usually classified into low-k and high-k materials according to their K value; generally, the K value of low-k materials is less than 3.0.

[0079] S800, etching the isolation structure to form a second etched hole that penetrates the isolation structure along the direction perpendicular to the substrate and is located between adjacent first electrodes along the first direction.

[0080] S900, a first dielectric layer covering the first electrode and a second electrode covering the first dielectric layer and filling the second etched hole are sequentially formed in the second etched hole.

[0081] For example, the first dielectric layer includes, but is not limited to, a high-K dielectric layer, wherein the K value of the high-K material is greater than 3.9.

[0082] For example, the second electrode includes, but is not limited to, a titanium nitride layer and a polycrystalline silicon layer stacked in a direction away from the first dielectric layer.

[0083] S1000, remove the sacrificial layer.

[0084] S1100, a second dielectric layer covering the first electrode and a third electrode covering the second dielectric layer and filling the first etched hole are sequentially formed in the first etched hole.

[0085] For example, the second dielectric layer includes, but is not limited to, a high-K dielectric layer, wherein the K value of the high-K material is greater than 3.9.

[0086] For example, the third electrode includes, but is not limited to, a titanium nitride layer and a polycrystalline silicon layer stacked in a direction away from the second dielectric layer.

[0087] Based on the above, the preparation method provided in the embodiments of this disclosure can be used to prepare a capacitor that facilitates three-dimensional stacking. The capacitor includes: a first electrode, a second electrode located outside the first electrode, and a third electrode located inside the first electrode.

[0088] In this embodiment, based on alternating layers of first dielectric layers and second dielectric layers, a stacked structure can be patterned and filled with an isolation structure. Then, by forming a first etching hole and etching the second dielectric layer to form a first receiving trench, a first electrode can be directly formed within the first receiving trench. Compared to the high aspect ratio etching process for metal thin films, this effectively reduces process difficulty and production costs.

[0089] Based on this, in this embodiment, after forming a sacrificial layer within the first etched hole, a second etched hole can be formed by etching the isolation structure between adjacent first electrodes, thereby sequentially forming a first dielectric layer and a second electrode within the second etched hole. Furthermore, after removing the sacrificial layer, a second dielectric layer and a third electrode can be sequentially formed within the first etched hole. Thus, the capacitor includes a first electrode, a second electrode located outside the first electrode, and a third electrode located inside the first electrode. This not only simplifies the capacitor fabrication process but also increases the effective electrode area in the capacitor, thereby increasing the capacitance value and improving the electrical performance of the capacitor and the electronic device.

[0090] Furthermore, in this embodiment, the first electrode is made of titanium nitride, which can avoid metal diffusion and metal oxidation problems caused by direct contact between the first electrode and the high-k dielectric layer (e.g., the first dielectric layer and the second dielectric layer), thus helping to ensure the reliability of the capacitor.

[0091] In some embodiments of this disclosure, step S600, which involves forming a first electrode within a first receiving groove, may include: forming a first electrode that fills the first receiving groove; or forming a first electrode that conformally covers the inner wall of the first receiving groove.

[0092] It is understood that the first receiving groove is obtained by widening the first etched hole, which ensures that the first electrode formed in the first receiving groove has a ring structure. Correspondingly, the first electrode filling the first receiving groove means that the inner sidewall of the first electrode ring is flush with the inner sidewall of the first etched hole, that is, they can form the same surface, which can be a plane or a curved surface. The first electrode conformally covering the inner wall of the first receiving groove means that the first electrode has a thin layer structure, and the surface of the first electrode conforms to the inner wall of the first receiving groove, so that the surface shape of the first electrode is similar to the surface shape of the inner wall of the first receiving groove.

[0093] In some embodiments of this disclosure, step S600, which forms a first electrode in a first receiving groove, may include steps S610 to S620.

[0094] S610, depositing a first electrode material layer in the first etched hole and the first receiving groove.

[0095] S620, remove the first electrode material layer on the inner wall of the first etched hole, so that the first electrode material layer retained in the first receiving groove constitutes the first electrode.

[0096] It should be added that the first receiving tank is formed by wet etching of the second dielectric layer.

[0097] In some embodiments of this disclosure, please refer to Figure 2 The method for fabricating the semiconductor structure may further include S750 after the sacrificial layer is formed and before the second etched hole is formed.

[0098] S750, remove each of the second dielectric layers retained in the stacked structure, and form a conductive layer in the area where the second dielectric layer was removed.

[0099] For example, the conductive layer includes, but is not limited to, a metallic conductive layer, such as a single layer or stack of titanium nitride or tungsten.

[0100] In this embodiment, the second dielectric layer in contact with the first electrode is replaced with a conductive layer, which may include, for example, a metallic conductive layer or a doped semiconductor conductive layer. This facilitates the fabrication of other electrical components connected to the first electrode based on this conductive layer, and allows for the reduction of contact resistance through the selection of materials for the first electrode and the conductive layer, thereby improving the electrical performance of the capacitor.

[0101] It should be added that, in some embodiments of this disclosure, the method for fabricating the semiconductor structure further includes: after forming the second etched hole and before forming the first dielectric layer, wet-removing the first dielectric layer in the target area above and below the first electrode to expose the sacrificial layer in at least the first direction and connect it to the adjacent second etched hole to form a second accommodating trench.

[0102] Accordingly, a first dielectric layer is also formed on the inner wall of the second receiving groove, and the second electrode also fills the second receiving groove.

[0103] In some embodiments of this disclosure, step S1100, in which a second dielectric layer covering the first electrode and a third electrode covering the second dielectric layer and filling the first etched hole are sequentially formed in the first etched hole, may include steps S1101 to S1103.

[0104] S1101, a second dielectric material layer is formed on the exposed surface of the first electrode away from the first dielectric layer, the exposed surface of the first dielectric layer away from the second electrode, and the top surface of the second electrode.

[0105] S1102, forming a third electrode material layer that covers the exposed surface of the second dielectric material layer and fills the first etched hole.

[0106] S1103, grind the third electrode material layer and the second dielectric material layer until the top surface of the second electrode is exposed, so that the second dielectric material layer retained in the first etched hole constitutes the second dielectric layer, and the third electrode material layer retained in the first etched hole constitutes the third electrode.

[0107] Accordingly, please continue reading Figure 2 The method for preparing the semiconductor structure further includes: S1200.

[0108] S1200, a contact layer is formed on the top surface of each second electrode and each third electrode, and the contact layer interconnects each second electrode and each third electrode.

[0109] For example, the contact layer includes, but is not limited to, a polysilicon layer.

[0110] In the embodiments disclosed above, unless otherwise expressly stated herein, the execution order of the steps in the method is not strictly limited. These steps may not necessarily be executed in the described order, but may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0111] To more clearly illustrate the fabrication methods of the semiconductor structures described in the above embodiments, the following embodiments use... Figure 2 The method shown is illustrated in detail, and please refer to it in conjunction with... Figures 3 to 20 I understand.

[0112] In step S100, please refer to Figure 3Figures (a) and (b) show a substrate 1 on which multiple layers of a first dielectric layer L1 and multiple layers of a second dielectric layer L2 are alternately formed along a direction perpendicular to the substrate (e.g., the Z direction).

[0113] For example, the first dielectric layer L1 is a silicon oxide layer. The second dielectric layer L2 is a silicon nitride layer.

[0114] For example, substrate 1 may be made of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 may be a single-layer structure or a multilayer structure. For example, substrate 1 may be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 may be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator.

[0115] For example, the number of stacked layers of the first dielectric layer L1 and the second dielectric layer L2 can be selected and set according to requirements. Furthermore, the alternating stacking of the first dielectric layer L1 and the second dielectric layer L2 can begin with the first dielectric layer L1 and end with the first dielectric layer L1. The following embodiments of this disclosure are described in detail using this as an example, but are not limited to this; for example, starting with the second dielectric layer L2 and ending with the first dielectric layer L1 is also permissible.

[0116] For example, the formation process of the first dielectric layer L1 and the second dielectric layer L2 includes, but is not limited to, chemical vapor deposition.

[0117] In step S200, please refer to Figure 4 Figures (a) and (b) show that multiple first dielectric layers L1 and multiple second dielectric layers L2 are etched along a direction perpendicular to the substrate (e.g., the Z direction) to form a stacked structure N. The stacked structure N includes a first portion N1 extending along a first direction (e.g., the Y direction) and a plurality of second portions N2 spaced apart along the first direction (e.g., the Y direction) and extending from the first portion N1 along a second direction (e.g., the X direction). The first direction (e.g., the Y direction) and the second direction (e.g., the X direction) are parallel to the substrate 1 and intersect, for example, orthogonal.

[0118] For example, the stacked structure N is patterned using a dry etching process.

[0119] For example, before etching multiple first dielectric layers L1 and multiple second dielectric layers L2 to form a stacked structure N, a hard mask layer can be formed on the top surface of the top first dielectric layer L1 to form the stacked structure N based on the mask pattern in the hard mask layer.

[0120] For example, the first part N1 in the stacked structure N can be used to define the orthographic projection shape of the bit line forming region on the substrate 1, and the second part N2 can be used to define the orthographic projection shape of the transistor and capacitor forming regions on the substrate 1. Furthermore, it can be understood that the first part N1 and the second part N2 are only divisions of the orthographic projection shape of the stacked structure N on the substrate 1, and both include the aforementioned first dielectric layer L1 and second dielectric layer L2 along the direction perpendicular to the substrate (e.g., the Z direction).

[0121] In step S300, please continue reading. Figure 4 Figures (a) and (b) show that the isolation structure 2 is filled in the etched regions of the multilayer first dielectric layer L1 and the multilayer second dielectric layer L2.

[0122] For example, the material of the isolation structure 2 can be the same as the material of the first dielectric layer L1, such as silicon oxide, to facilitate subsequent synchronous etching.

[0123] For example, after filling to form the isolation structure 2, the surface of the resulting structure can be polished using a chemical mechanical polishing process to expose the flat top layer, the first dielectric layer L1.

[0124] In step S400, please refer to Figure 5 In Figures (a) and (b), the stacked structure N is etched to form a first etch hole H1 that penetrates the second part N2 along the direction perpendicular to the substrate (e.g., the Z direction).

[0125] For example, the first etched hole H1 is formed using a dry etching process.

[0126] For example, the size of the first etched hole H1 along the first direction (e.g., the Y direction) is slightly smaller than the size of the second part N2 along the first direction (e.g., the Y direction).

[0127] In step S500, please refer to Figure 6 Figures (a), (b), and (c) show that the sidewall of the second dielectric layer L2 is etched based on the first etch hole H1 to expose the isolation structure 2 in at least the first direction (e.g., the Y direction) to form the first receiving groove G1.

[0128] For example, the first accommodating groove G1 is formed by wet etching of the second dielectric layer L2. The first accommodating groove G1 is an annular groove surrounding the first etched hole H1.

[0129] In step S600, please refer to Figure 7 Figures (a) and (b) in the text Figure 8 Figures (a) and (b) show that a first electrode 31 is formed in the first receiving groove G1.

[0130] For example, the first electrode 31 includes, but is not limited to, a titanium nitride layer.

[0131] For example, step S600, forming a first electrode 31 within the first receiving groove G1, may include: forming a first electrode 31 that fills the first receiving groove G1, for example... Figure 8 As shown in Figures (a) and (b); or, forming a first electrode 31 that conformally covers the inner wall of the first receiving groove G1, for example... Figures 16-20 As shown in Figures (a) and (b) in the text.

[0132] For example, step S600 may include steps S610 to S620.

[0133] In step S610, please refer to Figure 7 Figures (a) and (b) show that a first electrode material layer 310 is deposited in the first etched hole H1 and the first accommodating groove G1.

[0134] In step S620, please refer to Figure 8 In Figures (a) and (b), the first electrode material layer 310 on the inner wall of the first etched hole H1 is removed, so that the first electrode material layer 310 retained in the first receiving groove G1 constitutes the first electrode 31.

[0135] In step S700, please refer to Figure 9 Figures (a) and (b) show a sacrificial layer 4 forming a layer that covers the first electrode 31 and fills the first etched hole H1.

[0136] For example, sacrificial layer 4 includes, but is not limited to, a low-K dielectric layer. Here, K is the dielectric constant, used to measure the material's ability to store charge. Materials are typically classified into low-K and high-K materials based on their K value; generally, low-K materials have a K value less than 3.0.

[0137] In step S750, please continue reading. Figure 9 In Figures (a) and (b), the second dielectric layers L2 retained in the stacked structure N are removed, and a conductive layer L3 is formed in the region where the second dielectric layer L2 is removed.

[0138] For example, the conductive layer L3 includes, but is not limited to, a metallic conductive layer, such as a single layer or stack of titanium nitride or tungsten.

[0139] In some examples, the conductive layer L3 is a tungsten metal layer.

[0140] In step S800, please refer to Figure 10 In Figures (a) and (b), the isolation structure 2 is etched to form a second etched hole H2 that runs through the isolation structure 2 along a direction perpendicular to the substrate (e.g., the Z direction) and is located between adjacent first electrodes 31 along a first direction (e.g., the Y direction).

[0141] For example, the second etched hole H2 is formed using a dry etching process.

[0142] For example, after forming the second etched hole H2, the first dielectric layer L1 in the target area above and below the first electrode 31 is wet-removed to expose the sacrificial layer 4 in at least the first direction (e.g., the Y direction) and connect to the adjacent second etched hole H2 to form the second receiving groove G2.

[0143] Here, it can be understood that the first dielectric layer L1 in the target area above and below the first electrode 31 is only partially removed, that is, a wet etching process is used to expose the sidewall of the sacrificial layer 4 in the first direction (e.g., the Y direction) and connect it to the adjacent second etch hole H2.

[0144] In step S900, please refer to Figure 11 In Figures (a) and (b), a first dielectric layer 32 covering the first electrode 31 and a second electrode 33 covering the first dielectric layer 32 and filling the second etched hole H2 are sequentially formed in the second etched hole H2.

[0145] It is understood that, in the example where the second accommodating trench G2 is formed, the first dielectric layer 32 is deposited entirely within the second etched hole H2 and the second accommodating trench G2, meaning the first dielectric layer 32 also covers the inner wall of the second accommodating trench G2. Correspondingly, the second electrode 33 also fills the second accommodating trench G2.

[0146] For example, the first dielectric layer 32 includes, but is not limited to, a high-K dielectric layer, wherein the K value of the high-K material is greater than 3.9.

[0147] For example, the second electrode 33 includes, but is not limited to, a titanium nitride layer 331 and a polysilicon layer 332 stacked along a direction away from the first dielectric layer 32.

[0148] In step S1000, please refer to Figure 12 In Figures (a) and (b), sacrificial layer 4 is removed.

[0149] For example, sacrificial layer 4 can be removed by either dry etching or wet etching.

[0150] In step S1100, please refer to Figure 13 and Figure 14 In Figures (a) and (b), a second dielectric layer 34 covering the first electrode 31 and a third electrode 35 covering the second dielectric layer 34 and filling the first etched hole H1 are sequentially formed in the first etched hole H1.

[0151] For example, the second dielectric layer 34 includes, but is not limited to, a high-K dielectric layer, wherein the K value of the high-K material is greater than 3.9.

[0152] For example, the third electrode 35 includes, but is not limited to, a titanium nitride layer 351 and a polysilicon layer 352 stacked along a direction away from the second dielectric layer 34.

[0153] In some embodiments of this disclosure, step S1100 may include steps S1101 to S1103.

[0154] In step S1101, please refer to Figure 13 A second dielectric material layer 340 is formed on the exposed surface of the first electrode 31 away from the first dielectric layer 32, the exposed surface of the first dielectric layer 32 away from the second electrode 33, and the top surface of the second electrode 33.

[0155] In step S1102, please continue reading. Figure 13 A third electrode material layer is formed, which covers the exposed surface of the second dielectric material layer 340 and fills the first etched hole H1, such as a titanium nitride material layer 3510 and a polysilicon material layer 3520 formed by stacking.

[0156] In step S1103, please refer to Figure 14 In Figures (a) and (b), the third electrode material layer (including polysilicon material layer 3520 and titanium nitride material layer 3510) and the second dielectric material layer 340 are ground until the top surface of the second electrode 33 is exposed, such that the second dielectric material layer 340 retained in the first etch hole H1 constitutes the second dielectric layer 34, and the third electrode material layer retained in the first etch hole H1 constitutes the third electrode 35; for example, the titanium nitride material layer 3510 retained in the first etch hole H1 constitutes the titanium nitride layer 351, and the polysilicon material layer 3520 retained in the first etch hole H1 constitutes the polysilicon layer 352, and the third electrode 35 includes the titanium nitride layer 351 and the polysilicon layer 352.

[0157] In step S1200, please refer to Figure 15 A contact layer 36 is formed on the top surface of each second electrode 33 and each third electrode 35, and the contact layer 36 interconnects each second electrode 33 and each third electrode 35.

[0158] For example, contact layer 36 includes, but is not limited to, a polysilicon layer.

[0159] Based on the above, by using the preparation method provided in the embodiments of this disclosure, a capacitor 3 that is conducive to realizing three-dimensional stacking can be prepared. The capacitor 3 includes: a first electrode 31, a second electrode 33 located outside the first electrode 31, and a third electrode 35 located inside the first electrode 31.

[0160] It should be noted that, Figures 16-20 Taking the example of the first electrode 31 conformally covering the inner wall of the first accommodating groove G1, the subsequent steps of the semiconductor structure preparation method provided in this embodiment are illustrated. The specific steps can be adapted to the description of the aforementioned related steps, and will not be described in detail here.

[0161] This disclosure also provides a semiconductor structure in some embodiments, which can be prepared using the methods described in the above embodiments. This semiconductor structure also possesses all the technical advantages of the aforementioned preparation methods.

[0162] In some embodiments, please combine Figure 14 Figures (a) and (b) in the text Figure 20 As can be understood from Figures (a) and (b), the semiconductor structure includes: a substrate 1, a plurality of first electrodes 31, a plurality of first dielectric layers 32, a plurality of second electrodes 33, a plurality of second dielectric layers 34, and a plurality of third electrodes 35.

[0163] In some examples, a plurality of first electrodes 31 are spaced apart along a first direction (e.g., the Y direction) parallel to the substrate 1. The first electrodes 31 are in a ring-shaped structure and the axial direction of the ring structure is perpendicular to the substrate 1 (e.g., extending along the Z direction).

[0164] For example, multiple first electrodes 31 are stacked in three dimensions along a direction perpendicular to the substrate (e.g., the Z direction).

[0165] For example, the orthographic projection shape of the first electrode 31 on the substrate 1 is rectangular, circular, or elliptical, etc.

[0166] For example, the first electrode 31 includes, but is not limited to, a titanium nitride layer.

[0167] In some examples, the first dielectric layer 32 covers the inner sidewall of the first electrode 31 and extends to the surface of the substrate 1 in a cup-shaped structure along a direction perpendicular to the substrate (e.g., the Z direction). The second electrode 33 covers the surface of the first dielectric layer 32 opposite to the first electrode 31 and fills the cup-shaped region of the first dielectric layer 32.

[0168] Here, matching the sidewall shape of the first electrode 31, the inner and / or outer sides of the cup wall of the first dielectric layer 32 can be a flat surface or a non-flat surface with protrusions and depressions to fit into the first electrode 31 (e.g., Figure 14 and Figure 20 (as shown in the image).

[0169] In some examples, the second dielectric layer 34 is located between two adjacent first electrodes 31 along a first direction (e.g., the Y direction), covers the outer sidewall of the corresponding first electrode 31, and extends along a direction perpendicular to the substrate (e.g., the Z direction) to cover the surface of the first dielectric layer 32 opposite to the second electrode 33, and extends to the surface of the substrate 1 in a cup-shaped structure. The third electrode 35 covers the surface of the second dielectric layer 34 opposite to the first electrode 31 and fills the cup region of the second dielectric layer 34.

[0170] Here, matching the sidewall shape of the first electrode 31, the inner and / or outer sides of the cup wall of the second dielectric layer 34 can be flat surfaces (e.g., Figure 14 (as shown) or a non-flat surface with protrusions and depressions to engage with the first electrode 31 (e.g. Figure 20 (as shown in the image).

[0171] For example, both the first dielectric layer 32 and the second dielectric layer 34 include, but are not limited to, a high-k dielectric layer. The material of the high-k dielectric layer can be selected and set according to requirements, and this disclosure does not limit this aspect.

[0172] For example, the second electrode 33 includes, but is not limited to, a titanium nitride layer 331 and a polysilicon layer 332 stacked along a direction away from the first dielectric layer 32.

[0173] For example, the third electrode 35 includes, but is not limited to, a titanium nitride layer 351 and a polysilicon layer 352 stacked in a direction away from the second dielectric layer 35.

[0174] In some embodiments, please combine Figure 15 The semiconductor structure also includes a contact layer 36. The contact layer 36 is located on the top surface of each second electrode 33 and each third electrode 35, and interconnects the second electrode 32 and the third electrode 35. This facilitates the fabrication and utilization of the contact layer 36 to achieve interconnection between the second electrode 33 and the third electrode 35.

[0175] For example, contact layer 36 includes, but is not limited to, a polysilicon layer.

[0176] In summary, the structure of the capacitor 3 and the material of the first electrode 31 in the capacitor 3 have been optimized in this embodiment. Based on the thin film stack structure of the first dielectric layer L1 and the second dielectric layer L2, the second dielectric layer L2 can be selectively replaced with the first electrode 31 and the corresponding conductive layer L3, thereby avoiding the process complexity caused by the high aspect ratio etching of the metal film structure, which is beneficial to simplifying the process and reducing costs. Furthermore, the capacitor 3 provided by this embodiment reduces the implementation of the lateral etching process of the first dielectric layer L1, and also helps to provide stable process mechanical properties and support properties during the fabrication of the capacitor 3, thereby improving the process yield.

[0177] Furthermore, in this embodiment, the first electrode 31 of the capacitor 3 is made of titanium nitride, which avoids using a metallic element such as tungsten as the first electrode 31 in contact with the high-k dielectric layer, thereby avoiding the risk of metal diffusion and metal oxidation, and helping to ensure the reliability of the capacitor 3. In this embodiment, the first electrode 31 of the capacitor 3 adopts a ring structure, and the first dielectric layer 32 and the second dielectric layer 34 adopt a cup structure. It is also beneficial to have surrounding outer electrodes (i.e., the second electrode 33 and the third electrode 35) on both the inner and outer sides of the first electrode 31, so as to improve the capacitance value of the capacitor 3, for example, effectively improving the storage performance of the capacitor 3.

[0178] This disclosure also provides an electronic device, such as a data storage device, a photocopier, a network device, a home appliance, an instrument, a mobile phone, a computer, or other devices with data storage capabilities. The electronic device may include a housing and a circuit board disposed within the housing, and a memory integrated on the circuit board. The memory includes multiple storage units, and each storage unit includes a capacitor. The structure of the capacitor and its fabrication method can be found in the relevant descriptions in the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in this disclosure.

[0179] In some embodiments, the memory may be coupled to an external control device such as a processor or actuator. The processor is coupled to the memory, and the processor is able to control the read and write operations of the memory.

[0180] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0181] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, and alternately forming a plurality of layers of first dielectric layers and a plurality of layers of second dielectric layers on the substrate along a vertical substrate direction; etching the plurality of layers of first dielectric layers and the plurality of layers of second dielectric layers along the vertical substrate direction to form a stack structure; the stack structure comprises a first part extending along a first direction and a plurality of second parts spaced apart along the first direction and extending from the first part along a second direction; the first direction and the second direction are parallel to the substrate and intersect each other; filling an isolation structure in the etching region of the plurality of layers of first dielectric layers and the plurality of layers of second dielectric layers; etching the stack structure to form a first etching hole penetrating the second part along the vertical substrate direction; etching the sidewall of the second dielectric layer based on the first etching hole to expose the isolation structure at least in the first direction and form a first accommodation groove; forming a first electrode in the first accommodation groove; forming a sacrificial layer covering the first electrode and filling the first etching hole; etching the isolation structure to form a second etching hole penetrating the isolation structure along the vertical substrate direction and located between adjacent first electrodes along the first direction; sequentially forming a first dielectric layer covering the first electrode and a second electrode covering the first dielectric layer and filling the second etching hole in the second etching hole; removing the sacrificial layer; sequentially forming a second dielectric layer covering the first electrode and a third electrode covering the second dielectric layer and filling the first etching hole in the first etching hole; wherein the capacitor comprises the first electrode, the second electrode located outside the first electrode, and the third electrode located inside the first electrode.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The step of forming a first electrode in the first accommodation groove comprises: forming the first electrode to fill the first accommodation groove; or, forming the first electrode to conformally cover the inner wall of the first accommodation groove.

3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The step of forming a first electrode in the first accommodation groove comprises: depositing a first electrode material layer in the first etching hole and the first accommodation groove; removing the first electrode material layer on the inner wall of the first etching hole, so that the first electrode material layer remaining in the first accommodation groove constitutes the first electrode.

4. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The first accommodation groove is formed by wet etching the second dielectric layer.

5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Further comprising: after forming the sacrificial layer and before forming the second etching hole, removing each of the second dielectric layers remaining in the stack structure, and forming a conductive layer in the removed region of the second dielectric layer.

6. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Further comprising: after forming the second etching hole and before forming the first dielectric layer, wet-removing the first dielectric layer in the target region on and under the first electrode to expose the sacrificial layer at least in the first direction and connect adjacent second etching holes, forming a second accommodation groove; wherein the first dielectric layer is also formed on the inner wall of the second accommodation groove, and the second electrode also fills the second accommodation groove.

7. The method of claim 6, wherein the semiconductor structure is prepared by a method comprising: The step of sequentially forming a second dielectric layer covering the first electrode and a third electrode covering the second dielectric layer and filling the first etching hole in the first etching hole comprises: forming a second dielectric material layer on exposed surfaces of the first electrode away from the first dielectric layer, exposed surfaces of the first dielectric layer away from the second electrode, and a top surface of the second electrode; forming a third electrode material layer covering exposed surfaces of the second dielectric material layer and filling the first etching holes; polishing the third electrode material layer and the second dielectric material layer to expose the top surface of the second electrode, so that the second dielectric material layer remaining in the first etching holes forms the second dielectric layer, and the third electrode material layer remaining in the first etching holes forms the third electrode; wherein the preparation method further comprises forming a contact layer on top surfaces of each of the second electrodes and each of the third electrodes, the contact layer interconnecting each of the second electrodes and each of the third electrodes.

8. The method of producing a semiconductor structure according to any one of claims 1 to 7, wherein The first dielectric layer comprises an oxide layer, the second dielectric layer comprises a nitride layer, and the sacrificial layer comprises a low-K dielectric layer.

9. A semiconductor structure, characterized by comprising a substrate; a plurality of first electrodes spaced apart along a first direction parallel to the substrate; the first electrodes have a ring structure and the axis direction of the ring structure is perpendicular to the substrate; a plurality of first dielectric layers; the first dielectric layers cover inner sidewalls of the first electrodes and extend to the substrate surface in a direction perpendicular to the substrate to form a cup structure; a plurality of second electrodes; the second electrodes cover surfaces of the first dielectric layers away from the first electrodes and fill inner regions of the cups of the first dielectric layers; a plurality of second dielectric layers; the second dielectric layers are located between two first electrodes adjacent in the first direction, cover outer sidewalls of the first electrodes, and extend to cover surfaces of the first dielectric layers away from the second electrodes in a direction perpendicular to the substrate, and extend to the substrate surface to form a cup structure; a plurality of third electrodes; the third electrodes cover surfaces of the second dielectric layers away from the first electrodes and fill inner regions of the cups of the second dielectric layers.

10. The semiconductor structure of claim 9, wherein, further comprising: a contact layer on top surfaces of each of the second electrodes and each of the third electrodes, and interconnecting the second electrodes and the third electrodes.

11. The semiconductor structure of claim 10, wherein the first dielectric layer and the second dielectric layer each comprise a high-K dielectric layer; the first electrode comprises a titanium nitride layer; the second electrode and the third electrode each comprise a titanium nitride layer and a polysilicon layer stacked in a direction away from the corresponding dielectric layer.

12. An electronic device comprising the semiconductor structure of any one of claims 9-11.

Images