Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the technical field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a first doped structure having a first part, a second part and a third part arranged in sequence along a first direction; a second doped structure and a third doped structure arranged at intervals, the second doped structure being in contact with the first part, and the third doped structure being in contact with the third part; wherein one of N-type doping ions and P-type doping ions is doped in the first doped structure, the other of the N-type doping ions and the P-type doping ions is doped in the second doped structure and the third doped structure, and two first doped structures adjacent along a second direction are in contact with the same third doped structure; and a gate structure having a first surface and a second surface opposite along the second direction, at least the first surface being in contact with the second part, and the second direction intersecting the first direction. The embodiment of the present disclosure is at least beneficial to improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a memory device used to store programs and various data. DRAM typically includes capacitors and transistors connected to the capacitors. The capacitors store electrical charge representing the stored programs and data, while the transistors control the inflow and outflow of charge from the capacitors. When writing data, the word line is given a high level, the transistor turns on, and the bit line charges the capacitor. When reading data, the word line is also given a high level, the transistor turns on, the capacitor discharges, and the bit line receives the read signal.

[0003] However, with the continuous development of semiconductor manufacturing processes, the process nodes of semiconductor structures are constantly shrinking, leading to a gradual reduction in the size of each functional structure within the semiconductor structure, as well as a gradual reduction in the spacing between these functional structures. For example, the reduced spacing between capacitors and bit lines located on the same side of a transistor can easily increase the coupling effect between the capacitors and bit lines, resulting in a decrease in the electrical performance of the semiconductor structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the same, which at least helps to improve the electrical performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a first doped structure having a first portion, a second portion, and a third portion arranged sequentially along a first direction; a second doped structure and a third doped structure spaced apart, the second doped structure being contacted and connected to the first portion, and the third doped structure being contacted and connected to the third portion; wherein the first doped structure is doped with one of N-type dopant ions and P-type dopant ions, the second doped structure and the third doped structure are doped with the other of N-type dopant ions and P-type dopant ions, and two adjacent first doped structures along a second direction are contacted and connected to the same third doped structure, the second direction intersecting the first direction; a gate structure having a first surface and a second surface opposite to each other along the second direction, at least the first surface or the second surface being contacted and connected to the second portion.

[0006] In some embodiments, only the first side or only the second portion of the second side of the gate structure is contacted and connected.

[0007] In some embodiments, the gate structure has a third surface and a fourth surface opposite each other along the first direction, at least a portion of the third surface is also in contact with the second portion, and at least a portion of the fourth surface is also in contact with the second portion.

[0008] In some embodiments, the gate structure has a third and a fourth surface opposite each other along the first direction, and the second and the fourth surfaces are also in contact with the second portion.

[0009] In some embodiments, the semiconductor structure further includes an isolation layer that is in contact with the third surface, and both the isolation layer and the gate structure are embedded in the first doped structure.

[0010] In some embodiments, the semiconductor structure further includes an active region, the active region including two first doped structures adjacent to each other along the second direction, and two gate structures that are contacted and connected to the two first doped structures are spaced apart from each other and are both located in the active region.

[0011] In some embodiments, at least a portion of the second doped structure is embedded in the first portion, and / or at least a portion of the third doped structure is embedded in the third portion.

[0012] In some embodiments, a plurality of first doped structures and a plurality of second doped structures are arranged at intervals along a third direction upward, and the first doped structures, the second doped structures and the gate structure arranged at intervals along the third direction correspond one-to-one; the third doped structure extends along the third direction, and each of the third doped structures is in contact with and connected to a plurality of first doped structures arranged at intervals along the third direction, and the first direction, the second direction and the third direction intersect each other.

[0013] In some embodiments, a plurality of first doped structures, a plurality of second doped structures, and a plurality of third doped structures are arranged at intervals along a third direction upward, and the first doped structures, second doped structures, third doped structures, and gate structures arranged at intervals along the third direction correspond one-to-one; the semiconductor structure further includes a conductive layer extending along the third direction, and the same conductive layer is in contact with the plurality of third doped structures arranged at intervals along the third direction.

[0014] In some embodiments, the gate structure is in contact with the third doped structure.

[0015] In some embodiments, the semiconductor structure further includes a substrate, wherein the first doped structure, the second doped structure, the third doped structure and the gate structure are all located in the substrate.

[0016] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing an initial substrate; performing doping treatment on different portions of the initial substrate using different doping processes to form a first doped structure, a second doped structure, and a third doped structure; wherein the first doped structure has a first portion, a second portion, and a third portion arranged sequentially along a first direction; the second doped structure and the third doped structure are spaced apart, the second doped structure is in contact with the first portion, and the third doped structure is in contact with the third portion; the first doped structure is doped with one of N-type dopant ions and P-type dopant ions, and the second doped structure and the third doped structure are doped with the other of N-type dopant ions and P-type dopant ions; two adjacent first doped structures along a second direction are in contact with the same third doped structure, the second direction intersecting the first direction; forming a gate structure, the gate structure having a first surface and a second surface opposite each other along the second direction, at least the first surface being in contact with the second portion, and the gate structure being in contact with the third doped structure.

[0017] In some embodiments, the initial substrate has a front side and a back side opposite each other along the first direction; the steps of forming the second doped structure and the third doped structure include: performing a first doping treatment on a portion of the initial substrate to form a plurality of initial first doped structures spaced apart, the initial first doped structures extending from the front side into the interior of the initial substrate, the initial first doped structures also extending along a fourth direction, the initial first doped structures having a fourth portion, a fifth portion and a sixth portion arranged sequentially along the fourth direction; performing a second doping treatment on both the fourth portion and the sixth portion, such that a portion of the thickness of the fourth portion is transformed into a second doped structure along the first direction, and a portion of the thickness of the sixth portion is transformed into another second doped structure, the second doped structures extending from the front side into the interior of the initial substrate; patterning the initial substrate from the back side to expose at least a portion of the fifth portion; and performing a third doping treatment on the exposed fifth portion to form the third doped structure.

[0018] In some embodiments, a plurality of the fifth portions are spaced apart along a third direction upward, and the first direction, the second direction, and the third direction intersect each other; the patterning of the initial substrate from the back side includes: patterning the initial substrate from the back side to form a trench extending along the third direction, and the trench exposes a plurality of the fifth portions spaced apart along the third direction upward; the third doping of the exposed fifth portions includes: performing the third doping on the fifth portions exposed by the trench to form a third doped structure extending along the third direction; the manufacturing method further includes: forming a first electrical connection layer, the first electrical connection layer filling the trench.

[0019] In some embodiments, a plurality of the fifth portions are spaced apart along a third direction upward, and the first direction, the second direction, and the third direction intersect each other; the patterning of the initial substrate from the back side includes: patterning the initial substrate from the back side to form a plurality of vias spaced apart along the third direction upward, and one of the vias exposes one of the fifth portions; the third doping of the exposed fifth portions includes: performing the third doping on the fifth portions exposed by the vias to form a plurality of third doped structures spaced apart along the third direction upward; the manufacturing method further includes: forming conductive pillars that fill the vias, and the conductive pillars and vias corresponding one-to-one; forming a second electrical connection layer extending along the third direction, and the same second electrical connection layer being in contact with the plurality of conductive pillars spaced apart along the third direction upward.

[0020] The technical solutions provided in this disclosure have at least the following advantages:

[0021] The first and third parts are arranged at intervals along the first direction, and the second and third doped structures are arranged at intervals. The second doped structure is in contact with the first part, and the third doped structure is in contact with the third part. The second part is located between the first and third parts, and the gate structure is in contact with the second part. Thus, the second and third doped structures can be regarded as located on opposite sides of the gate structure along the first direction. That is, with a plane parallel to the first direction as the reference plane, the second and third doped structures are not directly opposite each other, that is, the orthogonal projections of the second and third doped structures on the reference plane do not overlap, so as to increase the spacing between the second and third doped structures, thereby helping to reduce the coupling effect between the second and third doped structures. Furthermore, by making the first conductive structure on the side of the second and third doped structures away from the gate structure and the second conductive structure on the side of the other doped structure away from the gate structure, it is beneficial to avoid the first and second conductive structures being directly opposite each other, thereby helping to reduce the coupling effect between the first and second conductive structures and improving the electrical performance of the semiconductor structure.

[0022] Furthermore, it is understandable that the first doped structure, the second doped structure, the third doped structure, and the gate structure together constitute a transistor structure. The second and third doped structures are not in direct contact, but they are each connected to the first doped structure. That is, one of the second and third doped structures can serve as the source of the transistor, and the other as the drain. A portion of the first doped structure can serve as the channel region of the transistor, and the gate structure controls the conduction or cutoff of the channel region. Two adjacent first doped structures along the second direction are connected to the same third doped structure, meaning two adjacent transistor structures along the second direction share a single third doped structure. This is beneficial for increasing the integration density of transistor structures in the semiconductor structure. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figures 1 to 4 Four partial cross-sectional structural diagrams of a semiconductor structure provided in an embodiment of this disclosure;

[0025] Figure 5 A top view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0026] Figure 6 and Figure 7 Two other partial cross-sectional structural diagrams of a semiconductor structure provided in an embodiment of this disclosure;

[0027] Figure 8 and Figure 9 Two other top view schematic diagrams of a semiconductor structure provided in one embodiment of this disclosure;

[0028] Figure 10 This is a partial cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure.

[0029] Figures 11 to 19 This is a cross-sectional structural diagram corresponding to each step in a method for manufacturing a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0030] As can be seen from the background technology, the electrical performance of semiconductor structures needs to be improved.

[0031] This disclosure provides a semiconductor structure and its manufacturing method. In the semiconductor structure, the second doped structure and the third doped structure can be considered as located on opposite sides of the gate structure along the first direction X, i.e., using a plane parallel to the first direction X as a reference plane. The second doped structure and the third doped structure are not directly opposite each other, meaning their orthogonal projections on the reference plane do not overlap, thereby increasing the spacing between them. This helps reduce the coupling effect between the second and third doped structures. Furthermore, when conductive structures are fabricated on one side of the gate structure of the second and third doped structures respectively, it helps avoid the two conductive structures being directly opposite each other, thus further reducing the coupling effect and improving the electrical performance of the semiconductor structure. Moreover, the first doped structure, the second doped structure, the third doped structure, and the gate structure together constitute a transistor structure. Two adjacent first doped structures along the second direction are connected to the same third doped structure, meaning two adjacent transistor structures along the second direction share a single third doped structure. This helps increase the integration density of the transistor structure in the semiconductor structure.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] This disclosure provides a semiconductor structure according to an embodiment. The semiconductor structure provided by this disclosure will be described in detail below with reference to the accompanying drawings. Figures 1 to 4 Four partial cross-sectional structural diagrams of a semiconductor structure provided in an embodiment of this disclosure; Figure 5 A top view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 6 and Figure 7 Two other partial cross-sectional structural diagrams of a semiconductor structure provided in an embodiment of this disclosure; Figure 8 and Figure 9 Two other top view schematic diagrams of a semiconductor structure provided in one embodiment of this disclosure; Figure 10 This is a partial cross-sectional view of a semiconductor structure provided in one embodiment of the present disclosure. It should be noted that, for ease of description and clear illustration of the semiconductor structure, the semiconductor structure in one embodiment of the present disclosure... Figures 1 to 10 These are partial structural diagrams of semiconductor structures.

[0034] refer to Figures 1 to 4 The semiconductor structure may include: a first doped structure 101 having a first portion 111, a second portion 121, and a third portion 131 arranged sequentially along a first direction X; a second doped structure 102 and a third doped structure 103 spaced apart, the second doped structure 102 being contacted and connected to the first portion 111, and the third doped structure 103 being contacted and connected to the third portion 131; wherein the first doped structure 101 is doped with one of N-type dopant ions and P-type dopant ions, the second doped structure 102 and the third doped structure 103 are doped with the other of N-type dopant ions and P-type dopant ions, and two adjacent first doped structures 101 along the second direction Y are contacted and connected to the same third doped structure 103, the second direction Y intersects the first direction X; and a gate structure 104 having a first surface 114 and a second surface 124 opposite to each other along the second direction Y, at least the first surface 114 or the second surface 124 being contacted and connected to the second portion 121.

[0035] In some embodiments, the first doped structure 101 may be doped with P-type dopant ions, and the second doped structure 102 and the third doped structure 103 may be doped with N-type dopant ions; in other embodiments, the first doped structure 101 may be doped with N-type dopant ions, and the second doped structure 102 and the third doped structure 103 may be doped with P-type dopant ions.

[0036] It should be noted that, for ease of description, the following explanation will use the example of the first doped structure 101 being doped with P-type dopant ions, and the second doped structure 102 and the third doped structure 103 being doped with N-type dopant ions.

[0037] In some embodiments, N-type dopant ions may include at least one of arsenic ions, phosphorus ions, or antimony ions; P-type dopant ions may include at least one of boron ions, indium ions, or gallium ions.

[0038] It is understood that the first doped structure 101, the second doped structure 102, the third doped structure 103, and the gate structure 104 together constitute a transistor structure. The second doped structure 102 and the third doped structure 103 are not in direct contact, but they are each connected to the first doped structure 101. That is, one of the second doped structure 102 and the third doped structure 103 can serve as the source of the transistor structure, and the other can serve as the drain. A portion of the first doped structure 101 can serve as the channel region of the transistor structure, and the gate structure 104 controls the conduction or cutoff of the channel region. It should be noted that, for ease of description, the following explanation will use the second doped structure 102 as the drain and the third doped structure 103 as the source of the transistor structure as an example.

[0039] Thus, two adjacent first doped structures 101 along the second direction Y are connected to the same third doped structure 103, that is, two adjacent transistor structures along the second direction Y share a third doped structure 103, which is beneficial to improving the integration density of transistor structures in semiconductor structures.

[0040] It should be noted that in the gate structure 104, at least the first surface 114 is in contact with the second part 121. The relative positional relationship between the gate structure 104 and the second part 121 will be explained in detail later.

[0041] It is understood that the first part 111 and the third part 131 are arranged at intervals along the first direction X, and the second doped structure 102 and the third doped structure 103 are arranged at intervals. The second doped structure 102 is in contact with the first part 111, and the third doped structure 103 is in contact with the third part 131. The second part 121 is located between the first part 111 and the third part 131, and the gate structure 104 is in contact with the second part 121. Thus, the second doped structure 102 and the third doped structure 103 can be regarded as located on opposite sides of the gate structure 104 along the first direction X. That is, with a plane parallel to the first direction X as the reference plane, the second doped structure 102 and the third doped structure 103 are not directly opposite each other. That is, the orthogonal projections of the second doped structure 102 and the third doped structure 103 on the reference plane do not overlap, so as to increase the spacing between the second doped structure 102 and the third doped structure 103, thereby helping to reduce the coupling effect of the second doped structure 102 and the third doped structure 103 on each other. Furthermore, by making the first conductive structure on the side of one of the second doped structure 102 and the third doped structure 103 away from the gate structure 104, and making the second conductive structure on the side of the other away from the gate structure 104, it is beneficial to avoid the first conductive structure and the second conductive structure being directly opposite each other, thereby reducing the coupling effect between the first conductive structure and the second conductive structure and improving the electrical performance of the semiconductor structure.

[0042] In some embodiments, the first conductive structure can be a capacitor structure and the second conductive structure can be a bit line structure. The bit line structure and the capacitor structure will be described in detail later.

[0043] The following description, in conjunction with the accompanying drawings, will provide a more detailed account of an embodiment of this disclosure.

[0044] In some embodiments, reference Figures 1 to 4 The gate structure 104 may include a gate dielectric layer 154 and a gate 164, wherein the gate dielectric layer 154 is located between the gate 164 and the second portion 121. It is understood that regardless of the positional relationship between the gate 164 and the second portion 121, the gate dielectric layer 154 is spaced between the gate 164 and the second portion 121.

[0045] In some embodiments, the gate dielectric layer 154 may be made of a material with a high relative permittivity, such as silicon oxide, hafnium oxide, or zirconium oxide.

[0046] In some embodiments, the material of the gate 164 may be a metallic material, such as titanium, tungsten or copper, or the material of the gate 164 may be a compound material such as titanium nitride.

[0047] The positional relationship between the gate structure 104 and the second part 121 includes at least the following embodiments.

[0048] In some embodiments, reference Figure 1 In the gate structure 104, only the first surface 114 is in contact with the second portion 121. In other embodiments, reference continues to... Figure 1 In the gate structure 104, only the second surface 124 is in contact with the second portion 121. It can be understood that, along the second direction Y, only one surface of the gate structure 104 is in contact with the second portion 121, that is, the gate dielectric layer 154 is located on the surface of the second portion 121 and is not embedded in the second portion 121, the gate 164 is located on the side of the gate dielectric layer 154 away from the second portion 121, and the gate dielectric layer 154 is at least located between the third doped structure 103 and the gate 164.

[0049] It should be noted that, Figure 1 Figure 1a is a partial cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure. Figure 1 Figure 1b is a cross-sectional schematic diagram of the two gate structures 104 shown in Figure 1a. It can be understood that, depending on the change in the relative positional relationship between the gate structure 104 and the second part 121, the gate dielectric layer 154 in the gate structure 104 can form either the first surface 114 or the second surface 124.

[0050] In some embodiments, continue to refer to Figure 1 Based on the contact connection between two adjacent first doped structures 101 along the second direction Y and the same third doped structure 103, two gate structures 104 corresponding to two adjacent second portions 121 along the second direction Y can both be located between the two second portions 121, and the two gate structures 104 are spaced apart from each other. For example, the two adjacent first doped structures 101 along the second direction Y can be divided into A and B. The gate structure 104 contacted with A is considered as C, and the gate structure 104 contacted with B is considered as D. Along the second direction Y, C is located on the side of A closer to B, and D is located on the side of B closer to A. That is, the first surface 114 of C is contacted with the second portion 121, and the second surface 124 of D is contacted with the second portion 121.

[0051] In practical applications, along the second direction Y, with C located on the side of A closer to B, D can also be located on the side of B farther from A, with only one C between A and B. In other words, both C and D are connected by the first surface 114 and the second part 121.

[0052] In other embodiments, reference is made to... Figure 2Based on the contact connection between the first surface 114 or the second surface 124 and the second portion 121 in the gate structure 104, the gate structure 104 has a third surface 134 and a fourth surface 144 opposite to each other along the first direction X. At least a portion of the third surface 134 is also in contact with the second portion 121, and at least a portion of the fourth surface 144 is also in contact with the second portion 121. It can be understood that the gate dielectric layer 154 forms a first groove with an opening facing the second direction Y. The outer wall of the first groove is in contact with the second portion 121, the inner wall of the first groove is in contact with the gate 164, and the gate 164 fills the first groove.

[0053] It should be noted that, Figure 2 In example 2a, the entire third surface 134 and the entire fourth surface 144 are in contact with the second portion 121, meaning the gate structure 104 is entirely embedded in the second portion 121, and the second portion 121 exposes either the first surface 114 or the second surface 124. In practical applications, a portion of the third surface 134 may be in contact with the second portion 121, and a portion of the fourth surface 144 may also be in contact with the second portion 121, meaning a portion of the gate structure 104 is embedded within the second portion 121. Furthermore, Figure 2 2a is a schematic diagram of another partial cross-sectional structure of a semiconductor structure provided in an embodiment of this disclosure. Figure 2 Figure 2b is a cross-sectional schematic diagram of the two gate structures 104 shown in Figure 2a.

[0054] In some embodiments, continue to refer to Figure 2 Based on the fact that two adjacent first doped structures 101 along the second direction Y are in contact with the same third doped structure 103, two gate structures 104 corresponding to two adjacent second portions 121 along the second direction Y can both be located between the two second portions 121, and the two gate structures 104 are spaced apart from each other. For example, the two adjacent first doped structures 101 along the second direction Y are divided into A and B. The gate structure 104 in contact with A is regarded as C, and the gate structure 104 in contact with B is regarded as D. Along the second direction Y, C is located on the side of A closer to B, and D is located on the side of B closer to A. That is, the first surface 114, at least part of the third surface 134, and at least part of the fourth surface 144 of C are all in contact with the second portion 121, and the second surface 124, at least part of the third surface 134, and at least part of the fourth surface 144 of D are all in contact with the second portion 121.

[0055] In practical applications, along the second direction Y, with C located on the side of A closer to B, D can also be located on the side of B farther from A, with only one C between A and B. In other words, both C and D have the first surface 114, at least a portion of the third surface 134, and at least a portion of the fourth surface 144 in contact with the second portion 121.

[0056] In yet other embodiments, reference is made to Figure 3 and Figure 4 Based on the contact connection between the first surface 114 or the second surface 124 and the second portion 121 in the gate structure 104, the gate structure 104 has a third surface 134 and a fourth surface 144 opposite to each other along the first direction X. The second surface 124 and the fourth surface 144 are also contacted and connected to the second portion 121, that is, the entire gate structure 104 is embedded in the second portion 121. It can be understood that the gate dielectric layer 154 forms a second groove with an opening facing the first direction X. The outer wall of the second groove is contacted and connected to the second portion 121, and the inner wall of the second groove is contacted and connected to the gate 164, and the gate 164 fills the second groove.

[0057] It should be noted that, Figure 3 Figure 3a is a partial cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure. Figure 3 Figure 3b is a cross-sectional view of any gate structure 104 shown in Figure 3a.

[0058] In some embodiments, continue to refer to Figure 3 and Figure 4 The semiconductor structure may further include: an isolation layer 105, which is in contact with the third surface 134, and both the isolation layer 105 and the gate structure 104 are embedded in the first doped structure 101.

[0059] In some embodiments, the material of the isolation layer 105 may be a dielectric material such as silicon nitride, silicon oxynitride, or silicon carbonitride.

[0060] In some embodiments, reference Figure 4 The semiconductor structure may further include an active region 106, which includes two first doped structures 101 adjacent to each other along the second direction Y, and two gate structures 104 that are in contact with the two first doped structures 101 are spaced apart from each other and are both located in the active region 106.

[0061] It should be noted that, Figure 4 The approximate regions of the two first doped structures 101 in the active region 106 are defined by boxes I and II, respectively. In practical applications, the active region 106 is an integral structure. To facilitate the description of the positional relationship between different second doped structures 102, different gate structures 104 and third doped structures 103 in the active region 106, the active region 106 is divided to identify the two first doped structures 101.

[0062] It is understood that when the active region 106 includes two adjacent first doped structures 101 along the second direction Y, it means that both adjacent first doped structures 101 along the second direction Y are portions of the active region 106. (Refer to the reference...) Figure 4 andFigure 5 An active region 106 corresponds to two second doped structures 102, two gate structures 104, and one third doped structure 103. One second doped structure 102, one gate structure 104, and the third doped structure 103 constitute a transistor structure, and another second doped structure 102, another gate structure 104, and the third doped structure 103 constitute another transistor structure. That is, one active region 106 corresponds to two transistor structures.

[0063] It should be noted that, Figure 5 Figure 5a is a top view schematic diagram showing the relative positional relationship between the active region 106, the bit line structure BL, and the word line structure WL in the semiconductor structure. Figure 5 5b is a top view of any active region 106 shown in 5a and its two corresponding second doped structures 102. Figure 4 For along Figure 5 The semiconductor structure shown in Figure 5a is a partial cross-sectional view along the first cross-sectional direction AA1, where the first cross-sectional direction AA1 is the second direction Y, i.e., the extension direction U of the active region 106. It can be understood that... Figure 5 The bit line structure BL and word line structure WL drawn in the image are only to show the relative positions of the bit line structure BL, word line structure WL, and active region 106 in the top view. Figure 5 There are no restrictions on the internal structure of the bit line structure BL and the word line structure WL, nor are there any restrictions on the three-dimensional positional relationship between the bit line structure BL, the word line structure WL, and the active region 106. Furthermore, to clearly illustrate the relative positional relationship of the active region 106, the bit line structure BL, and the word line structure WL in the top view, perspective drawing is used for both the word line structure WL and the active region 106. Moreover, for ease of illustration, Figure 5 The third doped structure 103 and the gate structure 104 embedded in the active region 106 are not shown in the figure.

[0064] In some embodiments, a shallow trench isolation structure (not shown) is provided between adjacent active regions 106.

[0065] In some embodiments, the bit line structure BL extends in a third direction Z, and the word line structure WL extends in a fifth direction V. (See reference) Figure 5In section 5a, multiple active regions 106 are not only spaced apart along the third direction Z and the fifth direction V, but adjacent groups of active regions spaced apart along the fifth direction V are staggered along the third direction Z. The extension direction U, the first direction X, and the second direction Y of the active region 106 intersect each other, and the extension direction U, the third direction Z, and the fifth direction V are located in the same plane. It can be understood that the multiple active regions 106 spaced apart along the third direction Z are considered as a column, and adjacent columns along the fifth direction V are staggered, with the arrangement of two columns spaced apart being the same.

[0066] It should be noted that in practical applications, multiple active regions can also be arranged along the third direction Z and the fifth direction V, or in other arrangements. The arrangement of multiple active regions can be adjusted according to actual needs, and no limitation is made here. For ease of explanation, multiple active regions 106 will be used in the following examples. Figure 5 The arrangement shown in 5a is provided as an example for detailed explanation.

[0067] In some embodiments, in conjunction with reference Figure 4 and Figure 5 The word line structure WL includes a plurality of gate structures 104 spaced apart along the third direction Z and an isolation layer 105 located on the gate structures 104. In other embodiments, the plurality of gate structures 104 spaced apart along the third direction Z can be an integral structure extending along the third direction Z, that is, a plurality of active regions 106 spaced apart along the third direction Z share a single gate structure 104. In this case, the isolation layer 105 is also an integral structure extending along the third direction Z.

[0068] In some embodiments, reference Figures 1 to 4 At least a portion of the second doped structure 102 is embedded in the first portion 111. It should be noted that... Figures 1 to 4 In the example, the second doped structure 102 along the entire thickness of the first direction X is embedded in the first part 111. In practical applications, the second doped structure 102 along a portion of the thickness of the first direction X can also be embedded in the first part 111.

[0069] In some embodiments, reference Figures 1 to 4 At least a portion of the third doped structure 103 is embedded in the third portion 131. It should be noted that... Figures 1 to 4 In the example, the third doped structure 103 along the entire thickness of the first direction X is embedded in the third part 131. In practical applications, the third doped structure 103 along a portion of the thickness of the first direction X can also be embedded in the third part 131.

[0070] It should be noted that the division of the first part 111, the second part 121 and the third part 131 in the first doped structure 101 is related to the relative positions of the second doped structure 102, the gate structure 104 and the third doped structure 103 with the first doped structure 101. The part of the first doped structure 101 that is at least in contact with the second doped structure 102 is regarded as the first part 111, the part that is at least in contact with the third doped structure 103 is regarded as the third part 131, and the remaining part of the first doped structure 101 is regarded as the second part 121.

[0071] In some embodiments, reference Figures 2 to 4 The gate structure 104 can be contacted and connected to the third doped structure 103.

[0072] In some embodiments, the gate structure 104 may include a gate dielectric layer 154 and a gate 164, and the third doped structure 103 is only in contact with the gate dielectric layer 154, that is, the gate 164 and the third doped structure 103 are at least separated by the gate dielectric layer 154.

[0073] In some embodiments, continue to refer to Figures 2 to 4 Based on the premise that the gate 164 and the second doped structure 102 are mutually insulated and the gate 164 and the third doped structure 103 are mutually insulated, the third doped structure 103 can not only contact and connect with the third part 131, but also contact and connect with the second part 121 with the upper part thickness along the first direction X.

[0074] In other embodiments, reference is made to... Figure 6 The second doped structure 102 and the gate structure 104 are in one-to-one correspondence. The second doped structure 102 is located on the same side of the corresponding gate structure 104 along the second direction Y, for example... Figure 6 The second doped structure 102 is located on the first side of the corresponding gate structure 104, and the two adjacent and spaced gate structures 104 are located in the same active region 106, and the two second doped structures 102 are located in the same active region 106.

[0075] It should be noted that the reference Figures 2 to 4 and Figure 6 The gate structure 104 can not only contact and connect with the second portion 121, but also, provided that the gate 164 and the second doped structure 102 are mutually insulated and the gate 164 and the third doped structure 103 are mutually insulated, the gate structure 104 can also contact and connect with the first portion 111 along the upper portion of the first direction X. In practical applications, the gate structure 104 can contact and connect only with the second portion 121. Furthermore, Figure 6 The approximate regions of the two first doped structures 101 in the active region 106 are outlined by boxes I and II, respectively.

[0076] In some embodiments, reference Figure 7 The semiconductor structure may further include: a substrate 100, and a first doped structure 101, a second doped structure 102, a third doped structure 103, and a gate structure 104 all located in the substrate 100. It is understood that the substrate 100 has multiple spaced active regions 106, and at least a portion of the first doped structure 101, the second doped structure 102, the third doped structure 103, and the gate structure 104 is embedded in the active regions 106.

[0077] Understandably, continue to refer to Figure 7 In the same active region 106, along the second direction Y, the third doped structure 103 is located between two adjacent gate structures 104, and the two adjacent gate structures 104 are located between two adjacent second doped structures 102, so that the two transistor structures share a third doped structure 103.

[0078] The third doped structure 103 will be described in detail below through two embodiments.

[0079] In some embodiments, in conjunction with reference Figure 5 and Figure 7 Multiple first doped structures 101 and multiple second doped structures 102 are arranged at intervals along the third direction Z. The first doped structures 101, second doped structures 102 and gate structure 104 arranged at intervals along the third direction Z are all in one-to-one correspondence. A third doped structure 103 extends along the third direction Z. A third doped structure 103 is in contact with and connected to multiple first doped structures 101 arranged at intervals along the third direction Z. The first direction X, the second direction Y and the third direction Z intersect each other.

[0080] It is understood that the first doped structure 101 is part of the active region 106. A second doped structure 102 is embedded at each end of the active region 106 along its extension direction U. The region within the active region 106 between the two second doped structures 102 that are in contact with it corresponds to one bit line structure BL and two word line structures WL. For any active region 106, the region corresponding to the word line structure WL has a gate structure 104 embedded, and the region corresponding to the bit line structure BL has a third doped structure 103 embedded. The relationship between the word line structure WL and the gate structure 104, as well as the relationship between the bit line structure BL and the third doped structure 103, will be explained in detail later.

[0081] In some embodiments, reference Figure 5In Figure 5a, multiple bit line structures BL are arranged at intervals along the fifth direction V, and multiple word line structures WL are arranged at intervals along the third direction Z. It can be understood that the multiple bit line structures BL and multiple word line structures WL form multiple rectangular windows in the top view. Each rectangular window forms a capacitor contact hole, and each capacitor contact hole exposes a second doped structure 102. The capacitor contact hole forms a capacitor structure that contacts and connects with the second doped structure 102.

[0082] In some embodiments, reference Figure 5 In section 5a, a gate structure 104 and an isolation layer 105 are embedded in the active region 106 directly opposite the word line structure WL. It can be understood that the word line structure WL includes the gate structure 104 and the isolation layer 105. Multiple active regions 106 arranged at intervals along the fifth direction V are directly opposite a portion of the word line structure WL. That is, the orthogonal projection of a portion of the gate structure 104 onto the active region 106 coincides with the active region 106. Multiple active regions 106 arranged at intervals along the fifth direction V share a single gate structure 104.

[0083] Reference Figure 7 and Figure 8 The third doped structure 103 extends along the third direction Z. It can be understood that the multiple active regions 106 arranged at intervals along the third direction Z are all directly opposite a portion of the third doped structure 103, meaning that the orthogonal projection of a portion of the third doped structure 103 onto the active region 106 coincides with the active region 106. The multiple active regions 106 arranged at intervals along the third direction Z share a single third doped structure 103. It should be noted that the bit line structure BL includes the third doped structure 103. Furthermore, the first doped structure 101 is part of the active region 106. A second doped structure 102 is embedded at each end of an active region 106 along its extending direction U. An active region 106 can be considered as a basic component constituting two transistor structures, which share a single third doped structure 103.

[0084] In some embodiments, reference Figure 7 The semiconductor structure may further include: a first electrical connection layer 117, which is located on the side of the third doped structure 103 away from the gate structure 104, and extends in the third direction Z. It is understood that the bit line structure BL (refer to...) Figure 5 It may include a first electrical connection layer 117 and a third doped structure 103 that is in contact with the first electrical connection layer 117, and a bit line structure BL corresponds to a first electrical connection layer 117 and a third doped structure 103.

[0085] It should be noted that, in order to clearly illustrate the relative positional relationship between the active region 106 and the third doped structure 103 in the top view, Figure 8The active region 106 is drawn using a perspective method.

[0086] In other embodiments, in conjunction with reference to Figure 9 and Figure 10 Multiple first doped structures 101, multiple second doped structures 102 and multiple third doped structures 103 are arranged at intervals along the third direction Z. The first doped structures 101, second doped structures 102, third doped structures 103 and gate structures 104 arranged at intervals along the third direction Z are all one-to-one correspondences.

[0087] It is understood that the first doped structure 101 is part of the active region 106, and a second doped structure 102 is embedded at each end of the active region 106 along its extension direction U. Figure 9 In the top view shown, the second doped structure 102 and the third doped structure 103 corresponding to the same active region 106 (reference) Figure 7 There is a gate structure 104 between them (reference) Figure 7 It is understood that the third doped structure 103 can serve as the bit line contact layer in the bit line structure BL. It should be noted that parts that are the same as or corresponding to those in the above embodiments will not be repeated here.

[0088] Continue to refer to Figure 9 and Figure 10 The semiconductor structure may further include a conductive layer 107 extending along the third direction Z, and the same conductive layer 107 is in contact with a plurality of third doped structures 103 arranged at intervals along the third direction Z. It is understood that a bit-line structure BL includes a plurality of third doped structures 103 arranged at intervals along the third direction Z and a conductive layer 107 in contact with them. Furthermore, an active region 106 can be considered as a basic component constituting two transistor structures, each having its own second doped structure 102 and its own gate structure 104, and the two transistor structures sharing a third doped structure 103.

[0089] In some embodiments, reference Figure 10 The conductive layer 107 may include: a second electrical connection layer 137 and a plurality of conductive pillars 127 that are in contact with the second electrical connection layer 137 and are spaced apart along the third direction Z. The conductive pillars 127 and the third doped structure 103 correspond one-to-one, and one conductive pillar 127 and one third doped structure 103 are in contact. The second electrical connection layer 137 extends along the third direction Z, and the same second electrical connection layer 137 is in contact with the plurality of conductive pillars 127 that are spaced apart along the third direction Z.

[0090] In some embodiments, the orthogonal projections of the conductive pillar 127 and the third doped structure 103 onto the substrate 100 may coincide.

[0091] It should be noted that, in order to clearly illustrate the relative positional relationship between the active region 106 and the third doped structure 103 in the top view, Figure 9 The active region 106 is drawn using a perspective method.

[0092] In the above embodiments, reference is made to Figure 7 or Figure 10 The semiconductor structure may further include: a capacitor structure 109 located on the side of the second doped structure 102 away from the gate structure 104, and a bit line structure BL including a third doped structure 103 located on the side of the gate structure 104 away from the capacitor structure 109. This helps to avoid the capacitor structure 109 and the bit line structure BL being directly opposite each other, thereby reducing the coupling effect between the capacitor structure 109 and the bit line structure BL and improving the electrical performance of the semiconductor structure.

[0093] In some cases, at least a portion of the second doped structure 102 is in contact with the gate dielectric layer 154 in the corresponding gate structure 104.

[0094] In summary, the second doped structure 102 and the third doped structure 103 can be considered as located on opposite sides of the gate structure 104 along the first direction X. That is, using a plane parallel to the first direction X as a reference plane, the second doped structure 102 and the third doped structure 103 are not directly opposite each other; that is, their orthogonal projections on the reference plane do not overlap. This increases the spacing between the second doped structure 102 and the third doped structure 103, thereby reducing their coupling influence on each other. Furthermore, the capacitor structure 109 is located on the side of the second doped structure 102 away from the gate structure 104, and the bit line structure BL is located on the side of the gate structure 104 away from the capacitor structure 109. This helps avoid the capacitor structure 109 and the bit line structure BL being directly opposite each other, thus reducing their coupling influence on each other and improving the electrical performance of the semiconductor structure. In addition, two adjacent transistor structures along the second direction Y share a single third doped structure 103, which helps increase the integration density of transistor structures in the semiconductor structure.

[0095] Another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure, used to form the semiconductor structure provided in the foregoing embodiments. Figures 11 to 19 This is a cross-sectional structural diagram corresponding to each step in a method for manufacturing a semiconductor structure according to another embodiment of this disclosure. It should be noted that, for ease of description and clear illustration of the steps in the semiconductor structure fabrication method, the diagram in this embodiment... Figures 11 to 19 These are partial structural diagrams of semiconductor structures. Furthermore, parts that are the same as or corresponding to those in the aforementioned embodiments will not be described again here.

[0096] refer to Figures 1 to 19 A method for manufacturing a semiconductor structure includes: providing an initial substrate 110; performing different doping processes on different portions of the initial substrate 110 to form a first doped structure 101, a second doped structure 102, and a third doped structure 103; wherein the first doped structure 101 has a first portion 111, a second portion 121, and a third portion 131 arranged sequentially along a first direction X; the second doped structure 102 and the third doped structure 103 are spaced apart, the second doped structure 102 is in contact with the first portion 111, and the third doped structure 103 is in contact with the third portion 131; the first doped structure 101... The first doped structure 101 is doped with one of N-type dopant ions and one of P-type dopant ions, and the second doped structure 102 and the third doped structure 103 are doped with the other of N-type dopant ions and one of P-type dopant ions. Two adjacent first doped structures 101 along the second direction Y are in contact with the same third doped structure 103, and the second direction Y intersects the first direction X. A gate structure 104 is formed, which has a first surface 114 and a second surface 124 opposite to each other along the second direction Y. At least the first surface 114 is in contact with the second portion 121, and the gate structure 104 is in contact with the third doped structure 103.

[0097] It should be noted that the order of the steps for forming the second doped structure 102, the third doped structure 103, and the gate structure 104 can be adjusted, which will be explained in detail below. Furthermore, for ease of understanding, the following will focus on the formation of... Figure 4 The semiconductor structure shown is an exemplary illustration of the manufacturing method. In practical applications, the various semiconductor structures in the foregoing embodiments can be manufactured by the manufacturing method provided in another embodiment of this disclosure.

[0098] In some embodiments, the initial substrate 110 has a front side 120 and a back side 130 opposite each other along a first direction X; Reference Figures 11 to 19 Forming the second doped structure 102 and the third doped structure 103 may include the following steps:

[0099] refer to Figure 11 and Figure 12 A portion of the initial substrate 110 is subjected to a first doping treatment to form a plurality of initial first doped structures 141 arranged at intervals. The initial first doped structures 141 extend from the front side 120 into the interior of the initial substrate 110. The initial first doped structures 141 also extend along the fourth direction U. The initial first doped structures 141 have a fourth part 151, a fifth part 161 and a sixth part 171 arranged sequentially along the fourth direction U.

[0100] It should be noted that the first doped structure 101 is subsequently formed based on the initial first doped structure 141, thereforeFigures 11 to 19 The initial first doped structure 141 is drawn using the same filling method as the first doped structure 101.

[0101] In some embodiments, performing a first doping treatment on a portion of the initial substrate 110 includes doping the portion of the initial substrate 110 with P-type dopant ions, such that the initial first doped structure 141 is doped with P-type dopant ions. In other embodiments, performing a first doping treatment on a portion of the initial substrate 110 includes doping the portion of the initial substrate 110 with N-type dopant ions, such that the initial first doped structure 141 is doped with N-type dopant ions.

[0102] It is understood that the initial first doped structure 141 can be regarded as the active region 106 before the second doped structure 102, the third doped structure 103 and the gate structure 104 are embedded. The orthographic projection of the initial first doped structure 141 on the top view coincides with the orthographic projection of the active region 106 on the top view. The top view is a plane formed by the third direction Z and the fifth direction V.

[0103] In some embodiments, in conjunction with reference Figure 11 and Figure 12 , Figure 11 for Figure 12 The schematic diagram shows a partial cross-sectional view of the semiconductor structure along the second cross-section direction BB1. Multiple initial first doped structures 141 are not only spaced apart along the third direction Z and the fifth direction V, but adjacent groups of initial first doped structures spaced apart along the fifth direction V are staggered along the third direction Z. The extension directions U, Z, and V of each initial first doped structure 141 intersect each other, and these directions are all located in a single plane. It can be understood that the multiple initial first doped structures 141 spaced apart along the third direction Z are considered as one column, and adjacent columns along the fifth direction V are staggered, with the arrangement of two columns separated by one column being identical.

[0104] It should be noted that in practical applications, multiple initial first-doped structures can also be arranged in the third direction Z and the fifth direction V, or in other arrangements. The arrangement of multiple active regions can be adjusted according to actual needs, and no limitation is made here. For ease of explanation, multiple initial first-doped structures 141 will be used in the following examples. Figure 12 The arrangement shown is an example for detailed explanation.

[0105] Reference Figures 11 to 14 , Figure 13 for Figure 14The diagram shows a partial cross-sectional view of the semiconductor structure along the second cross-sectional direction BB1. Both the fourth portion 151 and the sixth portion 171 undergo a second doping treatment along the first direction X, transforming a portion of the fourth portion 151 into a second doped structure 102, and a portion of the sixth portion 171 into another second doped structure 102. The second doped structures 102 extend from the front side 120 into the interior of the initial substrate 110.

[0106] It is understood that the two second doped structures 102 are fabricated from two different regions of an initial first doped structure 141, that is, the two second doped structures 102 correspond to an initial first doped structure 141. A third doped structure 103 and a gate structure 104 can subsequently be formed in the fifth part 161. Furthermore, the types of dopant ions used in the first and second doping processes are different.

[0107] In some embodiments, the second doping treatment of the fourth portion 151 and the sixth portion 171, based on the initial first doped structure 141 being doped with P-type dopant ions, includes doping the fourth portion 151 and the sixth portion 171 with N-type dopant ions, such that the second doped structure 102 is doped with N-type dopant ions. In other embodiments, the second doping treatment of the fourth portion 151 and the sixth portion 171, based on the initial first doped structure 141 being doped with N-type dopant ions, includes doping the fourth portion 151 and the sixth portion 171 with P-type dopant ions, such that the second doped structure 102 is doped with P-type dopant ions.

[0108] refer to Figure 15 and Figure 16 Or refer to Figure 18 and Figure 19 The initial substrate 110 is patterned from the back side 130 to expose at least a portion of the fifth portion 161; Reference Figure 17 Or refer to Figure 10 The exposed fifth part 161 is subjected to a third doping treatment to form a third doped structure 103.

[0109] The steps for forming the third doped structure 103 are described in detail below through two embodiments.

[0110] In some embodiments, in conjunction with reference Figure 13 and Figure 14 Multiple fifth parts 161 are arranged at intervals along the third direction Z, with the first direction X, the second direction Y, and the third direction Z intersecting each other. Among them, the second direction Y is the extension direction U of the initial first doped structure 141.

[0111] In some embodiments, the second direction Y, the third direction Z, and the fifth direction V intersect each other and form a plane, and the first direction X is perpendicular to the plane.

[0112] Graphicalizing the initial substrate 110 from the back side 130 may include the following steps:

[0113] refer to Figure 15 and Figure 16 , Figure 15 for Figure 16 The schematic diagram shows a partial cross-sectional structure of the semiconductor structure along the second cross-sectional direction BB1. The initial substrate 110 is patterned from the back side 130 to form a trench 108 extending along the third direction Z, and the trench 108 exposes a plurality of fifth portions 161 spaced apart along the third direction Z.

[0114] It should be noted that, in order to clearly illustrate the relative positional relationship between the trench 108 and the initial base 110 in the top view, Figure 16 The initial base 110 is drawn using a perspective method.

[0115] Reference Figures 15 to 17 and Figure 8 The step of performing a third doping treatment on the exposed fifth portion 161 may include performing the third doping treatment on the exposed fifth portion 161 of the trench 108 to form a third doped structure 103 extending in the third direction Z. It is understood that a third doped structure 103 is in contact with a plurality of fifth portions 161 spaced apart in the third direction Z. Furthermore, the ion types doped in the third doping treatment and the second doping treatment are the same.

[0116] In some embodiments, performing a third doping treatment on the exposed fifth portion 161, based on the initial first doped structure 141 being doped with P-type dopant ions, includes doping the exposed fifth portion 161 with N-type dopant ions, such that the third doped structure 103 is doped with N-type dopant ions. In other embodiments, performing a third doping treatment on the exposed fifth portion 161, based on the initial first doped structure 141 being doped with N-type dopant ions, includes doping the exposed fifth portion 161 with P-type dopant ions, such that the third doped structure 103 is doped with P-type dopant ions.

[0117] Reference Figure 17 and Figure 7The manufacturing method may further include: forming a first electrical connection layer 117, wherein the first electrical connection layer 117 fills the trench 108. It is understood that the bit line structure BL may include the first electrical connection layer 117 and a third doped structure 103 in contact with the first electrical connection layer 117, wherein a bit line structure BL corresponds to a first electrical connection layer 117 and a third doped structure 103.

[0118] In other embodiments, in conjunction with reference to Figure 13 and Figure 14 Multiple fifth parts 161 are arranged at intervals along the third direction Z, and the first direction X, the second direction Y, and the third direction Z intersect each other. It should be noted that the parts that are the same as or corresponding to those in the above embodiments will not be described again here.

[0119] Graphicalizing the initial substrate 110 from the back side 130 may include the following steps:

[0120] refer to Figure 18 and Figure 19 , Figure 18 for Figure 19 The schematic diagram shows a partial cross-sectional structure of the semiconductor structure along the second cross-sectional direction BB1. The initial substrate 110 is patterned from the back side 130 to form a plurality of vias 118 spaced apart along the third direction Z, and one via 118 exposes a fifth part 161.

[0121] It should be noted that, in order to clearly illustrate the relative positional relationship between the through hole 118 and the initial substrate 110 in the top view, Figure 19 The initial base 110 is drawn using a perspective method.

[0122] Reference Figures 18 to 19 , Figure 9 and Figure 10 The step of performing a third doping treatment on the exposed fifth portion 161 may include performing the third doping treatment on the fifth portion 161 exposed by the via 118 to form a plurality of third doped structures 103 spaced apart along the third direction Z. It is understood that a third doped structure 103 is only in contact with a fifth portion 161, that is, a third doped structure 103 corresponds to a fifth portion 161.

[0123] Reference Figure 18 and Figure 10 The manufacturing method may further include: forming conductive pillars 127, filling through holes 118 with the conductive pillars 127, and having a one-to-one correspondence between the conductive pillars 127 and the through holes 118. Thus, the conductive pillars 127 and the third doped structure 103 correspond one-to-one, meaning that one conductive pillar 127 and one third doped structure 103 are in contact connection.

[0124] Continue to refer to Figure 10A second electrical connection layer 137 extending along the third direction Z is formed, and the same second electrical connection layer 137 is in contact with a plurality of conductive pillars 127 arranged at intervals along the third direction Z.

[0125] It is understood that the second electrical connection layer 137 and a plurality of conductive pillars 127 that are in contact with the second electrical connection layer 137 and are spaced apart along the third direction Z together constitute the conductive layer 107. The bit line structure BL includes the conductive layer 107 and a plurality of third doped structures 103 that are in contact with the conductive layer 107.

[0126] In practical applications, after patterning the initial substrate from the back side to form multiple vias spaced apart along the third direction, and then performing a third doping treatment on the exposed fifth portion of the vias to form a third doped structure, the substrate on the back side is further patterned to form trenches extending along the third direction. Each trench exposes multiple third doped structures spaced apart along the third direction, and a third electrical connection layer is formed within the trench. Thus, the bit line structure can include a third electrical connection layer and multiple third doped structures in contact with and connected to this third electrical connection layer. It is understood that after forming the third doped structure using vias, the vias are expanded into trenches, and a third electrical connection layer is formed within the trenches, allowing one third electrical connection layer to supply power to multiple third doped structures.

[0127] In some embodiments, in conjunction with reference Figure 5 and Figure 10 The step of forming the gate structure 104 includes: from the front side 120 to the fifth portion 161 (reference) Figure 11 The process involves patterning to form a second trench (not shown) extending along the fifth direction V; wherein a fifth portion 161 corresponds to two adjacent second trenches along the third direction Z; a gate structure 104 and an isolation layer 105 are sequentially formed in the second trench. It should be noted that the manufacturing method provided in another embodiment of this disclosure does not limit the specific process for forming the gate structure 104 and the isolation layer 105, and can be adjusted according to actual needs.

[0128] It should be noted that the step of forming the gate structure 104 can be performed before or after the formation of the second doped structure 102 and the third doped structure 103. Furthermore, after forming the second doped structure 102, the third doped structure 103, and the gate structure 104 in the initial first doped structure 141, the remaining initial first doped structure 141 serves as the first doped structure 101.

[0129] It is understandable that after the formation of the second doped structure 102, the third doped structure 103 and the gate structure 104, the remaining initial first doped structure 141 serves as the first doped structure 101, and the remaining initial substrate 110 serves as the substrate 100.

[0130] In some embodiments, continue to refer to Figure 10 After forming the second doped structure 102, the manufacturing method may further include forming a capacitor structure 109 on the front side 120 that is in contact with and connected to the second doped structure 102, wherein the second doped structure 102 and the capacitor structure 109 correspond to each other.

[0131] In summary, in the formed semiconductor structure, the second doped structure 102 and the third doped structure 103 can be considered as located on opposite sides of the gate structure 104 along the first direction X. That is, with a plane parallel to the first direction X as the reference plane, the second doped structure 102 and the third doped structure 103 are not directly opposite each other, that is, the orthogonal projections of the second doped structure 102 and the third doped structure 103 on the reference plane do not overlap, so as to increase the spacing between the second doped structure 102 and the third doped structure 103, thereby helping to reduce the coupling effect between the second doped structure 102 and the third doped structure 103. Furthermore, the capacitor structure 109 is located on the side of the second doped structure 102 away from the gate structure 104, and the bit line structure BL is located on the side of the gate structure 104 away from the capacitor structure 109, which helps to avoid the capacitor structure 109 and the bit line structure BL being directly opposite each other, thereby helping to reduce the coupling effect between the capacitor structure 109 and the bit line structure BL, and thus improving the electrical performance of the semiconductor structure. Furthermore, two adjacent transistor structures along the second direction Y share a third doped structure 103, which is beneficial to increasing the integration density of transistor structures in the semiconductor structure.

[0132] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a first doped structure having a first portion, a second portion and a third portion arranged in sequence along a first direction; a second doped structure and a third doped structure arranged in sequence along a second direction, the second doped structure being in contact with the first portion, and the third doped structure being in contact with the third portion; wherein one of N-type and P-type doping ions is doped in the first doped structure, and the other of N-type and P-type doping ions is doped in the second doped structure and the third doped structure, and two first doped structures adjacent along a second direction are in contact with the same third doped structure, the second direction intersecting the first direction; a gate structure having a first face and a second face opposite along the second direction, at least one of the first face and the second face being in contact with the second portion.

2. The semiconductor structure of claim 1, wherein, Only the first face or only the second face of the gate structure is in contact with the second portion.

3. The semiconductor structure of claim 2, wherein, The gate structure has a third face and a fourth face opposite along the first direction, at least part of the third face and at least part of the fourth face being in contact with the second portion.

4. The semiconductor structure of claim 2, wherein, The gate structure has a third face and a fourth face opposite along the first direction, the second face and the fourth face being in contact with the second portion.

5. The semiconductor structure of claim 4, wherein, Further comprising: an isolation layer in contact with the third face, and the isolation layer and the gate structure being embedded in the first doped structure.

6. The semiconductor structure of claim 4, wherein, Further comprising: an active region, the active region comprising two first doped structures adjacent along the second direction, and two gate structures in contact with the two first doped structures being spaced apart and located in the active region.

7. The semiconductor structure of any one of claims 1 to 6, wherein, At least part of the second doped structure is embedded in the first portion, and / or at least part of the third doped structure is embedded in the third portion.

8. The semiconductor structure of any one of claims 1 to 6, wherein, A plurality of first doped structures and a plurality of second doped structures are arranged in sequence along a third direction, the first doped structures, the second doped structures and the gate structures arranged in sequence along the third direction corresponding one-to-one; the third doped structure extends along the third direction, and one third doped structure is in contact with a plurality of first doped structures arranged in sequence along the third direction, the first direction, the second direction and the third direction intersecting two by two.

9. The semiconductor structure of any one of claims 1 to 6, wherein, A plurality of first doped structures, a plurality of second doped structures and a plurality of third doped structures are arranged in sequence along a third direction, the first doped structures, the second doped structures, the third doped structures and the gate structures arranged in sequence along the third direction corresponding one-to-one; The semiconductor structure further comprises: a conductive layer extending along the third direction, and the same conductive layer being in contact with a plurality of third doped structures arranged in sequence along the third direction.

10. The semiconductor structure of any one of claims 1 to 6, wherein, The gate structure is in contact with the third doped structure.

11. The semiconductor structure of claim 1, wherein, Further comprising: a substrate, the first doped structure, the second doped structure, the third doped structure and the gate structure being located in the substrate.

12. A method of manufacturing a semiconductor structure, characterized by, Comprising: providing an initial substrate; The different portions of the initial substrate are doped by different doping processes to form a first doped structure, a second doped structure and a third doped structure; The first doped structure has a first portion, a second portion and a third portion arranged in sequence along a first direction; the second doped structure and the third doped structure are arranged at intervals, the second doped structure is connected with the first portion, and the third doped structure is connected with the third portion; one of N-type doping ions and P-type doping ions is doped in the first doped structure, and the other one of N-type doping ions and P-type doping ions is doped in the second doped structure and the third doped structure; two first doped structures adjacent along a second direction are connected with the same third doped structure, and the second direction intersects the first direction; A gate structure is formed, the gate structure has a first surface and a second surface opposite along the second direction, at least the first surface is connected with the second portion, and the gate structure is connected with the third doped structure.

13. The manufacturing method according to claim 12, characterized by The initial substrate has a front surface and a back surface opposite along the first direction; The steps of forming the second doped structure and the third doped structure include: A first doping process is performed on a partial region of the initial substrate to form a plurality of initial first doped structures arranged at intervals, the initial first doped structures extend from the front surface to the inside of the initial substrate, and the initial first doped structures also extend along a fourth direction, the initial first doped structures have a fourth portion, a fifth portion and a sixth portion arranged in sequence along the fourth direction; A second doping process is performed on the fourth portion and the sixth portion along the first direction, so that part of the thickness of the fourth portion is converted into a second doped structure, and part of the thickness of the sixth portion is converted into another second doped structure, and the second doped structures extend from the front surface to the inside of the initial substrate; A patterning process is performed on the initial substrate from the back surface to expose at least part of the fifth portion; A third doping process is performed on the exposed fifth portion to form the third doped structure.

14. The manufacturing method according to claim 13, wherein A plurality of fifth portions are arranged at intervals along a third direction, and the first direction, the second direction and the third direction intersect each other; The patterning process performed on the initial substrate from the back surface includes: A patterning process is performed on the initial substrate from the back surface to form a groove extending along the third direction, and the groove exposes a plurality of fifth portions arranged at intervals along the third direction; The third doping process performed on the exposed fifth portion includes: The third doping process is performed on the fifth portion exposed by the groove to form the third doped structure extending along the third direction; The manufacturing method further includes forming a first electrically connecting layer, and the first electrically connecting layer fills the groove.

15. The manufacturing method according to claim 13, wherein A plurality of fifth portions are arranged at intervals along a third direction, and the first direction, the second direction and the third direction intersect each other; The patterning the initial substrate from the back surface includes: The patterning the initial substrate from the back surface to form a plurality of through holes spaced along the third direction, and one of the through holes exposes one of the fifth portions; The third doping treatment on the exposed fifth portion includes: The third doping treatment on the exposed fifth portion of the through hole to form a plurality of third doping structures spaced along the third direction; The manufacturing method further includes: forming a conductive column, the conductive column fills the through hole, and the conductive column and the through hole correspond one by one; A second electrical connection layer extending along the third direction is formed, and the same second electrical connection layer is in contact with a plurality of conductive columns spaced along the third direction.

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