Semiconductor structure and manufacturing method thereof, memory and electronic equipment

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof, a memory and electronic equipment. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate, and forming a laminated structure on one side of the substrate; the laminated structure comprises a plurality of target material layers which are stacked along the direction vertical to the substrate, and a support material layer which is positioned between any two adjacent target material layers; etching the laminated structure along the direction vertical to the substrate to form an etching groove extending along the first direction; forming a sacrificial material layer in the etching groove; circularly executing a target process for multiple times on the obtained structure after the sacrificial material layers are formed, so that the reserved part of each target material layer correspondingly forms a first step, and a plurality of first steps are arranged in the second direction to form a stepped structure; the second direction intersects the first direction. According to the invention, efficient manufacturing of the step structure is realized.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a semiconductor structure and a manufacturing method thereof, a memory, and an electronic device. Background Art

[0002] With the development of semiconductor technology, in order to further pursue the miniaturization of device structure, changing the process from planar to three-dimensional, that is, arranging storage units in three-dimensional space, has become the main development direction of current memory structure research.

[0003] Currently, in three-dimensional memories, when wiring bit lines at different heights, each layer of bit lines needs to be wired individually. However, as the number of stacked memory cells increases to hundreds or thousands, the number of individual wiring steps also needs to increase by hundreds or thousands, which seriously increases the complexity of the process. Therefore, the manufacture of staircase structures is particularly important. Summary of the invention

[0004] Based on this, the embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, a memory, and an electronic device to achieve efficient manufacturing of a stepped structure.

[0005] In order to achieve the above-mentioned objectives, in a first aspect, some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, comprising: providing a substrate, forming a stacked structure on one side of the substrate; the stacked structure comprising: a plurality of target material layers stacked along a direction perpendicular to the substrate, and a supporting material layer located between any two adjacent target material layers; etching the stacked structure along a direction perpendicular to the substrate to form an etched groove extending along a first direction; forming a sacrificial material layer in the etched groove; cyclically performing multiple target processes on the resulting structure after forming the sacrificial material layer, so that the retained portion of each target material layer forms a first step corresponding to the retained portion, and the plurality of first steps are arranged into a stepped structure along a second direction; the second direction intersects with the first direction.

[0006] Among them, a target process includes: etching and removing the sacrificial material layer of the target height along the direction perpendicular to the substrate to expose the side wall of the target material layer of the target layer; etching the target material layer of the target layer along the direction parallel to the substrate, and simultaneously etching from top to bottom along the direction parallel to the substrate exposed each target material layer on the side of the target layer away from the substrate.

[0007] In some embodiments, the etching rates between the target material layer and the sacrificial material layer are different.

[0008] In some embodiments, the target material layer is etched using a wet etching process; and the etching selectivity ratio of the target material layer to the sacrificial material layer is greater than or equal to 10:1.

[0009] In some embodiments, the target material layer is etched using a remote plasma source etching process; the etching selectivity between the target material layer and the sacrificial material layer is greater than 1:1 and less than or equal to 5:1.

[0010] In some embodiments, the sacrificial material layer is etched using an anisotropic etching process.

[0011] In some embodiments, the target material layer of the target layer is etched along a direction parallel to the substrate, and simultaneously, each target material layer exposed on the side of the target layer facing away from the substrate is etched from top to bottom along a direction parallel to the substrate. It further includes: symmetrically etching each target material layer on opposite sides of the etching trench in a second direction to form a stepped structure symmetrically arranged with the etching trench as the center.

[0012] In some embodiments, the method for manufacturing a semiconductor structure further includes: forming an isolation barrier on one side of the substrate. Wherein, the stacked structure is formed on one side of the isolation barrier, and the etching trench exposes the sidewall of the isolation barrier facing the stacked structure.

[0013] In some embodiments, the target material layer includes a metal material layer or a semiconductor material layer. The method for preparing a semiconductor structure further includes: patterning the target material layer to form a common bit line respectively connected to each first step, and a bit line connected to the common bit line. Wherein, the common bit line extends in a second direction.

[0014] In some embodiments, the method for manufacturing a semiconductor structure further includes: forming an isolation structure to fill the etching trench and the etched removal regions of each target material layer; or, using each first step as a mask to etch adjacent support material layers respectively, so that the remaining portions of each support material layer correspondingly form second steps; forming an isolation structure to fill the etching trench and the etched removal regions of each target material layer and each support material layer.

[0015] In some embodiments, the method for manufacturing a semiconductor structure further includes: forming a through hole at least penetrating the isolation structure on the surface of the first step facing away from the substrate; forming a bit line lead in the through hole.

[0016] In a second aspect, the present disclosure also provides a semiconductor structure according to some embodiments, including a substrate, a stacked structure, and a sacrificial material layer. The stacked structure is located on one side of the substrate; the stacked structure includes: a plurality of target material layers stacked along a direction perpendicular to the substrate, and a supporting material layer located between any two adjacent target material layers; the stacked structure has an etching groove extending along a first direction; and the sacrificial material layer is filled in the etching groove. Wherein, each target material layer and the sacrificial material layer are configured such that: after executing the target process multiple times in a cycle, the retained portion of each target material layer forms a first step correspondingly, and the plurality of first steps are arranged into a stepped structure along a second direction; the second direction intersects with the first direction. The target process includes: etching and removing the sacrificial material layer of the target height along a direction perpendicular to the substrate to expose the sidewall of the target material layer of the target layer; etching the target material layer of the target layer along a direction parallel to the substrate, and simultaneously etching each target material layer exposed on the side of the target layer away from the substrate from top to bottom along a direction parallel to the substrate.

[0017] In some embodiments, the semiconductor structure further comprises: an isolation barrier wall located on one side of the stacked structure in a direction parallel to the substrate, wherein the sacrificial material layer is located between the isolation barrier wall and the stacked structure.

[0018] In a third aspect, the present disclosure further provides a memory according to some embodiments, comprising: at least one staircase structure, wherein the staircase structure is obtained by etching the semiconductor structure as described in the second aspect of the embodiment of the present disclosure; the staircase structure at least comprises: a plurality of first steps.

[0019] In some embodiments, the memory further comprises: a plurality of common bit lines, a plurality of bit lines, and a plurality of bit line leads. The common bit lines are connected to the first step correspondingly, the bit lines are connected to the common bit lines correspondingly, the connected first step, the common bit lines, and the bit lines are respectively parts of the same target material layer located in different regions; the bit line leads are located on the surface of the first step away from the substrate and extend in a direction perpendicular to the substrate.

[0020] In a fourth aspect, the present disclosure further provides an electronic device according to some embodiments, comprising: the memory described in the third aspect of the embodiments of the present disclosure.

[0021] The embodiments of the present disclosure may or at least have the following advantages:

[0022] In the embodiments of the present disclosure, after forming a stacked structure on one side of a substrate and forming a sacrificial material layer in the etched trenches of the stacked structure, a target process can be repeatedly executed on the obtained structure after forming the sacrificial material layer; wherein, any target process includes: etching and removing a sacrificial material layer with a target height along a direction perpendicular to the substrate to expose the sidewalls of the target material layer of the target layer; etching the target material layer of the target layer along a direction parallel to the substrate, and synchronously etching each target material layer exposed on the side of the target layer facing away from the substrate from top to bottom along a direction parallel to the substrate. Thus, the etching times of the target material layers of different layers in the spatial dimension can be utilized to form a first step corresponding to multiple target material layers, thereby obtaining a stepped structure. In this way, compared with the related art in which step partitions are manufactured by adjusting-etching multiple cycles and stepped structures are formed through multiple replication etching processes, this solution only requires one photomask pattern definition to achieve one-step manufacturing of multiple steps, thereby reducing the complexity of the process steps and realizing efficient manufacturing of stepped structures.

[0023] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 is a flowchart of a manufacturing method of a semiconductor structure provided in some embodiments;

[0026] Figure 2 is a cross-sectional schematic diagram of a semiconductor structure provided in some embodiments;

[0027] Figure 3 is a flowchart of a target process provided in some embodiments;

[0028] Figure 4 is a cross-sectional schematic diagram of the obtained structure after removing a sacrificial material layer with a target height in some embodiments;

[0029] Figure 5 is a cross-sectional schematic diagram of the obtained structure after etching the target material layer of the target layer in some embodiments;

[0030] Figure 6Schematic cross-sectional view of a structure obtained after forming a stepped structure with a double step in some embodiments;

[0031] Figure 7 Schematic cross-sectional view of a structure obtained after forming an isolation barrier in some embodiments;

[0032] Figure 8 Schematic cross-sectional view of a structure obtained after forming a stepped structure with a single step in some embodiments;

[0033] Figure 9 Schematic cross-sectional view of a structure obtained after forming an isolation structure in some embodiments;

[0034] Figure 10 Schematic cross-sectional view of a structure obtained after forming an isolation structure in some other embodiments;

[0035] Figure 11 Schematic three-dimensional view of a structure obtained after patterning a target material layer in some embodiments;

[0036] Figure 12 Top view schematic of a semiconductor structure provided in some embodiments;

[0037] Figure 13 Flowchart of a manufacturing method of another semiconductor structure provided in some embodiments;

[0038] Figure 14 Schematic cross-sectional view of a structure obtained after forming a mask structure in some embodiments;

[0039] Figure 15 Schematic cross-sectional view of a structure obtained after forming a patterned stacked structure in some embodiments;

[0040] Figure 16 Schematic cross-sectional view of a structure obtained after forming an insulating structure in some embodiments;

[0041] Figure 17 Schematic cross-sectional view of a structure obtained after etching an insulating structure on the sidewall of an array unit in some embodiments;

[0042] Figure 18 Schematic cross-sectional view of a structure obtained after forming a support frame in some embodiments;

[0043] Figure 19 Schematic cross-sectional view of a structure obtained after forming a hard mask layer in some embodiments;

[0044] Figure 20Schematic cross-sectional view of a structure obtained after etching each support material layer exposed in the first etching hole in some embodiments;

[0045] Figure 21 Schematic cross-sectional view of a structure obtained after removing the hard mask layer in some embodiments;

[0046] Figure 22 Schematic cross-sectional view of a structure obtained after forming a high-k dielectric material layer and a second electrode material layer in some embodiments;

[0047] Figure 23 Schematic cross-sectional view of a structure obtained after forming a high-k dielectric layer and a second electrode layer in some embodiments;

[0048] Figure 24 Schematic cross-sectional view of a structure obtained after forming a planarization layer in some embodiments;

[0049] Figure 25 Schematic cross-sectional view of a structure obtained after forming a word line hole in some embodiments;

[0050] Figure 26 Schematic cross-sectional view of a structure obtained after forming a transistor receiving groove in some embodiments;

[0051] Figure 27 Schematic cross-sectional view of a structure obtained after forming a transistor and a word line in some embodiments;

[0052] Figure 28 Schematic cross-sectional view of a structure obtained after forming a through hole in some embodiments;

[0053] Figure 29 Schematic cross-sectional view of a structure obtained after forming a bit line lead in some embodiments.

[0054] Explanation of reference numerals:

[0055] 1 - Substrate, 2 - Stacked structure, 21 - Target material layer, 22 - Support material layer, G - Etching trench, 3 - Sacrificial material layer, 4 - Step structure, 41 - First step, 42 - Second step, 5 - Isolation barrier, 6 - Isolation structure, A - Array region, B - Peripheral region, C - Capacitor, 71 - First electrode, 72 - Second electrode, 720 - Second electrode material layer, 721 - Second electrode conductive layer, 722 - Polysilicon layer, 73 - High - K dielectric layer, 730 - High - K dielectric material layer, T - Transistor, 81 - Gate, 82 - Gate dielectric layer, 83 - Semiconductor layer, BL - Bit line, CBL - Common bit line, WL - Word line, 9 - Mask structure, 91 - Photoresist pattern layer, 92 - First anti - reflection layer, 93 - Mask material layer, 94 - Second anti - reflection layer, 10 - Array unit, 101 - Conductive branch, 11 - Insulating structure, 111 - Nitride layer, 112 - Oxide layer, 12 - Support frame, 13 - Hard mask layer, 14 - First protective layer, 15 - First etching hole, 16 - Second protective layer, 17 - Planarization layer, 18 - Word line hole, 19 - Third protective layer, S - Transistor accommodation groove, 20 - Insulating seal layer, H - Through - hole, CT - Bit line lead, CT1 - Seed layer, CT2 - Metal wire. Detailed implementation manners

[0056] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant accompanying drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0058] It should be understood that when an element or layer is referred to as "on", "adjacent to", or "connected to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0059] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups thereof are not excluded from the presence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0060] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, and such variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0061] In three-dimensional memories, the staircase structure relying on the metal-oxide stack structure has received extensive attention. The staircase structure can be formed by alternately laminating multiple insulating layers and multiple conductive layers, so as to lead out the signal lines connecting the corresponding layer memory cells by using any conductive layer, and solve the problem that it is difficult to lead out the signal lines after the three-dimensional stacking of the memory cells.

[0062] In the current manufacturing method, it is necessary to manufacture the step partitions through multiple cycles of trimming-etching, and multiple replication etching processes to form the staircase structure. However, as the number of stacked layers of memory cells in three-dimensional memories increases, this manufacturing method of the staircase structure that requires repeated etching also becomes more complicated. Therefore, a more efficient manufacturing method for the staircase structure is urgently needed.

[0063] Based on this, some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which is beneficial to reducing the complexity of the process steps and realizing the efficient manufacturing of a stepped structure.

[0064] In a first aspect, please refer to Figure 1 , some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including the following steps S100 to S400.

[0065] S100, please refer to Figure 2 , provide a substrate 1, and form a stacked structure 2 on one side of the substrate 1. The stacked structure 2 includes: a plurality of target material layers 21 stacked along a direction perpendicular to the substrate 1, and a support material layer 22 located between any two adjacent target material layers 21.

[0066] Exemplarily, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0067] Exemplarily, please continue to refer to Figure 2 , the stacked structure 2 starts to be stacked with the support material layer 22.

[0068] It should be noted that the stacked structure 2 can also start to be stacked with the target material layer 21, and the present disclosure does not limit this.

[0069] In some examples, the target material layer 21 includes a metal material layer or a semiconductor material layer.

[0070] Exemplarily, the target material layer 21 can be W, or can also be Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, and Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive materials such as conductive metal nitrides (e.g., titanium nitride TiN), conductive metal silicides, conductive metal carbides, conductive doped semiconductors (e.g., doped polysilicon), conductive metal oxide semiconductors (e.g., indium tin oxide), etc. It can also be semiconductor or dielectric materials such as SiNx, doped polysilicon, amorphous silicon, doped polysilicon germanium, AsGa, AlAsGa, InP, etc.

[0071] Exemplarily, the support material layer 22 can be SiO2 material, or can also be SiNx, AlOx, HfOx, TiOx, SiOxNy, SiOxCzNy or other insulating materials.

[0072] In some embodiments, the thicknesses of the multiple target material layers 21 can be the same or different, the thicknesses of the multiple support material layers 22 can be the same or different, and the thicknesses of the target material layer 21 and the support material layer 22 can be set according to specific process requirements. In addition, the stacked structure 2 can include multiple pairs of target material layers 21 and support material layers 22 that are alternately stacked. For example, the stacked structure 2 can include 3 pairs, 6 pairs, 32 pairs, 64 pairs, 128 pairs or more than 128 pairs of target material layers 21 and support material layers 22. It should be noted that although the specific number of pairs of the target material layer 21 and the support material layer 22 is exemplified here, other numbers of pairs of the target material layer 21 and the support material layer 22 can also be used in other embodiments, and the present disclosure does not limit this.

[0073] S200, please continue to refer to Figure 2 , etch the stacked structure 2 along the direction perpendicular to the substrate 1 to form an etched trench G extending in the first direction (e.g., the Z direction).

[0074] In some embodiments, please continue to refer to Figure 2 , the etched trench G can penetrate through the stacked structure 2 and extend to the substrate 1, or can only penetrate through several pairs of the target material layer 21 and the support material layer 22 in the stacked structure 2. It should be noted that in the embodiments of the present disclosure, the number of steps in the finally formed stepped structure 4 is less than or equal to the number of pairs of the target material layer 21 and the support material layer 22 penetrated by the etched trench G.

[0075] Exemplarily, the etched trench G can be formed by dry etching based on a photomask.

[0076] S300, please continue to refer to Figure 2 , and form a sacrificial material layer 3 in the etched trench G.

[0077] Exemplarily, the sacrificial material layer 3 can be a metal nitride layer, such as titanium nitride (TiN) or silicon nitride (SiN).

[0078] Exemplarily, the sacrificial material layer 3 is formed by a deposition process, including but not limited to physical vapor deposition process, chemical vapor deposition process, epitaxial deposition process, or atomic layer deposition process, etc.

[0079] Exemplarily, after the sacrificial material layer 3 is formed in the etched trench G, the manufacturing method of the semiconductor structure further includes: using a grinding process to make the surface of the sacrificial material layer 3 facing away from the substrate 1 flush with the surface of the stacked structure 2 facing away from the substrate 1, and the grinding process includes but is not limited to chemical mechanical polishing (CMP) process.

[0080] S400, please refer to Figure 2 and Figure 6 , and repeatedly perform a plurality of target processes on the obtained structure after the sacrificial material layer 3 is formed (such as the structure shown in Figure 2 ) so that the remaining portions of the respective target material layers 21 correspondingly form first steps 41 (such as the structure shown in Figure 6 ), and the plurality of first steps 41 are arranged in a stepped structure 4 along a second direction (such as the X direction). Wherein, the second direction (such as the X direction) intersects with the first direction (such as the Z direction).

[0081] Exemplarily, the etching rates between the target material layer 21 and the sacrificial material layer 3 are different.

[0082] Exemplarily, there is a high etching selectivity between the target material layer 21 and the support material layer 22, which is easy to avoid or reduce the etching damage of the support material layer 22 while etching the target material layer 21.

[0083] In some embodiments, please refer to Figure 3 , one target process includes the following steps S410~S420.

[0084] S410, please refer to Figure 4 , etch and remove the sacrificial material layer 3 with a target height along the direction perpendicular to the substrate 1 to expose the sidewalls of the target material layer 21 of the target layer.

[0085] In some examples, the sacrificial material layer 3 is etched by an anisotropic etching process.

[0086] Exemplarily, the anisotropic etching process can be a dry etching process, such as a radio frequency plasma source dry etching process.

[0087] For example, see Figure 4 , the target height may be 50nm, 100nm or 200nm, etc., and the target height is, for example, 100nm.

[0088] For example, the target height may be the sum of the heights of a target material layer 21 and a support material layer 22 (ie, the dimension in a direction perpendicular to the substrate 1 ).

[0089] In some embodiments, the target material layer 21 and the sacrificial material layer 3 are etched at different rates, which is beneficial for separately etching the target material layer 21 and the sacrificial material layer 3 .

[0090] S420, see Figure 5 , the target material layer 21 of the target layer is etched along a direction parallel to the substrate 1 , and simultaneously, each target material layer 21 exposed on the side of the target layer away from the substrate 1 is etched from top to bottom along a direction parallel to the substrate 1 .

[0091] In some examples, the etching width of the target material layer 21 of the target layer can be determined by matching the step width to be formed, and the etching width can be, for example, 300nm, 500nm, or 700nm. For example, the target width includes, but is not limited to, 500nm. Thus, the embodiment of the present disclosure can control the width of the corresponding step in the step structure 4 by adjusting the etching width of the target material layer 21 of the target layer.

[0092] It is worth mentioning that in the embodiment of the present disclosure, the width of each step in the stepped structure 4 can also be controlled by one or more of adjusting the etching selectivity ratio of each target material layer 21 relative to the sacrificial material layer 3, adjusting the thickness of the supporting material layer 22, or adjusting the width of the etching groove G.

[0093] In some examples, the target material layer 21 is etched using a wet etching process; the etching selectivity ratio of the target material layer 21 to the sacrificial material layer 3 is greater than or equal to 10:1.

[0094] By way of example, the etching selectivity ratio of the target material layer 21 to the sacrificial material layer 3 is 10:1, 15:1 or 20:1.

[0095] In some examples, the target material layer 21 is etched using a remote plasma source etching process; the etching selectivity ratio of the target material layer 21 to the sacrificial material layer 3 is greater than 1:1 and less than or equal to 5:1.

[0096] Illustratively, the etching selectivity ratio of the target material layer 21 to the sacrificial material layer 3 is 1.5:1, 2:1, 3:1, 4:1 or 5:1.

[0097] Exemplarily, the target material layer 21 is etched using a remote plasma source etching process, and the reaction gas of the plasma source can be nitrogen trifluoride gas (NF 3 ), helium gas (He), and chlorine gas (Cl 2 ). The volume ratio of nitrogen trifluoride gas to chlorine gas can be 1:5 to 2:5, and the ratio of the volume of helium gas to the sum of the volumes of nitrogen trifluoride and chlorine gas can be 1:3 to 1:1.

[0098] In some examples, the target material layer 21 can be etched using a vapor etch process.

[0099] It should be noted that the target material layer 21 is etched using an isotropic etching process; it should be noted that in the isotropic etching process, when etching the same material, the etching rates in all directions are the same.

[0100] In some embodiments, please refer to Figure 6 , step S420 further includes: S421, symmetrically etching each target material layer 21 on opposite sides of the etching trench G in the second direction (e.g., the X direction) to form a double-step stepped structure 4 symmetrically disposed with the etching trench G as the center.

[0101] In some embodiments, before forming the stacked structure 2 on one side of the substrate 1 in step S100, the following step S110 is further included.

[0102] S110, please refer to Figure 7 , form an isolation barrier 5 on one side of the substrate 1.

[0103] Correspondingly, please continue to refer to Figure 7 , the stacked structure 2 is formed on one side of the isolation barrier 5 in step S100; the etching trench G exposes the side wall of the isolation barrier 5 facing the stacked structure 2 in step S200.

[0104] Exemplarily, the isolation barrier 5 can be made of the same material as the support material layer 22.

[0105] Exemplarily, the isolation barrier 5 can be made of SiO2 material, or can also be SiNx, AlOx, HfOx, TiOx, SiOxNy, SiOxCzNy, or other insulating materials.

[0106] In some examples, please refer to Figure 8 , step S420 further includes: S422, etching each target material layer 21 on the side of the etching trench G away from the isolation barrier 5 in the second direction (e.g., the X direction) to form a single-step stepped structure 4 located on the side of the etching trench G away from the isolation barrier 5 in the second direction (e.g., the X direction).

[0107] In some embodiments, after step S400, the method for fabricating a semiconductor structure further includes step S500a or S500b as follows.

[0108] S500a, please refer to Figure 9 , to form an isolation structure 6 that fills the etching trench G and the etching removal regions of each target material layer 21.

[0109] S500b, please refer to Figure 10 , using each first step 41 as a mask to etch adjacent support material layers 22 respectively, so that the remaining portions of each support material layer 22 correspondingly form second steps 42; to form an isolation structure 6 that fills the etching trench G and the etching removal regions of each target material layer 21 and each support material layer 22.

[0110] Exemplarily, in step S500b, dry etch process can be adopted to etch adjacent support material layers 22 using each first step 41 as a mask respectively.

[0111] Exemplarily, the isolation structure 6 can be made of the same material as the support material layer 22.

[0112] Exemplarily, the isolation structure 6 can be made of SiO2 material, and can also be SiNx, AlOx, HfOx, TiOx, SiOxNy, SiOxCzNy or other insulating materials.

[0113] In some embodiments, please refer to Figure 11 , the semiconductor structure includes an array region A and a peripheral region B. The stepped structure 4 can be disposed in the peripheral region B. The semiconductor structure further includes a plurality of array units 10 arrayed in the array region A.

[0114] It should be noted that in the embodiments of the present disclosure, the distribution position, the distribution quantity, and the number of stacked steps therein of the stepped structure 4 in the semiconductor structure can all be set according to requirements. The embodiments of the present disclosure do not limit this.

[0115] In some embodiments, after step S500a or S500b, the method for fabricating a semiconductor structure further includes step S600 as follows.

[0116] S600, please continue to refer to Figure 11 , to pattern the target material layer 21, to form a common bit line CBL respectively connected to each first step 41, and a bit line BL connected to the common bit line CBL. Wherein, the common bit line CBL extends along the second direction (for example, the X direction).

[0117] Exemplarily, the common bit line CBL, the bit line BL and the first step 41 can be an integral structure.

[0118] In some embodiments, please refer to Figure 12 , the array unit 10 includes: a transistor T and a capacitor C. The transistor T includes a gate 81, and a gate dielectric layer 82 and a semiconductor layer 83 surrounding the sidewalls of the gate 81; wherein, the gate 81 is electrically connected to the word line WL; the semiconductor layer 83 can serve as the channel region and source / drain electrodes of the transistor T, and the outer walls of the two opposite sides of the semiconductor layer 83 in the X direction are respectively electrically connected to the bit line BL and the first electrode 71 of the capacitor C. The word line WL can extend in a direction perpendicular to the substrate 1. The bit line BL can extend in a third direction (e.g., the Y direction). And, a plurality of array units 10 can be arranged at intervals in the third direction (e.g., the Y direction) to form a column. Wherein, the third direction intersects with the second direction.

[0119] Exemplarily, a column of array units 10 shares the same bit line BL.

[0120] Exemplarily, two adjacent columns of array units 10 are respectively located on both sides of the bit line BL and share the same bit line BL.

[0121] Exemplarily, each bit line BL can be respectively electrically connected to the common bit line CBL of the same layer through a corresponding selection transistor ( Figure 12 not shown in the figure). Here, the same layer setting means that the heights of the two from the surface of the substrate 1 are substantially the same.

[0122] It should be added that in some of the above embodiments, each first step 41 in the stepped structure 4 can be respectively an external connection end of the corresponding common bit line CBL and is led out through a lead CT.

[0123] It should be noted that in the following embodiments, the preparation of each array unit 10 in the array region A of the semiconductor structure is exemplified.

[0124] In some examples, please refer to Figure 13 , the preparation method of the semiconductor structure further includes the following steps S710 to S716.

[0125] S701, please combine Figure 12 and Figure 14 to understand that a mask structure 9 is formed above the stacked structure 2, including: a photoresist pattern layer 91, a first anti-reflection layer 92, a mask material layer 93, and a second anti-reflection layer 94 stacked from top to bottom.

[0126] Exemplarily, the first anti-reflection layer 92 can be a silicon oxynitride (SiON) layer.

[0127] Exemplarily, the mask material layer 93 can be a carbide layer.

[0128] Exemplarily, the second anti-reflection layer 94 can be a nitride layer, such as silicon nitride (SiN).

[0129] S702, please understand in combination with Figure 12 and Figure 15 that based on the photoresist pattern layer 91, the underlying structure is etched, and polished until the upper surface of the second anti-reflection layer 94 facing away from the substrate 1 is exposed, obtaining the patterned stacked structure 2, forming the array unit 10, and enabling the target material layer 21 retained in the array unit 10 to include bit lines BL extending along the first direction, and a plurality of conductive branches 101 that are spaced apart in the first direction (e.g., the Z direction) and extend along the second direction (e.g., the X direction) outside the bit lines BL.

[0130] Exemplarily, the stacked structure 2 can be etched using a photolithography process.

[0131] S703, please understand in combination with Figure 12 and Figure 16 that an insulating structure 11 is formed to cover the stacked structure 2 and fill the etched area of the stacked structure 2. The insulating structure 11 includes, for example, a stacked nitride layer 111 and oxide layer 112.

[0132] Exemplarily, the nitride layer 111 can be a silicon nitride (SiN) layer.

[0133] Exemplarily, the oxide layer 112 can be a silicon oxide (SiO) layer.

[0134] S704, please understand in combination with Figure 12 and Figure 17 that the insulating structure 11 on the sidewalls of the array unit 10 is etched until the sidewalls of each target material layer 21 are exposed.

[0135] S705, please understand in combination with Figure 12 and Figure 18 that a support frame 12 is formed in the etched area of the insulating structure 11, and polished until the top support material layer 22 of the stacked structure 2 is exposed.

[0136] Exemplarily, the support frame 12 can be formed of silicon nitride (SiN).

[0137] S705, please understand in combination with Figure 12 and Figure 19 that a hard mask layer 13 is formed to cover the stacked structure 2.

[0138] In some examples, please refer to Figure 19 , before forming the hard mask layer 13 in step S705, a first protective layer 14 covering the top support material layer 22 in the stacked structure 2 can also be formed, and the hard mask layer 13 is formed on the surface of the first protective layer 14 facing away from the substrate 1.

[0139] Exemplarily, the first protective layer 14 can be a silicon nitride (SiN) layer.

[0140] S706, please refer to Figure 12 and Figure 19 Figure (b) and Figure (d) in

[0141] For example, the hard mask layer 13 can be a polysilicon (poly) layer.

[0142] S707, please refer to Figure 12 and Figure 20 to understand that each support material layer 22 exposed in the first etching hole 15 is etched so that the end of the corresponding conductive branch 101 away from the bit line BL is exposed, and this exposed end constitutes the first electrode 71 of the capacitor C.

[0143] For example, each support material layer 22 exposed in the first etching hole 15 can be etched by a wet etching process.

[0144] S708, please refer to Figure 12 and Figure 21 to understand that the hard mask layer 13 is removed.

[0145] In some examples, the capacitor C further includes a high-K dielectric layer 73 and a second electrode 72. The method for preparing the semiconductor structure further includes the following steps S709 - S710.

[0146] S709, please refer to Figure 12 and Figure 22 to understand that a high-K dielectric material layer 730 covering the first electrode 71 and a second electrode material layer 720 covering the high-K dielectric material layer 730 and filling the removed areas of the support material layers 22 and the first etching hole 15 are formed.

[0147] In some examples, both the second electrode material layer 720 and the second electrode 72 include a second electrode conductive layer 721 and a polysilicon layer 722 arranged in a stacked manner, where the second electrode conductive layer 721 covers the high-K dielectric layer 73 and the polysilicon layer 722 covers the second electrode conductive layer 721.

[0148] For example, the material of the second electrode conductive layer 721 can be titanium (Ti) or titanium nitride (TiN).

[0149] S710, please refer to Figure 12 and Figure 23 to understand that the high-K dielectric material layer 730 and the second electrode material layer 720 are patterned to obtain the high-K dielectric layer 73 and the second electrode 72.

[0150] It should be noted that, please refer to Figure 23, before patterning the high-K dielectric material layer 730 and the second electrode material layer 720, a second protective layer 16 covering the surface of the second electrode 72 facing away from the substrate 1 can be formed; correspondingly, after patterning the high-K dielectric material layer 730 and the second electrode material layer 720, the unetched portion of the surface of the second electrode 72 facing away from the substrate 1 is covered with the second protective layer 16.

[0151] S711, please refer to Figure 12 and Figure 24 for understanding, a planarization layer 17 is formed in the etching regions of the high-K dielectric material layer 730 and the second electrode material layer 720.

[0152] In some examples, the surface of the planarization layer 17 facing away from the substrate 1 is flush with the surface of the second protective layer 16 facing away from the substrate 1.

[0153] Exemplarily, the planarization layer 17 can be an oxide layer, such as a silicon oxide (SiO) layer.

[0154] S712, please refer to Figure 12 and Figure 25 for understanding, a word line hole 18 penetrating the corresponding conductive branch 101 in the direction perpendicular to the substrate 1 is formed between the first electrode 71 and the bit line BL.

[0155] It should be noted that, please refer to Figure 25 , before forming the word line hole 18, a third protective layer 19 covering the surfaces of the planarization layer 17 and the second protective layer 16 facing away from the substrate 1 can be formed; correspondingly, after forming the word line hole 18, the unetched portions of the surfaces of the planarization layer 17 and the second protective layer 16 facing away from the substrate 1 are covered with the third protective layer 19.

[0156] S713, please refer to Figure 12 and Figure 26 for understanding, the corresponding conductive branch 101 is etched based on the word line hole 18 to form a transistor accommodation groove S.

[0157] Exemplarily, the etching of each conductive branch 101 based on the word line hole 18 can adopt an isotropic etching process, such as wet etching (Wet etch), isotropic dry remote plasma source (Remote plasma source, abbreviated as RPS) etching or vapor etching (Vapor etch).

[0158] S714, please refer to Figure 12 and Figure 27 for understanding, a semiconductor layer 83 covering the inner sidewall of the transistor accommodation groove S, a gate dielectric layer 82, and a word line WL covering the gate dielectric layer 82 and filling the word line hole 18 are formed.

[0159] It should be noted that, please refer to Figure 27In FIG. (a1), the transistor T includes a gate 81, a gate dielectric layer 82 and a semiconductor layer 83 surrounding the sidewalls of the gate 81; wherein, the gate 81 is electrically connected to the word line WL.

[0160] S715, please refer to Figure 27 , an insulating encapsulation layer 20 is formed on the top of the second electrode 72, the word line WL and the planarization layer 17.

[0161] Exemplarily, the insulating encapsulation layer 20 may be an oxide layer, such as a silicon oxide (SiO) layer.

[0162] In some embodiments, the manufacturing method of the semiconductor structure further includes the following steps S810 - S820.

[0163] S810, please refer to Figure 12 and Figure 28 for understanding, a through hole H penetrating at least the isolation structure 6 is formed on the surface of the first step 41 away from the substrate 1.

[0164] It should be noted that, for clearly exemplifying the through hole H, Figure 28 the isolation structure 6 is not shown in Figure 9 or Figure 10 , but it can be understood that for the location and structure of the isolation structure 6 in this semiconductor structure, etc., please refer to

[0165] S820, please refer to Figure 12 and Figure 29 for understanding, a bit line lead CT is formed in the through hole H.

[0166] In some examples, the bit line lead CT includes a seed layer CT1 and a metal wire CT2, wherein, the seed layer CT1 covers the through hole H, and the metal wire CT2 covers the seed layer CT1 and fills the through hole H.

[0167] Exemplarily, the material of the seed layer CT1 includes titanium (Ti) or titanium nitride (TiN).

[0168] Exemplarily, the metal wire CT2 may be made of the same material as the target material layer 21, such as tungsten (W).

[0169] Regarding the regulation of the etching selectivity mentioned in some embodiments of the present disclosure, some possible solutions are listed as follows.

[0170] In some embodiments, the etching selectivity can be regulated by using different etching agents and / or different infrared heating times.

[0171] In some examples, the etching selectivity of the target material layer 21 and the sacrificial material layer 3 can be controlled by using different etching agents.

[0172] Exemplarily, the etchant can be a mixed gas of nitrogen trifluoride (NF 3 ), oxygen (O2), a mixed gas of sulfur hexafluoride (SF6), oxygen (O2) and argon (Ar), a mixed gas of trifluoromethane (CHF3) and oxygen (O2), or a mixed gas of difluoromethane (CH2F2), oxygen (O2) and argon (Ar).

[0173] In some examples, the etching selectivity between the target material layer 21 and the sacrificial material layer 3 can be controlled by adopting different infrared heating times.

[0174] In a second aspect, the present disclosure also provides a semiconductor structure according to some embodiments. It should be noted that the semiconductor structure has all the technical advantages of the manufacturing method of the foregoing semiconductor structure, and has the same or corresponding technical features as those in the above embodiments. For the corresponding descriptions of the corresponding technical features in the foregoing embodiments, no detailed description will be given below.

[0175] In some embodiments, referring to Figure 2 , the semiconductor structure includes: a substrate 1, a stacked structure 2, and a sacrificial material layer 3. The stacked structure 2 is located on one side of the substrate 1 and includes: a plurality of target material layers 21 stacked along a direction perpendicular to the substrate 1, and a support material layer 22 located between any two adjacent target material layers 21; the stacked structure 2 has an etching trench G extending in a first direction (for example, the Z direction). The sacrificial material layer 3 is filled in the etching trench G.

[0176] In some examples, each of the target material layers 21 and the sacrificial material layer 3 is configured to: after performing the target process multiple times in a cycle, the remaining portions of each of the target material layers 21 correspondingly form a first step 41, and the plurality of first steps 41 are arranged in a stepped structure 4 in a second direction (as Figure 6 shown); the second direction intersects the first direction. The target process includes: etching and removing the sacrificial material layer 3 with a target height along a direction perpendicular to the substrate 1 to expose the sidewalls of the target material layers 21 of the target layer; etching the target material layers 21 of the target layer along a direction parallel to the substrate 1, and synchronously etching the target material layers 21 exposed on the side of the target layer facing away from the substrate 1 from top to bottom along a direction parallel to the substrate 1.

[0177] In some embodiments, referring to Figure 7 , the semiconductor structure further includes: an isolation barrier 5, located on one side of the stacked structure 2 along a direction parallel to the substrate 1. Among them, the sacrificial material layer 3 is located between the isolation barrier 5 and the stacked structure 2.

[0178] It should be noted that the etching trench G exposes the sidewall of the isolation barrier 5 facing the stacked structure 2, and the sacrificial material layer 3 is filled in the etching trench G and located between the isolation barrier 5 and the stacked structure 2.

[0179] In some examples, the etching rates between the target material layer 21 and the sacrificial material layer 3 are different.

[0180] In some examples, the etching rates between the target material layer 21 and the support material layer 22 are different.

[0181] In a third aspect, the present disclosure also provides a memory according to some embodiments. It should be noted that the memory also has the technical advantages of the foregoing semiconductor structure and its manufacturing method, and for the same or corresponding parts as those in the above embodiments, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be elaborated in detail hereinafter.

[0182] In some embodiments, the memory includes at least one stepped structure 4. The stepped structure 4 is obtained by etching the semiconductor structure as described in the second aspect of the embodiments of the present disclosure. The stepped structure 4 includes at least a plurality of first steps 41.

[0183] In some embodiments, please refer to Figure 12 and Figure 29 for understanding. The memory further includes a plurality of common bit lines CBL, a plurality of bit lines BL, and a plurality of bit line leads CT. The common bit line CBL is correspondingly connected to the first step 41, the bit line BL is correspondingly connected to the common bit line CBL, and the connected first step 41, common bit line CBL, and bit line BL are respectively parts of the same target material layer 21 in different regions; the bit line lead CT is located on the surface of the first step 41 facing away from the substrate 1 and extends in a direction perpendicular to the substrate 1.

[0184] It should be noted that here, please refer to Figure 11 for understanding. The fact that the first step 41, the common bit line CBL, and the bit line BL are respectively parts of the same target material layer 21 in different regions means that the first step 41, the common bit line CBL, and the bit line BL of the same layer can be obtained by patterning the corresponding target material layer 21.

[0185] In a fourth aspect, the present disclosure also provides an electronic device according to some embodiments. The electronic device includes the memory as described in the third aspect of the embodiments of the present disclosure. It should be noted that the electronic device also has the technical advantages of the foregoing semiconductor structure, its manufacturing method, and the memory, and for the same or corresponding parts as those in the above embodiments, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be elaborated in detail hereinafter.

[0186] The technical features of the above embodiments can be combined arbitrarily. For the sake of brief description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0187] The above-described embodiments merely represent several implementation manners of the present disclosure. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all fall within the protection scope of the present disclosure.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, comprising: providing a substrate, and forming a stacked structure on one side of the substrate; the stacked structure includes: a plurality of target material layers stacked along a direction perpendicular to the substrate, and a support material layer located between any two adjacent target material layers; etching the stacked structure along a direction perpendicular to the substrate to form an etching trench extending in a first direction; forming a sacrificial material layer in the etching trench; performing a plurality of target processes on the obtained structure after forming the sacrificial material layer in a cyclic manner, so that the remaining portions of the respective target material layers correspondingly form first steps, and the plurality of first steps are arranged in a stepped structure along a second direction; the second direction intersects with the first direction; wherein, one target process includes: etching and removing the sacrificial material layer with a target height along a direction perpendicular to the substrate to expose the sidewalls of the target material layer of the target layer; etching the target material layer of the target layer along a direction parallel to the substrate, and synchronously etching the respective target material layers exposed on the side of the target layer facing away from the substrate from top to bottom along a direction parallel to the substrate.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, the etching rates between the target material layer and the sacrificial material layer are different.

3. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, the target material layer is etched by a wet etching process; the etching selectivity between the target material layer and the sacrificial material layer is greater than or equal to 10:

1.

4. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, the target material layer is etched by a remote plasma source etching process; the etching selectivity between the target material layer and the sacrificial material layer is greater than 1:1 and less than or equal to 5:

1.

5. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, the sacrificial material layer is etched by an anisotropic etching process.

6. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, the etching of the target material layer of the target layer along a direction parallel to the substrate, and the synchronous etching of the respective target material layers exposed on the side of the target layer facing away from the substrate from top to bottom along a direction parallel to the substrate further includes: symmetrically etching the respective target material layers on opposite sides of the etching trench in the second direction to form the stepped structure symmetrically arranged with the etching trench as the center.

7. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, further comprising: forming an isolation barrier on one side of the substrate; wherein, the stacked structure is formed on one side of the isolation barrier, and the etching trench exposes the sidewall of the isolation barrier facing the stacked structure.

8. The manufacturing method of the semiconductor structure according to any one of claims 1 to 7, characterized in that, the target material layer includes a metal material layer or a semiconductor material layer; the manufacturing method further includes: patterning the target material layer to form a common bit line respectively connected to each of the first steps, and a bit line connected to the common bit line; wherein, the common bit line extends along the second direction.

9. The manufacturing method of the semiconductor structure according to claim 8, characterized in that, further comprising: forming an isolation structure to fill the etched trench and the etched removal regions of the target material layers; or, respectively etching adjacent support material layers with each of the first steps as a mask, so that the remaining portions of the support material layers respectively form second steps; forming an isolation structure to fill the etched trench and the etched removal regions of the target material layers and the support material layers.

10. The manufacturing method of the semiconductor structure according to claim 9, characterized in that, further comprising: forming a through hole at least penetrating the isolation structure on a surface of the first step facing away from the substrate; forming a bit line lead in the through hole.

11. A semiconductor structure, characterized in that, comprising: a substrate; a stacked structure located on one side of the substrate, including: a plurality of target material layers stacked along a direction perpendicular to the substrate, and support material layers located between any two adjacent target material layers; the stacked structure has an etched trench extending in a first direction; a sacrificial material layer filled in the etched trench; wherein, each of the target material layers and the sacrificial material layer are configured to: after performing a target process multiple times in a cycle, the remaining portions of the target material layers respectively form first steps, and the plurality of first steps are arranged in a stepped structure along a second direction; the second direction intersects the first direction; the target process includes: etching and removing the sacrificial material layer with a target height along a direction perpendicular to the substrate to expose the sidewalls of the target material layers of the target layer; etching the target material layers of the target layer along a direction parallel to the substrate, and synchronously etching each of the target material layers exposed on a side of the target layer facing away from the substrate from top to bottom along a direction parallel to the substrate.

12. The semiconductor structure according to claim 11, characterized in that, further comprising: an isolation barrier located on one side of the stacked structure along a direction parallel to the substrate; wherein, the sacrificial material layer is located between the isolation barrier and the stacked structure.

13. A memory, characterized in that, comprising: at least one stepped structure; wherein, the stepped structure is obtained by etching the semiconductor structure according to claim 11 or 12, and the stepped structure at least includes: a plurality of the first steps.

14. The memory according to claim 13, characterized in that, further comprising: a plurality of common bit lines, a plurality of bit lines and a plurality of bit line leads; wherein, the common bit lines are correspondingly connected to the first steps, the bit lines are correspondingly connected to the common bit lines, and the connected first steps, common bit lines and bit lines are respectively parts of the same target material layer in different regions; the bit line leads are located on a surface of the first step facing away from the substrate and extend along a direction perpendicular to the substrate.

15. An electronic device, characterized in that, comprising: the memory according to claim 13 or 14.

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