Semiconductor element structure with back pickup region and preparation method thereof

Abstract

The invention provides a semiconductor element structure and a preparation method thereof. The semiconductor device structure includes a substrate, a first well region, a source / drain feature, and a pickup region. The substrate has a first surface and a second surface opposite to the first surface. The first well region adjoins the second surface of the substrate and has a first conductivity type. The source / drain feature adjoins the second surface of the substrate and has a second conductivity type different from the first conductivity type. The pickup region adjoins the first surface of the substrate and has the first conductivity type.

Description

[0001] Cross-reference

[0002] This application claims the priority of U.S. Patent Application No. 18 / 536,597 (i.e., the priority date is "December 12, 2023"), the content of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device structure. In particular, it relates to a semiconductor device structure having a backside pick-up region and a method of manufacturing the same. Background Art

[0004] With the rapid development of the electronics industry, the development of integrated circuits (ICs) has reached high performance and miniaturization. Technological advancements in IC materials and design have resulted in several generations of ICs, each having smaller and more complex circuits than the previous generation.

[0005] A dynamic random access memory (DRAM) device is a random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Typically, a DRAM is arranged in a square array with one capacitor and one transistor per cell. A vertical transistor has been developed for 4F 2 DRAM cells, where F represents the minimum feature width or critical dimension (CD) of lithography. However, recently, with the improvement of technology nodes, DRAM manufacturers are facing significant challenges.

[0006] The above description of "prior art" only provides background art and does not admit that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above "prior art" should not be taken as any part of the present disclosure. Summary of the Invention

[0007] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first well region, source / drain (S / D) features, and a first pick-up region. The substrate has a first surface and a second surface opposite to the first surface. The first well region is adjacent to the second surface of the substrate and has a first conductivity type. The source / drain features are adjacent to the second surface of the substrate and have a second conductivity type, which is different from the first conductivity type. The first pick-up region is adjacent to the first surface of the substrate and has the first conductivity type.

[0008] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first well region, a source / drain feature, an isolation structure, and a first pick-up region. The substrate has a first surface and a second surface opposite to the first surface. The first well region is adjacent to the second surface of the substrate and has a first conductivity type. The source / drain feature is adjacent to the second surface of the substrate and has a second conductivity type, which is different from the first conductivity type. The isolation structure is embedded in the substrate and extends from the second surface of the substrate towards the first surface. The first pick-up region has the first conductivity type and is located between the first surface of the substrate and the isolation structure.

[0009] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device structure. The manufacturing method includes providing a substrate having a first surface and a second surface opposite to the first surface. The manufacturing method also includes forming a first well region adjacent to the second surface of the substrate. The first well region has a first conductivity type. The manufacturing method further includes forming a source / drain feature adjacent to the second surface of the substrate. The source / drain feature has a second conductivity type, which is different from the first conductivity type. In addition, the manufacturing method includes forming a pick-up region adjacent to the first surface of the substrate. The pick-up region has the first conductivity type.

[0010] Embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure includes a pick-up region and a source / drain feature located on opposite two surfaces of a substrate. The pick-up region is configured to provide a low-resistance path to guide a drift current out of the semiconductor device structure through a back surface. The pick-up region can provide a relatively short drift current transmission path and reduce leakage caused by a cosmic ray incident on the semiconductor device structure.

[0011] The technical features and advantages of the present disclosure have been outlined quite extensively above, so that a better understanding of the detailed description of the present disclosure below can be obtained. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts and specific embodiments disclosed below can be quite easily used as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent constructs cannot depart from the spirit and scope of the present disclosure as defined by the claims. Description of the Drawings

[0012] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and the claims. The present disclosure should also be understood as being associated with the element numbers in the drawings, and the element numbers in the drawings represent similar elements throughout the description.

[0013] Figure 1 is a cross-sectional schematic diagram illustrating the semiconductor element structure of some embodiments of the present disclosure.

[0014] Figure 2 is a cross-sectional schematic diagram illustrating the semiconductor element structure including a depletion region of some embodiments of the present disclosure.

[0015] Figure 3 is a cross-sectional schematic diagram illustrating the semiconductor device structure including an induced depletion region of some embodiments of the present disclosure.

[0016] Figure 4 is a cross-sectional schematic diagram illustrating the semiconductor element structure of some embodiments of the present disclosure.

[0017] Figure 5 is a cross-sectional schematic diagram illustrating the semiconductor element structure of some embodiments of the present disclosure.

[0018] Figure 6 is a cross-sectional schematic diagram illustrating the semiconductor element structure of some embodiments of the present disclosure.

[0019] Figure 7 is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor element structure of some embodiments of the present disclosure.

[0020] Figure 8 is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor element structure of some embodiments of the present disclosure.

[0021] Figure 9 is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor element structure of some embodiments of the present disclosure.

[0022] Figure 10 is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor element structure of some embodiments of the present disclosure.

[0023] Figure 11 is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor element structure of some embodiments of the present disclosure.

[0024] Figure 12 is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor element structure of some embodiments of the present disclosure.

[0025] Figure 13 is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor element structure of some embodiments of the present disclosure.

[0026] Figure 14is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device structure according to some embodiments of the present disclosure.

[0027] Figure 15 is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device structure according to some embodiments of the present disclosure.

[0028] Figure 16 is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device structure according to some embodiments of the present disclosure.

[0029] Figure 17 is a flowchart illustrating a method for preparing a semiconductor device structure according to some embodiments of the present disclosure.

[0030] Description of reference numerals:

[0031] 100a: Semiconductor device structure

[0032] 100b: Semiconductor device structure

[0033] 100c: Semiconductor device structure

[0034] 100d: Semiconductor device structure

[0035] 102: Substrate

[0036] 102s1: Surface

[0037] 102s2: Surface

[0038] 104: Isolation layer

[0039] 110: Isolation structure

[0040] 122: Well region

[0041] 124: Well region

[0042] 126: Depletion region

[0043] 128: Induced depletion region

[0044] 132: Gate dielectric layer

[0045] 134: Gate electrode

[0046] 136: Spacer

[0047] 141a: Doped region

[0048] 141b: Doped region

[0049] 142a: Doped region

[0050] 142b: Doped region

[0051] 143a: Pickup area

[0052] 143b: Pickup area

[0053] 152: Pickup area

[0054] 154: Pickup area

[0055] 156a: Pickup area

[0056] 156b: Pickup area

[0057] 158a: Pickup area

[0058] 158b: Pickup area

[0059] 160: Conductive element

[0060] 170: Electrical connector

[0061] 200: Preparation method

[0062] 202: Step

[0063] 204: Step

[0064] 206: Step

[0065] 208: Step

[0066] 210: Step

[0067] 212: Step

[0068] L1: Cosmic rays Detailed implementation manners

[0069] The following describes specific examples of components and configurations to simplify the embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, when it is described that the first component is formed on the second component, it may include embodiments where the first and second components are in direct contact, or it may include embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, the embodiments of the present disclosure may repeat reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between various embodiments and / or the configurations discussed.

[0070] It should be understood that when an element is referred to as "connected to" or "coupled to" another element, the initial element can be directly connected to or coupled to the other element, or there may be other intermediate elements.

[0071] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, without departing from the teachings of the inventive concept of progressiveness, the first element, component, region, layer or section discussed below may be referred to as the second element, component, region, layer or section.

[0072] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0073] It should be understood that in the description of the present disclosure, the term "about" modifies the amounts of the ingredients, compositions or reactants of the present disclosure, meaning, for example, the variations in amounts that may occur through typical measurements used to prepare concentrates or solutions and liquid handling procedures. Moreover, inadvertent errors in measurement procedures, differences in the manufacture, source or purity of the ingredients used to make the compositions or implement the methods, etc. may result in variations. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. Further, in yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

[0074] Figure 1 is a cross-sectional schematic diagram illustrating the semiconductor element structure 100a of some embodiments of the present disclosure. In some embodiments, the semiconductor element structure 100a may be included in a memory element, such as a dynamic random access memory (DRAM) element, a one-time programmable (OTP) memory element, a static random access memory (SRAM) element device, or other suitable memory elements.

[0075] In some embodiments, the semiconductor element structure 100a may include a substrate 102. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 102 may include an elemental semiconductor, including silicon or germanium in a single crystal form, a polycrystalline form, or an amorphous form; a compound semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy having a graded Ge profile, wherein the Si and Ge components change from one ratio at one location of the graded SiGe profile to another ratio at another location. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 102 may have a multi-layer structure, or the substrate 102 may include a multi-layer compound semiconductor structure. The substrate 102 may have a surface 102s1 (or a bottom surface or a back surface) and a surface 102s2 (or a top surface or an active surface) opposite to the surface 102s1. As used herein, the term "active surface" may refer to a surface on which gate electrodes and / or source / drain features are disposed.

[0076] In some embodiments, the semiconductor element structure 100a may include an isolation layer 104. The isolation layer 104 may be disposed above or below the surface 102s1 of the substrate 102. The isolation layer 104 may include a dielectric material. The isolation layer 104 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0077] In some embodiments, the semiconductor element structure 100a may include an isolation structure 110. The isolation structure 110 may be at least partially embedded within the substrate 102. The isolation structure 110 may be recessed from the surface 102s2 towards the surface 102s1. In some embodiments, the isolation structure 110 may be a shallow trench isolation (STI). In other embodiments, the isolation structure 110 may include a local oxidation of silicon (LOCOS) structure or any other suitable isolation structure. The isolation structure 110 may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable materials.

[0078] In some embodiments, the semiconductor device structure 100a may include a well region 122. In some embodiments, the well region 122 may be located within the substrate 102. The well region 122 may surround the isolation structure 110. In some embodiments, the well region 122 may cover the lower surface (not labeled) of the isolation structure 110. The well region 122 may have a first conductivity type, such as n-type. In some embodiments, the n-type dopants include arsenic (As), phosphorus (P), antimony (Sb), other Group V elements, or any combination thereof. In some embodiments, the doping concentration of the well region 122 may be in the range between 1E14 atoms / cm 3 and 1E16 atoms / cm 3 3.

[0079] In some embodiments, the semiconductor device structure 100a may include a well region 124. In some embodiments, the well region 124 may be located within the substrate 102. The well region 124 may be adjacent to the well region 122. The well region 124 may surround the isolation structure 110. In some embodiments, the well region 124 may cover the lower surface (not labeled) of the isolation structure 110. The well region 124 may have a second conductivity type, which is different from the first conductivity type, such as p-type. In some embodiments, the p-type dopants include boron (B), other Group III elements, or any combination thereof. In some embodiments, the doping concentration of the well region 124 may be in the range between 1E14 atoms / cm 3 and 1E16 atoms / cm 3 3.

[0080] In some embodiments, the semiconductor device structure 100a may include a gate dielectric layer 132. The gate dielectric layer 132 may be disposed on or above the surface 102s2 of the substrate 102. In some embodiments, the gate dielectric layer 132 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or a combination thereof. In some embodiments, the gate dielectric layer 132 is a multi-layer structure, which includes an interface layer and a high-k (dielectric constant greater than 4) dielectric layer. The interface layer may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or a combination thereof. The high-k dielectric layer may include a high-k dielectric material, such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, other suitable high-k dielectric materials, or a combination thereof. In some embodiments, the high-k dielectric material may also be selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, and combinations thereof.

[0081] In some embodiments, the semiconductor device structure 100a may include a gate electrode 134. The gate electrode 134 may be disposed on or above the gate dielectric layer 132. The gate electrode 134 may include polysilicon, silicon-germanium, and / or at least one metal material, which includes elements and compounds, such as Mo, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, or other suitable conductive materials well-known in the art. In some embodiments, the gate electrode 134 includes a work function metal layer that provides an n-type metal work function or a p-type metal work function for a metal gate. The p-type metal work function materials include ruthenium, palladium, platinum, cobalt, nickel, materials of conductive metal oxides, or other suitable materials. The n-type metal work function materials include hafnium zirconium, titanium, tantalum, aluminum, metal carbides (such as hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or other suitable materials.

[0082] In some embodiments, the semiconductor device structure 100a may include a spacer 136. The spacer 136 may be disposed on opposite sides of the gate electrode 134 (or the gate dielectric layer 132). In some embodiments, the spacer 136 includes a dielectric material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, and may have a single-layer structure or a multi-layer structure including multiple dielectric layers.

[0083] In some embodiments, the semiconductor device structure 100a may include doped regions 141a and 142a. The doped regions 141a and 142a may be disposed within the substrate 102. The doped regions 141a and 142a may be adjacent to the surface 102s2 of the substrate 102. The doped regions 141a and 142a may be disposed within the well region 122. The doped regions 141a and 142a may jointly serve as a source / drain (S / D) feature. Each of the doped regions 141a and 142a may have a second conductivity type, such as p-type. In some embodiments, the doping concentration of each of the doped regions 141a and 142a may range between 1E17 atoms / cm 3 and 1E20 atoms / cm 3 . In some embodiments, the well region 122, the doped region 141a, and the doped region 142a may define a p-type metal oxide semiconductor field effect transistor (PMOS).

[0084] In some embodiments, the semiconductor device structure 100a may include a pick-up region 143a. The pick-up region 143a may be disposed within the substrate 102. The pick-up region 143a may be adjacent to the surface 102s2 of the substrate 102. The pick-up region 143a may be disposed within the well region 122. The pick-up region 143a may be spaced apart from source / drain features (e.g., doped regions 141a and 142a) by the isolation structure 110. The pick-up region 143a may be configured to provide a low-resistance path to direct current (e.g., a drift current) or the like out of the semiconductor device structure 100a through the surface 102s2 of the substrate 102. The pick-up region 143a may have a first conductivity type, such as n-type. In some embodiments, the doping concentration of the pick-up region 143a may be in the range of 1E17 atoms / cm 3 and 1E20 atoms / cm 3 between.

[0085] In some embodiments, the semiconductor device structure 100a may include a doped region 141b and a doped region 142b. The doped regions 141b and 142b may be disposed within the substrate 102. The doped regions 141b and 142b may be adjacent to the surface 102s2 of the substrate 102. The doped regions 141b and 142b may be disposed within the well region 124. The doped regions 141b and 142b may be jointly used as a source / drain feature. Each of the doped regions 141b and 142b may have a first conductivity type, such as n-type. In some embodiments, the range of the doping concentration of each of the doped regions 141b and 142b may be in the range of 1E17 atoms / cm 3 and 1E20 atoms / cm 3 between. In some embodiments, the well region 124, the doped region 141b, and the doped region 142b may define an n-type metal-oxide-semiconductor field-effect transistor (NMOS).

[0086] In some embodiments, the semiconductor device structure 100a may include a pick-up region 143b. The pick-up region 143b may be disposed within the substrate 102. The pick-up region 143b may be adjacent to the surface 102s2 of the substrate 102. The pick-up region 143b may be disposed within the well region 124. The pick-up region 143b may be spaced apart from the gate / drain features (e.g., doped regions 141b and 142b) by the isolation structure 110. The pick-up region 143b may be configured to provide a low-resistance path to direct a drift current or the like out of the semiconductor device structure 100a through the surface 102s2 of the substrate 102. The pick-up region 143b may have a second conductivity type, such as p-type. In some embodiments, the doping concentration of the pick-up region 143b may be in the range of 1E17 atoms / cm 3 and 1E20 atoms / cm 3 between.

[0087] In some embodiments, the semiconductor element structure 100a may include a pick-up region 152. The pick-up region 152 may be disposed within the substrate 102. In some embodiments, the pick-up region 152 may be adjacent to the surface 102s1 of the substrate 102. In some embodiments, the pick-up region 152 may be exposed through the surface 102s1 of the substrate 102. In some embodiments, the pick-up region 152 may be spaced apart from the isolation structure 110. In some embodiments, the pick-up region 152 may be located below the lower surface of the isolation structure 110. In some embodiments, the pick-up region 152 may be adjacent to or in contact with the well region 122.

[0088] In some embodiments, the pick-up region 152 may be configured to provide a low-resistance path to direct drift current or the like out of the semiconductor element structure 100a through the surface 102s1 of the substrate 102. The pick-up region 152 may have a first conductivity type, such as n-type. In some embodiments, the doping concentration of the pick-up region 152 may be greater than the doping concentration of the well region 122. In some embodiments, the doping concentration of the pick-up region 152 may be in the range between 1E17 atoms / cm 3 and 1E20 atoms / cm 3 In some embodiments, the doping concentration of the pick-up region 152 may be substantially equal to the doping concentration of the pick-up region 143a. In some embodiments, the doping concentration of the pick-up region 152 may be electrically connected to ground. In some embodiments, the same power as that applied to the pick-up region 143a may be applied to the pick-up region 152.

[0089] In some embodiments, the semiconductor element structure 100a may include a pick-up region 154. The pick-up region 154 may be disposed within the substrate 102. In some embodiments, the pick-up region 154 may be adjacent to the surface 102s1 of the substrate 102. In some embodiments, the pick-up region 154 may be exposed through the surface 102s1 of the substrate 102. In some embodiments, the pick-up region 154 may be spaced apart from the isolation structure 110. In some embodiments, the pick-up region 154 may be located below the lower surface of the isolation structure 110. In some embodiments, the pick-up region 154 may be adjacent to or in contact with the well region 124.

[0090] In some embodiments, the pick-up region 154 may be configured to provide a low-resistance path to direct drift current or the like out of the semiconductor element structure 100a through the surface 102s1 of the substrate 102. The pick-up region 154 may have a second conductivity type, such as p-type. In some embodiments, the doping concentration of the pick-up region 154 may be greater than the doping concentration of the well region 124. In some embodiments, the doping concentration of the pick-up region 154 may be in the range between 1E17 atoms / cm 3 and 1E20 atoms / cm 3within a range. In some embodiments, the doping concentration of the pickup region 154 can be substantially equal to the doping concentration of the pickup region 143b. In some embodiments, the doping concentration of the pickup region 154 can be electrically connected to ground. In some embodiments, the same power as that applied to the pickup region 143b can be applied to the pickup region 154.

[0091] In some embodiments, the semiconductor element structure 100a can include a plurality of conductive elements 160. In some embodiments, the conductive elements 160 can be disposed above or below the surface 102s1 of the substrate 102. In some embodiments, the conductive elements 160 can be embedded within the isolation layer 104. In some embodiments, the conductive elements 160 can be in contact with or electrically connected to the pickup region 152 (or 154). The conductive element 160 can include a conductive via, a conductive pillar, or other suitable conductive element. The conductive element 160 can include a conductive material such as tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or a combination thereof.

[0092] In some embodiments, the semiconductor element structure 100a can include an electrical connector 170. The electrical connector 170 can be disposed above or below the conductive element 160. The electrical connector 170 can be electrically connected to the conductive element 160. The electrical connector 170 can be configured to connect to an external element, such as a printed circuit board or a power supply. In some embodiments, the electrical connector 170 can include a ball grid array (BGA). In other embodiments, the electrical connector 170 includes an array, such as a land grid array (LGA) or a pin grid array (PGA). In some embodiments, the electrical connector 170 includes a plurality of solder balls, which can include lead or can be lead-free (e.g., including one or more materials such as an alloy of gold and tin solder or an alloy of silver and tin solder).

[0093] Figure 2 and Figure 3 is a cross-sectional schematic diagram illustrating a semiconductor element structure 100a according to some embodiments of the present disclosure including a depletion region and an induced depletion region.

[0094] As Figure 2 shown, the semiconductor element structure 100a can include a depletion region 126 between the doped region 141a and the well region 122. Although Figure 2Although not shown, it should be understood that the semiconductor device structure 100a may include other depletion regions located between doped regions and / or well regions having different conductivity types.

[0095] As Figure 3 shown, when a cosmic ray L1 is incident on the semiconductor device structure 100a, an induced depletion region 128 may be generated. The cosmic ray L1 may include a high-energy particle or a particle cluster (e.g., a proton, a neutron, or other particles). The induced depletion region 128 may extend from the depletion region 126 and extend along a direction substantially the same as or similar to the incident direction of the cosmic ray L1.

[0096] When the cosmic ray L1 passes through the semiconductor device structure 100a, a plurality of electron-hole pairs are generated, thereby forming the induced depletion region 128. As a result, a drift current may be generated. In some cases where the pickup region 152 and / or the pickup area 154 are not formed, the drift current may be guided to the surface 102s2 of the substrate 102 through the well region 122 and the pickup region 143a, and the drift current passes through the isolation structure 110. However, this path is still relatively long. In this case, the drift current induced by the cosmic ray L1 may cause leakage.

[0097] In some embodiments of the present disclosure, the pickup region 152 (or the pickup region 154) may be configured to provide a path for guiding the drift current to flow out through the surface 102s1 of the substrate 102 or neutralizing the carriers in the induced depletion region 128. As a result, leakage can be reduced. In some embodiments, the pickup region 152 (or the pickup region 154) is in contact with the induced depletion region 128. Therefore, the depth and / or height of the pickup region 152 may depend on the profile of the induced depletion region 128, and the induced depletion region 128 depends on the doping concentration of the source / drain features, the well region, and / or other doped regions.

[0098] Figure 4 is a cross-sectional schematic diagram illustrating a semiconductor device structure 100b according to some embodiments of the present disclosure. The semiconductor device structure 100b is similar to Figure 1 the semiconductor device structure 100a shown, and the differences are as follows.

[0099] In some embodiments, the semiconductor device structure 100b may include a pickup region 156a and a pickup region 156b. In some embodiments, the pickup region 156a may be spaced apart from the pickup region 156b. Each of the pickup regions 156a and 156b may be disposed in the substrate 102. In some embodiments, the pickup region 156a may be disposed below the doped region 141a. The pickup region 156a may vertically overlap the doped region 141a. In some embodiments, the pickup region 156b may be disposed below the doped region 142a. The pickup region 156b may vertically overlap the doped region 142a.

[0100] In some embodiments, each of the pickup regions 156a and 156b may be adjacent to the surface 102s1 of the substrate 102. In some embodiments, each of the pickup regions 156a and 156b may be exposed through the surface 102s1 of the substrate 102. In some embodiments, each of the pickup regions 156a and 156b may be spaced apart from the isolation structure 110. In some embodiments, each of the pickup regions 156a and 156b may be located below the lower surface of the isolation structure 110. In some embodiments, each of the pickup regions 156a and 156b may be adjacent to or in contact with the well region 122. In some embodiments, the well region 122 may also be disposed between the pickup regions 156a and 156b. In some embodiments, each of the pickup regions 156a and 156b may be configured to provide a low resistance path to direct drift current or the like out of the semiconductor device structure 100b through the surface 102s1 of the substrate 102. For example, the pickup region 156a may be configured to direct the drift current caused by the induced depletion region from the doped region 141a or to neutralize the carriers in the induced depletion region from the doped region 141a, and the pickup region 156b may be configured to direct the drift current caused by the induced depletion region from the doped region 142a or to neutralize the carriers in the induced depletion region from the doped region 142a. Each of the pickup regions 156a and 156b may have a first conductivity type, such as n-type. In some embodiments, the doping concentration of each of the pickup regions 156a and 156b may be in the range between 1E17 atoms / cm 3 and 1E20 atoms / cm 3 between.

[0101] In some embodiments, the semiconductor device structure 100b may include a pickup region 158a and a pickup region 158b. In some embodiments, the pickup region 158a may be spaced apart from the pickup region 158b. Each of the pickup regions 158a and 158b may be disposed within the substrate 102. In some embodiments, the pickup region 158a may be disposed below the doped region 141b. The pickup region 158a may vertically overlap the doped region 141b. In some embodiments, the pickup region 158b may be disposed below the doped region 142b. The pickup region 158b may vertically overlap the doped region 142b.

[0102] In some embodiments, each of the pick-up regions 158a and 158b may be adjacent to the surface 102s1 of the substrate 102. In some embodiments, each of the pick-up regions 158a and 158b may be exposed through the surface 102s1 of the substrate 102. In some embodiments, each of the pick-up regions 158a and 158b may be spaced apart from the isolation structure 110. In some embodiments, each of the pick-up regions 158a and 158b may be located below the lower surface of the isolation structure 110. In some embodiments, each of the pick-up regions 158a and 158b may be adjacent to or in contact with the well region 124. In some embodiments, the well region 122 may also be disposed between the pick-up regions 158a and 158b. In some embodiments, each of the pick-up regions 158a and 158b may be configured to provide a low-resistance path to direct drift current or the like out of the semiconductor element structure 100b through the surface 102s1 of the substrate 102 or to neutralize carriers in the induced depletion region. For example, the pick-up region 158a may be configured to direct the drift current caused by the induced depletion region from the doped region 141b or to neutralize the carriers from the induced depletion region of the doped region 141b, and the pick-up region 158b may be configured to direct the drift current caused by the induced depletion region from the doped region 142b or to neutralize the carriers from the induced depletion region of the doped region 142b. Each of the pick-up regions 158a and 158b may have a second conductivity type, such as p-type. In some embodiments, the doping concentration of each of the pick-up regions 158a and 158b may be in the range between 1E17 atoms / cm 3 and 1E20 atoms / cm 3 in the range.

[0103] Figure 5 is a cross-sectional schematic diagram illustrating a semiconductor element structure 100c according to some embodiments of the present disclosure. The semiconductor element structure 100c is similar to the semiconductor element structure 100a shown in Figure 1 as follows.

[0104] In some embodiments, the boundary between the well region 122 and the pick-up region 152 may be located at a plane that is higher than a plane of the lower surface of the isolation structure 110. In some embodiments, the pick-up region 152 may cover or contact a side surface (not labeled) of the isolation structure 110. In some embodiments, the pick-up region 152 may contact the lower surface of the isolation structure 110.

[0105] In some embodiments, the boundary between the well region 124 and the pick-up region 154 may be located at a plane that is higher than a plane of the lower surface of the isolation structure 110. In some embodiments, the pick-up region 154 may cover a side surface (not labeled) of the isolation structure 110. In some embodiments, the pick-up region 154 may contact the lower surface of the isolation structure 110.

[0106] Figure 6 is a cross-sectional schematic diagram illustrating the semiconductor element structure 100d of some embodiments of the present disclosure. The semiconductor element structure 100d is similar to the semiconductor element structure 100a shown in Figure 1 as follows.

[0107] In some embodiments, the semiconductor element structure 100d may not form a pick-up area 143a as shown in Figure 1 In some embodiments, the semiconductor element structure 100d may not form a pick-up area 143b as shown in Figure 1

[0108] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 are schematic diagrams illustrating multiple stages of an exemplary method for manufacturing a semiconductor element structure of some embodiments of the present disclosure.

[0109] Please refer to Figure 7 , a substrate 102 may be provided. In some embodiments, the substrate 102 is a semiconductor-on-insulator (SOI) substrate. An isolation layer 104 is disposed between a first portion (or a lower portion) and a second portion (or an upper portion) of the substrate 102. The substrate 102 has a surface 102s1 and a surface 102s2 opposite to the surface 102s1.

[0110] Please refer to Figure 8 , an isolation structure 110 may be formed. The isolation structure 110 may be adjacent to the surface 102s2 of the substrate 102. In some embodiments, the isolation structure 110 includes a pad oxide (not shown in the figure), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 102. The pad oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), or other suitable techniques. The isolation structure 110 may further include a dielectric material located above the pad oxide, and the manufacturing technique of the dielectric material may include using flowable chemical vapor deposition (FCVD), spin coating, or similar processes. An annealing technique may be formed after the isolation structure 110 is formed.

[0111] Please refer to Figure 9 ​, a well region 122 and a well region 124 can be formed. The well region 122 can be formed within the second part (or upper part) of the substrate 102. The well region 124 can be formed within the second part (or upper part) of the substrate 102.

[0112] Please refer to Figure 10 , a gate dielectric layer 132 and a gate electrode 134 can be formed above or on the surface 102s2 of the substrate 102. In some embodiments, the fabrication techniques for the gate dielectric layer material and the gate electrode material (not shown in the figures) can include ALD, CVD, FCVD, or other suitable techniques. Additionally, an etching technique can be performed to pattern the gate dielectric layer material and the gate electrode material, thereby forming the gate dielectric layer 132 and the gate electrode 134.

[0113] Please refer to Figure 11 , a spacer 136 can be formed on opposite sides of the gate dielectric layer 132 and the gate electrode 134. The fabrication techniques for the spacer 136 can include ALD, CVD, and / or FCVD as well as etching techniques.

[0114] Please refer to Figure 12 , doped regions 141a, 141b, 142a, and 142b can be formed adjacent to the surface 102s2 of the substrate 102. Pickup regions 143a and 143b can be formed adjacent to the surface 102s2 of the substrate 102. The doped region 141a, the doped region 142a, and the pickup region 143a can be formed within the well region 122. The doped region 141b, the doped region 142b, and the pickup region 143b can be formed within the well region 124.

[0115] Please refer to Figure 13 , a part (e.g., the lower part) of the substrate 102 can be removed. The isolation layer 104 can be exposed. A grinding technique or a polishing technique (e.g., chemical mechanical polishing technique) can be performed to remove the lower part of the substrate 102.

[0116] Please refer to Figure 14 , a pickup region 152 and a pickup region 154 can be formed. The pickup region 152 can be adjacent to the surface 102s1 of the substrate 102. The pickup region 152 can be in contact with or adjacent to the well region 122. The pickup region 154 can be adjacent to the surface 102s1 of the substrate 102. The pickup region 154 can be in contact with or adjacent to the well region 124. In some embodiments, dopants can be implanted into the substrate 102 through the surface 102s1 of the substrate 102, thereby forming the pickup regions 152 and 154.

[0117] Please refer to Figure 15, a plurality of conductive elements 160 may be formed within the isolation layer 104. In some embodiments, an etching technique may be performed to pattern the isolation layer 104, thereby defining a plurality of openings. Then, a conductive material may be formed within the openings to form the conductive elements 160. In some embodiments, the fabrication techniques for the conductive material may include physical vapor deposition (PVD), ALD, CVD, or a combination thereof.

[0118] Please refer to Figure 16 , a plurality of electrical connectors 170 may be formed above or below the conductive elements 160. Thus, a semiconductor element structure (e.g., the semiconductor element structure as Figure 1 shown) may be produced.

[0119] Figure 17 is a process flow diagram illustrating a method 200 for fabricating a semiconductor element structure according to some embodiments of the present disclosure.

[0120] The fabrication method 200 may begin at step 202, where a substrate is provided. The substrate may include a semiconductor-on-insulator substrate, and an isolation layer is formed therein. Figure 7 illustrates the stage corresponding to step 202.

[0121] The fabrication method 200 may proceed to step 204, where a well region is formed within the substrate and a gate electrode is formed above the second surface of the substrate. The well region has a first conductivity type. Figures 8 to 11 illustrates the stage corresponding to step 204.

[0122] The fabrication method 200 may proceed to step 206, where a source / drain feature is formed. The source / drain feature has a second conductivity type that is different from the first conductivity type. The source / drain feature abuts the second surface of the substrate. Additionally, a first pick-up region may be formed. The first pick-up region abuts the second surface of the substrate and has the first conductivity type. Figure 12 illustrates the stage corresponding to step 206.

[0123] The fabrication method 200 may proceed to step 208, where the first surface of the substrate is polished or ground. The isolation layer may be exposed. Figure 13 illustrates the stage corresponding to step 208.

[0124] The fabrication method 200 may proceed to step 210, where a second pick-up region may be formed. The second pick-up region abuts the first surface of the substrate and has the first conductivity type. The second pick-up region vertically overlaps with the source / drain feature. The second pick-up region is configured to direct or neutralize a drift current from an induced depletion region of the source / drain caused by a cosmic ray to the first surface of the substrate.Figure 14 Shows the stage corresponding to step 210.

[0125] The manufacturing method 200 may proceed to step 212, where a plurality of conductive elements and a plurality of electrical connectors are formed. The conductive elements are formed within the isolation layer. The electrical connectors are formed on the conductive elements and electrically connected to the conductive elements. Figure 15 and Figure 16 Shows the stage corresponding to step 212.

[0126] The manufacturing method 200 is only an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional steps may be provided before, during, or after each step of the manufacturing method 200, and some of the described steps may be replaced, eliminated, or reordered for additional embodiments of the manufacturing method. In some embodiments, the manufacturing method 200 may include Figure 17 other steps not shown. In some embodiments, the manufacturing method 200 may include Figure 17 one or more of the steps shown.

[0127] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first well region, a source / drain feature, and a first pickup region. The substrate has a first surface and a second surface opposite to the first surface. The first well region is adjacent to the second surface of the substrate and has a first conductivity type. The source / drain feature is adjacent to the second surface of the substrate and has a second conductivity type, which is different from the first conductivity type. The first pickup region is adjacent to the first surface of the substrate and has the first conductivity type.

[0128] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first well region, a source / drain feature, an isolation structure, and a first pickup region. The substrate has a first surface and a second surface opposite to the first surface. The first well region is adjacent to a second surface of the substrate and has a first conductivity type. The source / drain feature is adjacent to the second surface of the substrate and has a second conductivity type, which is different from the first conductivity type. The isolation structure is embedded within the substrate and extends from the second surface of the substrate towards the first surface. The first pickup region has the first conductivity type and is located between the first surface of the substrate and the isolation structure.

[0129] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device structure. The manufacturing method includes providing a substrate having a first surface and a second surface opposite to the first surface. The manufacturing method also includes forming a first well region adjacent to the second surface of the substrate. The first well region has a first conductivity type. The manufacturing method further includes forming a source / drain feature adjacent to the second surface of the substrate. The source / drain feature has a second conductivity type, which is different from the first conductivity type. In addition, the manufacturing method includes forming a pick-up region adjacent to the first surface of the substrate. The pick-up region has the first conductivity type.

[0130] Embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure includes a pick-up region and a source / drain feature located on two opposite surfaces of a substrate. The pick-up region is configured to provide a low-resistance path to direct a drift current out of the semiconductor device structure through a back surface. The pick-up region can provide a relatively short drift current transmission path and reduce leakage caused by a cosmic ray incident on the semiconductor device structure.

[0131] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0132] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same function or achieve substantially the same result as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor device structure, comprising: A substrate having a first surface and a second surface opposite to the first surface; a first well region, adjacent to the second surface of the substrate and having a first conductivity type; a source / drain feature adjacent the second surface of the substrate and having a second conductivity type different from the first conductivity type; as well as A first pickup region is adjacent to the first surface of the substrate and has the first conductivity type. 2 . The semiconductor device structure as claimed in claim 1 , wherein the first pickup region is exposed through the first surface of the substrate.

3. The semiconductor device structure according to claim 1, further comprising: An electrical connector is disposed on the first surface and electrically connected to the first pickup area.

4. The semiconductor device structure according to claim 3, further comprising: an isolation layer disposed between the electrical connector and the substrate; as well as A conductive element is embedded in the isolation layer and electrically connects the first pickup area and the electrical connector. The semiconductor device structure as claimed in claim 3 , wherein the electrical connector is electrically connected to ground.

6. The semiconductor device structure according to claim 1, further comprising: An isolation structure is embedded in the substrate and adjacent to the second surface, wherein the first pickup region is spaced apart from the isolation structure.

7. The semiconductor device structure according to claim 1, further comprising: An isolation structure is embedded in the substrate and adjacent to the second surface, wherein the first pickup region contacts the isolation structure. 8 . The semiconductor device structure as claimed in claim 1 , wherein the first pickup region has a first portion and a second portion, and the second portion is spaced apart from the first portion. 9 . The semiconductor device structure as claimed in claim 8 , wherein the first well region is further disposed between the first portion and the second portion of the first pickup region. 10 . The semiconductor device structure of claim 8 , wherein the first portion of the first pickup region vertically overlaps the source / drain feature.

11. The semiconductor device structure of claim 1, wherein the first pickup region is configured to contact an induced depletion region between the first well region and the source / drain feature when a cosmic ray is incident on the semiconductor device structure.

12. The semiconductor device structure according to claim 1, further comprising: an isolation structure embedded in the substrate and adjacent to the second surface; as well as A second pickup region is adjacent to the second surface of the substrate and has the second conductivity type, wherein the second pickup region is separated from the source / drain feature by the isolation structure. 13 . The semiconductor device structure as claimed in claim 12 , wherein a doping concentration of the second pickup region is substantially equal to a dopant concentration of the first pickup region.

14. A semiconductor device structure, comprising: A substrate having a first surface and a second surface opposite to the first surface; A first well region adjacent to a second surface of the substrate and having a first conductivity type; a source / drain feature adjacent the second surface of the substrate and having a second conductivity type different from the first conductivity type; an isolation structure embedded in the substrate and extending from the second surface of the substrate toward the first surface; as well as A first pickup region has the first conductivity type and is located between the first surface of the substrate and the isolation structure.

15. The semiconductor device structure according to claim 14, further comprising: An electrical connector is disposed on the first surface and electrically connected to the first pickup area.

16. The semiconductor device structure according to claim 15, further comprising: an isolation layer disposed between the electrical connector and the substrate; as well as A conductive element is embedded in the isolation layer and electrically connects the first pickup area and the electrical connector. 17 . The semiconductor device structure as claimed in claim 15 , wherein the electrical connector is electrically connected to ground. 18 . The semiconductor device structure as claimed in claim 14 , wherein the first pickup region is spaced apart from the isolation structure. 19 . The semiconductor device structure as claimed in claim 14 , wherein the first pickup region has a first portion and a second portion, and the second portion is spaced apart from the first portion. 20 . The semiconductor device structure as claimed in claim 19 , wherein the first well region is further disposed between the first portion and the second portion of the first pickup region.

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