A semiconductor structure and its manufacturing method

Abstract

This disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate and a multi-channel heterojunction layer stacked together. The multi-channel heterojunction layer has heterojunction layers 1, ..., m, ..., n in the direction away from the substrate. Each heterojunction layer includes a channel layer and a barrier layer. An anode and a cathode are located at opposite ends of the multi-channel heterojunction layer. The anode includes at least one set of anode fingers, which comprises n anode fingers of different lengths (1, ..., m, ..., n). The m-th anode finger partially penetrates the multi-channel heterojunction layer to the corresponding m-th heterojunction layer. This disclosure independently controls multiple channels of the semiconductor structure through multiple anode fingers, thereby avoiding electric field concentration at the Schottky interface between the anode metal and the semiconductor when the semiconductor structure is subjected to a large reverse bias voltage, preventing electric field spikes, and improving the breakdown voltage of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and specifically to a semiconductor structure and its manufacturing method. Background Technology

[0002] Junction Barrier Schottky diodes (JBS), as a type of enhancement-mode Schottky diode, have become a research hotspot. The outstanding advantages of JBS diodes are that they possess the on-state and fast switching characteristics of Schottky barrier diodes, as well as the off-state and low leakage current characteristics of PIN diodes.

[0003] Compared to junction barrier Schottky diodes with a single two-dimensional electron gas (2DEG) channel, junction barrier Schottky diodes with multiple 2DEG channels can exhibit higher electron mobility and lower sheet resistance, thereby further reducing series resistance. However, under a large reverse bias, junction barrier Schottky diodes with multiple 2DEG channels will experience electric field concentration at the anode metal-semiconductor Schottky interface, generating electric field spikes that can lead to premature device breakdown. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for manufacturing the same, in order to solve the technical problem of premature device breakdown caused by electric field concentration at the anode metal of a multi-channel junction barrier Schottky diode in the prior art.

[0005] According to one aspect of this disclosure, an embodiment of this disclosure provides a semiconductor structure, characterized in that it includes:

[0006] A substrate and a multi-channel heterojunction layer are stacked together. The multi-channel heterojunction layer is the 1st, ..., mth, ..., nth heterojunction layer in the direction away from the substrate, where 1≤m≤n, n≥2, and m and n are both integers. Each heterojunction layer includes a channel layer and a barrier layer.

[0007] The anode and cathode are located at both ends of the multi-channel heterojunction layer. The anode includes at least one set of anode fingers. The set of anode fingers includes n anode fingers of different lengths, namely the 1st, ..., the mth, ..., the nth anode fingers, where 1 ≤ m ≤ n, n ≥ 2, and m and n are both integers. The mth anode finger extends through the multi-channel heterojunction layer to the corresponding mth layer heterojunction.

[0008] As an optional embodiment, the bottom surface of the m-th anode finger is located in the channel layer of the corresponding m-th heterojunction, at the interface between the channel layer and the barrier layer, or in the barrier layer.

[0009] As an optional embodiment, the width of the m-th anode finger is less than the width of the (m-1)-th anode finger, 2≤m≤n, where m and n are both integers.

[0010] As an optional embodiment, the set of anodes refers to electrical connections.

[0011] As an optional embodiment, a plurality of the first anodes are electrically connected, ..., a plurality of the m-th anodes are electrically connected, ..., a plurality of the n-th anodes are electrically connected.

[0012] As an optional embodiment, the semiconductor structure further includes:

[0013] A plurality of first P-type regions are spaced apart at one end of the multi-channel heterojunction layer. The first P-type regions extend from the surface of the multi-channel heterojunction layer away from the substrate toward the substrate. The bottom surface of at least one of the first P-type regions is located in the channel layer of the first heterojunction.

[0014] As an optional embodiment, at least one of the first P-type regions is included between two adjacent sets of anode fingers.

[0015] As an optional embodiment, at least two adjacent anode fingers in the set of anode fingers include a first P-type region.

[0016] As an optional embodiment, along the direction from the anode to the cathode, the length of each first P-type region increases uniformly or in a stepped manner in the direction away from the substrate.

[0017] As an optional embodiment, along the direction from one anode finger to the other anode finger, the length of each first P-type region increases uniformly or in a stepped manner in the direction away from the substrate.

[0018] As an optional embodiment, the semiconductor structure further includes a second P-type layer located on the multi-channel heterojunction layer and the plurality of first P-type regions, the second P-type layer being connected to the plurality of first P-type regions.

[0019] As an optional embodiment, the length of the second P-type layer is greater than or equal to the length of the first P-type region along the direction from the anode to the cathode.

[0020] According to another aspect of this disclosure, one embodiment of this disclosure provides a method for manufacturing a semiconductor structure, characterized by comprising the following steps:

[0021] S1. A multi-channel heterojunction layer is grown on a substrate. The multi-channel heterojunction layer is the 1st, ..., mth, ..., nth heterojunction layer in the direction away from the substrate, where 1≤m≤n, n≥2, and m and n are both integers. Each heterojunction layer includes a channel layer and a barrier layer.

[0022] S2. Etch both ends of the multi-channel heterojunction layer to form an anode region and a cathode region. The anode region includes at least one set of anode finger grooves. The set of anode finger grooves includes anode finger grooves of different lengths, namely the 1st, ..., the mth, ..., the nth anode finger grooves, where 1 ≤ m ≤ n, n ≥ 2, and m and n are both integers. The mth anode finger groove at least partially penetrates the multi-channel heterojunction layer to the corresponding mth heterojunction layer.

[0023] S3. An anode is provided in the anode region and a cathode is provided in the cathode region. The 1st, ..., mth, ..., nth anode fingers are located in the grooves. The mth anode finger extends through the multi-channel heterojunction layer to the corresponding mth heterojunction layer.

[0024] As an optional embodiment, the bottom surface of the m-th anode finger groove is located in the channel layer of the corresponding m-th heterojunction, at the interface between the channel layer and the barrier layer, or in the barrier layer.

[0025] As an optional embodiment, the width of the m-th anode finger groove is less than the width of the (m-1)-th anode finger groove, 2≤m≤n, where m and n are both integers.

[0026] As an optional embodiment, step S1 is further followed by:

[0027] S11. A plurality of first P-type regions are provided at one end of the multi-channel heterojunction layer, the first P-type regions extending from the surface of the multi-channel heterojunction layer away from the substrate toward the substrate, and the bottom surface of at least one of the first P-type regions is located in the channel layer of the first heterojunction.

[0028] As an optional embodiment, step S11 is further followed by:

[0029] S12. Continue to extend the first P-type region to form a healed second P-type layer.

[0030] This disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate and a multi-channel heterojunction layer stacked together. The multi-channel heterojunction layer has heterojunction layers 1, ..., m, ..., n in the direction away from the substrate. Each heterojunction layer includes a channel layer and a barrier layer. An anode and a cathode are located at opposite ends of the multi-channel heterojunction layer. The anode includes at least one set of anode fingers, which comprises n anode fingers of different lengths (1, ..., m, ..., n). The m-th anode finger partially penetrates the multi-channel heterojunction layer to the corresponding m-th heterojunction layer. This disclosure independently controls multiple channels of the semiconductor structure through multiple anode fingers, thereby avoiding electric field concentration at the Schottky interface between the anode metal and the semiconductor when the semiconductor structure is subjected to a large reverse bias voltage, preventing electric field spikes, and improving the breakdown voltage of the semiconductor structure. The multiple anodes of this design are located on the same side of the multi-channel heterojunction layer. Multiple anodes that can be independently controlled by multiple channels can be formed without etching steps. The space occupied by the anode area can be effectively reduced without sacrificing the channel length, while achieving independent control of multiple channels. Attached Figure Description

[0031] Figure 1 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0032] Figures 2a to 2c The image shown is a side view of a semiconductor structure provided in some embodiments of this disclosure.

[0033] Figure 3 The image shown is a side view of a semiconductor structure provided in some embodiments of this disclosure.

[0034] Figures 4a to 4b The image shown is a side view of a semiconductor structure provided in some embodiments of this disclosure.

[0035] Figure 5 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0036] Figures 6a to 6b The image shown is a side view of a semiconductor structure provided in some embodiments of this disclosure.

[0037] Figures 7a to 7b The image shown is a cross-sectional view of the first P-type region of a semiconductor structure provided in an embodiment of this disclosure.

[0038] Figures 8a to 8b The image shown is a side view of a semiconductor structure provided in an embodiment of this disclosure.

[0039] Figure 9 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0040] Figure 10The diagram shown is a flowchart of a semiconductor structure manufacturing method according to an embodiment of this disclosure.

[0041] Figures 11 to 18 The diagram shown is a schematic diagram of the intermediate structure of a semiconductor structure provided in an embodiment of this disclosure during the manufacturing process. Detailed Implementation

[0042] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0043] To address the technical problem of premature breakdown caused by electric field concentration at the anode metal of multi-channel barrier Schottky diodes in the prior art, this disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate and a multi-channel heterojunction layer stacked together. The multi-channel heterojunction layer has heterojunction layers 1, ..., m, ..., n on the direction away from the substrate. Each heterojunction layer includes a channel layer and a barrier layer. An anode and a cathode are located at opposite ends of the multi-channel heterojunction layer. The anode includes at least one set of anode fingers, which comprises n anode fingers of different lengths (1, ..., m, ..., n). The m-th anode finger partially penetrates the multi-channel heterojunction layer into the corresponding m-th heterojunction layer. This disclosure independently controls multiple channels of the semiconductor structure through multiple anode fingers, thereby avoiding electric field concentration at the Schottky interface between the anode metal and the semiconductor when the semiconductor structure is subjected to a large reverse bias voltage, preventing electric field spikes, and improving the breakdown voltage of the semiconductor structure. The multiple anodes of this design are located on the same side of the multi-channel heterojunction layer. Multiple anodes that can be independently controlled by multiple channels can be formed without etching steps. The space occupied by the anode area can be effectively reduced without sacrificing the channel length, while achieving independent control of multiple channels.

[0044] The following is combined with Figures 1 to 18 A further example illustrates a semiconductor structure and its manufacturing method mentioned in this disclosure.

[0045] Figure 1 The diagram shown is a schematic representation of a semiconductor structure provided in an embodiment of this disclosure. Figure 1As shown, the semiconductor structure includes a substrate 10 and a multi-channel heterojunction layer 20 stacked together. The multi-channel heterojunction layer 20 has heterojunction layers 1, ..., m, ..., n in the direction away from the substrate 10, where 1 ≤ m ≤ n, n ≥ 2, and m and n are both integers. Each heterojunction layer includes a channel layer 21 and a barrier layer 22. An anode 41 and a cathode 42 are located at both ends of the multi-channel heterojunction layer 20. The anode 41 includes at least one set of anode fingers. Each set of anode fingers includes n anode fingers of different lengths of the 1st, ..., mth, ..., nth anode fingers, where 1 ≤ m ≤ n, n ≥ 2, and m and n are both integers. The mth anode finger extends through the multi-channel heterojunction layer 20 to the corresponding mth heterojunction layer.

[0046] In this embodiment, the multi-channel heterojunction layer 20 may include only two heterojunction layers, namely, a first heterojunction layer and a second heterojunction layer stacked away from the substrate 10. In other embodiments, the multi-channel heterojunction layer 20 may include three or more heterojunction layers, namely, a first heterojunction layer, a second heterojunction layer, ..., an nth heterojunction layer stacked away from the substrate 10, where n ≥ 3. Each heterojunction layer includes a channel layer 21 and a barrier layer 22. The bandgap of the material of the barrier layer 22 is greater than the bandgap of the material of the channel layer 21. The materials of the channel layer 21 and the barrier layer 22 may include group III nitride materials, and a two-dimensional electron gas may be formed at the interface between the channel layer 21 and the barrier layer 22. In one optional embodiment, the channel layer 21 is a GaN layer, and the barrier layer 22 is an AlGaN layer. In other alternatives, the material combination of the channel layer 21 and the barrier layer 22 can also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. The materials of the multilayer heterojunction layers can be the same or different, and this disclosure does not impose specific limitations.

[0047] Figures 2a to 2c The image shown is a side view of a semiconductor structure provided in some embodiments of this disclosure. In this embodiment, the m-th anode finger extends through the multi-channel heterojunction layer 20 into the corresponding m-th heterojunction layer, and the bottom surface of the m-th anode finger is located in the channel layer 21 of the corresponding m-th heterojunction layer (e.g., ...). Figure 2a As shown), the interface between the channel layer 21 and the barrier layer 22 (as shown) Figure 2b (as shown) or in barrier layer 22 (such as Figure 2c (As shown). By designing the anode fingers to be located at different depths in the multi-channel heterojunction layer 20, the control capability of the anode fingers over the corresponding channels can be adjusted.

[0048] Figure 3 The image shown is a side view of a semiconductor structure provided in some embodiments of this disclosure. In one embodiment, such as... Figure 3As shown, the width of the m-th anode finger is less than the width of the (m-1)-th anode finger, 2≤m≤n, where m and n are both integers. This means that the width of the anode finger corresponding to the heterojunction further away from the substrate 10 is smaller. The larger the anode finger width, the greater the control capability. Under the same anode finger width, the anode control capability of the heterojunction further away from the substrate 10 is greater. Therefore, the width of the anode finger corresponding to the heterojunction further away from the substrate 10 can be reduced, thus reducing the use of anode material.

[0049] Figures 4a to 4b The image shown is a side view of a semiconductor structure provided in some embodiments of this disclosure. In this embodiment, all anode fingers can be electrically connected, such as... Figure 1 As shown; in one embodiment, one group of anodes are electrically connected, and different groups of anodes are not electrically connected, such as... Figure 4a As shown; in another embodiment, multiple first anodes are electrically connected, ..., multiple m-th anodes are electrically connected, ..., multiple n-th anodes are electrically connected. Different electrical connection methods for the anodes allow for joint or independent control of different channels of the semiconductor structure.

[0050] Figure 5 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure. Figures 6a to 6b The image shown is a side view of a semiconductor structure provided in some embodiments of this disclosure. In one embodiment, such as... Figure 5 As shown, the semiconductor structure further includes: a plurality of spaced first P-type regions 31 located at one end of the multi-channel heterojunction layer 20, the first P-type regions 31 extending from the surface of the multi-channel heterojunction layer 20 away from the substrate 10 toward the substrate 10, and the bottom surface of at least one first P-type region 31 located in the channel layer 21 of the first heterojunction. Figure 6a As shown, at least one first P-type region 31 is included between two adjacent sets of anode fingers; as Figure 6b As shown, at least two adjacent anode fingers in a set of anode fingers include a first P-type region 31. A lateral PN junction is formed between the first P-type region 31 and the two-dimensional electron gas in the heterojunction. Under reverse bias, the depletion region of the PN junction widens, effectively pinching off the current path and shielding the low-barrier-height Schottky junction. This suppresses the Schottky barrier reduction effect and controls the reverse leakage current, thereby increasing the breakdown voltage and maintaining a low turn-on voltage. Simultaneously, the stacking of multiple heterojunctions forms multiple parallel two-dimensional electron gas paths between the anode 41 and the cathode 42, compensating for the depletion of the two-dimensional electron gas by the first P-type region 31 and ensuring the forward current of the diode.

[0051] Figures 7a to 7b The image shown is a cross-sectional view of the first P-type region of a semiconductor structure provided in an embodiment of this disclosure. Figures 8a to 8bThe image shown is a side view of a semiconductor structure provided in an embodiment of this disclosure. In one embodiment, the contact interface between the channel layer 21 and the barrier layer 22 in each heterojunction has a two-dimensional electron gas, and the lengths of the first P-type regions 31 at different two-dimensional electron gases are different along the direction from the anode 41 to the cathode 42 and / or along the direction from one anode finger to another. Specifically, along the direction from the anode 41 to the cathode 42, the length of each first P-type region 31 increases uniformly in the direction away from the substrate 10 (e.g., ...). Figure 7a (as shown) or step-like increase (such as) Figure 7b As shown), and / or, along the direction from one anode finger to another, the length of each first P-type region 31 increases uniformly in the direction away from the substrate 10 (e.g. Figure 8a (as shown) or step-like increase (such as) Figure 8b (As shown). By changing the length of the first P-type region 31, the channel shape can be changed, increasing the electron movement path and thus reducing the on-state resistance. On the other hand, the depletion layer width can be changed, reducing the peak electric field and thus increasing the breakdown voltage.

[0052] Figure 9 The diagram shown is a schematic representation of a semiconductor structure provided in an embodiment of this disclosure. In one embodiment, as... Figure 9 As shown, the P-type epitaxial layer 30 also includes a second P-type layer 32 located on the multi-channel heterojunction layer 20 and multiple first P-type regions 31, and the second P-type layer 32 is connected to the multiple first P-type regions 31. Along the direction from the anode 41 to the cathode 42, the length of the second P-type layer 32 is greater than or equal to the length of the first P-type regions 31. The first P-type regions 31 and the second P-type layer 32 can work together to redistribute the surface electric field of the heterojunction structure between the anode 41 and the cathode 42, improving the electric field distribution at the edge of the anode 41, preventing avalanche breakdown, further increasing the device breakdown voltage, and reducing reverse leakage current.

[0053] According to another aspect of this disclosure, Figure 10 The diagram shown is a flowchart of a semiconductor structure manufacturing method according to an embodiment of this disclosure. Figures 11 to 18 The diagram shown is a schematic representation of an intermediate structure during the manufacturing process of a semiconductor structure according to an embodiment of this disclosure. Figure 10 As shown, a semiconductor structure manufacturing method provided in one embodiment of this disclosure includes the following steps:

[0054] Step S1: Grow a multi-channel heterojunction layer on the substrate. The multi-channel heterojunction layer is the 1st, ..., mth, ..., nth heterojunction layer in the direction away from the substrate, where 1≤m≤n, n≥2, and m and n are both integers. Each heterojunction layer includes a channel layer and a barrier layer.

[0055] Specifically, such as Figure 11As shown, a multi-channel heterojunction layer 20 is grown on the substrate 10. The multi-channel heterojunction layer 20 is the 1st, ..., mth, ..., nth heterojunction layer in the direction away from the substrate 10, where 1 ≤ m ≤ n, n ≥ 2, and m and n are both integers. Each heterojunction layer includes a channel layer 21 and a barrier layer 22. The material of the substrate 10 includes any one or more combinations of Si, Al2O3, GaN, SiC, or AlN. The method for growing the multi-channel heterojunction layer 20 on the substrate 10 can be in-situ growth, or it can be prepared by atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or a combination thereof.

[0056] Step S11: A plurality of first P-type regions are provided at one end of the multi-channel heterojunction layer. The first P-type regions extend from the surface of the multi-channel heterojunction layer away from the substrate toward the substrate, and the bottom surface of at least one first P-type region is located in the channel layer of the first heterojunction.

[0057] Specifically, such as Figure 12 As shown, a plurality of spaced first P-type regions 31 are disposed at one end of the multi-channel heterojunction layer 20. The first P-type regions 31 extend from the surface of the multi-channel heterojunction layer 20 away from the substrate 10 toward the substrate 10, and the bottom surface of at least one first P-type region 31 is located in the channel layer 21 of the first heterojunction. A lateral PN junction is formed by the first P-type regions 31 and the two-dimensional electron gas in the heterojunction. When reverse biased, the depletion region of the PN junction widens, thereby pinching off the current path and effectively shielding the low barrier height Schottky junction. This can suppress the Schottky barrier reduction effect and control the reverse leakage current, thereby improving the breakdown voltage and maintaining a low turn-on voltage.

[0058] Step S12: Continue to extend the first P-type region to form a healed second P-type layer.

[0059] Specifically, such as Figure 13As shown, a healed second P-type layer 32 is formed by epitaxy on the first P-type region 31. The first P-type region 31 and the second P-type layer 32 can work together to redistribute the surface electric field of the heterojunction structure between the anode 41 and the cathode 42, which can improve the electric field distribution at the edge of the anode 41, prevent avalanche breakdown, further improve the device breakdown voltage and reduce the reverse leakage current.

[0060] Step S2: Etch the two ends of the multi-channel heterojunction layer 20 to form an anode region and a cathode region. The anode region includes at least one set of anode finger grooves. The set of anode finger grooves includes anode finger grooves of different lengths, namely the 1st, ..., the mth, ..., the nth anode finger groove, where 1≤m≤n, n≥2, and m and n are both integers. The mth anode finger groove at least partially penetrates the multi-channel heterojunction layer to the corresponding mth layer heterojunction.

[0061] Specifically, such as Figure 14 As shown, the two ends of the etched multi-channel heterojunction layer 20 form an anode region and a cathode region. The anode region includes at least one set of anode finger grooves 401. The set of anode finger grooves 401 includes anode finger grooves 401 of different lengths, namely the 1st, ..., the mth, ..., the nth anode finger grooves 401, where 1≤m≤n, n≥2, and m and n are both integers. The mth anode finger groove 401 at least partially penetrates the multi-channel heterojunction layer 20 to the corresponding mth heterojunction layer.

[0062] In one embodiment, the bottom surface of the m-th anode recess 401 is located in the channel layer 21 of the corresponding m-th heterojunction (e.g., Figure 15 As shown), the interface between the channel layer 21 and the barrier layer 22 (as shown) Figure 16 (as shown) or in barrier layer 22 (such as Figure 17 (As shown). By designing the anode fingers to be located at different depths in the multi-channel heterojunction layer 20, the control capability of the anode fingers over the corresponding channels can be adjusted.

[0063] In one embodiment, such as Figure 18 As shown, the width of the m-th anode finger groove 401 is less than the width of the (m-1)-th anode finger groove 401, 2≤m≤n, where m and n are both integers.

[0064] Step S3: Set an anode in the anode region and a cathode in the cathode region. The 1st, ..., mth, ..., nth anodes are located in the grooves. The mth anode partially penetrates the multi-channel heterojunction layer to the corresponding mth heterojunction layer.

[0065] Specifically, an anode 41 is provided in the anode region, and a cathode 42 is provided in the cathode region. The 1st, ..., mth, ..., nth anode fingers are located in the groove 401. The mth anode finger penetrates the multi-channel heterojunction layer 20 to the corresponding mth heterojunction layer, forming a structure as shown in the figure. Figure 9The semiconductor structure shown.

[0066] This disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate and a multi-channel heterojunction layer stacked together. The multi-channel heterojunction layer has heterojunction layers 1, ..., m, ..., n in the direction away from the substrate. Each heterojunction layer includes a channel layer and a barrier layer. An anode and a cathode are located at opposite ends of the multi-channel heterojunction layer. The anode includes at least one set of anode fingers, which comprises n anode fingers of different lengths (1, ..., m, ..., n). The m-th anode finger partially penetrates the multi-channel heterojunction layer to the corresponding m-th heterojunction layer. This disclosure independently controls multiple channels of the semiconductor structure through multiple anode fingers, thereby avoiding electric field concentration at the Schottky interface between the anode metal and the semiconductor when the semiconductor structure is subjected to a large reverse bias voltage, preventing electric field spikes, and improving the breakdown voltage of the semiconductor structure. The multiple anodes of this design are located on the same side of the multi-channel heterojunction layer. Multiple anodes that can be independently controlled by multiple channels can be formed without etching steps. The space occupied by the anode area can be effectively reduced without sacrificing the channel length, while achieving independent control of multiple channels.

[0067] It should be understood that the term "comprising" and its variations as used in this disclosure are open-ended, meaning "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0068] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications or equivalent substitutions made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate (10) and a multi-channel heterojunction layer (20) are stacked together. The multi-channel heterojunction layer (20) is the first, ..., the m, ..., the nth heterojunction layer in the direction away from the substrate (10), where 1 ≤ m ≤ n, n ≥ 2, and m and n are both integers. Each heterojunction layer includes a channel layer (21) and a barrier layer (22). Anode (41) and cathode (42) are located at both ends of the multi-channel heterojunction layer (20). The anode (41) includes at least one set of anode fingers. The set of anode fingers includes n anode fingers of different lengths, namely the 1st, ..., the mth, ..., the nth anode fingers, where 1 ≤ m ≤ n, n ≥ 2, and m and n are both integers. The mth anode finger extends through the multi-channel heterojunction layer (20) to the corresponding mth layer heterojunction. A plurality of first P-type regions (31) are spaced apart at one end of the multi-channel heterojunction layer (20). The first P-type regions (31) extend from the surface of the multi-channel heterojunction layer (20) away from the substrate (10) toward the substrate (10). The bottom surface of at least one of the first P-type regions (31) is located in the channel layer (21) of the first heterojunction. The first P-type regions (31) satisfy one of the following relationships: Along the direction from the anode (41) to the cathode (42), the length of each of the first P-type regions (31) increases uniformly or in a stepped manner in the direction away from the substrate (10); or Along the direction from one anode finger to the other anode finger, the length of each first P-type region (31) increases uniformly or in a stepped manner in the direction away from the substrate (10).

2. The semiconductor structure according to claim 1, characterized in that, The bottom surface of the m-th anode finger is located in the channel layer (21) of the corresponding m-th heterojunction, at the interface between the channel layer (21) and the barrier layer (22), or in the barrier layer (22).

3. The semiconductor structure according to claim 1, characterized in that, The width of the m-th anode finger is less than the width of the (m-1)-th anode finger, 2≤m≤n, and m and n are both integers.

4. The semiconductor structure according to claim 1, characterized in that, The set of anodes refers to electrical connections.

5. The semiconductor structure according to claim 1, characterized in that, Multiple first anodes are electrically connected, ..., multiple m-th anodes are electrically connected, ..., multiple n-th anodes are electrically connected.

6. The semiconductor structure according to claim 1, characterized in that, At least one first P-type region (31) is included between two adjacent sets of anode fingers.

7. The semiconductor structure according to claim 1, characterized in that, At least two adjacent anode fingers in the set of anode fingers include a first P-type region (31).

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a second P-type layer (32) located on the multi-channel heterojunction layer (20) and the plurality of first P-type regions (31), the second P-type layer (32) being connected to the plurality of first P-type regions (31).

9. The semiconductor structure according to claim 8, characterized in that, Along the direction from the anode (41) to the cathode (42), the length of the second P-type layer (32) is greater than or equal to the length of the first P-type region (31).

10. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: S1. A multi-channel heterojunction layer (20) is grown on a substrate (10). The multi-channel heterojunction layer (20) is the first, ..., the m, ..., the nth heterojunction layer in the direction away from the substrate (10), where 1≤m≤n, n≥2, and m and n are both integers. Each heterojunction layer includes a channel layer (21) and a barrier layer (22). S2. Etch the two ends of the multi-channel heterojunction layer (20) to form an anode region and a cathode region. The anode region includes at least one set of anode finger grooves (401). The set of anode finger grooves (401) includes anode finger grooves (401) of different lengths of the 1st, ..., mth, ..., nth, 1≤m≤n, n≥2, and m and n are both integers. The mth anode finger groove (401) at least partially penetrates the multi-channel heterojunction layer (20) to the corresponding mth heterojunction layer. S3. An anode (41) is provided in the anode region and a cathode (42) is provided in the cathode region. The first, ..., the m, ..., the nth anode finger groove (401) contains the first, ..., the m, ..., the nth anode finger. The mth anode finger partially penetrates the multi-channel heterojunction layer (20) to the corresponding mth layer heterojunction. Step S1 is further followed by: S11, a plurality of spaced first P-type regions (31) are provided at one end of the multi-channel heterojunction layer (20), the first P-type regions (31) extend from the surface of the multi-channel heterojunction layer (20) away from the substrate (10) toward the substrate (10), at least one bottom surface of the first P-type region (31) is located in the channel layer (21) of the first heterojunction, and the first P-type region (31) satisfies one of the following relationships: Along the direction from the anode (41) to the cathode (42), the length of each of the first P-type regions (31) increases uniformly or in a stepped manner in the direction away from the substrate (10); or Along the direction from one anode finger to the other anode finger, the length of each first P-type region (31) increases uniformly or in a stepped manner in the direction away from the substrate (10).

11. The method for manufacturing the semiconductor structure according to claim 10, characterized in that, The bottom surface of the m-th anode finger groove (401) is located in the channel layer (21) of the corresponding m-th heterojunction, at the interface between the channel layer (21) and the barrier layer (22), or in the barrier layer (22).

12. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The width of the m-th anode finger groove (401) is less than the width of the (m-1)-th anode finger groove (401), 2≤m≤n, where m and n are both integers.

13. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, Step S11 is followed by: S12. Continue to extend the first P-type region (31) to form a healed second P-type layer (32).

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