Semiconductor structure and method of fabricating the same

Abstract

The embodiment of the present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a channel layer, a barrier layer, a first passivation layer and a second passivation layer which are sequentially stacked, a through hole is arranged through the first passivation layer and the second passivation layer, a cross-sectional area of the through hole located in the first passivation layer is greater than that of the through hole located in the second passivation layer, and a semiconductor layer fills the through hole. The semiconductor layer comprises a P-type activation region and a first high-resistance region. The P-type activation region penetrates the first passivation layer and the second passivation layer, and is used for depleting 2DEG of the underlying channel to realize an enhancement mode device. The first high-resistance region is located between the P-type activation region and the first passivation layer and is covered by the projection of the second passivation layer on the substrate. The first high-resistance region is located at an included angle formed by the P-type activation region and the barrier layer, and is used for reducing the leakage current near the P-type activation region and improving the reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] Compared with the first and second generation semiconductor materials, the third generation semiconductor material, especially GaN (gallium nitride) based material, has the advantages of large band gap, high breakdown field strength, large electron mobility, strong radiation resistance, etc. The GaN based HEMT (high electron mobility transistor) device has great development potential in high-frequency and high-power fields such as wireless communication base stations, radars and automotive electronics.

[0003] Generally, the GaN based HEMT device is a depletion mode field effect transistor. In radio frequency microwave applications, a negative turn-on voltage is required, which makes the circuit structure complex and the anti-misoperation protection function of the circuit is affected, thereby reducing the safety of the circuit. Therefore, it is necessary to develop an enhancement mode GaN based HEMT device.

[0004] Common methods for realizing an enhancement mode device include slot gate technology, fluorine ion implantation technology and P-type gate technology. The P-type gate technology is to add a layer of P-type GaN based epitaxial layer between the gate metal and the barrier layer, which reduces the barrier height of the barrier layer. Due to the difference in conduction band between the P-type GaN based epitaxial layer and the barrier layer, the conduction band of the entire heterojunction is lifted above the Fermi level, thereby depleting the 2DEG (two dimensional electron gas) at the channel under the gate to realize the enhancement mode. However, in the process of device manufacturing, the P-type GaN based epitaxial layer between the gate source and the gate drain needs to be etched away, which is difficult to control the etching precision and introduces etching damage, thereby finally causing the reduction of output current density, the increase of gate leakage current and the reduction of device stability. SUMMARY

[0005] Therefore, the embodiments of the present application provide a semiconductor structure and a manufacturing method thereof to solve the technical problem of gate leakage current of a power device in the prior art.

[0006] According to an aspect of the present application, one embodiment of the present application provides a semiconductor structure, the semiconductor structure comprising: a substrate, a channel layer, a barrier layer, a first passivation layer and a second passivation layer which are sequentially stacked; a via hole, the via hole penetrating through the first passivation layer and the second passivation layer, a cross-sectional area of the via hole located at the first passivation layer being larger than a cross-sectional area of the via hole located at the second passivation layer; a semiconductor layer, the semiconductor layer being located in the via hole; wherein the semiconductor layer comprises a P-type active region and a first high-resistance region, the P-type active region penetrating through the first passivation layer and the second passivation layer, the first high-resistance region being located between the P-type active region and the first passivation layer, a projection of the second passivation layer on the substrate covering a projection of the first high-resistance region on the substrate.

[0007] According to another aspect of the present application, one embodiment of the present application provides a method for manufacturing a semiconductor structure. The method comprises: sequentially epitaxially manufacturing a channel layer and a barrier layer on a substrate; manufacturing a first passivation layer and a second passivation layer with a via hole on the barrier layer, the via hole penetrating through the first passivation layer and the second passivation layer, a cross-sectional area of the via hole located at the first passivation layer being larger than a cross-sectional area of the via hole located at the second passivation layer; epitaxially manufacturing a semiconductor material layer in the via hole; and performing annealing treatment, the semiconductor material layer being converted into a semiconductor layer, wherein the semiconductor layer comprises a P-type active region and a first high-resistance region, the P-type active region penetrating through the first passivation layer and the second passivation layer, the first high-resistance region being located between the P-type active region and the first passivation layer, a projection of the second passivation layer on the substrate covering a projection of the first high-resistance region on the substrate.

[0008] The semiconductor structure and the manufacturing method thereof provided by the embodiments of the present application comprise: a substrate, a channel layer, a barrier layer, a first passivation layer and a second passivation layer which are sequentially stacked, a via hole penetrating through the first passivation layer and the second passivation layer, a cross-sectional area of the via hole located at the first passivation layer being larger than a cross-sectional area of the via hole located at the second passivation layer, and a semiconductor layer filling the via hole, wherein the semiconductor layer comprises a P-type active region and a first high-resistance region, the P-type active region penetrating through the first passivation layer and the second passivation layer, the P-type active region being used for depleting 2DEG of the underlying channel to realize an enhancement-mode device, the first high-resistance region being located between the P-type active region and the first passivation layer and being covered by a projection of the second passivation layer on the substrate, the first high-resistance region being located at an included angle formed by the P-type active region and the barrier layer, and being used for reducing leakage current near the P-type active region and improving reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 Fig. 1 shows a structure schematic diagram of a semiconductor structure provided by one embodiment of the present application;

[0010] Figure 2 Fig. 2 shows a structure schematic diagram of an intermediate structure provided by one embodiment of the present application;

[0011] Figure 3Fig. 2 shows a structural schematic diagram of another semiconductor structure according to an embodiment of the present application;

[0012] Figure 4 Fig. 3 shows a structural schematic diagram of another semiconductor structure according to an embodiment of the present application;

[0013] Figure 5 Fig. 4 shows a structural schematic diagram of another semiconductor structure according to an embodiment of the present application;

[0014] Figure 6 Fig. 5 shows a structural schematic diagram of another semiconductor structure according to an embodiment of the present application;

[0015] Figure 7 Fig. 6 shows a structural schematic diagram of another semiconductor structure according to an embodiment of the present application;

[0016] Figures 8 to 17 Fig. 7 shows an intermediate structure diagram for manufacturing a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0018] To solve the above problems, the present application provides a semiconductor structure, which comprises: a substrate, a channel layer, a barrier layer, a first passivation layer and a second passivation layer which are sequentially stacked; a via hole, the via hole penetrates the first passivation layer and the second passivation layer, the cross-sectional area of the via hole located in the first passivation layer is larger than the cross-sectional area of the via hole located in the second passivation layer; a semiconductor layer, the semiconductor layer is located in the via hole; wherein the semiconductor layer comprises a P-type active region and a first high resistance region, the P-type active region penetrates the first passivation layer and the second passivation layer, the first high resistance region is located between the P-type active region and the first passivation layer, and a projection of the second passivation layer on the substrate covers a projection of the first high resistance region on the substrate.

[0019] The semiconductor structure and the manufacturing method thereof mentioned in the present application will be further illustrated below. Figures 1 to 17 The semiconductor structure and the manufacturing method thereof mentioned in the present application will be further illustrated below.

[0020] Figure 1 Fig. 1 shows a structural schematic diagram of a semiconductor structure according to an embodiment of the present application, Figure 2 Fig. 7 shows an intermediate structure diagram for manufacturing a semiconductor structure according to an embodiment of the present application. Figure 1 and Figure 2As shown, the semiconductor structure comprises: a substrate 10, a channel layer 20, a barrier layer 30, a first passivation layer 401 and a second passivation layer 402 which are sequentially stacked; a via 50, the via 50 penetrates the first passivation layer 401 and the second passivation layer 402, the cross-sectional area of the via 50 located in the first passivation layer 401 is greater than the cross-sectional area of the via 50 located in the second passivation layer 402; a semiconductor layer 60, the semiconductor layer 60 is located in the via 50; wherein the semiconductor layer 60 comprises a P-type active region 601 and a first high resistance region 602, the P-type active region 601 penetrates the first passivation layer 401 and the second passivation layer 402, the first high resistance region 602 is located between the P-type active region 601 and the first passivation layer 401, and the projection of the second passivation layer 402 on the substrate 10 covers the projection of the first high resistance region 602 on the substrate 10.

[0021] Specifically, as shown in Figure 1 and Figure 2 the via 50 penetrates the first passivation layer 401 and the second passivation layer 402, and in the longitudinal cross-section, the width a1 of the via 50 at the first passivation layer 401 is greater than the width a2 of the via 50 at the second passivation layer 402. Accordingly, the semiconductor layer 60 is located in the via 50, and the width a1 of the semiconductor layer 60 at the first passivation layer 401 is greater than the width a2 of the semiconductor layer 60 at the second passivation layer 402; and the via 50 located in the first passivation layer 401 comprises the first high resistance region 602 and part of the P-type active region 601, and the via 50 located in the second passivation layer 402 only comprises the remaining part of the P-type active region 601.

[0022] Specifically, as shown in Figure 1 the semiconductor layer 60 comprises the P-type active region 601 and the first high resistance region 602, the first high resistance region 602 is located in the region covered by the second passivation layer 402, so that the projection of the second passivation layer 402 on the substrate 10 covers the projection of the first high resistance region 602 on the substrate 10; the region of the semiconductor layer 60 not covered by the second passivation layer 402 is the P-type active region 601, so that the P-type active region 601 penetrates the first passivation layer 401 and the second passivation layer 402. In other words, the cross-sectional area of the via 50 located in the second passivation layer 402 is equal to the projected area of the P-type active region 601 on the substrate 10; the cross-sectional area of the via 50 located in the first passivation layer 401 minus the cross-sectional area of the via 50 located in the second passivation layer 402 is equal to the projected area of the first high resistance region 602 on the substrate 10.

[0023] Specifically, the channel layer 20 and the barrier layer 30 form a heterojunction, and a channel of 2DEG is formed at a surface of the channel layer 20 close to the barrier layer 30, when the semiconductor device is in an off state, the P-type activation region 601 can deplete the 2DEG at the channel, so as to realize an enhancement-mode device; the first high-resistance region 602 is located between the P-type activation region 601 and the first passivation layer 401, and is covered by the projection of the second passivation layer 402 on the substrate 10, the first high-resistance region 602 is located at an included angle formed by the P-type activation region 601 and the barrier layer 30, and the first high-resistance region can share the leakage current or the electric field intensity near the P-type activation region, so as to reduce the leakage current near the P-type activation region and improve the reliability of the device.

[0024] Optionally, the semiconductor structure adopts GaN-based semiconductor materials, for example, the material of the channel layer 20 is GaN, and the material of the barrier layer 30 is AlGaN. Optionally, the material of the substrate 10 is selected from any one of single crystal silicon, single crystal germanium, sapphire, diamond, SiC and GaN.

[0025] Optionally, as shown in Figure 1 the second passivation layer 402 is flush with the side wall of the first high-resistance region 602 close to the P-type activation region 601. It can be understood that, when the P-type activation region 601 is activated, due to the blocking of the second passivation layer 402 to H atoms, the first high-resistance region 602 and the second passivation layer 402 have a common side wall.

[0026] In one embodiment, the hydrogen concentration of the first high-resistance region 602 is greater than the hydrogen concentration of the P-type activation region 601, so that the resistivity of the first high-resistance region 602 is greater than the resistivity of the P-type activation region 601, and the first high-resistance region 602 is used to reduce the leakage current near the P-type activation region 601. Specifically, the P-type activation region 601 and the first high-resistance region 602 are formed at the same time in an annealing process, the Mg-H bonds in the P-type activation region 601 are broken, H atoms escape, and Mg is released, and the P-type activation region 601 presents a P-type conductivity type, while due to the blocking of the second passivation layer 402, H atoms cannot escape, the Mg-H bonds in the first high-resistance region 602 remain in a bonding state, and compared with the P-type activation region 601, the first high-resistance region 602 presents a high-resistance state.

[0027] It should be noted that the hydrogen concentration refers to the number of H atoms per unit volume.

[0028] In one embodiment, Figure 3 as shown in FIG. 6, another semiconductor structure provided by an embodiment of the present application is shown, and the semiconductor structure is similar to the semiconductor structure shown in FIG. 1, and the difference is that the semiconductor structure shown in FIG. 6 further comprises a second high-resistance region 603. Figure 3As shown, the semiconductor structure also includes: a gate 701 located on the side of the P-type active region 601 away from the substrate 10, and a source 702 and a drain 703 located on the side of the channel layer 20 away from the substrate 10, with the source 702 and drain 703 located on both sides of the gate 701. Specifically, as... Figure 3 As shown, source 702 and drain 703 are located above barrier layer 30, and source 702 and drain 703 form ohmic contacts with barrier layer 30 respectively; optionally, source 702 and drain 703 penetrate barrier layer 30 and form ohmic contacts with channel layer 20 (not shown).

[0029] In one embodiment, Figure 4 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 4 As shown, the first high-resistivity region 602 is located on the side of the P-type active region 601 near the drain 703. Specifically, the electric field strength on the side of the gate 701 near the drain 703 is relatively large. The first high-resistivity region 602 can reduce the electric field strength and improve the withstand voltage of the semiconductor structure; and in the off state, the first high-resistivity region 602 can reduce the leakage current.

[0030] In one embodiment, such as Figure 1 and Figure 3 As shown, the second passivation layer 402 is a single-layer structure, which includes either a SiN layer or an AlN layer. The material of the second passivation layer 402 is SiN or AlN; or, Figure 5 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 5 As shown, the second passivation layer 402 has a multilayer structure, which includes a SiN layer 4021 and an AlN layer 4022 stacked together. Specifically, whether the second passivation layer 402 is a single-layer structure or a multilayer structure, the cross-sectional area of ​​the vias in the second passivation layer 402 is small. During the annealing process of the semiconductor layer 60, the semiconductor layer 60 not covered by the second passivation layer 402 is activated to form a P-type activation region 601, while the semiconductor layer 60 covered by the second passivation layer 402 is not activated and remains in a high-resistance state, which is the first high-resistance region 602.

[0031] It should be noted that when the second passivation layer 402 is a multilayer structure, especially a two-layer structure, the SiN layer 4021 can be located between the AlN layer 4022 and the first passivation layer 401, or the AlN layer 4022 can be located between the SiN layer 4021 and the first passivation layer 401; optionally, the thickness of the SiN layer 4021 and the AlN layer 4022 is not limited. Optionally, when the second passivation layer 402 is a multilayer structure with more than 2 layers, the film layer closest to the first passivation layer 401 in the second passivation layer 402 can be either the SiN layer 4021 or the AlN layer 4022.

[0032] In one embodiment, the material of the first passivation layer 401 includes SiO2. Specifically, the material of the first passivation layer 401 is SiO2, the material of the second passivation layer 402 is SiN and / or AlN, the material of the first passivation layer 401 is different from the material of the second passivation layer 402, and the via hole 50 can be formed by dry etching followed by wet etching. Alternatively, the material of the first passivation layer 401 and the material of the second passivation layer 402 are both SiN, and the via hole 50 can be formed by removing the sacrificial layer.

[0033] In one embodiment, Figure 6 Fig. 6 shows a structure diagram of a semiconductor structure according to another embodiment of the present application. Figure 6 As shown, when the second passivation layer 402 includes a SiN layer, the hydrogen content of the SiN layer is 5% to 20%, and the semiconductor layer 60 further includes a second high resistance region 603 in contact with the SiN layer. Specifically, when the hydrogen content of the SiN layer is 5% to 20%, the H in the SiN layer will diffuse reversely into the P-type active region 601 during the annealing process, so that the free Mg in the P-type active region 601 near the surface of the second passivation layer 402 bonds with the H, and a second high resistance region 603 in high resistance state is finally formed between the P-type active region 601 and the second passivation layer 402. The second high resistance region 603 can reduce the leakage current near the P-type active region 601, and thus improve the reliability of the device.

[0034] It should be noted that the hydrogen content of the SiN is 5% to 20%, which means that the percentage of H atoms is between 5% and 20%.

[0035] Alternatively, the hydrogen concentration of the second high resistance region 603 is greater than the hydrogen concentration of the P-type active region 601. Alternatively, the second high resistance region 603 also retains part of the Mg that has not bonded with H, and the hydrogen concentration of the second high resistance region 603 is between the hydrogen concentration of the P-type active region 601 and the hydrogen concentration of the first high resistance region 602. Therefore, the second high resistance region 603 can be used to reduce the electric field intensity near the P-type active region in the on state, and improve the withstand voltage of the semiconductor structure. Alternatively, due to the blocking of H atoms by the second passivation layer 402, the hydrogen concentration of the first high resistance region 602 is equal to the hydrogen concentration of the second high resistance region 603.

[0036] Alternatively, as shown in Fig. 6, when the second passivation layer 402 is a single-layer structure of a SiN layer, the second high resistance region 603 covers the side surface of the second passivation layer 402 near the P-type active region 601. Specifically, when the second passivation layer 402 is a single-layer structure of a SiN layer, the first high resistance region 602 covers the side surface of the P-type active region 601 adjacent to the first passivation layer 401, and the second high resistance region 603 covers the side surface of the P-type active region 601 adjacent to the second passivation layer 402. The side surface of the P-type active region 601 is covered by the semiconductor in high resistance state, which can reduce the gate leakage current in the off state, and improve the withstand voltage of the semiconductor structure in the on state. Figure 6 ​

[0037] In one embodiment, Figure 7 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 7 As shown, when the second passivation layer 402 is a multilayer structure including a SiN layer 4021 and an AlN layer 4022, the second high-resistivity region 603 contacts the SiN layer 4021 and at least partially covers the side of the second passivation layer 402 near the P-type active region 601. Specifically, as... Figure 7 As shown, the second high-resistivity region 603 is located between the side of the P-type activation region 601 and the SiN layer 4021. The number of SiN layers 4021 corresponds to the number of the second high-resistivity regions 603. Multiple second high-resistivity regions 603 are arranged at intervals on the side of the P-type activation region 601, which can improve the electric field strength near the P-type activation region 601.

[0038] In one embodiment, the thickness of the second high-resistivity region 603 is 1–50 nm in a direction parallel to the plane of the substrate 10.

[0039] One embodiment of this application also provides a method for fabricating a semiconductor structure. Figures 8 to 17 The diagram shown is an intermediate structure diagram for fabricating a semiconductor structure according to an embodiment of this application. The fabrication method includes:

[0040] Step S1, as follows Figure 8 As shown, a channel layer 20 and a barrier layer 30 are sequentially epitaxially fabricated on a substrate 10. Specifically, before epitaxially fabricating the channel layer 20, a nucleation layer and a buffer layer are first epitaxially fabricated on the substrate 10 to improve the crystal quality of the subsequent epitaxial fabrication.

[0041] Step S2, as follows Figure 2 As shown, a first passivation layer 401 and a second passivation layer 402 with vias 50 are fabricated on the barrier layer 30. The vias 50 penetrate the first passivation layer 401 and the second passivation layer 402. The cross-sectional area of ​​the via 50 located in the first passivation layer 401 is larger than the cross-sectional area of ​​the via 50 located in the second passivation layer 402. Specifically, the first passivation layer 401 and the second passivation layer 402 with vias 50 are fabricated on the barrier layer 30 in the following two ways:

[0042] The first method, such as Figure 9 and Figure 10 As shown, the first passivation layer 401 and the second passivation layer 402 are dry etched to form an initial via 501 that penetrates the first passivation layer 401 and the second passivation layer 402; specifically, the cross-sectional area of ​​the initial via 501 located in the first passivation layer 401 is equal to the cross-sectional area of ​​the initial via 501 located in the second passivation layer 402.

[0043] like Figure 2As shown in the figure, the first passivation layer 401 is etched by wet etching in the initial via hole 501 to form the via hole 50; specifically, the material of the first passivation layer 401 is different from that of the second passivation layer 402, in the wet etching, the etching rate of the first passivation layer 401 is greater than that of the second passivation layer 402, or only the first passivation layer 401 is etched, so that the cross-sectional area of the via hole 50 located in the first passivation layer 401 is greater than that of the via hole 50 located in the second passivation layer 402. It should be noted that, due to the wet etching of the first passivation layer 401, the via hole sidewall of the via hole 50 located in the first passivation layer 401 can be arc-shaped (not shown).

[0044] The second way is to etch the first passivation layer 401 by dry etching in the initial via hole 501 to form the via hole 50; specifically, the material of the first passivation layer 401 is different from that of the second passivation layer 402, in the dry etching, the etching rate of the first passivation layer 401 is greater than that of the second passivation layer 402, or only the first passivation layer 401 is etched, so that the cross-sectional area of the via hole 50 located in the first passivation layer 401 is greater than that of the via hole 50 located in the second passivation layer 402. Figure 11 As shown in the figure, a first sacrificial layer 801 is made on the barrier layer 30; optionally, the first sacrificial layer 801 is made by full-area deposition and regional etching.

[0045] As shown in the figure, a first passivation layer 401 is deposited on the first sacrificial layer 801 and the barrier layer 30; specifically, the first passivation layer 401 is deposited on the first sacrificial layer 801 and the barrier layer 30. Figure 12 As shown in the figure, the first passivation layer 401 located on the first sacrificial layer 801 is treated by chemical mechanical polishing until the first sacrificial layer 801 is exposed; specifically, the chemical mechanical polishing can make the processing surface smoother.

[0046] Figure 13 As shown in the figure, a second sacrificial layer 802 is made on the first sacrificial layer 801, and the projection of the first sacrificial layer 801 on the substrate 10 covers the projection of the second sacrificial layer 802 on the substrate 10; optionally, the second sacrificial layer 802 is made by full-area deposition and regional etching.

[0047] As shown in the figure, a second passivation layer 402 is deposited on the second sacrificial layer 802 and the barrier layer 30; specifically, the second passivation layer 402 is deposited on the second sacrificial layer 802 and the barrier layer 30. Figure 14 As shown in the figure, the second passivation layer 402 located on the second sacrificial layer 802 is treated by chemical mechanical polishing until the second sacrificial layer 802 is exposed.

[0048] Figure 15 As shown in the figure, the first sacrificial layer 801 and the second sacrificial layer 802 are etched to form the via hole 50; optionally, the material of the first sacrificial layer 801 and the second sacrificial layer 802 is the same.

[0049] As shown in the figure, the first passivation layer 401 is etched by wet etching in the initial via hole 501 to form the via hole 50; specifically, the material of the first passivation layer 401 is different from that of the second passivation layer 402, in the wet etching, the etching rate of the first passivation layer 401 is greater than that of the second passivation layer 402, or only the first passivation layer 401 is etched, so that the cross-sectional area of the via hole 50 located in the first passivation layer 401 is greater than that of the via hole 50 located in the second passivation layer 402. It should be noted that, due to the wet etching of the first passivation layer 401, the via hole sidewall of the via hole 50 located in the first passivation layer 401 can be arc-shaped (not shown). Figure 16 As shown in the figure, the first passivation layer 401 is etched by dry etching in the initial via hole 501 to form the via hole 50; specifically, the material of the first passivation layer 401 is different from that of the second passivation layer 402, in the dry etching, the etching rate of the first passivation layer 401 is greater than that of the second passivation layer 402, or only the first passivation layer 401 is etched, so that the cross-sectional area of the via hole 50 located in the first passivation layer 401 is greater than that of the via hole 50 located in the second passivation layer 402.

[0050] Figure 2 As shown in the figure, the first passivation layer 401 is etched by dry etching in the initial via hole 501 to form the via hole 50; specifically, the material of the first passivation layer 401 is different from that of the second passivation layer 402, in the dry etching, the etching rate of the first passivation layer 401 is greater than that of the second passivation layer 402, or only the first passivation layer 401 is etched, so that the cross-sectional area of the via hole 50 located in the first passivation layer 401 is greater than that of the via hole 50 located in the second passivation layer 402.

[0051] As shown in the figure, the first passivation layer 401 is etched by dry etching in the initial via hole 501 to form the via hole 50; specifically, the material of the first passivation layer 401 is different from that of the second passivation layer 402, in the dry etching, the etching rate of the first passivation layer 401 is greater than that of the second passivation layer 402, or only the first passivation layer 401 is etched, so that the cross-sectional area of the via hole 50 located in the first passivation layer 401 is greater than that of the via hole 50 located in the second passivation layer 402. Figure 17 ​​​As shown, a semiconductor material layer 600 is selectively epitaxially fabricated in the via 50. Optionally, the semiconductor material layer 600 fills the entire via 50.

[0052] Step S4, as follows Figure 1 As shown, annealing transforms semiconductor material layer 600 into semiconductor layer 60. Semiconductor layer 60 includes a P-type active region 601 and a first high-resistivity region 602. The P-type active region 601 penetrates the first passivation layer 401 and the second passivation layer 402. The first high-resistivity region 602 is located between the P-type active region 601 and the first passivation layer 401. The projection of the second passivation layer 402 onto the substrate 10 covers the projection of the first high-resistivity region 602 onto the substrate 10. Specifically, annealing breaks the Mg-H bonds in the P-type active region 601 of the semiconductor material layer 600, allowing H atoms to escape and release Mg, resulting in P-type conductivity. Simultaneously, due to the obstruction of the second passivation layer 402, H atoms cannot escape, and the Mg-H bonds in the first high-resistivity region 602 remain bonded. Compared to the P-type active region 601, the first high-resistivity region 602 has less free Mg, exhibiting a high-resistivity state.

[0053] Optionally, such as Figure 1 As shown, the sidewall of the second passivation layer 402 near the P-type activation region 601 is flush with the sidewall of the first high-resistivity region 602 near the P-type activation region 601.

[0054] Optionally, the annealing process includes: treating in an N2 atmosphere at 500°C to 1000°C for at least 20 minutes, thereby activating the P-type activation region 601 and making it P-type conductive.

[0055] Optionally, such as Figure 6 and Figure 7 As shown, the second passivation layer 402 includes a SiN layer 4021, and the hydrogen content of the SiN layer 4021 is 5% to 20%. The semiconductor layer 60 also includes a second high-resistivity region 603 adjacent to the SiN layer 4021. Specifically, during the annealing process, hydrogen from the SiN layer 4021 enters the P-type activation region 601, causing the region adjacent to the SiN layer 4021 in the P-type activation region 601 to be passivated, forming the second high-resistivity region 603. The hydrogen concentration of the second high-resistivity region 603 is greater than the hydrogen concentration of the P-type activation region 601.

[0056] The semiconductor structure and the manufacturing method thereof provided by the embodiments of the present application, the semiconductor structure comprises a substrate, a channel layer, a barrier layer, a first passivation layer and a second passivation layer which are sequentially stacked, a via is arranged through the first passivation layer and the second passivation layer, the cross-sectional area of the via located in the first passivation layer is greater than the cross-sectional area of the via located in the second passivation layer, and a semiconductor layer fills the via, wherein the semiconductor layer comprises a P-type activation region and a first high-resistance region, the P-type activation region penetrates through the first passivation layer and the second passivation layer, the P-type activation region is used for depleting 2DEG of the underlying channel to realize an enhancement mode device, and the first high-resistance region is located between the P-type activation region and the first passivation layer and is covered by the projection of the second passivation layer on the substrate, the first high-resistance region is located at the included angle formed by the P-type activation region and the barrier layer, and is used for reducing the leakage current near the P-type activation region and improving the reliability of the device.

[0057] It should be understood that the term "comprising" and its variants used in the present application are open and inclusive, i.e., "comprising but not limited to". The term "one embodiment" means "at least one embodiment". In the present specification, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. Moreover, the skilled person in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

Claims

1. A semiconductor structure, characterized by, Comprise: Substrate, channel layer, barrier layer, first passivation layer and second passivation layer arranged in sequence, the second passivation layer comprises SiN layer, the hydrogen content of the SiN layer is 5%~20%; Through hole, the through hole penetrates the first passivation layer and the second passivation layer, the cross-sectional area of the through hole located in the first passivation layer is greater than the cross-sectional area of the through hole located in the second passivation layer; Semiconductor layer, the semiconductor layer is located in the through hole; And Second high resistance area, the second high resistance area is in contact with the SiN layer; Wherein, the semiconductor layer comprises P type activation area and first high resistance area, the P type activation area penetrates the first passivation layer and the second passivation layer, the first high resistance area is located between the P type activation area and the first passivation layer, the projection of the second passivation layer on the substrate covers the projection of the first high resistance area on the substrate.

2. The semiconductor structure of claim 1, wherein, The hydrogen concentration of the first high resistance area is greater than the hydrogen concentration of the P type activation area.

3. The semiconductor structure of claim 1, wherein, The second passivation layer is single-layer structure, and the single-layer structure comprises SiN layer; or, The second passivation layer is multilayer structure, and the multilayer structure comprises SiN layer and AlN layer arranged in sequence.

4. The semiconductor structure of claim 3, wherein, When the second passivation layer is single-layer structure of the SiN layer, the second high resistance area covers the side of the second passivation layer close to the P type activation area.

5. The semiconductor structure of claim 3, wherein, When the second passivation layer is multilayer structure comprising the SiN layer and the AlN layer, the second high resistance area is in contact with the SiN layer and at least partially covers the side of the second passivation layer close to the P type activation area.

6. The semiconductor structure of claim 1, wherein, In the direction parallel to the plane where the substrate is located, the thickness of the second high resistance area is 1~50nm.

7. The semiconductor structure of claim 1, wherein, The hydrogen concentration of the second high resistance area is greater than the hydrogen concentration of the P type activation area.

8. The semiconductor structure of claim 1, wherein, The material of the first passivation layer comprises SiO2.

9. The semiconductor structure of claim 1, wherein, The side wall of the second passivation layer close to the P type activation area is flush with the side wall of the first high resistance area close to the P type activation area.

10. The semiconductor structure of claim 1, wherein, Further comprise: Gate located on the side of the P type activation area away from the substrate, Source and drain located on the side of the channel layer away from the substrate, and the source and the drain are located on both sides of the gate.

11. The semiconductor structure of claim 10, wherein, The first high resistance area is located on the side of the P type activation area close to the drain.

12. A method of fabricating a semiconductor structure, the method comprising: Comprise: Sequentially epitaxially fabricate channel layer and barrier layer on substrate; Fabricate first passivation layer and second passivation layer with through hole on the barrier layer, the through hole penetrates the first passivation layer and the second passivation layer, the cross-sectional area of the through hole located in the first passivation layer is greater than the cross-sectional area of the through hole located in the second passivation layer; In the through hole, selectively epitaxially fabricate semiconductor material layer; Annealing treatment, the semiconductor material layer is converted into semiconductor layer, wherein the semiconductor layer comprises P type activation area and first high resistance area, the P type activation area penetrates the first passivation layer and the second passivation layer, the first high resistance area is located between the P type activation area and the first passivation layer, and the projection of the second passivation layer on the substrate covers the projection of the first high resistance area on the substrate.

13. The method of manufacturing according to claim 12, wherein, The first passivation layer and the second passivation layer with through hole fabricated on the barrier layer comprise: dry-etching the first passivation layer and the second passivation layer to form an initial via hole penetrating through the first passivation layer and the second passivation layer; wet-etching the first passivation layer in the initial via hole to form the via hole.

14. The method of manufacturing according to claim 12, wherein, The annealing treatment comprises: being treated in a N2 atmosphere at 500-1000 ℃ for at least 20 minutes.

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