Esd device of ldmosfet structure and manufacturing method, chip

Abstract

The application relates to the technical field of semiconductors, and provides an ESD device of an LDMOSFET structure, a manufacturing method and a chip. The device comprises a substrate, a body region, a drift region, a source region, a drain region and a gate structure. The gate structure comprises a polysilicon gate, a polysilicon resistor, a metal silicide layer, a field oxide layer and a gate oxide layer. The polysilicon gate is connected with the polysilicon resistor. The metal silicide layer is formed on the surface of the polysilicon gate and is connected with the polysilicon resistor. The field oxide layer is formed on the side end and the bottom of the polysilicon gate and is connected with the drain region. The polysilicon gate, the field oxide layer and the drain region form a capacitor structure. The polysilicon gate and the field oxide layer form a field plate structure. According to the embodiment of the application, the on-resistance between the polysilicon resistor and the polysilicon gate is reduced by the metal silicide layer, and the breakdown voltage is improved by the field plate structure formed by the polysilicon gate and the field oxide layer, so that the high-voltage protection capability of the ESD device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an ESD device with an LDMOSFET structure, its manufacturing method, and a chip. Background Technology

[0002] ESD (Electrostatic Discharge) refers to the charge transfer caused by objects with different electrostatic potentials approaching or coming into direct contact. When static charge accumulated in the external environment or inside an IC (integrated circuit) chip flows into or out through the chip's pins, the instantaneous ESD current can damage the thick gate oxide and metal lines of the internal components, leading to device failure. With the continuous improvement of VLSI (Very Large Scale Integration) process technology, Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits have entered the ultra-deep submicron stage. The size of MOS devices is constantly shrinking, and the harm of electrostatic discharge (ESD) to integrated circuits is becoming increasingly significant, necessitating ESD protection design for integrated circuits.

[0003] Existing technologies use ESD circuits to protect integrated circuits from electrostatic discharge. Figure 1 This is an RC-type ESD protection circuit employing gate coupling technology. By continuously adjusting the values ​​of capacitor Cn and resistor Rn, a suitable voltage can be coupled to the gate of the NMOS device Mn1 under high ESD stress, thereby reducing the turn-on voltage of the NMOS and achieving electrostatic discharge (ESD) protection. For NMOS and PMOS devices, a high bias voltage coupled to the gate will cause more channel current and a higher electric field, making the thin gate oxide layer more susceptible to damage, and rapidly reducing the robustness of ESD protection. However, in power management chips in the power field, the voltage during ESD discharge can reach several thousand volts or even tens of thousands of volts, making it difficult for this type of ESD circuit to achieve high-voltage ESD protection. Furthermore, this ESD circuit connects capacitors and resistors externally to the NMOS or PMOS device, resulting in a large area occupied by the ESD circuit, which is detrimental to chip miniaturization and integration. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides an ESD device with an LDMOSFET structure and a manufacturing method thereof.

[0005] The present invention provides an ESD device with an LDMOSFET structure, comprising: a substrate, a body region, a drift region, a source region, a drain region, and a gate structure, wherein the body region, the drift region, and the gate structure are formed in the substrate, the source region is embedded inside the body region, and the drain region is embedded inside the drift region;

[0006] The source region is connected to the source metal layer, and the drain region is connected to the drain metal layer;

[0007] The gate structure includes: a polysilicon gate, a polysilicon resistor, a metal silicide layer, and a field oxide layer. The polysilicon gate is connected to the polysilicon resistor, the polysilicon resistor is connected to the source metal layer, the metal silicide layer is formed on the surface of the polysilicon gate and is connected to the polysilicon resistor, and the polysilicon gate forms a conductive channel with the polysilicon resistor through the metal silicide layer.

[0008] The field oxide layer is formed on the side and bottom of the polysilicon gate and is connected to the drain region. The polysilicon gate, the field oxide layer and the drain region constitute a capacitor structure. The polysilicon gate and the field oxide layer constitute a field plate structure.

[0009] In this embodiment of the invention, the gate structure further includes a gate oxide layer;

[0010] The gate oxide layer is formed on the surface of the bulk region and the drift region;

[0011] The polysilicon gate, polysilicon resistor, and field oxide layer are formed on the surface of the gate oxide layer.

[0012] In this embodiment of the invention, one end of the polysilicon resistor is connected to the source metal layer, and the other end of the polysilicon resistor is connected to the polysilicon gate and the metal silicide layer.

[0013] In this embodiment of the invention, the source region includes a lateral extension region, which extends below the polysilicon resistor;

[0014] The leak region includes a lateral extension region that extends below the field oxide layer.

[0015] In this embodiment of the invention, the field oxide layer includes a vertical region, which is located between the polysilicon gate and the drain region.

[0016] In this embodiment of the invention, a contact end is formed on the surface of the body region, and the body region is connected to the source metal layer through the contact end.

[0017] In this embodiment of the invention, the source metal layer is grounded, and the drain metal layer serves as the input terminal.

[0018] The present invention also provides a method for manufacturing an ESD device with the above-described LDMOSFET structure, comprising:

[0019] Forming bulk regions and drift regions in the substrate;

[0020] The source region is formed inside the body region, and the drain region is formed inside the drift region;

[0021] Trenches are formed inside the body region and the drift region, and a field oxide layer is formed at the bottom of the trenches, so that the field oxide layer is in contact with the drain region;

[0022] A polysilicon gate and a polysilicon resistor are formed in the trench, such that one end of the polysilicon gate is connected to the polysilicon resistor, and the other end and bottom of the polysilicon gate are connected to the field oxide layer.

[0023] A metal silicide layer is formed on the surface of the polysilicon gate, and the metal silicide layer is connected to the polysilicon resistor.

[0024] A source metal layer connected to the source region and a drain metal layer connected to the drain region are formed.

[0025] In this embodiment of the invention, forming a body region and a drift region in a substrate includes: performing P-type ion implantation and N-type ion implantation on the surface of the substrate, and performing high-temperature propulsion to form a P-type body region and an N-type drift region.

[0026] In this embodiment of the invention, a source region is formed inside the body region and a drain region is formed inside the drift region. This includes: performing photolithography on the surface of the P-type body region and the surface of the N-type drift region to form an ion implantation window, implanting N-type ions into the ion implantation window, and performing annealing to form the source region inside the P-type body region and the drain region inside the N-type drift region.

[0027] In this embodiment of the invention, trenches are formed inside the body region and the drift region, and a field oxide layer is formed at the bottom of the trenches, including:

[0028] Dry etching is used to etch the volume region and drift region to form trenches;

[0029] A gate oxide layer is formed at the bottom of the trench, and a field oxide layer is formed on the surface of the gate oxide layer and the sidewalls of the trench.

[0030] In this embodiment of the invention, forming a polysilicon gate and a polysilicon resistor within a trench includes:

[0031] First-doped polysilicon is deposited in a trench with a field oxide layer to form a polysilicon layer. The concentration of the first doping is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 ;

[0032] The polysilicon layer near the drain region is doped a second time. The doped polysilicon serves as the polysilicon gate, while the undoped polysilicon serves as the polysilicon resistor. The concentration of the second doping is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 .

[0033] In this embodiment of the invention, a metal silicide layer is formed on the surface of a polysilicon gate, comprising:

[0034] Silicon dioxide is formed on a substrate with polysilicon gates and polysilicon resistors as a barrier layer;

[0035] Metal is deposited on the surface of the barrier layer and then heat-treated to form metal silicide;

[0036] Unreacted metal on the surface of the barrier layer is removed to form a metal silicide layer.

[0037] In this embodiment of the invention, forming a source metal layer connected to the source region and a drain metal layer connected to the drain region includes:

[0038] An isolation oxide layer is formed above the body region, drift region, polysilicon gate, and polysilicon resistor, and the isolation oxide layer is etched to form contact holes;

[0039] Metal is deposited inside the contact hole to form a metal layer;

[0040] The metal layer is etched to form a source metal layer connected to the source region and a drain metal layer connected to the drain region.

[0041] The present invention also provides a chip comprising the above-described LDMOSFET structure for ESD devices.

[0042] This invention designs an ESD device based on the LDMOSFET structure. Utilizing the high-voltage withstand capability of the LDMOSFET, a polysilicon resistor within the embedded region and a capacitor structure consisting of a polysilicon gate, field oxide layer, and drain region are added to the LDMOSFET structure. The polysilicon resistor is connected in series with the capacitor structure through a metal silicide layer, forming a high-voltage ESD device equivalent to an RC-type ESD protection circuit. This eliminates the need to add resistors and capacitors external to the MOS device, reducing the area of ​​the ESD device. Furthermore, this invention reduces the on-resistance between the polysilicon resistor and the polysilicon gate through the metal silicide layer, and simultaneously improves the breakdown voltage using the field plate structure formed by the polysilicon gate and the field oxide layer, thereby enhancing the high-voltage protection capability of the ESD device.

[0043] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description

[0044] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0045] Figure 1It is an existing gate-coupled RC type ESD protection circuit;

[0046] Figure 2 This is a schematic diagram of the structure of the ESD device with the LDMOSFET structure provided in the embodiment of the present invention;

[0047] Figure 3 This is a flowchart of a method for manufacturing an ESD device with an LDMOSFET structure provided in an embodiment of the present invention;

[0048] Figure 4a This is a schematic diagram of the structure of the body region and drift region formed in the manufacturing method provided in the embodiments of the present invention;

[0049] Figure 4b This is a schematic diagram of the source region, drain region, and contact end formed in the manufacturing method provided in the embodiments of the present invention;

[0050] Figure 4c This is a schematic diagram of the groove formed in the manufacturing method provided in the embodiment of the present invention;

[0051] Figure 4d This is a schematic diagram of the structure of the field oxide layer formed in the manufacturing method provided in the embodiments of the present invention;

[0052] Figure 4e This is a schematic diagram of the structure of the polycrystalline silicon resistor formed in the manufacturing method provided in the embodiments of the present invention;

[0053] Figure 4f This is a schematic diagram of the structure of the polycrystalline silicon gate formed in the manufacturing method provided in the embodiments of the present invention;

[0054] Figure 4g This is a schematic diagram of the structure of the metal silicide layer formed in the manufacturing method provided in the embodiments of the present invention;

[0055] Figure 4h This is a schematic diagram of the structure of the isolation oxide layer formed in the manufacturing method provided in the embodiments of the present invention;

[0056] Figure 4i This is a schematic diagram of the source metal layer and drain metal layer formed in the manufacturing method provided in the embodiments of the present invention.

[0057] Explanation of reference numerals in the attached figures

[0058] 10-Substrate, 11-Bulk region, 12-Drift region, 13-Source region, 13a-Lateral extension region of the source region.

[0059] 14 - Drain region, 14a - Lateral extension region of the drain region, 15 - Gate oxide layer,

[0060] 16-field oxide layer, vertical region of 16a-field oxide layer,

[0061] 17-Polysilicon resistor, 18-Polysilicon gate, 19-Metal silicide layer, 20-Contact terminal.

[0062] 21-Isolation oxide layer, 22-Source metal layer, 23-Drain metal layer. Detailed Implementation

[0063] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0064] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "side," "bottom," "surface," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0065] In this invention, unless otherwise explicitly specified and limited, the terms "connected," "interlocked," and "linked" should be interpreted broadly. For example, they can refer to direct connection or indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0066] Figure 2 This is a schematic diagram of the ESD device with an LDMOSFET structure provided in an embodiment of the present invention. Figure 2As shown, the ESD device with an LDMOSFET structure provided in this embodiment includes: a substrate 10, a body region 11, a drift region 12, a source region 13, a drain region 14, and a gate structure. The body region 11, the drift region 12, and the gate structure are formed in the substrate 10. The source region 13 is embedded inside the body region 11, and the drain region 14 is embedded inside the drift region 12. The source region 13 is connected to the source metal layer 22, and the drain region 14 is connected to the drain metal layer 23. The gate structure includes a polysilicon gate 18, a polysilicon resistor 17, a metal silicide layer 19, a field oxide layer 16, and a gate oxide layer 15. The gate oxide layer 15 is formed on the surface of the body region 11 and the drift region 12. The polysilicon gate 18, the polysilicon resistor 17, and the field oxide layer 16 are formed on the surface of the gate oxide layer 15. The polysilicon gate 18 is connected to the polysilicon resistor 17, and the polysilicon resistor 17 is connected to the source metal layer 22. A metal silicide layer 19 is formed on the surface of the polysilicon gate 18 and is connected to the polysilicon resistor 17. The polysilicon gate 18 forms a conductive channel with the polysilicon resistor 17 through the metal silicide layer 19. A field oxide layer 16 is formed on the side and bottom of the polysilicon gate 18 and is connected to the drain region 14. The polysilicon gate 18 and the drain region 14 serve as the two plates of a capacitor, and the field oxide layer 16 serves as the dielectric layer between the two plates. The polysilicon gate 18, the field oxide layer 16, and the drain region 14 constitute a capacitor structure. At the same time, the polysilicon gate 18 and the field oxide layer 16 constitute a field plate structure. With the source metal layer 22 grounded and the drain metal layer 23 serving as the input terminal, the above-described LDMOSFET structure is equivalent to an RC-type ESD protection circuit.

[0067] In this embodiment, one end of the polysilicon resistor 17 is connected to the source metal layer 22, and the other end of the polysilicon resistor 17 is connected to the polysilicon gate 18 and the metal silicide layer 19. When the polysilicon resistor 17 is connected in series with the capacitor structure, a large on-resistance will be formed inside the device due to the large resistance between the polysilicon gate 18 and the polysilicon resistor 17. Therefore, a metal silicide layer 19 is added to one end of the polysilicon resistor 17. The polysilicon gate 18 forms a conductive channel with the polysilicon resistor 17 through the metal silicide layer 19. The metal silicide layer 19 reduces the resistance between the polysilicon resistor 17 and the polysilicon gate 18, thereby increasing the conduction effect.

[0068] In this embodiment, the polysilicon gate 18 is made of heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 The polycrystalline silicon resistor 17 is made of lightly doped polycrystalline silicon, with a doping concentration of 1 × 10⁻⁶ ions. 16 cm -3 ~1×10 18 cm-3 .

[0069] In this embodiment, the source region 13 includes a lateral extension region 13a that extends below the polysilicon resistor 17. The drain region 14 includes a lateral extension region 14a that extends below the field oxide layer 16. This embodiment provides lateral extension regions on opposite sides of the embedded source region 13 and drain region 14, which can shorten the conductive channel between the source region 13 and drain region 14 and enhance the device's conductivity.

[0070] In this embodiment, the field oxide layer 16 includes a lateral region (field oxide layer body) and a vertical region. The vertical region 16a of the field oxide layer is located between the polysilicon gate 18 and the drain region 14, serving as a dielectric layer between the polysilicon gate 18 and the drain region 14, thereby forming a capacitor structure.

[0071] In this embodiment, a contact terminal 20 is formed on the surface of the body region 11, and the body region 11 is connected to the source metal layer 22 through the contact terminal 20. An isolation oxide layer 21 is formed on the surface of the metal silicide layer 19, part of the surface of the body region 11 and the drift region 12, and the isolation oxide layer 21 isolates the source metal layer 22 from the drain metal layer 23.

[0072] This invention adds a polysilicon resistor within the embedded region and a capacitor structure consisting of a polysilicon gate, a field oxide layer, and a drain region to the LDMOSFET structure. The polysilicon resistor is connected in series with the capacitor structure through a metal silicide layer, forming a high-voltage ESD device equivalent to an RC-type ESD protection circuit. This eliminates the need to add resistors and capacitors externally to the MOS device, thus reducing the area of ​​the ESD device. This invention also reduces the on-resistance between the polysilicon resistor and the polysilicon gate through the metal silicide layer, and simultaneously improves the breakdown voltage using the field plate structure formed by the polysilicon gate and the field oxide layer, thereby enhancing the high-voltage protection capability of the ESD device.

[0073] The present invention also provides a method for manufacturing an ESD device with the above-described LDMOSFET structure, such as... Figure 3 As shown, the method includes the following steps:

[0074] S301, forming a bulk region and a drift region in the substrate;

[0075] S302, a source region is formed inside the body region, and a drain region is formed inside the drift region;

[0076] S303 forms trenches inside the bulk region and drift region, and forms a field oxide layer at the bottom of the trenches;

[0077] S304, forming a polysilicon gate and a polysilicon resistor within the trench;

[0078] S305, a metal silicide layer is formed on the surface of the polysilicon gate;

[0079] S306, forming a source metal layer connected to the source region and a drain metal layer connected to the drain region.

[0080] In one specific embodiment, in step S301 above, a P-type silicon substrate 10 is selected, and P-type ion implantation and N-type ion implantation are performed on the surface of the P-type silicon substrate 10, respectively, followed by high-temperature propagation to form a structure as shown in the figure. Figure 4a The P-type body region 11 and N-type drift region 12 are shown.

[0081] In one specific embodiment, in step S302 above, a thin layer of SiO2 is formed by thermal oxidation on the surface of the substrate 10. Photolithography is then performed on the surfaces of the P-type body region 11 and the N-type drift region 12 to form ion implantation windows. N-type ions are implanted into these windows (the ion implantation depth extends to near the bottom of the P-type body region and the N-type drift region), followed by annealing. This forms a source region 13 inside the P-type body region 11 and a drain region 14 inside the N-type drift region 12. Simultaneously, P-type ions can also be implanted into another ion implantation window of the P-type body region 11 to form a P+ contact terminal 20 on the surface of the P-type body region 11, forming a... Figure 4b The structure shown.

[0082] In one specific embodiment, in step S303 above, photolithography is performed on the surface of the P-type body region 11 and the surface of the N-type drift region 12, and a dry etching method is used to etch the P-type body region 11 and the N-type drift region 12. The etching depth does not exceed the depth of the source region 13 and the drain region 14, forming a shape as shown in the figure. Figure 4c The groove shown.

[0083] Then, the SiO2 on the surface of the P-type body region 11 and the N-type drift region 12 is removed by wet etching. A thin layer of SiO2 is formed by thermal oxidation in the trench as the gate oxide layer 15. A thicker layer of SiO2 is deposited on the surface of the gate oxide layer 15 at the bottom of the trench and on the sidewalls of the trench, and then dry etching is performed to form a layer as shown in the figure. Figure 4d The field oxide layer 16 is shown. The field oxide layer 16 includes a lateral region and a vertical region. The vertical region 16a of the field oxide layer is connected to the drain region 14 and serves as the dielectric layer of the capacitor structure.

[0084] In one specific embodiment, in step S304 above, a first-doped polysilicon layer is then deposited in the trench using a low-pressure chemical vapor deposition (LPCVD) method, wherein the concentration of the first doping is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3At this point, the doping concentration of the polycrystalline silicon layer is low, and its resistance is high. As a polycrystalline silicon resistor 17, it forms a structure like... Figure 4e The structure is shown. Next, the portion of the polysilicon layer near the drain region 14 is subjected to secondary doping. The secondary-doped polysilicon serves as the polysilicon gate 18, and the undoped polysilicon serves as the polysilicon resistor 17. The concentration of secondary doping is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 , forming as Figure 4f The structure is shown. At this point, one side of the polysilicon gate 18 is connected to the polysilicon resistor 17, and the other side and bottom of the polysilicon gate 18 are connected to the field oxide layer 16. This step can form the polysilicon resistor and polysilicon gate using only one polysilicon photolithography process (existing technologies typically require two photolithography processes). The polysilicon gate also serves as a capacitor electrode, simplifying the process and reducing the gate's footprint.

[0085] In one specific embodiment, in step S305 above, a thin layer of silicon dioxide (SiO2) is formed on the substrate 10 containing the polysilicon gate 18 and the polysilicon resistor 17 as a barrier layer for the silicide region. Dry etching is then performed on the silicon dioxide to open the silicide region. Metal (such as Ti, Co, Ni, etc.) is deposited on the surface of the barrier layer, and rapid thermal processing (RTP) is performed to form metal silicides. Then, wet etching is used to remove unreacted metal from the surface of the barrier layer, forming a metal silicide. Figure 4g The metal silicide layer 19 is shown. At this time, the metal silicide layer 19 is connected to one end of the polysilicon resistor 17.

[0086] In one specific embodiment, in step S306 above, an isolation oxide layer (e.g., SiO2) is formed above the body region 11, drift region 12, polysilicon gate 18, and polysilicon resistor 17. The isolation oxide layer is then etched to form multiple contact holes. Simultaneously, a high SiO2 / Si etching selectivity process condition is used to over-etch away the SiO2 between the source region 13 and the polysilicon resistor 17, forming a... Figure 4h The isolation oxide layer 21 is shown.

[0087] Next, a physical vapor deposition (PVD) process is used to deposit metal within the contact holes to form a metal layer. This metal layer is then etched to create a surface resembling... Figure 4i The source metal layer 22 and drain metal layer 23 shown are used to obtain an ESD device with an LDMOSFET structure.

[0088] The present invention also provides a chip that includes an ESD device with the above-described LDMOSFET structure, thereby achieving electrostatic protection for the integrated circuit in the chip.

[0089] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Furthermore, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. As long as such combination does not violate the spirit of the embodiments of the present invention, it should also be considered as the content disclosed in the embodiments of the present invention.

Claims

1. An ESD device with an LDMOSFET structure, comprising: A substrate, a body region, a drift region, a source region, a drain region, and a gate structure, characterized in that the body region, the drift region, and the gate structure are formed in the substrate, the source region is embedded inside the body region, and the drain region is embedded inside the drift region; The source region is connected to the source metal layer, and the drain region is connected to the drain metal layer; The gate structure includes: a polysilicon gate, a polysilicon resistor, a metal silicide layer, and a field oxide layer. The polysilicon gate is connected to the polysilicon resistor, the polysilicon resistor is connected to the source metal layer, the metal silicide layer is formed on the surface of the polysilicon gate and is connected to the polysilicon resistor, and the polysilicon gate forms a conductive channel with the polysilicon resistor through the metal silicide layer. The field oxide layer is formed on the side and bottom of the polysilicon gate and is connected to the drain region. The polysilicon gate, the field oxide layer and the drain region constitute a capacitor structure. The polysilicon gate and the field oxide layer constitute a field plate structure.

2. The ESD device with an LDMOSFET structure according to claim 1, characterized in that, The gate structure further includes a gate oxide layer; The gate oxide layer is formed on the surface of the bulk region and the drift region; The polysilicon gate, polysilicon resistor, and field oxide layer are formed on the surface of the gate oxide layer.

3. The ESD device with an LDMOSFET structure according to claim 1, characterized in that, One end of the polysilicon resistor is connected to the source metal layer, and the other end of the polysilicon resistor is connected to the polysilicon gate and the metal silicide layer.

4. The ESD device with an LDMOSFET structure according to claim 1, characterized in that, The source region includes a lateral extension region that extends below the polysilicon resistor. The leak region includes a lateral extension region that extends below the field oxide layer.

5. The ESD device with an LDMOSFET structure according to claim 1, characterized in that, The field oxide layer includes a vertical region located between the polysilicon gate and the drain region.

6. The ESD device with an LDMOSFET structure according to claim 1, characterized in that, The surface of the body region has a contact end, and the body region is connected to the source metal layer through the contact end.

7. The ESD device with an LDMOSFET structure according to claim 1, characterized in that, The source metal layer is grounded, and the drain metal layer serves as the input terminal.

8. A method for manufacturing an ESD device with an LDMOSFET structure, characterized in that, include: Forming bulk regions and drift regions in the substrate; The source region is formed inside the body region, and the drain region is formed inside the drift region; Trenches are formed inside the body region and the drift region, and a field oxide layer is formed at the bottom of the trenches, so that the field oxide layer is in contact with the drain region; A polysilicon gate and a polysilicon resistor are formed in the trench, such that one end of the polysilicon gate is connected to the polysilicon resistor, and the other end and bottom of the polysilicon gate are connected to the field oxide layer. A metal silicide layer is formed on the surface of the polysilicon gate, and the metal silicide layer is connected to the polysilicon resistor. A source metal layer connected to the source region and a drain metal layer connected to the drain region are formed.

9. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 8, characterized in that, Forming bulk regions and drift regions in the substrate, including: P-type ion implantation and N-type ion implantation are performed on the surface of the substrate, and high-temperature propulsion is carried out to form a P-type bulk region and an N-type drift region.

10. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 9, characterized in that, The source region is formed within the body region, and the drain region is formed within the drift region, including: Photolithography is performed on the surface of the P-type body region and the surface of the N-type drift region to form ion implantation windows. N-type ions are implanted into the ion implantation windows and then annealed to form the source region inside the P-type body region and the drain region inside the N-type drift region.

11. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 8, characterized in that, Trenches are formed inside the bulk region and drift region, and a field oxide layer is formed at the bottom of the trenches, including: Dry etching is used to etch the volume region and drift region to form trenches; A gate oxide layer is formed at the bottom of the trench, and a field oxide layer is formed on the surface of the gate oxide layer and the sidewalls of the trench.

12. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 8, characterized in that, Forming a polysilicon gate and a polysilicon resistor within the trench includes: First-doped polysilicon is deposited in a trench with a field oxide layer to form a polysilicon layer. The concentration of the first doping is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 ; The part of the polysilicon layer close to the drain region is secondarily doped, the secondarily doped polysilicon serves as a polysilicon gate, and the polysilicon not secondarily doped serves as a polysilicon resistor, the concentration of the secondary doping is 1×10 20 cm -3 ~1×10 21 cm -3 .

13. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 8, characterized in that, A metal silicide layer is formed on the surface of the polysilicon gate, including: Silicon dioxide is formed on a substrate with polysilicon gates and polysilicon resistors as a barrier layer; Metal is deposited on the surface of the barrier layer and then heat-treated to form metal silicide; Unreacted metal on the surface of the barrier layer is removed to form a metal silicide layer.

14. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 8, characterized in that, Forming a source metal layer connected to the source region and a drain metal layer connected to the drain region, including: An isolation oxide layer is formed above the body region, drift region, polysilicon gate, and polysilicon resistor, and the isolation oxide layer is etched to form contact holes; Metal is deposited inside the contact hole to form a metal layer; The metal layer is etched to form a source metal layer connected to the source region and a drain metal layer connected to the drain region.

15. A chip, characterized in that, The chip includes an ESD device with an LDMOSFET structure as described in any one of claims 1-7.

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