LDMOS device and manufacturing method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The device comprises a substrate; the drift region is located in the substrate, a plurality of holes are formed in the drift region, and the holes are filled with isolation materials to form a hole isolation structure; the gate electrode at least covers the hole isolation structure and covers part of the drift region; and the field plate at least covers part of the gate electrode and is positioned above the hole isolation structure. According to the invention, the plurality of hole isolation structures are arranged in the drift region, compared with a large-region shallow trench isolation structure, the process of the hole isolation structures is easier to realize, so that the process difficulty is reduced, and meanwhile, the plurality of hole isolation structures form a shunt capacitor, so that more charges can be accumulated to increase the number of carriers, and the on-resistance is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and particularly relates to an LDMOS device and a manufacturing method thereof. Background Art

[0002] LDMOS (Lateral Diffused Metal Oxide Semiconductor) is one of the core devices of the BCD (Bipolar-CMOS-DMOS) process platform, which can be compatible with the BJT (bipolar junction transistor) and CMOS (Complementary Metal Oxide Semiconductor) processes, has the characteristics of high-voltage and large-current driving capabilities, and has extremely low power consumption in the switching mode.

[0003] The main technical indicators of the LDMOS device include on-resistance (Rdson), breakdown voltage (BVdss), and threshold voltage (Vth). Adding STI (Shallow Trench Isolation) to the drift region of the LDMOS device can significantly improve the breakdown voltage without increasing the chip area. This is because the dielectric constant of the silicon dioxide used in the shallow trench isolation structure is one-third of that of the silicon material, so that the electric field strength it can withstand is more than three times that of the silicon material. Then, under the same electric field strength at the end of the gate field plate, due to the thicker silicon dioxide in the shallow trench isolation structure, the electric field strength dropping to the silicon surface in contact with the silicon dioxide will be lower, thus a higher breakdown voltage can be achieved. In addition, the current path of the shallow trench isolation structure will be shorter than that of the LOCOS (Local Oxidation of Silicon) structure, so that a lower on-resistance can be achieved.

[0004] However, the on-resistance and breakdown voltage of the existing LDMOS devices still need to be continuously improved. Summary of the Invention

[0005] The purpose of the present invention is to provide an LDMOS device and a manufacturing method thereof, which can reduce the process difficulty and the on-resistance.

[0006] To solve the above technical problems, according to the first aspect of the present invention, an LDMOS device is provided, including:

[0007] A substrate;

[0008] A drift region, located in the substrate, and a plurality of holes are formed in the drift region, and the holes are filled with an isolation material to form a hole isolation structure;

[0009] A gate electrode that covers at least the hole isolation structure and covers part of the drift region; and

[0010] A field plate that covers at least part of the gate electrode and is located above the hole isolation structure.

[0011] Optionally, a plurality of the hole isolation structures are regularly arranged in the row direction and the column direction.

[0012] Optionally, the gate electrode includes two connected parts. The first part of the gate electrode is a block structure that covers part of the drift region, and the second part of the gate electrode includes a plurality of strip structures extending in the row direction, and each strip structure covers the hole isolation structures arranged in a certain row respectively.

[0013] Optionally, the field plate includes a plurality of strip structures extending in the column direction, and each strip structure is located above the hole isolation structures arranged in a certain column respectively.

[0014] Optionally, the hole isolation structure includes a high-k material layer covering the side wall and bottom of the hole and an insulating material layer filling the hole.

[0015] Optionally, the material of the high-k material layer includes hafnium-based oxide, aluminum-based oxide or zirconium-based oxide.

[0016] Optionally, the material of the insulating material layer includes silicon dioxide.

[0017] Optionally, the LDMOS device further includes a body region located in the substrate, a source electrode located in the body region, and a drain electrode located in the drift region. The drain electrode is located on the side of the drift region away from the source electrode, and the hole isolation structure is located on the side of the drain electrode close to the source electrode.

[0018] Optionally, the doping types of the drift region and the body region are opposite.

[0019] To solve the above technical problems, according to the second aspect of the present invention, a manufacturing method of an LDMOS device is further provided, including the following steps:

[0020] Provide a substrate and form a drift region in the substrate;

[0021] Form a plurality of holes in the drift region, and fill the holes with an isolation material to form hole isolation structures;

[0022] Form a gate electrode that covers at least the hole isolation structure and covers part of the drift region; and

[0023] Form a field plate that covers at least part of the gate electrode, and the field plate is located above the hole isolation structure.

[0024] In the LDMOS device and its manufacturing method provided by the present invention, a plurality of hole isolation structures are formed in the drift region. Compared with the large-area shallow trench isolation structure, the process of the hole isolation structure is easier to implement, thereby reducing the process difficulty. At the same time, the plurality of hole isolation structures form a parallel capacitor, which can accumulate more charges to make more carriers, thereby reducing the on-resistance.

[0025] Furthermore, a high-k material layer is formed on the sidewall and bottom of the hole, and an insulating material layer is filled in the hole. The high-k material can introduce the electric field into the insulating material, thereby reducing the electric field and increasing the breakdown voltage. Description of the Drawings

[0026] Figure 1 is a schematic structural diagram of an LDMOS device.

[0027] Figure 2 is a schematic diagram of the positional relationship among the hole isolation structure, the gate electrode, and the field plate provided by an embodiment of the present invention.

[0028] Figure 3 is a schematic flow diagram of the manufacturing method of the LDMOS device provided by an embodiment of the present invention.

[0029] Description of the Reference Numerals:

[0030] 10 - Substrate; 11 - High-voltage well region; 12 - Drift region; 13 - Body region; 14 - Shallow trench isolation structure; 15 - Drain; 16 - Source; 17 - Body electrode; 18 - Gate electrode; 19 - Field plate; 20 - Hole; 30 - Hole isolation structure; 31 - High-k material layer; 32 - Insulating material layer. Detailed Embodiments

[0031] Figure 1 is a schematic structural diagram of an LDMOS device. Please refer to Figure 1 As shown, the LDMOS device includes: a substrate 10, a high-voltage well region 11 located in the substrate 10, a drift region 12 and a body region 13 located in the high-voltage well region 11, a shallow trench isolation structure 14 and a drain 15 located in the drift region 12, a source 16 and a body electrode 17 located in the body region 13. The shallow trench isolation structure 14 is located on the side of the drain 15 close to the source 16, and the body electrode 17 is located on the side of the source 16 away from the drain 15. Exemplarily, the substrate 10 is a P-type substrate, the high-voltage well region 11 is a high-voltage N-well, the drift region 12 is an N-type drift region, the body region 13 is a P-type body region, the source 16 and the drain 15 are N+ regions, and the body electrode 17 is a P+ region.

[0032] The LDMOS device further includes a gate electrode 18 and a field plate (not shown). The gate electrode 18 covers a part of the drift region 12, a part of the body region 13, and a part of the shallow trench isolation structure 14. The gate electrode 18 is located on a part of the drift region 12 and a part of the body region 13 between the source electrode 16 and the drain electrode 15. The field plate covers a part of the gate electrode 18 and a part of the isolation trench 14.

[0033] Regarding Figure 1 For the structure shown, through research, it is found that setting the large-area shallow trench isolation structure 14 as a multi-hole isolation structure can not only reduce the process difficulty, but also the multi-hole isolation structures form a parallel capacitor, which can accumulate more charges to make more carriers, thereby reducing the on-resistance. In addition, the hole isolation structure can be set to include a high-k material layer covering the sidewalls and bottom of the holes, and an insulating material layer filling the holes. The high-k material can introduce the electric field into the insulating material, thereby reducing the electric field and increasing the breakdown voltage.

[0034] Through further research, the present invention provides an LDMOS device, including: a substrate; a drift region located in the substrate, and a plurality of holes are formed in the drift region, and the holes are filled with an isolation material to form a hole isolation structure; a gate electrode that covers at least the hole isolation structure and covers a part of the drift region; and a field plate that covers at least a part of the gate electrode and is located above the hole isolation structure.

[0035] Correspondingly, the present invention also provides a manufacturing method of an LDMOS device, including the following steps: providing a substrate and forming a drift region in the substrate; forming a plurality of holes in the drift region and filling the holes with an isolation material to form a hole isolation structure; forming a gate electrode, the gate electrode covering at least the hole isolation structure and covering a part of the drift region; and forming a field plate, the field plate covering at least a part of the gate electrode, and the field plate being located above the hole isolation structure.

[0036] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and are not drawn to scale, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often a part of the actual structure. In particular, the emphasis to be shown in each drawing is different, and sometimes different scales are used.

[0037] As used in the present invention, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. As used in the present invention, the term "or" is generally used in the sense of including "and / or" unless the context clearly dictates otherwise. As used in the present invention, the term "several" is generally used in the sense of including "at least one" unless the context clearly dictates otherwise. As used in the present invention, the term "at least two" is generally used in the sense of including "two or more" unless the context clearly dictates otherwise. In addition, the terms "first", "second", "third" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features unless the context clearly dictates otherwise.

[0038] Figure 2 FIG. is a schematic diagram of the positional relationship among a hole isolation structure, a gate electrode, and a field plate provided by an embodiment of the present invention. Please refer to Figure 1 and Figure 2 As shown, the LDMOS device includes: a substrate 10; a drift region 12 located within the substrate 10, in which a plurality of holes 20 are formed, and an isolation material is filled in the holes 20 to form a hole isolation structure 30; a gate electrode 18 that at least covers the hole isolation structure 30 and covers a part of the drift region 12; and a field plate 19 that at least covers a part of the gate electrode 18 and is located above the hole isolation structure 30.

[0039] A part of the gate electrode 18 covers the hole isolation structure 30, the field plate 19 covers a part of the gate electrode 18, and the gate electrode 18 covered by the field plate 19 simultaneously covers the hole isolation structure 30, that is, the hole isolation structure 30 is sequentially covered by the gate electrode 18 and the field plate 19. In one embodiment, the gate electrode 18 may cover all of the hole isolation structure 30, and in another embodiment, the gate electrode 18 may cover a part of the hole isolation structure 30. The present invention does not limit this.

[0040] Please refer to Figure 2 As shown, a plurality of the hole isolation structures 30 are regularly arranged in a row direction and a column direction, and the row direction and the column direction refer to Figure 2 the horizontal direction and the vertical direction in, and the row direction and the column direction are perpendicular to each other. A plurality of the hole isolation structures 30 are regularly arranged in the row direction and the column direction to form a hole isolation structure matrix. Figure 2Only three rows and three columns of the hole isolation structure matrix are shown. In other embodiments, it can be set as a two-row and two-column hole isolation structure matrix, or can be set as an array of hole isolation structures with four rows or more and four columns or more. The number of rows and columns of the hole isolation structure can be the same or different. The number of the hole isolation structures 30 can be determined according to the actual size of the drift region 12 and the size of the hole isolation structure 30. Of course, the multiple hole isolation structures 30 can also adopt other arrangements, not limited to Figure 2 shown. The size of the hole isolation structure 30 (such as the cross-sectional width and depth) can be determined according to actual requirements and actual process conditions.

[0041] The gate electrode 18 includes two parts. The first part of the gate electrode (please refer to the right part of the gate electrode 18 in Figure 2 ) is a block structure. The first part of the gate electrode covers part of the drift region 12. The second part of the gate electrode (please refer to the left side of the gate electrode 18 in Figure 2 ) includes a plurality of strip structures extending in the row direction. Each strip structure respectively covers the hole isolation structures 30 arranged in a certain row. For example Figure 2 there are 3 rows of hole isolation structures 30 set in. The second part of the gate electrode includes 3 strip structures, and each strip structure covers one row of the hole isolation structures 30.

[0042] The field plate 19 includes a plurality of strip structures extending in the column direction. Each strip structure is respectively located above the hole isolation structures 30 arranged in a certain column. For example Figure 2 there are 3 columns of hole isolation structures set in. The field plate 19 includes 3 strip structures, and each strip structure covers one column of the hole isolation structures 30 (of course, the strip structure actually covers the gate electrode 18, and the gate electrode 18 covered by the strip structure then covers the hole isolation structures 30). The field plate 19 covers part of the gate electrode 18 and also covers part of the drift region 12 (the part of the drift region 12 not covered by the gate electrode 18).

[0043] In the LDMOS device provided by the embodiment of the present invention, a plurality of hole isolation structures 30 are formed in the drift region 12. Compared with the large-area shallow trench isolation structure, the process of the hole isolation structure 30 is easier to implement, thereby reducing the process difficulty. At the same time, the multiple hole isolation structures 30 form a parallel capacitor, which can accumulate more charges to make more carriers, thereby reducing the on-resistance.

[0044] In one embodiment of the present invention, the hole isolation structure 30 includes a high-k material layer 31 covering the sidewalls and bottom of the hole 20 and an insulating material layer 32 filling the hole 30. Exemplarily, the material of the high-k material layer 31 includes hafnium-based oxide, aluminum-based oxide or zirconium-based oxide. Hafnium-based oxide is, for example, hafnium dioxide (HfO 2 ), hafnium silicon oxide (HfSiO) or hafnium silicon oxynitride (HfSiON). Aluminum-based oxide is, for example, aluminum oxide (Al2O 3 ). Zirconium-based oxide is, for example, zirconium dioxide (ZrO 2 ). The material of the high-k material layer 31 may also be titanium oxide (TiO 2 ), tantalum pentoxide (Ta 2 O 5 ), barium strontium titanate (BST), strontium titanate (STO), lead titanate (PZT), etc. The material of the insulating material layer 32 includes silicon dioxide. Of course, the materials of the high-k material layer 31 and the insulating material layer 32 are not limited thereto.

[0045] The high-k material layer 31 is filled on the sidewalls and bottom of the hole 20, and the insulating material layer 32 is filled in the hole 20. The high-k material can introduce an electric field into the insulating material, thereby reducing the electric field and increasing the breakdown voltage.

[0046] Please refer to Figure 1 As shown, the LDMOS device further includes a body region 13 located in the substrate 10. A high-voltage well region 11 is also formed in the substrate 10. The drift region 12 and the body region 13 are located in the high-voltage well region 11. In one embodiment, the doping types of the drift region 12 and the body region 13 are opposite. For example, the substrate 10 is a P-type substrate, the high-voltage well region 11 is a high-voltage N-well, the drift region 12 is an N-type drift region, and the body region 13 is a P-type body region.

[0047] The LDMOS device further includes a source electrode 16 located in the body region 13 and a drain electrode 15 located in the drift region 12. The drain electrode 15 is located on the side of the drift region 12 away from the source electrode 16. The hole isolation structure 30 is located on the side of the drain electrode 15 close to the source electrode 16. A body electrode 17 is also formed in the body region 13. The body electrode 17 is located on the side of the source electrode 16 away from the drain electrode 15. Exemplarily, both the source electrode 16 and the drain electrode 15 are N+ regions, and the body electrode 17 is a P+ region.

[0048] Please refer to Figure 1As shown, the substrate 10 extends in the x direction and the y direction, and a high-voltage well region 11, a drift region 12, a body region 13, a drain 15, a source 16, and a body electrode 17 are sequentially formed in the Z direction. The drain 15, the source 16, and the body electrode 17 extend in the y direction.

[0049] In summary, in the LDMOS device provided by the present invention, a plurality of hole isolation structures 30 are formed in the drift region 12. Compared with a large-area shallow trench isolation structure, the process of the hole isolation structure 30 is easier to implement, thereby reducing the process difficulty. At the same time, the plurality of hole isolation structures 30 form a parallel capacitor, which can accumulate more charges to make more carriers, thereby reducing the on-resistance.

[0050] Further, a high-k material layer 31 is formed on the sidewall and the bottom of the hole 20, and an insulating material layer 32 is filled in the hole 20. The high-k material can introduce an electric field into the insulating material, thereby reducing the electric field and increasing the breakdown voltage.

[0051] Correspondingly, the present invention also provides a manufacturing method of an LDMOS device for manufacturing the LDMOS device as described above. Figure 3 It is a schematic flowchart of a manufacturing method of an LDMOS device provided by an embodiment of the present invention. As Figure 3 shown, the manufacturing method of the LDMOS device includes the following steps:

[0052] S1: Provide a substrate and form a drift region in the substrate;

[0053] S2: Form a plurality of holes in the drift region, and fill an isolation material in the holes to form hole isolation structures;

[0054] S3: Form a gate electrode, and the gate electrode covers at least the hole isolation structures and covers part of the drift region; and

[0055] S4: Form a field plate, and the field plate covers at least part of the gate electrode and the field plate is located above the hole isolation structures.

[0056] Next, the manufacturing method of the LDMOS device provided by the embodiment of the present invention will be described in detail in combination with Figures 1 to 3 In step S1, a substrate 10 is provided, and a drift region 12 is formed in the substrate 10.

[0057] Among them, the material of the substrate 10 may be silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium gallium arsenide, etc., or may be silicon on insulator, germanium on insulator; or may also be other materials, such as III-V group compounds such as gallium arsenide. In this embodiment, the substrate 10 is a silicon substrate.

[0058] ​

[0059] In one embodiment of the present invention, the substrate 10 is a P-type substrate, a high-voltage well region 11 is formed in the substrate 10. The high-voltage well region 11 is, for example, a high-voltage N well. A drift region 12 and a body region 13 are formed in the high-voltage well region 11. The doping types of the drift region 12 and the body region 13 are opposite. The drift region 12 is, for example, an N-type drift region, and the body region 13 is, for example, a P-type body region.

[0060] In step S2, a plurality of holes 20 are formed in the drift region 12, and an isolation material is filled in the holes 20 to form a hole isolation structure 30.

[0061] In one embodiment, please refer to Figure 2 As shown, a plurality of the hole isolation structures 30 are regularly arranged in the row direction and the column direction. The row direction and the column direction refer to Figure 2 the horizontal direction and the vertical direction in Figure 2 and the row direction and the column direction are perpendicular to each other. A plurality of the hole isolation structures 30 regularly arranged in the row direction and the column direction constitute a hole isolation structure matrix. Figure 2 Only three rows and three columns of the hole isolation structure matrix are shown in

[0062] In the manufacturing method of the LDMOS device provided by the embodiment of the present invention, a plurality of hole isolation structures 30 are formed in the drift region 12. Compared with a large-area shallow trench isolation structure, the process of the hole isolation structure 30 is easier to implement, that is, the process difficulty is reduced. At the same time, a plurality of hole isolation structures 30 form a parallel capacitor, which can accumulate more charges to make more carriers, thereby reducing the on-resistance.

[0063] In one embodiment of the present invention, the hole isolation structure 30 includes a high-k material layer 31 covering the sidewalls and the bottom of the hole 20 and an insulating material layer 32 filling the hole 20. Exemplarily, the material of the high-k material layer 31 includes hafnium-based oxides, aluminum-based oxides or zirconium-based oxides. The hafnium-based oxides are, for example, hafnium dioxide (HfO 2 2), hafnium silicon oxide (HfSiO), or hafnium silicon oxynitride (HfSiON). The aluminum-based oxides are, for example, aluminum oxide (Al2O 3 3), and the zirconium-based oxides are, for example, zirconium dioxide (ZrO2 ), the material of the high-k material layer 31 can also be titanium oxide (TiO 2 ), tantalum pentoxide (Ta 2 O 5 ), strontium barium titanate (BST), strontium titanate (STO), lead titanate (PZT), etc. The material of the insulating material layer 32 includes silicon dioxide. Of course, the materials of the high-k material layer 31 and the insulating material layer 32 are not limited to this.

[0064] The high-k material layer 31 is filled on the sidewall and bottom of the hole 20, and the insulating material layer 32 is filled in the hole 20. The high-k material can introduce the electric field into the insulating material, thereby reducing the electric field and increasing the breakdown voltage.

[0065] In an embodiment of the present invention, before or after forming the hole isolation structure 30, a drain 15 can also be formed in the drift region 12, and a source 16 and a body electrode 17 can be formed in the body region 13. The drain 15 is located on a side of the drift region 12 away from the source 16, and the hole isolation structure 30 is located on a side of the drain 15 close to the source 16. The body electrode 17 is located on a side of the source 16 away from the drain 15. Exemplarily, both the source 16 and the drain 15 are N+ regions, and the body electrode 17 is a P+ region.

[0066] In step S3, a gate electrode 18 is formed, and the gate electrode 18 covers at least the hole isolation structure 30 and covers a part of the drift region 12.

[0067] In an embodiment, the gate electrode 18 is located on the high-voltage well region 11 between the source 16 and the drain 15. The gate electrode 18 covers a part of the drift region 12, a part of the body region 13, and a part of the high-voltage well region 11 between the drift region 12 and the body region 13, and the gate electrode 18 covers the hole isolation structure 30. In an embodiment, the gate electrode 18 can cover all of the hole isolation structure 30. In another embodiment, the gate electrode 18 can cover a part of the hole isolation structure 30. The present invention does not limit this.

[0068] In an embodiment, please refer to Figure 2 as shown, the gate electrode 18 includes two parts. The first part of the gate electrode (please refer to the right part of the gate electrode 18 in Figure 2 ) is a block structure, and the first part of the gate electrode covers a part of the drift region 12. The second part of the gate electrode (please refer to the left side of the gate electrode 18 in Figure 2 ) includes a plurality of strip structures extending in the row direction, and each strip structure respectively covers the hole isolation structure 30 arranged in a certain row. For example Figure 2There are 3 rows of hole isolation structures 30 provided therein, and the second part of the gate electrode includes 3 strip-shaped structures, and each strip-shaped structure covers one row of the hole isolation structures 30.

[0069] In step S4, a field plate 19 is formed. The field plate 19 covers at least a part of the gate electrode 18, and the field plate 19 is located above the hole isolation structure 30.

[0070] In one embodiment, please refer to Figure 2 As shown, the field plate 19 includes a plurality of strip-shaped structures extending in the column direction, and each strip-shaped structure is respectively located above the hole isolation structures 30 arranged along a certain column. For example Figure 2 There are 3 columns of hole isolation structures provided therein. The field plate 19 includes 3 strip-shaped structures, and each strip-shaped structure covers one column of the hole isolation structures 30 (of course, the strip-shaped structure actually covers the gate electrode 18, and the gate electrode 18 covered by the strip-shaped structure further covers the hole isolation structure 30).

[0071] In summary, in the LDMOS device and its manufacturing method provided by the present invention, a plurality of hole isolation structures are formed in the drift region. Compared with the large-area shallow trench isolation groove structure, the process of the hole isolation structure is easier to implement, thereby reducing the process difficulty. At the same time, the plurality of hole isolation structures form a parallel capacitor, which can accumulate more charges to make more carriers, thereby reducing the on-resistance.

[0072] Furthermore, a high-k material layer is formed on the sidewall and bottom of the hole, and an insulating material layer is filled in the hole. The high-k material can introduce an electric field into the insulating material, thereby reducing the electric field and increasing the breakdown voltage.

[0073] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the scope of protection of the claims.

Claims

1. An LDMOS device, characterized in that: include: substrate; A drift region is located in the substrate, a plurality of holes are formed in the drift region, and the holes are filled with isolation materials to form a hole isolation structure; A gate electrode, covering at least the hole isolation structure and a portion of the drift region; as well as A field plate covers at least a portion of the gate electrode and is located above the hole isolation structure.

2. The LDMOS device according to claim 1, characterized in that: The plurality of hole isolation structures are regularly arranged in the row direction and the column direction.

3. The LDMOS device according to claim 2, characterized in that: The gate electrode includes two connected parts. The first part of the gate electrode is a block structure covering part of the drift region. The second part of the gate electrode includes a plurality of strip structures extending along the row direction. Each strip structure covers the hole isolation structure arranged along a row.

4. The LDMOS device according to claim 2, characterized in that: The field plate includes a plurality of strip structures extending along a column direction, and each strip structure is located above the hole isolation structure arranged along a certain column.

5. The LDMOS device according to claim 1, characterized in that: The hole isolation structure includes a high-k material layer covering the sidewall and the bottom of the hole and an insulating material layer filling the hole.

6. The LDMOS device according to claim 5, characterized in that: The material of the high-k material layer includes hafnium-based oxide, aluminum-based oxide or zirconium-based oxide.

7. The LDMOS device according to claim 5, characterized in that: The insulating material layer includes silicon dioxide.

8. The LDMOS device according to claim 1, characterized in that: The LDMOS device further includes a body region located in the substrate, a source located in the body region, and a drain located in the drift region. The drain is located on a side of the drift region away from the source, and the hole isolation structure is located on a side of the drain close to the source.

9. The LDMOS device according to claim 8, characterized in that: The drift region and the body region have opposite doping types.

10. A method for manufacturing an LDMOS device, characterized in that: The following steps are involved: providing a substrate, forming a drift region in the substrate; forming a plurality of holes in the drift region, and filling the holes with isolation materials to form a hole isolation structure; forming a gate electrode, wherein the gate electrode at least covers the hole isolation structure and covers a portion of the drift region; as well as A field plate is formed, wherein the field plate at least covers a portion of the gate electrode and is located above the hole isolation structure.

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