Impact-resistant groove device and manufacturing method thereof

Abstract

The invention provides an impact-resistant trench device and a manufacturing method thereof. The device comprises at least one cell located in a first conduction type drift layer, and the cell comprises a conduction unit, an anti-impact unit and an isolation unit. The conduction unit comprises a source electrode region and a channel gate, and the channel gate is adjacent to one side of the source electrode region. The anti-impact unit is located on at least one side of the conduction unit and comprises at least one first anti-impact structure, the first anti-impact structure comprises an anti-impact gate and a second conduction type doped region at least wrapping the bottom of the anti-impact gate, and the anti-impact unit is configured to reduce overvoltage impact of the channel gate in an overvoltage state. And the isolation unit is positioned on one side, far away from the region, of the channel gate, so that one part of the anti-impact unit is electrically isolated from the conduction unit. Due to the fact that the device is provided with the anti-impact unit and the isolation unit, the anti-impact capacity and reliability of the device are effectively improved, and meanwhile the cellular pitch size can be reduced. The manufacturing method is simple in process step and low in cost.

Description

Technical Field

[0001] This application belongs to the technical field of semiconductor devices and manufacturing, and relates to an impact-resistant trench device and a manufacturing method thereof. Background Art

[0002] The third-generation semiconductor silicon carbide material has many advantages, such as a large bandgap width, high thermal conductivity, high breakdown field strength, and high electron saturation velocity, enabling silicon carbide power semiconductor devices to be applied to high-temperature, high-pressure, and high-frequency working environments. Compared with planar devices, trench devices have many advantages, such as better gate oxide quality and higher mobility on the vertical plane, and a smaller size area of a single cell structure, resulting in a higher current density and more chips produced per wafer. For SiC-based devices, the cost per chip can be significantly reduced.

[0003] At present, although SiC trench devices have excellent performance in terms of conduction ability, their impact resistance is relatively weak. Please refer to Figure 1 , Figure 1 , which shows a schematic diagram of the overall structure of an existing SiC trench device. The SiC trench device includes an N-type drift layer 102 located on a substrate 101. A P-type body region 103, an N-type source region 104, a P+ contact region 105, and a trench gate 106 are formed in the N-drift layer 102. In the off state, a high voltage at the drain (e.g., on the side of the substrate 101 away from the N-drift layer 102) acts on the N-type drift layer 102, resulting in a highly concentrated electric field in the bottom corner region of the trench gate 106 ( Figure 1 the region shown as a polygon in 2 ). That is, the trench structure of the SiC trench device greatly reduces the device area and increases the current density. However, at the same time, a high electric field is concentrated at the bottom corner of the trench. When overcurrent or overvoltage occurs, hot electrons damage the oxide layer at the corner, which may lead to parameter degradation and an irreversible increase in the on-resistance. At the same time, since the dielectric constant of SiC is 2.5 times that of SiO 2 , according to Gauss's theorem, the SiO

[0004] layer needs to withstand about 2.5 times the electric field strength of the N-drift layer 102. When the gate dielectric (not labeled) at the bottom of the trench suffers from overvoltage impact or overcurrent impact, the device is extremely likely to fail.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely explaining the technical solutions of this application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art merely because these solutions are described in the background art part of this application. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of this application is to provide an impact-resistant trench device and a manufacturing method thereof, which are used to solve the problem that the impact resistance of trench devices in the prior art needs to be improved.

[0007] To achieve the above purpose and other related purposes, this application provides an impact-resistant trench device, including at least one cell located in a drift layer of a first conductivity type, and the cell includes:

[0008] A conduction unit, including a source region and a channel gate, and the channel gate is adjacent to one side of the source region;

[0009] An impact-resistant unit, located on at least one side of the conduction unit, and the impact-resistant unit includes at least one first impact-resistant structure, and the first impact-resistant structure includes an impact-resistant gate and a doping region of a second conductivity type covering at least the bottom of the impact-resistant gate. The impact-resistant unit is configured to reduce the overvoltage impact on the channel gate in an overvoltage state;

[0010] An isolation unit, located on one side of the conduction unit, so as to electrically isolate a part of the impact-resistant unit from the conduction unit.

[0011] In an optional embodiment, the channel gate includes a first gate and a first gate dielectric, and the first gate dielectric covers the bottom of the first gate and the side of the first gate close to the source region, and the isolation unit is adjacent to the first gate.

[0012] In an optional embodiment, the ratio of the depth of the impact-resistant gate to the depth of the channel gate ranges from 1.5 to 5; the doping depth of the doping region of the second conductivity type is greater than 0.35 μm.

[0013] In an optional embodiment, the impact-resistant unit further includes at least one second impact-resistant structure, and the second impact-resistant structure includes a well region of a second conductivity type and a first metal, and there is a Schottky contact between the first metal and the well region of the second conductivity type. The doping depth of the well region of the second conductivity type is greater than the doping depth of the source region; the impact-resistant unit is further configured to reduce the overcurrent impact on the channel gate in an overcurrent state.

[0014] In an optional embodiment, the doping concentration range of the drift layer of the first conductivity type is 1E14 cm -3~1E17 cm -3 ; The doping concentration range of the second conductivity type well region is 1E18 cm -3 ~5E18 cm -3 ; The doping concentration range of the second conductivity type doping region is 1E17 cm -3 ~1E19 cm -3 .

[0015] In an alternative embodiment, the cell includes one of the first shock-resistant structure and one of the second shock-resistant structure; wherein,

[0016] both the first shock-resistant structure and the second shock-resistant structure are located on a side of the channel gate away from the source region; or, both the first shock-resistant structure and the second shock-resistant structure are located on a side of the source region away from the channel gate; or, the first shock-resistant structure and the second shock-resistant structure are respectively arranged on opposite sides of the on-resistance.

[0017] In an alternative embodiment, the cell includes two of the first shock-resistant structures and two of the second shock-resistant structures; wherein,

[0018] the two first shock-resistant structures are respectively arranged on opposite sides of the conduction unit; the two second shock-resistant structures are located on the same side of one of the first shock-resistant structures; or, the two second shock-resistant structures are respectively located on a side of one of the first shock-resistant structures away from the conduction unit.

[0019] This application also provides a method for manufacturing a shock-resistant trench device, including the following steps of forming at least one cell in a first conductivity type drift layer:

[0020] Forming a conduction unit, the conduction unit includes a source region and a channel gate, the channel gate is located on a side of the source region, and the channel gate is adjacent to the source region;

[0021] Forming a shock-resistant unit, the shock-resistant unit is at least located on a side of the conduction unit, the shock-resistant unit includes at least one first shock-resistant structure, the first shock-resistant structure includes a shock-resistant gate and at least a second conductivity type doping region covering the bottom of the shock-resistant gate, and the shock-resistant unit is configured to reduce the overvoltage impact on the channel gate in an overvoltage state;

[0022] Forming an isolation unit, the isolation unit is located on a side of the conduction unit to isolate the conduction unit from a part of the shock-resistant unit.

[0023] In an alternative embodiment, it includes the following steps:

[0024] Forming a source region.

[0025] A first trench and a second trench are formed, and the first trench and the second trench are respectively arranged on opposite sides of the source region;

[0026] An isolation material layer is formed, and the isolation material layer covers the side wall and at least a part of the bottom wall of the second trench close to the source region;

[0027] The regions of the first trench and the second trench not covered by the isolation material layer are deepened to respectively obtain a third trench;

[0028] A second conductivity type doped region is formed, and the second conductivity type doped region at least covers the bottom of the third trench;

[0029] A part of the isolation material layer is removed to expose a part of the side wall and the bottom wall of the second trench close to the source region, and the remaining part of the isolation material layer constitutes an isolation unit;

[0030] A dielectric material layer and a gate material layer are sequentially formed. The part of the dielectric material layer covering the exposed inner wall of the second trench and the part of the gate material layer filled in the second trench constitute the channel gate, and the part of the dielectric material layer covering the inner wall of the third trench and the part of the gate material layer filled in the third trench constitute the impact-resistant gate.

[0031] In an optional embodiment, forming the second conductivity type doped region includes a first ion implantation and a second ion implantation; wherein, the implantation direction of the first ion implantation is parallel to the depth direction of the third trench, the implantation direction of the first ion implantation is parallel to the depth direction of the third trench, and the implantation direction of the second ion implantation has an included angle α with the depth direction of the third trench, and the included angle α satisfies: 7° < α < (w / d) × 180 / π, where w is the width of the third trench and d is the depth of the third trench.

[0032] As described above, the impact-resistant trench device of the present application includes a channel gate, an impact-resistant unit, and an isolation unit. The first impact-resistant structure in the impact-resistant unit can reduce the overvoltage impact on the trench gate, so as to improve the overvoltage impact resistance and reliability of the device. The isolation unit is used to achieve electrical isolation between the channel gate and the local structure in the impact-resistant unit, and at the same time can reduce the cell pitch size. The second impact-resistant structure in the impact-resistant unit can reduce the overcurrent impact on the channel gate, further improving the reliability of the device. When the isolation unit isolates the first gate of the channel gate and the first impact structure, the setting of the isolation unit also reduces the gate drive capacitance, thereby reducing the dynamic loss of the device and improving the working performance of the device. The manufacturing method of the impact-resistant trench device of the present application can manufacture a trench device with improved impact resistance, and the manufacturing process is simple, the cost is low, and it is suitable for large-scale mass production. Description of the Drawings

[0033] Figure 1 It shows a schematic diagram of the overall structure of an existing SiC trench device;

[0034] Figure 2 It shows a schematic diagram of the structure of an impact-resistant trench device;

[0035] Figure 3 It shows a flowchart of the steps of the manufacturing method of the impact-resistant trench device;

[0036] Figure 4 It shows a schematic diagram of the structure obtained after forming the first trench and the second trench in the manufacturing method of the impact-resistant trench device;

[0037] Figure 5 It shows a schematic diagram of the structure obtained after forming the isolation material layer in the manufacturing method of the impact-resistant trench device;

[0038] Figure 6 It shows a schematic diagram of the structure obtained after forming the third trench in the manufacturing method of the impact-resistant trench device;

[0039] Figure 7 It shows a schematic diagram of the structure obtained after forming the second conductivity type doping region in the manufacturing method of the impact-resistant trench device;

[0040] Figure 8 It shows a schematic diagram of the structure obtained after forming the isolation unit in the manufacturing method of the impact-resistant trench device;

[0041] Figure 9 It shows a schematic diagram of the structure obtained after forming the impact-resistant gate and the channel gate in the manufacturing method of the impact-resistant trench device;

[0042] Description of the Reference Numerals:

[0043] 101 - Substrate, 102 - N - drift layer, 103 - P - type body region, 104 - N - type source region, 105 - P+ contact region, 106 - trench gate;

[0044] 10 - Drift layer of the first conductivity type, 10a - Substrate; 20 - Conducting unit, 21 - Source region, 211 - Body region of the second conductivity type, 212 - Source region, 22 - Channel gate, 22a - Second trench, 221 - First gate, 222 - First gate dielectric;

[0045] 30 - First anti - shock structure, 31 - Anti - shock gate, 31a - First trench, 31b - Third trench, 311 - Second gate, 312 - Second gate dielectric, 32 - Doped region of the second conductivity type; 40 - Second anti - shock structure, 41 - Well region of the second conductivity type, 42 - First metal; 50 - Isolation unit, 50a - Isolation material layer; 60 - Source metal; 70 - Second metal, 80 - Isolation passivation layer. Detailed implementation manners

[0046] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0047] Please refer to Figures 2 to 9 . It should be noted that the drawings provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Therefore, only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0048] Embodiment 1

[0049] This embodiment provides an anti - shock type trench device (hereinafter referred to as "device" for short). Please refer to Figure 2 , Figure 2 . The structure diagram of the device is shown. The device includes at least one cell located in the drift layer 10 of the first conductivity type. The cell includes a conducting unit 20, an anti - shock unit (not labeled), and an isolation unit 50.

[0050] Specifically, the conduction unit 20 includes a source region 21 and a channel gate 22, and the channel gate 22 is adjacent to one side of the source region 21. The shock-resistant unit is located on at least one side of the conduction unit 20, and the shock-resistant unit includes at least one first shock-resistant structure 30. The first shock-resistant structure 30 includes a shock-resistant gate 31 and a second-conductivity-type doped region 32 that at least coats the bottom of the shock-resistant gate 31. The shock-resistant unit is configured to reduce the overvoltage impact on the channel gate 22 in an overvoltage state. The isolation unit 50 is located on one side of the conduction unit 20 to electrically isolate a part of the shock-resistant unit from the conduction unit 20.

[0051] In the embodiment of the present application, during the operation of the device, there is a certain electric field distribution between the channel gate and the shock-resistant gate. When an overvoltage impact occurs, under the action of a high electric field, the electric field intensity in the second-conductivity-type doped region that coats the periphery of the bottom of the shock-resistant gate increases, the internal carriers will be depleted, and the depletion layer will further expand towards the region with a higher electric field intensity, resulting in the expansion of its depletion width towards the channel direction, preferentially and effectively bearing the voltage impact, thereby avoiding the channel gate region from bearing too high an electric field intensity, and thus protecting the channel gate from overvoltage impact.

[0052] In some embodiments, the ratio range of the depth of the shock-resistant gate 31 to the depth of the channel gate 22 is 1.5 to 5 (including the end values). For example, the ratio of the depth of the shock-resistant gate 31 to the depth of the channel gate 22 can be 2.0, 2.5, or 3.0. As Figure 2 shown, the doping depth d1 of the second-conductivity-type doped region 32 is greater than 0.35 μm. For example, the doping depth d1 of the second-conductivity-type doped region 32 can be 0.38 μm, 0.4 μm, or 0.42 μm.

[0053] In the embodiment of the present application, if the depth of the shock-resistant gate is less than 1.5 times the depth of the channel gate, the depletion range of the second-conductivity-type doped region that at least coats the bottom of the shock-resistant gate in the horizontal direction will be limited and cannot be fully depleted, resulting in that under an overvoltage impact, its depletion state cannot form an effective electric field shielding for the gate oxide region, and the gate oxide region may be directly exposed to a high electric field, and the effective reduction of the overvoltage impact on the trench gate cannot be achieved. As the depth of the shock-resistant gate increases, the complexity and difficulty of the manufacturing process will both increase significantly, and the process difficulty of forming the second-conductivity-type doped region by ion implantation based on the shock-resistant gate will also increase significantly. In addition to higher performance requirements for the implantation equipment, problems such as uneven implantation and increased defects may also occur, affecting the consistency and reliability of the device. Therefore, the depth of the shock-resistant gate is preferably within 2.5 times the depth of the channel gate, which is optimal in terms of the overvoltage impact protection effect on the channel gate, device consistency, and cost.

[0054] In some embodiments, as Figure 2 shown, the source region 21 includes a body region 211 of a second conductivity type and a source region 212, and the source region 212 is located in the body region 211 of the second conductivity type. Further, the source region 212 includes a source region of the second conductivity type (not labeled) and a source region of the first conductivity type (not labeled), and the source region of the first conductivity type is used to reduce the contact resistance between the subsequent source metal 60 (or ohmic contact metal) and the source region 21, and improve the conduction performance.

[0055] In some embodiments, as Figure 2 shown, the channel gate 22 includes a first gate 221 and a first gate dielectric 222. The first gate dielectric 222 covers the bottom of the first gate 221 and the side of the first gate 221 close to the source region 21. The isolation unit 50 is adjacent to the first gate 221 to electrically isolate the first gate 221 from the structure on the side of the first gate 221 away from the source region 21 based on the isolation unit 50, avoiding electrical interference from surrounding structures to the first gate 221 and affecting the normal operation of the channel gate 22. That is, the channel gate 22 forms a channel in the region adjacent to the source region 21 to achieve conduction between the source and the drain. And on the side of the channel gate 22 away from the source region 21, there is no need to form a source region 21, that is, in the traditional structure, the source regions 21 on both sides of the trench gate are symmetrically structured (for example, as Figure 1 shown), in the embodiments of the present application, a source region 21 is only formed on one side of the channel gate 22 to jointly form a conduction unit, and a first anti-impact structure 30 (or the second anti-impact structure 40 described later) in the anti-impact unit is provided on the other side of the channel gate 22, and the channel gate 22 and the local structure of the anti-impact unit are separated by the isolation unit 50, so that the isolation unit 50 can be arranged in the area of the saved source region 21, and the area of the isolation unit 50 relative to the source region 21 is significantly reduced, reducing the overall cell pitch.

[0056] In some embodiments, the anti-impact gate 31 includes a second gate 311 and a second gate dielectric 312. The second gate dielectric 312 covers the bottom surface and the side surface of the second gate 311. The materials of the first gate 221 and the second gate 311 both include polysilicon, the materials of the first gate dielectric 222 and the second gate dielectric 312 both include silicon dioxide, and the material of the isolation unit 50 includes at least one of silicon dioxide and silicon nitride.

[0057] In some embodiments, the impact-resistant unit further includes at least one second impact-resistant structure 40, and the second impact-resistant structure 40 includes a second-conductivity-type well region 41 and a first metal 42. There is a Schottky contact between the first metal 42 and the second-conductivity-type well region 41. The doping depth of the second-conductivity-type well region 41 is greater than the doping depth of the source region 21 (that is, the doping depth of the second-conductivity-type well region 41 is greater than the doping depth of the second-conductivity-type body region 211). At this time, the impact-resistant unit is further configured to reduce the overcurrent impact on the channel gate 22 in an overcurrent state. Herein, to avoid ambiguity, an "overvoltage state" refers to a working state where the voltage across the two ends of the device exceeds its rated maximum voltage value, and an "overcurrent state" refers to a working state where the current flowing through the device exceeds its rated maximum current value.

[0058] In some embodiments, the first metal 42 includes at least one of Au, Ti, Mo, Pt, Ni, Pd, and W, and can be a single metal layer, a multi-metal stack, or a multi-metal composite layer.

[0059] Specifically, there is a Schottky contact between the second-conductivity-type well region and the first metal in the second impact-resistant structure, and then, in combination with the first-conductivity-type drift region, an MPS diode is formed. The MPS diode has a high surge capacity. When an overcurrent impact occurs, the Schottky contact region (i.e., the region where the second-conductivity-type well region contacts the first metal) can quickly conduct in response to the overcurrent impact due to its low forward conduction voltage, forming a low-impedance current path, such that most of the current will be shunted through the Schottky contact region and will not flow through the channel gate region. In this way, the current impact on the channel gate is greatly reduced, thereby protecting the channel gate from the influence of the overcurrent impact.

[0060] In some embodiments, the doping concentration range of the first-conductivity-type drift layer 10 is 1E14 cm -3 ~1E17 cm -3 (including the end values). For example, the doping concentration of the first-conductivity-type drift layer 10 can be 1E15 cm -3 or 1E16 cm -3 . The doping concentration range of the second-conductivity-type doping region 32 is 1E17 cm -3 ~1E19 cm -3 (including the end values). For example, the doping concentration of the second-conductivity-type doping region 32 can be 5E17 cm -3 , 1E18 cm -3 or 5E18 cm -3The doping concentration of the second-conductivity-type doped region 32 is higher than that of the first-conductivity-type drift layer 10. During an overvoltage impact, the depletion width of the second-conductivity-type doped region 32 can promptly expand towards the channel direction, preferentially bear the voltage impact, and ensure that the depletion width can be fully expanded during the depletion process to bear the voltage impact. The doping concentration range of the second-conductivity-type well region 41 is 1E18 cm -3 ~5E18 cm -3 (including the endpoint values). For example, the doping concentration of the second-conductivity-type well region 41 can be 2E18cm -3 、3E18cm -3 or 4E18cm -3 . In the embodiments of the present application, when the doping concentration of the second-conductivity-type well region 41 is within the above range, it can ensure that during an overcurrent impact, the MPS diode can be quickly turned on and form a current path with low impedance, and at the same time avoid the influence of too high doping concentration on the reverse breakdown voltage ability of the Schottky contact.

[0061] In some embodiments, as Figure 2 shown, the cell includes two of the first impact-resistant structures 30 and two of the second impact-resistant structures 40. Among them, the two first impact-resistant structures 30 are arranged on opposite sides of the conduction unit 20; the two second impact-resistant structures 40 are located on the same side of one of the first impact-resistant structures 30. Alternatively, the two second impact-resistant structures 40 are respectively located on the side of one of the first impact-resistant structures 30 away from the conduction unit 20 (that is, each side of one of the first impact-resistant structures 30 away from the conduction unit 20 has one of the second impact-resistant structures 40). In the device, the distance d2 between any two adjacent second impact-resistant structures 40 is less than or equal to 1 μm. For example, it can be 0.5 μm. In the case where the second impact-resistant structure 40 only includes the second-conductivity-type well region 41, that is, the distance between any two adjacent second-conductivity-type well regions 41 is less than or equal to 1 μm, where any two adjacent second-conductivity-type well regions 41 can be located in a single cell or in two adjacent cells.

[0062] In some other embodiments, the cell includes the first impact-resistant structure 30 and the second impact-resistant structure 40. Among them, both the first impact-resistant structure 30 and the second impact-resistant structure 40 are located on the side of the channel gate 22 away from the source region 21. Alternatively, both the first impact-resistant structure 30 and the second impact-resistant structure 40 are located on the side of the source region 21 away from the channel gate 22. Alternatively, the first impact-resistant structure 30 and the second impact-resistant structure 40 are arranged on opposite sides of the on-resistance. That is, on the premise of meeting the good protection effect of the impact-resistant unit on the channel gate 22, the specific structure of the impact-resistant unit, for example, the number of the first impact-resistant structures 30 included in the impact-resistant unit, the number of the second impact-resistant structures 40, and the arrangement manner of the first impact-resistant structure 30 and the second impact-resistant structure 40, etc., can be adjusted according to actual needs.

[0063] In an alternative embodiment, the first conduction type is N-type and the second conduction type is P-type. That is, the device includes an N-type drift layer, a P-type body region, a P-type well region, etc. In other embodiments, the first conduction type is P-type and the second conduction type is N-type.

[0064] In an alternative embodiment, the device further includes a second metal 70, an isolation passivation layer 80, a source metal 60, and a gate metal. The isolation passivation layer 80 is located on the first conduction type drift layer. The first metal 42 penetrates through the isolation passivation layer 80 to be electrically connected to the second conduction type well region 41. The second metal 70 penetrates through the isolation passivation layer 80 to be electrically connected to the source region 212. The source metal 60 and the gate metal are both located on the isolation passivation layer 80 and are electrically isolated from each other. The source metal 60 is electrically connected to the second metal 70, the first metal 42, and the second gate 311. The gate metal is electrically connected to the first gate 221.

[0065] The impact-resistant trench device according to the embodiment of the present application includes a channel gate, an impact-resistant unit, and an isolation unit. The first impact-resistant structure in the impact-resistant unit can reduce the overvoltage impact on the trench gate to improve the overvoltage impact resistance and reliability of the device. The isolation unit is used to achieve electrical isolation between the channel gate and the local structure in the impact-resistant unit, and at the same time, it can reduce the cell pitch size. The second impact-resistant structure in the impact-resistant unit can reduce the overcurrent impact on the channel gate, thereby further improving the reliability of the device. When the isolation unit isolates the first gate of the channel gate from the first impact-resistant structure, the setting of the isolation unit also reduces the gate drive capacitance, thereby reducing the dynamic loss of the device and improving the working performance of the device.

[0066] Embodiment 2

[0067] The present application also provides a manufacturing method for an impact-resistant trench device. This manufacturing method can manufacture the device described above or other suitable devices. Please refer to Figure 3 , Figure 3 . FIG. Figure 3 shows a flowchart of the steps of this manufacturing method. This manufacturing method includes the following steps S1 to S3 of forming at least one cell in a drift layer of a first conductivity type.

[0068] S1: Form a conducting unit, the conducting unit includes a source region and a channel gate, the channel gate is located on one side of the source region, and the channel gate is adjacent to the source region;

[0069] S2: Form an impact-resistant unit, the impact-resistant unit is at least located on one side of the conducting unit, the impact-resistant unit includes at least one first impact-resistant structure, the first impact-resistant structure includes an impact-resistant gate and a doping region of a second conductivity type that at least coats the bottom of the impact-resistant gate, and the impact-resistant unit is configured to reduce the overvoltage impact on the channel gate in an overvoltage state;

[0070] S3: Form an isolation unit, the isolation unit is located on one side of the conducting unit to isolate the conducting unit from a part of the impact-resistant unit.

[0071] Next, please refer to Figures 2 to 9 together. An exemplary introduction to the manufacturing method of this device is given in the embodiments of the present application.

[0072] First, as Figure 4 shown, provide a substrate 10a, and form a drift layer 10 of a first conductivity type on the substrate 10a.

[0073] In an optional embodiment, the material of the substrate 10a includes SiC, and the doping concentration range of the substrate 10a is 1E18 cm -3 ~ 1E20 cm -3 . The drift layer 10 of the first conductivity type can be formed by epitaxial growth, and the doping concentration range of the first conductivity type doping layer 10 is 1E14 cm -3 ~ 1E17 cm -3 , and the thickness range of the first conductivity type doping layer 10 is 3 μm to 5 μm. Before forming the drift layer 10 of the first conductivity type, a step of forming a buffer layer (not shown) may also be included, and the thickness range of the buffer layer is 1 μm to 2 μm.

[0074] In an optional embodiment, steps S1 to S3 include the following steps:

[0075] As Figure 4As shown, a source region 21 is formed. The source region 21 includes a body region 211 of a second conductivity type and a source region 212. The source region 212 is located in the body region 211 of the second conductivity type. The source region 212 may further include a source region 212 of the second conductivity type and a source region 212 of the first conductivity type. For example, a mask layer (not shown) is formed on the drift layer 10 of the first conductivity type, and the mask layer is patterned. Ion implantation is performed based on the patterned mask layer to form structures such as the body region 211 of the second conductivity type, the source region of the second conductivity type, and the source region of the first conductivity type. Among them, the material of the mask layer includes silicon dioxide, and the thickness of the mask layer is 2 μm to 4 μm. For ion implantation of different conductivity types, different mask layers need to be formed, and the mask layer formed in the previous step is removed before the next ion implantation.

[0076] In an alternative embodiment, the manufacturing method further includes a step of forming at least one well region 41 of the second conductivity type. The well region 41 of the second conductivity type and the first metal formed subsequently constitute a second impact structure. The well region 41 of the second conductivity type is formed based on multiple steps of ion implantation. For example, 3 steps or 4 steps, and the temperature range of ion implantation is 500 °C to 700 °C (including the end values), which can be 550 °C, 600 °C, or 650 °C.

[0077] As Figure 4 shown, a first trench 31a and a second trench 22a are formed. The first trench 31a and the second trench 22a are respectively located on opposite sides of the source region 21. For example, a first etching mask layer (e.g., silicon dioxide formed by CVD method) is formed on the drift layer of the first conductivity type, and the first etching mask layer is patterned (e.g., lithographic etching patterning). Etching (e.g., ICP etching) is performed based on the patterned first etching mask layer to obtain the first trench 31a and the second trench 22a.

[0078] In an alternative embodiment, the width range of the first trench 31a is 0.2 μm to 2 μm (including the end values), which can be 0.6 μm, 1 μm, or 1.5 μm. The width range of the second trench 22a is 0.4 μm to 4 μm (including the end values), which can be 1.5 μm, 2.0 μm, or 3.0 μm. The depth range of the first trench 31a and the second trench 22a is 1 μm to 4 μm (including the end values), which can be 2 μm, 2.5 μm, or 3 μm.

[0079] As Figure 5As shown, an isolation material layer 50a is formed, and the isolation material layer 50a covers the sidewalls and at least a part of the bottom wall of the second trench 22a close to the source region 21. For example, a second etching mask layer (not shown) is formed and patterned, and the isolation material layer 50a is formed by lift-off lithography and HDP method. The material of the isolation material layer 50a includes silicon dioxide.

[0080] As Figure 6 shown, the regions of the first trench 31a and the second trench 22a not covered by the isolation material layer 50a are deepened to obtain a third trench 31b respectively. That is, one third trench 31b is obtained by deepening the first trench 31a, and the other third trench 31b is obtained by locally deepening the second trench 22a. For example, a third etching mask layer (not shown) is formed and patterned to obtain the third trench 31b based on the patterned third etching mask layer.

[0081] As Figure 7 shown, a second conductivity type doped region 32 is formed, and the second conductivity type doped region 32 at least covers the bottom of the third trench 31b. For example, an implantation mask layer (not shown) is formed and patterned, and ion implantation is performed based on the patterned implantation mask layer to form the second conductivity type doped region 32. When the second conductivity type is P type, the doping ions of the second conductivity type doped region 32 include Al ions or other suitable ions.

[0082] In an alternative embodiment, forming the second conductivity type doped region 32 includes a first ion implantation and a second ion implantation; wherein, the implantation direction of the first ion implantation is parallel to the depth direction of the third trench 31b ( Figure 7 the direction indicated by the center dotted line), that is, vertical implantation. The implantation direction of the second ion implantation has an angle α with the depth direction of the third trench, and the angle α satisfies: 7° < α < (w / d) × 180 / π, where w is the width of the third trench and d is the depth of the third trench. For example, after the first ion implantation and the second ion implantation, the photoresist and the implantation mask layer are removed and cleaned (e.g., RCA cleaning); then, a graphite layer (not shown) is formed for high-temperature annealing to activate the impurity ions in the second conductivity type doped region 32. The thickness of the graphite layer is 10 nm to 100 nm, the temperature of the high-temperature annealing is greater than 1600 °C, and the annealing time is greater than 3 min. Then, the graphite layer is removed by plasma etching (e.g., O 2 2, N 2 2 plasma etching) or thermal oxidation method.

[0083] As Figure 8As shown, a part of the isolation material layer 50a is removed to expose a part of the side wall and the bottom wall of the second trench 22a close to the source region 21, and the remaining part of the isolation material layer 50a constitutes the isolation unit 50. That is, the isolation material layer 50a is selectively etched to remove the part of the isolation material layer 50a on the side close to the source region 21, and the part far from the source region 21 is retained as the isolation unit 50. For example, after removing a part of the isolation material layer 50a, a cleaning and sacrificial oxidation step is also performed, that is, the exposed side wall of the third trench 31b is oxidized by thermal oxidation to form a thermal oxide layer (not shown), and then removed by the BOE method.

[0084] As Figure 9 shown, a dielectric material layer (not labeled) and a gate material layer (not labeled) are sequentially formed. The part of the dielectric material layer covering the exposed inner wall of the second trench 22a (i.e., the first gate dielectric 222) and the part of the gate material layer filling the second trench 22a (i.e., the first gate 221) constitute the channel gate 22. The part of the dielectric material layer covering the inner wall of the third trench 31b (i.e., the second gate dielectric 312) and the part of the gate material layer filling the third trench 31b (i.e., the second gate 311) constitute the impact-resistant gate 31. When the dielectric material layer is formed by thermal oxidation (performed in an O 2 atmosphere), an annealing step is also included after forming the dielectric material layer (for example, annealing in an NO or N 2 O or POCl 3 atmosphere). The thickness range of the dielectric material layer is 10 nm to 100 nm, and the thermal oxidation temperature range is 1200 °C to 1500 °C. The material of the gate material layer includes polysilicon. For example, a polysilicon material layer (not labeled) is formed to fill the regions in the third trench 31b and the second trench 22a that are not filled by the first gate dielectric, and the polysilicon material layer is planarized to obtain the gate material layer. A step of doping and annealing the polysilicon material layer may also be included to form doped polysilicon.

[0085] In an alternative embodiment, as Figure 2 shown, after forming the channel gate 22 and the impact-resistant gate 31, the following steps are also included:

[0086] An isolation passivation layer 80 is formed. For example, a SiO 2 or SiO x N y layer deposited by the CVD method is used as the isolation passivation layer 80, and the thickness range of the isolation passivation layer 80 is 0.5 μm to 1 μm.

[0087] A first contact hole (not labeled) is formed in the isolation passivation layer 80, and at least a part of the source region 212 is exposed by the first contact hole;

[0088] A second metal 70 (i.e., source ohmic contact metal) is formed in the first contact hole (and on the side of the substrate away from the first conductive type drift layer), and rapid thermal annealing is carried out in a vacuum or inert atmosphere to form a source ohmic contact (and a drain ohmic contact). For example, the ohmic contact metal includes Ni or Ti / Ni. The annealing temperature range of the rapid thermal annealing is between 900 °C and 1100 °C, and the time range is 0.5 min to 30 min.

[0089] A second contact hole (not labeled) is formed in the isolation passivation layer 80, and at least a part of the second conductive type well region 41 is exposed by the second contact hole (the second contact hole exposes at least a part of two adjacent second conductive type well regions 41 at the same time);

[0090] A first metal 42 (i.e., Schottky contact metal) is formed in the second contact hole, and rapid thermal annealing is carried out in a vacuum or inert atmosphere to form a Schottky contact between the first metal 42 and the second conductive type well region 41, so as to form a second impact structure 40, and further form an MPS diode. For example, the annealing temperature range of the rapid thermal annealing is 400 °C to 600 °C, and the time range is 5 - 30 minutes, and it is carried out in a nitrogen protection atmosphere.

[0091] A source electrode metal 60, a gate metal (not labeled), and a drain metal (not labeled) are formed. The source electrode metal 60 and the gate metal are both located on the isolation passivation layer 80, and the two are electrically isolated. The source electrode metal 60 is electrically connected to the second metal 70, the first metal 42, and the second gate 311, and the gate metal is electrically connected to the first gate 221;

[0092] A passivation layer (not shown) is formed above the source electrode metal 60 and the gate metal, and a source electrode window (not shown) and a gate window (not shown) are formed in the passivation layer. The source electrode window exposes at least a part of the source electrode metal 60, the gate window exposes at least a part of the gate metal, and the material of the passivation layer includes at least one of silicon dioxide, silicon nitride (Si3N4), and a polyimide layer.

[0093] The manufacturing method of the impact-resistant trench device according to the embodiment of the present application can manufacture a trench device with improved impact resistance, and the manufacturing process is simple, the cost is low, and it is suitable for large-scale mass production.

[0094] In summary, the anti-impact trench device of the present application includes a channel gate, an anti-impact unit, and an isolation unit. The first anti-impact structure in the anti-impact unit can reduce the overvoltage impact on the trench gate, so as to improve the overvoltage impact resistance and reliability of the device. The isolation unit is used to achieve electrical isolation between the channel gate and the local structure in the anti-impact unit, and at the same time can reduce the cell pitch size. The second anti-impact structure in the anti-impact unit can reduce the overcurrent impact on the channel gate, further improving the reliability of the device. When the isolation unit isolates the first gate of the channel gate and the first impact structure, the setting of the isolation unit also reduces the gate drive capacitance, thereby reducing the dynamic loss of the device and improving the working performance of the device. The manufacturing method of the anti-impact trench device of the present application can manufacture a trench device with improved anti-impact performance, and the manufacturing process is simple, the cost is low, and it is suitable for large-scale mass production. Therefore, the present application effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0095] The above embodiments are only illustrative of the principles and effects of the present application, and are not used to limit the present application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present application should still be covered by the claims of the present application.

Claims

1. A shock-resistant trench device, characterized in that: The method comprises at least one cell located in a first conductive type drift layer, wherein the cell comprises: A conduction unit, comprising a source region and a channel gate, wherein the channel gate is adjacent to one side of the source region; An anti-shock unit is located at least on one side of the conduction unit, the anti-shock unit includes at least one first anti-shock structure, the first anti-shock structure includes an anti-shock gate and a second conductive type doping region at least covering the bottom of the anti-shock gate, and the anti-shock unit is configured to reduce the overvoltage shock of the channel gate in an overvoltage state; The isolation unit is located at one side of the conducting unit to electrically isolate a part of the anti-shock unit from the conducting unit.

2. The impact-resistant trench device according to claim 1, characterized in that: The channel gate includes a first gate and a first gate dielectric, the first gate dielectric covers the bottom of the first gate and a side of the first gate close to the source region, and the isolation unit is adjacent to the first gate.

3. The impact-resistant trench device according to claim 1, characterized in that: The ratio of the depth of the anti-shock gate to the depth of the trench gate is in the range of 1.5 to 5; and the doping depth of the second conductive type doping region is greater than 0.35 μm.

4. The impact-resistant trench device according to any one of claims 1 to 3, characterized in that: The anti-shock unit also includes at least one second anti-shock structure, the second anti-shock structure includes a second conductive type well region and a first metal, a Schottky contact is formed between the first metal and the second conductive type well region, and the doping depth of the second conductive type well region is greater than the doping depth of the source region; the anti-shock unit is also configured to reduce the overcurrent impact of the channel gate in an overcurrent state.

5. The impact-resistant trench device according to claim 4, characterized in that: The doping concentration range of the first conductive type drift layer is 1E14cm -3 ~1E17cm -3 The doping concentration range of the second conductivity type well region is 1E18cm -3 ~5E18 cm -3 The doping concentration range of the second conductive type doping region is 1E17cm -3 ~1E19cm -3 .

6. The impact-resistant trench device according to claim 4, characterized in that: The cell includes a first impact-resistant structure and a second impact-resistant structure; wherein, The first anti-shock structure and the second anti-shock structure are both located on a side of the channel gate away from the source region; or, the first anti-shock structure and the second anti-shock structure are both located on a side of the source region away from the channel gate; or, the first anti-shock structure and the second anti-shock structure are arranged on opposite sides of the on-resistance.

7. The impact-resistant trench device according to claim 4, characterized in that: The cell includes two of the first impact-resistant structures and two of the second impact-resistant structures; wherein, The two first impact-resistant structures are arranged on opposite sides of the conduction unit; the two second impact-resistant structures are located on the same side of the first impact-resistant structure; or the two second impact-resistant structures are respectively located on one side of the first impact-resistant structure away from the conduction unit.

8. A method for manufacturing a shock-resistant groove device, characterized in that: The following steps are performed to form at least one cell in the first conductivity type drift layer: forming a conduction unit, the conduction unit comprising a source region and a channel gate, the channel gate being located at one side of the source region, and the channel gate being adjacent to the source region; forming an anti-shock unit, the anti-shock unit being at least located on one side of the conduction unit, the anti-shock unit comprising at least one first anti-shock structure, the first anti-shock structure comprising an anti-shock gate and a second conductive type doping region at least covering the bottom of the anti-shock gate, the anti-shock unit being configured to reduce the overvoltage shock of the channel gate in an overvoltage state; An isolation unit is formed, and the isolation unit is located at one side of the conducting unit to isolate the conducting unit from a portion of the anti-shock unit.

9. The method for manufacturing a shock-resistant trench device according to claim 8, characterized in that: The following steps are involved: forming a source region; forming a first trench and a second trench, wherein the first trench and the second trench are arranged at opposite sides of the source region; forming an isolation material layer, wherein the isolation material layer covers the sidewalls and at least a portion of the bottom wall of the second trench close to the source region; Deepening the first trench and the second trench in the area not covered by the isolation material layer to obtain a third trench respectively; forming a second conductive type doped region, wherein the second conductive type doped region at least covers a bottom of the third trench; removing a portion of the isolation material layer to expose a portion of the sidewall and bottom wall of the second trench close to the source region, wherein the remaining portion of the isolation material layer constitutes an isolation unit; A dielectric material layer and a gate material layer are formed in sequence, wherein the dielectric material layer covers the exposed inner wall portion of the second trench and the gate material layer fills the second trench to form the trench gate, and the dielectric material layer covers the inner wall portion of the third trench and the gate material layer fills the third trench to form the anti-shock gate.

10. The method for manufacturing a shock-resistant trench device according to claim 9, characterized in that: Forming the second conductive type doping region includes first ion implantation and second ion implantation; wherein, The injection direction of the first ion implantation is parallel to the depth direction of the third groove, and there is an angle α between the injection direction of the second ion implantation and the depth direction of the third groove, and the angle α satisfies: 7°<α<(w / d)×180 / π, wherein w is the width of the third groove and d is the depth of the third groove.

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