Semiconductor structure and memory chip

Abstract

The invention discloses a semiconductor structure and a memory chip. The semiconductor structure comprises a first well region; the first active region is positioned in the first well region and extends along a first direction; the second active region is located in the first well region and extends in the first direction, and in the second direction, the first active region is closer to the side edge of the first well region relative to the second active region; the grid electrode is positioned on the first well region and is in contact with the first active region and the second active region; wherein in the first direction, the grid electrode has a first length on the first active region, the grid electrode has a second length on the second active region, and the first length is smaller than the second length. The semiconductor structure is good in performance.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a memory chip. Background Art

[0002] In the layout of a DRAM (Dynamic Random Access Memory), it includes a memory cell region (Array), a sense amplifier (SA), and a word line driver (SWD). Among them, the word line driver is mainly responsible for providing a driving voltage for the word line of the memory to turn on. The word line driver consists of a huge number of repeated driving units, and there are a large number of transistors in the driving units. The performance of some transistors does not match, resulting in low reliability of the device. Summary of the Invention

[0003] According to a first aspect of the embodiments of the present disclosure, a semiconductor structure is provided, including: A first well region; A first active region, located in the first well region and extending along a first direction; A second active region, located in the first well region and extending along the first direction. In a second direction, the first active region is closer to the side edge of the first well region than the second active region; A gate, located on the first well region and in contact with the first active region and the second active region; Wherein, in the first direction, the gate has a first length on the first active region and a second length on the second active region, and the first length is less than the second length.

[0004] In some embodiments, in the second direction, the gate has a first width on the first active region and a second width on the second active region, and the second width is equal to the first width.

[0005] In some embodiments, in the second direction, the gate has a first width on the first active region and a second width on the second active region, and the second width is less than the first width.

[0006] In some embodiments, the first active region includes an extension portion, the second active region includes a recessed portion, the extension portion is embedded in the recessed portion, and in the second direction, the width of the extension portion is greater than the width of the recessed portion.

[0007] In some embodiments, a second well region is further included. In the second direction, the second well region is located on both sides of the first well region, where the ion doping type of the second well region is different from that of the first well region.

[0008] In some embodiments, there is also a mixed well region between the first well region and the second well region, and the mixed well region includes the ion doping type of the first well region and the ion doping type of the second well region.

[0009] In some embodiments, the mixed well region is the overlapping region of the first well region and the second well region.

[0010] In some embodiments, the gate further includes a first protrusion, and the first protrusion is located outside the first active region, where, in the first direction, the length of the first protrusion is greater than the first length.

[0011] In some embodiments, the gate further includes a second protrusion, and the second protrusion is located between the first active region and the second active region, where, in the first direction, the length of the second protrusion is greater than the second length.

[0012] In some embodiments, in the first direction, the first protrusion protrudes beyond the edge of the first active region, and the second protrusion protrudes beyond the edge of the first active region.

[0013] In some embodiments, in the first direction, the length of the first protrusion is equal to the length of the second protrusion.

[0014] In some embodiments, the gate includes a first gate and a second gate, and the first gate and the second gate are arranged in parallel on the first active region and the second active region.

[0015] In some embodiments, the first protrusion on the first gate and the first protrusion on the second gate extend in opposite directions, and the second protrusion on the first gate and the second protrusion on the second gate extend in opposite directions.

[0016] In some embodiments, the gate and the first active region form a first transistor, the gate and the second active region form a second transistor, the first transistor and the second transistor are transistors of the same type, the first length is the channel length of the first transistor, the second length is the channel length of the second transistor, the first width is the channel width of the first transistor, and the second width is the channel width of the second transistor.

[0017] According to a second aspect of the embodiments of the present disclosure, a storage chip is provided, including the semiconductor structure described above.

[0018] In summary, the embodiments of the present disclosure propose a semiconductor structure and a storage chip. The semiconductor structure includes a first active region and a second active region, and a gate is located on the first active region and the second active region, so that a first transistor and a second transistor can be formed respectively. At the same time, since the first active region is closer to the side edge of the first well region than the second active region, that is, the first transistor is closer to the side edge of the first well region. At the same time, in the first direction, the length of the gate on the first active region is less than the length of the gate on the second active region, that is, the channel length of the first transistor is smaller. Reducing the channel length can increase the driving current of the transistor, thereby improving the driving ability of the first transistor, so that the driving ability of the first transistor matches the driving ability of the second transistor, and further reducing the impact on the reliability of the device. Description of the Drawings

[0019] Figure 1 is a circuit diagram of a driving unit shown according to an exemplary embodiment; Figure 2 is a schematic diagram of a semiconductor structure shown according to an exemplary embodiment; Figure 3 is another schematic diagram of a semiconductor structure shown according to an exemplary embodiment; Figure 4 is shown according to an exemplary embodiment Figure 3 a cross-sectional view in the AA direction; Figure 5 is another schematic diagram of a semiconductor structure shown according to an exemplary embodiment; Figure 6 is another schematic diagram of a semiconductor structure shown according to an exemplary embodiment; Figure 7 is a schematic diagram of the first active region and the second active region shown according to an exemplary embodiment; Figure 8 is a cross-sectional view of the first active region and the second active region shown according to an exemplary embodiment; Figure 9 is another schematic diagram of a semiconductor structure shown according to an exemplary embodiment; Figure 10 is shown according to an exemplary embodiment Figure 9 a cross-sectional view in the BB direction; Figure 11 is another schematic diagram of a semiconductor structure shown according to an exemplary embodiment; Figure 12 is a schematic diagram of a storage chip shown according to an exemplary embodiment. Detailed implementation manners

[0020] The technical solutions of the present disclosure will be further elaborated in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners set forth herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0021] The present disclosure will be described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present disclosure will be more apparent according to the following description and claims. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0022] It can be understood that the meanings of "on...", "above...", and "over..." in the present disclosure should be interpreted in the broadest manner, so that "on..." not only means "on" something and there is no intervening feature or layer therebetween (i.e., directly on something), but also includes the meaning of being "on" something and there are intervening features or layers therebetween.

[0023] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and do not necessarily need to be used to describe a specific order or sequence.

[0024] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including a region having a thickness. The layer can extend over the entire underlying or overlying structure, or can have a scope smaller than the scope of the underlying or overlying structure. In addition, the layer can be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0025] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0026] In a Dynamic Random Access Memory (DRAM), the opening and closing of memory cells are controlled by word lines, and the control of DRAM word lines is achieved through a Sub Wordline Driver (SWD). As the chip technology node advances, there is an increasing requirement for miniaturization of device dimensions. At the same time, due to the huge number of driving units and transistors, some transistors are closer to the side edges of the well region, resulting in performance mismatches among transistors.

[0027] As Figure 1 shown, Figure 1 it is a circuit diagram of a driving unit of a word line driver. The driving unit may include a first NMOS transistor N1, a second NMOS transistor N2, and a PMOS transistor P1. The drain of the PMOS transistor P1 is connected to the word line WL and is used to drive the memory array connected to the word line WL. The source of the PMOS transistor P1 receives the word line selection signal PXID. The gate of the PMOS transistor P1 receives the word line turn-on voltage MWLB and uses the word line turn-on voltage MWLB as the control voltage of its gate, and controls whether the word line is turned on by controlling whether the word line selection signal PXID passes through.

[0028] As Figure 1 shown, the gate of the first NMOS transistor N1 receives the word line turn-on voltage MWLB and uses the word line turn-on voltage MWLB as the control voltage of its gate. The drain of the first NMOS transistor N1 is connected to the word line WL, and the source of the first NMOS transistor N1 is grounded to VSS. The word line WL can be grounded to VSS through the drain and source of the first NMOS transistor N1, thereby controlling the word line WL to be turned off. The gate of the second NMOS transistor N2 receives the word line selection complementary signal PXIB. The drain of the second NMOS transistor N2 is connected to the word line WL. The source of the second NMOS transistor N2 is grounded to VSS. The word line WL can be grounded to VSS through the drain and source of the second NMOS transistor N2, thereby controlling the word line WL to be turned off. If the word line WL is to be turned on, the word line turn-on voltage MWLB needs to be a low-level signal, the word line selection signal PXID needs to be a high-level signal, and the word line selection complementary signal PXIB needs to be a low-level signal. In this case, the PMOS transistor P1 is turned on, the first NMOS transistor N1 and the second NMOS transistor N2 are turned off, and the word line WL is turned on.

[0029] As Figure 1As shown, the driving unit of the word line driver includes a PMOS and a pair of NMOSs, that is, a 2N1P structure. This pair of NMOSs are located on both sides of the PMOS. The applicant has found through research that there is a difference in the driving capabilities of the transistors in the PMOS that are close to the NMOS and those that are far from the NMOS, which in turn leads to low reliability of the device. The applicant further studies and finds that when the PMOS is formed, more ions are doped in the active region close to the NMOS, and fewer ions are doped in the active region far from the NMOS, which leads to a difference in the driving capabilities of these two transistors.

[0030] Given that the size of the memory device is increasingly tending towards miniaturization, the applicant improves the channel lengths of these two transistors, thereby reducing the difference in the driving capabilities of these two transistors, while also ensuring the miniaturization of the memory device.

[0031] As Figure 2 As shown, an embodiment of the present disclosure provides a semiconductor structure 100, which may include a first well region 101, in which there are a first active region 103 and a second active region 104. The first active region 103 and the second active region 104 may be separated by an isolation structure. The first active region 103 and the second active region 104 may extend along a first direction (X direction), and the first active region 103 and the second active region 104 may be arranged along a second direction (Y direction). The first active region 103 and the second active region 104 may have the same structure. The first active region 103 and the second active region 104, for example, have a regular structure. In the second direction, the side edge of the first active region 103 close to the first well region 101, and the side edge of the second active region 104 far from the first well region 101, that is, the first active region 103 is closer to the side edge of the first well region 101 relative to the second active region 104.

[0032] As Figure 2As shown, there is also a gate 105 in the first well region 101. The gate 105 can be located on the first active region 103 and the second active region 104, that is, the gate 105 is in contact with both the first active region 103 and the second active region 104. The gate 105 can extend along the second direction, so that the gate 105 can extend to the outside of the first active region 103 and the second active region 104. In the first direction, since the gate 105 has a certain length, the gate 105 has a first length L1 in the first active region 103 and a second length L2 on the second active region 104, and the first length L1 can be less than the second length L2. In the embodiments of the present disclosure, the gate 105 can be divided into two parts. The first part is, for example, located on the first active region 103, and the second part is, for example, located on the second active region 104. The length of the first part in the first direction is the first length L1, and the length of the second part in the first direction is the second length L2. The first length L1 of the first part changes between the first active region 103 and the second active region 104 to the second length L2 of the second part, thereby realizing that the same gate 105 has different lengths on the first active region 103 and the second active region 104.

[0033] As Figure 2As shown, in the embodiment of the present disclosure, the first active region 103 and the second active region 104 are formed prior to the first well region 101. That is, the first active region 103 and the second active region 104 can be first formed in the substrate, and then the substrate is ion-doped to form the first well region 101, and at the same time, the first active region 103 and the second active region 104 can be located in the first well region 101. The first well region 101 is, for example, an N-type well region (Nwell). At this time, the doping ions of the first well region 101 are N-type, such as one or several of phosphorus ions, arsenic ions, and antimony ions. Since in the second direction, the first active region 103 is closer to the side edge of the first well region 101 than the second active region 104, when performing N-type ion doping, the ion doping concentration in the first active region 103 will be greater than that in the second active region 104. At this time, if in the first direction, the lengths of the gate 105 in the first active region 103 and the second active region 104 are the same, that is, the channel length of the first transistor (formed by the gate 105 and the first active region 103) is equal to the channel length of the second transistor (formed by the gate 105 and the second active region 104), the driving ability of the first transistor is worse than that of the second transistor at this time. In this embodiment, due to the well proximity effect, the driving ability of the first transistor is less than that of the second transistor, that is, there is a performance difference between these two transistors. In this embodiment, the first length L1 of the gate 105 on the first active region 103 is less than the second length L2 of the gate 105 on the second active region 104, so that the channel length of the first transistor becomes smaller. According to the transistor turn-on power formula, reducing the channel length will increase the driving current of the transistor, and thus can improve the driving ability of the first transistor, so as to better match the driving ability of the second transistor, reduce the performance difference between the two transistors, and thus improve the reliability of the device.

[0034] As Figure 2 shown, in the embodiment of the present disclosure, the first direction (X direction) is the direction of the channel length of the transistor generated based on the first active region 103 or the second active region 104, and the second direction (Y direction) is the direction of the channel width of the transistor generated based on the first active region 103 or the second active region 104.

[0035] As Figure 3 shown, the embodiment of the present disclosure provides a semiconductor structure 100, which may include a first well region 101 and a second well region 102. The second well region 102 is located on both sides of the first well region 101. The ion doping types of the first well region 101 and the second well region 102 are different. The first well region 101 is used to form PMOS, and the second well region 102 is used to form NMOS. The first well region 101 can be doped with various dopants such as phosphorus, silicon, germanium, selenium, sulfur, and / or tellurium, and the second well region 102 can be doped with dopants such as boron, beryllium, strontium, barium, zinc, and / or magnesium.

[0036] As Figure 3 shown, in the first well region 101, there are a first active region 103 and a second active region 104. The first active region 103 and the second active region 104 are arranged in an orderly manner according to a rule. The first active region 103 and the second active region 104 extend along a first direction (X direction), and the first active region 103 and the second active region 104 are arranged along a second direction (Y direction). In the second direction, the first active region 103 is closer to the side edge of the first well region 101 than the first active region 104, that is, the first active region 103 is closer to the second well region 102 than the second active region 104. The arrangement of the first active region 103 and the second active region 104 is different from Figure 2 the arrangement of the first active region 103 and the second active region 104 in Figures 2 - 3 which both the first active region 103 and the second active region 104 extend along the first direction, and in the second direction, the first active region 103 is closer to the side edge of the first well region 101 than the second active region 104. The first active region 103 and the second active region 104 can have the same structure. For example, in the first direction, the first active region 103 and the second active region 104 have the same length.

[0037] As Figure 3 shown, on the first well region 101, there is a gate 105, and the gate 105 can be in contact with the first active region 103 and the second active region 104. In the first direction, the gate 105 has a first length L1 on the first active region 103, and the gate 105 has a second length L2 on the second active region 104, and the first length L1 is less than the second length L2. The gate 105 extends along the second direction. The gate 105 can be divided into two parts. The first part is located on the first active region 103, and the first part has a first length L1 on the first active region 103. The second part is located on the second active region 104, and the second part has a second length L2 on the second active region 104. The first part and the second part extend along the second direction and are joined between the first active region 103 and the second active region 104, thereby forming the gate 105. In this embodiment, the gate 105 can be polysilicon.

[0038] As Figures 3 - 4 shown, Figure 4 is Figure 3Cross-sectional view in the AA direction. The first active region 103 and the second active region 104 are both formed in the substrate. The substrate is, for example, a bulk material such as silicon (Si, such as single-crystalline silicon, polycrystalline silicon, or amorphous silicon), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), etc.; it can also be a composite structural material such as silicon-on-insulator (SOI), germanium-on-insulator (GOI), germanium-silicon-on-insulator, or silicon-carbon-on-insulator, or other materials such as group III-V compounds like gallium arsenide. Another example is a composite structural material such as silicon-on-insulator (SOI), germanium-on-insulator (GOI), germanium-silicon-on-insulator, or silicon-carbon-on-insulator. In this embodiment, the first active region 103 and the second active region 104 are formed prior to the first well region 101 and the second well region 102. After forming the first active region 103 and the second active region 104, the second well region 102 is formed, and then the first well region 101 is formed. After forming the second well region 102, a mask layer is formed on the second well region 102, and then ion doping is performed to form the first well region 101. However, during the process of forming the first well region 101, since the first active region 103 is closer to the side edge of the first well region 101, that is, the first active region 103 is closer to the second well region 102, during the ion doping process, due to the certain thickness of the mask layer, the ion doping process is uneven, resulting in more ions being doped in the first active region 103, that is, the ion doping concentration in the first active region 103 is greater than the ion doping concentration in the second active region 104. Therefore, if the lengths of the gate 105 on the first active region 103 and the second active region 104 are the same, it will cause a large difference in the driving capabilities of the first transistor (formed by the gate 105 and the first active region 103) and the second transistor (formed by the gate 105 and the second active region 104), that is, the driving capabilities of the two do not match, and further result in low reliability of the device.

[0039] As Figure 3 shown, in the embodiment of the present disclosure, the gate 105 has a first length L1 on the first active region 103, and the gate 105 has a second length L2 on the second active region 104. The first length L1 is less than the second length L2, that is, the channel length of the first transistor (formed by the gate 105 and the first active region 103) is less than the channel length of the second transistor (formed by the gate 105 and the second active region 104). That is, the channel length of the first transistor is reduced, and thus the driving capability of the first transistor can be improved, so as to better match the driving capability of the second transistor, thereby improving the reliability of the device.

[0040] As Figures 3 - 4As shown, in some embodiments, the ion doping concentration in the second active region 104 can also be increased, for example, by a multiple doping process to increase the ion doping concentration in the second active region 104, thereby enabling the driving capability of the first transistor to match that of the second transistor. However, the multiple doping process is relatively complex. In this embodiment, by reducing the channel length of the first transistor, the driving capability of the first transistor is increased, enabling the driving capability of the first transistor to match that of the second transistor. The process of this embodiment is relatively simple.

[0041] As Figure 5 shown, in the semiconductor structure 100, the first active region 103 and the second active region 104 can have the same structure or shape. Figure 5 In it, the first active region 103 and the second active region 104 can have the same length in the first direction. The first active region 103 and the second active region 104 can have the same width in the second direction. For example, the first active region 103 can have a first width W1 in the second direction, and the second active region 104 can have a second width W2 in the second direction. The first width W1 can be equal to the second width W2. Thus, in the second direction (Y direction), the gate 105 has a first width W1 over the first active region 103 and a second width W2 over the second active region 104, and the first width W1 can be equal to the second width W2. At the same time, in the first direction (X direction), the gate 105 has a first length L1 over the first active region 103 and a second length L2 over the second active region 104, and the first length L1 can be less than the second length L2. Since the gate 105 and the first active region 103 can form a first transistor (PMOS), and the gate 105 and the second active region 104 can form a second transistor (PMOS), at this time, the channel length of the first transistor is less than that of the second transistor, and the channel width of the first transistor is equal to that of the second transistor. When the channel width of the PMOS transistor increases, the driving capability of this PMOS transistor can be improved. In this embodiment, the channel width of the first transistor is made equal to that of the second transistor, so that the driving capability of the first transistor can match that of the second transistor. At the same time, by reducing the channel length of the first transistor, the first transistor can further match the driving capability of the second transistor, thereby improving the reliability of the device. If the channel width of the second transistor is further increased, the driving capability of the second transistor will be further improved. Although the driving capability of the first transistor is increased by reducing its channel length, the driving capability of the second transistor is improved by increasing the channel width, making the driving capabilities of the first transistor and the second transistor still unmatched. Therefore, the channel width of the second transistor cannot be greater than that of the first transistor.

[0042] As Figure 5 shown, the first active region 103, the second active region 104, and the gate 105 are all located in the first well region 101, and there are second well regions 102 on both sides of the first well region 101. The first well region 101 can be an N-type well region (NWELL), the second well region 102 can be a P-type well region (PWELL), and the first well region 101 and the second well region 102 are doped with different ion types. The first well region 101 can be used to form PMOS, and the second well region 102 can be used to form NMOS. In the second direction, the first active region 103 is closer to the side edge of the first well region 101 than the second active region 104, that is, the first active region 103 is closer to the second well region 102. The gate 105 extends from the first active region 103 to the second active region 104, and thus the first transistor and the second transistor can be formed. In this embodiment, the first direction (X direction) can be the direction of the channel length of the transistor, and the second direction (Y direction) can be the direction of the channel width of the transistor.

[0043] As Figure 3 and Figure 5 shown, there are two gates 105 on the first active region 103 and the second active region 104. These two gates 105 are arranged in parallel, and the structures of these two gates 105 can be the same. Since in the first direction, the first length L1 is less than the second length L2, the gap between these two gates 105 on the first active region 103 is larger, and the gap between these two gates 105 on the second active region 104 is smaller.

[0044] As Figure 6 shown, in the semiconductor structure 100, the first active region 103 is rectangular, and the second active region 104 is rectangular. In the first direction (X direction), the first active region 103 and the second active region 104 have the same length. In the second direction (Y direction), the first active region 103 has a first width W1, the second active region 104 has a second width, and the second width W2 can be less than the first width W1. At the same time, in the second direction, the first active region 103 is closer to the side edge of the first well region 101 than the second active region 104, that is, the first active region 103 is closer to the second well region 102 than the second active region 104. During the formation of the first well region 101, the first active region 103 is doped with more ions than the second active region 104, that is, the ion doping concentration in the first active region 103 is higher. There is a gate 105 on the first well region 101, and the gate 105 extends along the second direction, and thus extends from the first active region 103 to the second active region 104. At the same time, in the first direction, the length of the gate 105 on the first active region 103 is less than the length of the gate 105 on the second active region 104 (please refer to Figure 5). The gate 105 and the first active region 103 form the first transistor 107, and the gate 105 and the second active region 104 form the second transistor 108. The first transistor 107 and the second transistor 108 are transistors of the same type, for example, both are PMOS transistors. In the first direction, the length of the gate 105 on the first active region 103 can be the channel length of the first transistor 107, and the length of the gate 105 on the second active region 104 can be the channel length of the second transistor 108. In the second direction, the width of the gate 105 on the first active region 103 (the first width W1) can be the channel width of the first transistor 107, and the width of the gate 106 on the second active region 104 (the second width W2) can be the channel width of the second transistor 108.

[0045] As Figure 6 shown, in this embodiment, the ion doping concentration of the first active region 103 is greater than that of the second active region 104. The channel length of the first transistor 107 is less than that of the second transistor 108, thereby improving the driving ability of the first transistor 107, and further enabling the driving ability of the first transistor 107 to match that of the second transistor 108. At the same time, the channel width of the first transistor 107 is greater than that of the second transistor 108, thereby further improving the driving ability of the first transistor 107, and further enabling the driving ability of the first transistor 107 to match that of the second transistor 108, thereby improving the reliability of the device.

[0046] As Figures 6 - 7 shown, in Figure 6 , both the first active region 103 and the second active region 104 are regular rectangular shapes. In Figure 7 , the first active region 103 can be a regular rectangular shape, and the second active region 104 can be an irregular shape. For example, a groove is dug out from the regular first active region 103, so that the second active region 104 can have a smaller second width W2, so that the first width W1 of the first active region 103 is greater than the second width W2 of the second active region 104. The gate 105 also contacts the first active region 103 and the second active region 104. The width of the gate 105 on the first active region 103 is the first width W1, and the width of the gate 105 on the second active region 104 is the second width W2. At this time, the second width W1 is less than the first width W1, thereby improving the driving ability of the first transistor 107, and further enabling the driving ability of the first transistor 107 to match that of the second transistor 108.

[0047] As Figure 8As shown in the figure, embodiments of the present disclosure also disclose another structure of the first active region 103 and the second active region 104. The first active region 103 includes an extension portion 1031, and the second active region 104 includes a recessed portion 1041. The extension portion 1031 can extend onto the recessed portion 1041. However, in the second direction, the width D1 of the extension portion 1031 can be greater than the width D2 of the recessed portion 1041. Therefore, when the gate 105 is located on the first active region 103 and the second active region 104, when the gate 105 extends from the extension portion 1031 to the second active region 104, the width of the gate 105 on the first active region 103 can be greater than the width of the gate 105 on the second active region 104, thereby enabling the driving capability of the first transistor to match the driving capability of the second transistor and improving the reliability of the device.

[0048] As Figure 9 As shown in the figure, embodiments of the present disclosure also propose a semiconductor structure 100, which includes a first well region 101, a second well region 102, and a mixed well region 106. There are a first active region 103 and a second active region 104 in the first well region 101. There is a gate 105 on the first active region 103 and the second active region 104. In the first direction (X direction), the gate 105 has a first length L1 on the first active region 103, and the gate 105 has a second length L2 on the second active region 104. The first length L1 can be less than the second length L2. In the second direction (Y direction), the width of the gate 105 on the first active region 103 can be equal to the width of the gate 105 on the second active region 104. The gate 105 and the first active region 103 form a first transistor 107, and the gate 105 and the second active region 104 form a second transistor 108. The channel length of the first transistor 107 is the first length L1, and the channel length of the second transistor 108 is the second length L2. At this time, the channel length of the first transistor 107 is less than the trench length of the second transistor 108. The channel width of the first transistor 107 can be equal to the channel width of the second transistor 108. Of course, if the width of the gate 105 on the first active region 103 can be greater than the width of the gate 105 on the second active region 104, at this time, the channel width of the first transistor 107 is greater than the channel width of the second transistor 108.

[0049] As Figures 9 - 10 shown Figure 10 For Figure 9Cross-sectional view in the BB direction. The second well region 102 is located on both sides of the first well region 101. The first well region 101 can be an N-type well region, and the second well region 102 can be a P-type well region. There is also a mixed well region 106 between the first well region 101 and the second well region 102. In this embodiment, the second well region 102 can be formed first, and then while forming the first well region 101, doping ions are doped into the second well region 102, thereby forming the mixed well region 106. The mixed well region 106 can include P-type ions and N-type ions. The first well region 101 is used to form PMOS, for example, and the second well region 102 is used to form NMOS, for example. In Figure 10 this structure, due to the existence of the mixed well region 106, it is equivalent to the extension of the first well region 101 into the second well region 102, so that the distance from the first active region 103 to the side edge of the first well region 101 becomes larger. Therefore, when ion doping is performed on the first well region 101, less ions can be doped into the first active region 103, so that the ion doping concentrations in the first active region 103 and the second active region 104 are more balanced, thereby reducing the difference in the driving capabilities of the first transistor 107 and the second transistor 108.

[0050] As Figures 9 - 10 shown, due to the existence of the mixed well region 106, the difference in ion concentrations in the first active region 103 and the second active region 104 is reduced. At the same time, the channel length of the first transistor 107 is less than the channel length of the second transistor 108, which can further improve the driving capability of the first transistor 107, so that the driving capability of the first transistor 107 can match the driving capability of the second transistor 108, thereby improving the reliability of the device.

[0051] As Figure 11 shown, an embodiment of the present disclosure also proposes a semiconductor structure 100, which can include a first well region 101 and a second well region 102. The second well region 102 is located on both sides of the first well region 101. The first well region 101 can be used to form PMOS, and the second well region 102 can be used to form NMOS. The descriptions of the first well region 101 and the second well region 102 can refer to the above descriptions. Of course, the first well region 101 and the second well region 102 can also have a mixed well region 106 ( Figure 9 shown).

[0052] As Figure 11As shown, there are a first active region 103 and a second active region 104 in the first well region 101. In the first direction (X direction), the first active region 103 and the second active region 104 are arranged in parallel. In the second direction (Y direction), the first active region 103 and the second active region 104 are arranged at intervals, and the first active region 103 is closer to the side edge of the first well region 101 than the second active region 104, and this side edge is the edge where the first well region 101 contacts the second well region 102. Since the first active region is closer to the second well region 102, the ion doping concentration in the first active region 103 is higher than that in the second active region 104.

[0053] As Figure 11 shown, there is a first gate 1051 and a second gate 1052 in the first well region 101, and the first gate 1051 and the second gate 1052 constitute the gate 105. The structures of the first gate 1051 and the second gate 1051 are the same. The first gate 1051 and the second gate 1051 are arranged in parallel. In some embodiments, the first gate 1051 and the second gate 1052 can also be defined as the gate 105, that is, there can be multiple gates 105 in the first well region 101. Both the first gate 1051 and the second gate 1052 are in contact with the first active region 103 and the second active region 104. In this embodiment, the second gate 1052 is taken as an example for description. In the first direction (X direction), the length of the second gate 1052 on the first active region 103 is less than the length of the second gate 1052 on the second active region 104, so that the channel length of the first transistor is less than that of the second transistor, thereby improving the driving ability of the first transistor, reducing the difference in the driving abilities of the first transistor and the second transistor, and improving the reliability of the device. In the second direction (Y direction), the width of the second gate 1052 on the first active region 103 can be equal to the width of the second gate 1052 on the second active region 104, so that the channel width of the first transistor can be equal to the channel width of the second transistor. If the channel width of the second transistor is large, the driving ability of the second transistor will be further improved, and thus the difference in the driving abilities of the first transistor and the second transistor will be further increased. In the embodiment, the channel width of the first transistor is equal to the channel width of the second transistor, which can ensure that the difference in the driving abilities of the first transistor and the second transistor is not increased, that is, it can ensure that by reducing the channel length of the first transistor, the difference in the driving abilities of the first transistor and the second transistor is reduced.

[0054] As Figure 11As shown, the second gate 1052 further includes a first protrusion 109 and a second protrusion 110. The first protrusion 109 is located outside the first active region 103, and the second protrusion 110 is located between the first active region 103 and the second active region 104. The first protrusion 109 and the second protrusion 110 extend along a first direction, and in the first direction, both the first protrusion 109 and the second protrusion 110 protrude beyond the lower edge of the first active region 103. In the first direction, the length of the first protrusion 109 is greater than the length of the second gate 1052 on the first active region 103 (the first length L1). At the same time, the length of the second protrusion 110 is greater than the length of the second gate 1052 on the second active region 104 (the second length L2). The first protrusion 109 on the first gate 1051 extends in the positive direction of the first direction, and the first protrusion 109 on the second gate 1052 extends in the opposite direction of the first direction. The second protrusion 110 on the first gate 1051 extends in the positive direction of the first direction, and the second protrusion 110 on the second gate 1052 extends in the opposite direction of the first direction, thereby leaving sufficient space between the first gate 1051 and the second gate 1052, which is beneficial to forming a contact plug in this space.

[0055] As Figure 11 shown, both the first protrusion 109 and the second protrusion 110 are located outside the first active region 103 and the second active region 104. The first protrusion 109 and the second protrusion 110 do not increase the channel length of the first transistor, thereby ensuring that the first transistor has good driving ability. At the same time, in the first direction, both the first protrusion 109 and the second protrusion 110 have a relatively large length, and the lengths of the two can be the same. The first protrusion 109 and the second protrusion 110 can also improve the reliability of the second gate 1052, compensate for the degradation of the turn-off characteristics of the transistor caused by the electron accumulation generated by the trench isolation structure capturing hot electrons resulting in the hot electron induced punch-through effect, and thereby improve the performance of the semiconductor structure.

[0056] As Figure 12As shown, an embodiment of the present disclosure provides a storage chip 10, which may include a word line driving region 11 and a storage region 12. The word line driving region 11 may include the above semiconductor structure. The storage chip 10 is, for example, a volatile memory semiconductor chip (such as a dynamic random access memory (DRAM) or a static random access memory (SRAM)) or a non-volatile memory semiconductor chip (such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM)). According to some exemplary embodiments, the storage chip 10 may be a flash memory, for example, a NAND flash memory. The storage chip 10 may be applied in an electronic device, which may include one or more of the following: for example, a smart phone, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MPEG-1 audio layer 3 (MP3) player, a mobile medical device, a camera, a household appliance, a medical device, an Internet of Things (IoT) device, and a wearable device. The wearable device may be of an accessory type, a fabric or clothing type, a body-attached type, or an implantable circuit type. The accessory-type wearable device may be, for example, a watch, a ring, a bracelet, an ankle chain, a necklace, glasses, contact lenses, or a head-mounted device (HMD). The storage chip 10 may also be applied in a large server, such as a data center, an AI computer, and other fields. The storage chip 10 may also be applied in a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, and / or a drone.

[0057] In summary, an embodiment of the present disclosure provides a semiconductor structure and a storage chip. The semiconductor structure includes a first active region and a second active region, and a gate is located on the first active region and the second active region, so that a first transistor and a second transistor can be formed respectively. At the same time, since the first active region is closer to the side edge of the first well region than the second active region, that is, the first transistor is closer to the side edge of the first well region. At the same time, in the first direction, the length of the gate on the first active region is less than the length of the gate on the second active region, that is, the channel length of the first transistor is smaller, so that the driving ability of the first transistor can be improved, so that the driving ability of the first transistor matches the driving ability of the second transistor, thereby reducing the impact on the reliability of the device.

[0058] As described above, it is only the specific implementation manner of the present disclosure. However, the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: a first well region; A first active region, located in the first well region and extending along a first direction; a second active region, located in the first well region and extending along the first direction, wherein in a second direction, the first active region is closer to a side edge of the first well region than the second active region; a gate, located on the first well region and contacting the first active region and the second active region; In the first direction, the gate has a first length on the first active region, the gate has a second length on the second active region, and the first length is smaller than the second length.

2. The semiconductor structure according to claim 1, characterized in that: In the second direction, the gate has a first width on the first active region, and the gate has a second width on the second active region, and the second width is equal to the first width.

3. The semiconductor structure according to claim 1, characterized in that: In the second direction, the gate has a first width on the first active region, and the gate has a second width on the second active region, and the second width is smaller than the first width.

4. The semiconductor structure according to claim 3, characterized in that: The first active region includes an extension portion, and the second active region includes a recessed portion, the extension portion is embedded in the recessed portion, and in the second direction, a width of the extension portion is greater than a width of the recessed portion.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: It also includes a second well region, which is located at both sides of the first well region in the second direction, wherein the ion doping type of the second well region is different from the ion doping type of the first well region.

6. The semiconductor structure according to claim 5, characterized in that: There is also a mixed well region between the first well region and the second well region, and the mixed well region includes the ion doping type of the first well region and the ion doping type of the second well region.

7. The semiconductor structure according to claim 6, characterized in that: The mixed well region is an overlapping region of the first well region and the second well region.

8. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The gate further includes a first protrusion, which is located outside the first active region, wherein in the first direction, a length of the first protrusion is greater than the first length.

9. The semiconductor structure according to claim 8, characterized in that: The gate further includes a second protrusion located between the first active region and the second active region, wherein in the first direction, a length of the second protrusion is greater than the second length.

10. The semiconductor structure according to claim 9, characterized in that: In the first direction, the first protrusion protrudes from an edge of the first active region, and the second protrusion protrudes from an edge of the first active region.

11. The semiconductor structure according to claim 9, characterized in that: In the first direction, the length of the first protrusion is equal to the length of the second protrusion.

12. The semiconductor structure according to claim 8, characterized in that The gate includes a first gate and a second gate, and the first gate and the second gate are arranged in parallel on the first active region and the second active region.

13. The semiconductor structure according to claim 12, characterized in that: The first protrusion on the first grid and the first protrusion on the second grid extend in opposite directions, and the second protrusion on the first grid and the second protrusion on the second grid extend in opposite directions.

14. The semiconductor structure according to any one of claims 2 to 4, characterized in that: The gate and the first active area form a first transistor, the gate and the second active area form a second transistor, the first transistor and the second transistor are transistors of the same type, the first length is the channel length of the first transistor, the second length is the channel length of the second transistor, the first width is the channel width of the first transistor, and the second width is the channel width of the second transistor.

15. A memory chip, characterized in that: Comprising the semiconductor structure described in any one of claims 1-14.

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