Molybdenum disulfide-based transistor PUF preparation method

Abstract

The invention discloses a molybdenum disulfide-based transistor PUF preparation method, which comprises the following steps: pretreating the surface of a silicon oxide substrate, and removing natural organic matters and other impurities on the surface of the silicon oxide substrate; based on liquid-liquid interface self-assembly, molybdenum disulfide ink forms a continuous and non-uniform molybdenum disulfide film on a silicon oxide substrate; performing patterning treatment on the surface of the molybdenum disulfide film to obtain patterns of source and drain electrodes; and depositing a titanium thin film and a palladium thin film on the silicon oxide substrate covered with the molybdenum disulfide thin film, and completing patterning of a source electrode and a drain electrode to obtain the molybdenum disulfide transistor PUF array. The method is applied to the fields of information security and chip encryption, has good attack resistance and high uniqueness, and can effectively improve the security protection performance of the electronic equipment.

Description

Technical Field

[0001] The present invention relates to the fields of information security and chip encryption technology, and particularly to a preparation method of a transistor PUF based on molybdenum disulfide. Background Art

[0002] Physical Unclonable Function (PUF) technology captures the inherent randomness characteristics generated by material defects, process deviations, and thermal fluctuations at the microscale of semiconductor devices to construct an encryption mechanism with a unique fingerprint. The response characteristics of such devices are strongly related to the physical implementation path. Even in the face of atomic-level precision reverse engineering attacks, attackers cannot reproduce the same output-input mapping relationship, thus providing fundamental security for chip-level security. Compared with the traditional cryptography defense method that relies on mathematical problems, PUF technology roots security in the principle of non-clonability in the physical world and realizes a security paradigm of "once manufactured, bound for life".

[0003] In the field of information security, PUF has been successfully applied to key generation for Internet of Things devices, identity authentication in Trusted Execution Environments (TEEs), and hardware anchoring of blockchain nodes. Its dynamic response characteristics enable unique authentication vectors to be generated for each access, effectively resisting side-channel attacks and replay attacks. The latest research shows that PUF chips based on FinFET technology can achieve an integration density of more than 1×10 6 random entropy sources per square millimeter on a 300mm wafer, with a bit error rate lower than 1×10 -6 order of magnitude.

[0004] However, as Moore's Law approaches the physical limit, silicon-based PUF faces multiple technical bottlenecks: the reliability degradation caused by the quantum tunneling effect in process nodes below 7nm, the local heat accumulation problem caused by the three-dimensional FinFET structure, and the exponential growth of manufacturing costs brought about by the improvement of lithography accuracy. Experimental data shows that when the process is scaled down to 5nm, the entropy value of silicon-based SRAM PUF decreases by about 37% compared with the 28nm process, and the device yield loss increases to 12%. These challenges urgently require breaking through the limitations of material dimensions. Summary of the Invention

[0005] Aiming at the deficiencies in the above-mentioned prior art, the present invention provides a preparation method of a transistor PUF based on molybdenum disulfide, which can not only overcome the limitations of traditional silicon materials, but also significantly enhance the response uniqueness, stability, and attack defense ability of the PUF, thereby providing an efficient and energy-saving hardware security protection scheme, and providing new ideas and directions for the development of new hardware security devices and their applications in fields such as the Internet of Things and embedded systems.

[0006] To achieve the above object, the present invention provides a preparation method of a transistor PUF based on molybdenum disulfide, including the following steps: Step 1, pretreat the surface of the silicon oxide substrate to remove natural organic matter and other impurities on its surface; Step 2, based on liquid-liquid interface self-assembly, form a continuous and uneven molybdenum disulfide thin film on the silicon oxide substrate with molybdenum disulfide ink; Step 3, perform patterning treatment on the surface of the molybdenum disulfide thin film to obtain the pattern of source and drain electrodes; Step 4, deposit a titanium thin film and a palladium thin film on the silicon oxide substrate covered with the molybdenum disulfide thin film to complete the patterning of the source and drain electrodes, and obtain a molybdenum disulfide transistor PUF array.

[0007] In one embodiment, in Step 2, based on liquid-liquid interface self-assembly, form the molybdenum disulfide thin film on the silicon oxide substrate at least twice, so as to form a continuous and uneven molybdenum disulfide thin film on the silicon oxide substrate.

[0008] In one embodiment, Step 2 specifically includes: Step 201, after placing the silicon oxide substrate on a customized lifting rack, put the lifting rack into a glass petri dish, then add deionized water and n-hexane. When an obvious layered interface appears in the glass petri dish, for the first time, use a pipette to slowly and continuously drip molybdenum disulfide ink in the glass petri dish. After a stable thin film is formed, extract the lifting rack to make the molybdenum disulfide thin film spread flat on the silicon oxide substrate, and place the silicon oxide substrate on a heating table for heat treatment to ensure that the liquid is completely evaporated, so as to form the first layer of molybdenum disulfide thin film on the sample surface; Step 202, after placing the sample obtained in Step 201 on the lifting rack again, put the lifting rack into a glass petri dish, then add deionized water and n-hexane. When an obvious layered interface appears in the glass petri dish, for the second time, use a pipette to slowly and continuously drip molybdenum disulfide ink in the glass petri dish. After a stable thin film is formed, extract the lifting rack to make the molybdenum disulfide thin film spread flat on the sample, and place the sample on a heating table for heat treatment to ensure that the liquid is completely evaporated, so as to form the second layer of molybdenum disulfide thin film on the sample surface; Step 203, after placing the sample obtained in Step 202 on the lifting rack again, put the lifting rack into a glass petri dish, then add deionized water and n-hexane. When an obvious layered interface appears in the glass petri dish, for the third time, use a pipette to slowly and continuously drip molybdenum disulfide ink in the glass petri dish. After a stable thin film is formed, extract the lifting rack to make the molybdenum disulfide thin film spread flat on the sample, and place the sample on a heating table for heat treatment to ensure that the liquid is completely evaporated, so as to form the third layer of molybdenum disulfide thin film on the sample surface.

[0009] In one embodiment, in Step 201, when dripping molybdenum disulfide ink in the glass petri dish for the first time, drip it at the middle position of the glass petri dish; In step 202, when the molybdenum disulfide ink is dropped onto the glass petri dish for the second time, it is dropped at the upper left corner of the glass petri dish; In step 203, when the molybdenum disulfide ink is dropped onto the glass petri dish for the third time, it is dropped at the lower right corner of the glass petri dish.

[0010] In one embodiment, in step 3, patterning is performed by electron beam lithography, ultraviolet lithography, extreme ultraviolet lithography or nanoimprinting.

[0011] In one embodiment, in step 4, the process of depositing a titanium film and a palladium film on the silicon oxide substrate covered with the molybdenum disulfide film is as follows: First, deposit 10 nm of metallic titanium at a rate of 0.01 nm / s, and then deposit 50 nm of metallic palladium at a rate of 0.05 nm / s.

[0012] Compared with the prior art, the present invention has the following beneficial technical effects: 1. The present invention prepares a transistor PUF array based on molybdenum disulfide. By forming a continuous and uneven molybdenum disulfide film during the array preparation process, the drain current Id of the transistor is distributed between 0.1 and 1 mA and is different when the gate voltage is -100 V, showing a large difference, demonstrating excellent performance and high stability, and is expected to play an important role in fields such as chip encryption and information security protection; 2. The molybdenum disulfide film prepared by the present invention has a significantly improved density compared with the commonly used spin coating, spraying, and drop coating methods, with a porosity of only about 10%, and the uneven stacking of nanosheets can improve the uniqueness and unpredictability of the PUF; 3. The process of the present invention is simple, requires low experimental equipment, and can prepare array devices in large quantities at room temperature. Description of the Drawings

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0014] Figure 1 It is a flowchart of the method for preparing a transistor PUF based on molybdenum disulfide in an embodiment of the present invention; Figure 2 It is a design diagram of the source-drain electrode pattern in an embodiment of the present invention; Figure 3 It is an optical schematic diagram of the transistor channel in an embodiment of the present invention; Figure 4Raman characterization diagram of molybdenum disulfide thin film on 300nm silicon oxide substrate in the embodiment of the present invention; Figure 5 AFM characterization diagram of molybdenum disulfide thin film on 300nm silicon oxide substrate in the embodiment of the present invention; Figure 6 SEM characterization diagram of molybdenum disulfide thin film on 300nm silicon oxide substrate in the embodiment of the present invention; Figure 7 Test diagram of transfer characteristic curve of transistor array in the embodiment of the present invention.

[0015] The realization, functional characteristics and advantages of the object of the present invention will be further described in conjunction with the embodiments with reference to the accompanying drawings. Detailed implementation manners

[0016] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0017] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement it. When the combination of technical solutions appears to be contradictory or unable to be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0018] This embodiment discloses a preparation method of a transistor PUF based on molybdenum disulfide. Molybdenum disulfide (MoS 2 ), as a two-dimensional material with excellent electrical properties, has become an ideal choice for realizing high-efficiency hardware devices due to its high electron mobility, low power consumption and good chemical stability. The unique layered structure of MoS 2 endows it with superior electron transport characteristics at the nanoscale. Especially at extremely small sizes, it can maintain strong switching performance and anti-interference ability. These characteristics enable molybdenum disulfide to show broad application potential in electronic devices, sensors and integrated circuits, especially in the field of hardware security. Therefore, the transistor PUF technology based on molybdenum disulfide can not only overcome the limitations of traditional silicon materials, but also has good anti-attack ability and high uniqueness. It can effectively improve the security protection performance of electronic devices, significantly enhance the response uniqueness, stability and anti-attack ability of PUF, thus providing an efficient and energy-saving hardware security guarantee scheme, and providing new ideas and directions for the development of new hardware security devices and their applications in fields such as the Internet of Things and embedded systems.

[0019] ReferenceFigure 1 , in this embodiment, the preparation method of the molybdenum disulfide-based transistor PUF specifically includes the following steps: Step 1, pretreat the surface of the silicon oxide substrate to remove natural organic substances and other impurities on its surface; Step 2, based on liquid-liquid interface self-assembly, make the molybdenum disulfide ink form a continuous and uneven molybdenum disulfide thin film on the silicon oxide substrate; Step 3, perform patterning treatment on the surface of the molybdenum disulfide thin film to obtain the pattern of the source and drain electrodes; Step 4, deposit a titanium thin film and a palladium thin film on the silicon oxide substrate covered with the molybdenum disulfide thin film to complete the patterning of the source and drain electrodes, and obtain the molybdenum disulfide transistor PUF array.

[0020] In the specific implementation process of Step 1, the process of pretreating the surface of the silicon oxide substrate is specifically as follows: Take an N-type heavily doped silicon wafer with a

[100] crystal orientation and a resistivity less than 0.005 Ω·cm and 300 nm silicon oxide prepared by the CZ method, place it in acetone and ultrasonically treat it for 5 min to 10 min, then take it out with tweezers and soak it in isopropanol and continue to ultrasonically treat it for 5 min to 10 min to thoroughly remove surface organic substances and other impurities, and finally take it out and dry it with a nitrogen gun.

[0021] In this embodiment, the molybdenum disulfide ink is prepared by an electrochemically assisted liquid-phase exfoliation method, and its specific implementation process is as follows: When performing the electrochemically assisted liquid-phase exfoliation experiment, use a CS2350H electrochemical workstation, clamp a molybdenum disulfide crystal with a copper flat alligator clip as the working electrode, a platinum wire as the reference electrode, and a graphite rod as the counter electrode; In the experiment, tetraheptylammonium bromide is used as the intercalated ionic liquid solute, and acetonitrile is used as the solvent, and its concentration is controlled at 3 mg / ml to 10 mg / ml, the intercalation voltage is set at -10 V to -4 V, and the intercalation time is maintained at 10 min to 60 min; After the intercalation is completed, add the fluffy block to a stabilizer with PVP as the solute and ultrasonically treat it for 5 min to 30 min, where the molecular weight of PVP is 8000 to 40000, the solvent is N,N-dimethylformamide (DMF), and the concentration is 0.1 mol / L to 0.5 mol / L; Then, use a centrifuge to centrifuge at 1000 r / min to 3000 r / min for 5 min to 10 min to take the supernatant, centrifuge at 8000 r / min to 10000 r / min for 10 min to 20 min to take the precipitate (this step is repeated three times), and then centrifuge at 3000 r / min to 5000 r / min for 5 min to 10 min to take the supernatant to obtain the final molybdenum disulfide ink. Isopropanol (IPA) is used as the solvent throughout the centrifugation process.

[0022] In the specific implementation process of Step 2, based on liquid-liquid interface self-assembly, molybdenum disulfide films are formed on the silicon oxide substrate in multiple times, thereby forming a continuous and uneven molybdenum disulfide film on the silicon oxide substrate, making the drain current Id distributions of the individual transistors in the transistor array different from each other, showing significant differences, thereby enhancing the uniqueness and unpredictability of the PUF. The implementation process of Step 2 in this embodiment is specifically as follows: Step 201: After placing the silicon oxide substrate on a customized lifting frame, place the lifting frame into a glass Petri dish, and then add 20 mL of deionized water with a density of 995 kg·m -3 and 20 mL of n-hexane with a density of 655 kg·m -3 . When an obvious layered interface appears in the glass Petri dish, for the first time, use a pipette to slowly and continuously drip molybdenum disulfide ink into the glass Petri dish, and the added dose is 1 mL to 2 mL. After a stable film is formed (that is, the materials at the interface do not move significantly), extract the lifting frame to make the molybdenum disulfide film lie flat on the silicon oxide substrate, and place the silicon oxide substrate on a heating table for heat treatment, heating to 70 °C and lasting for 3 to 5 minutes to ensure that the liquid is completely evaporated, thereby forming the first layer of molybdenum disulfide film on the sample surface; Step 202: After placing the sample obtained in Step 201 on the lifting frame again, place the lifting frame into a glass Petri dish, and then add 20 mL of deionized water with a density of 995 kg·m -3 and 20 mL of n-hexane with a density of 655 kg·m -3 . When an obvious layered interface appears in the glass Petri dish, for the second time, use a pipette to slowly and continuously drip molybdenum disulfide ink into the glass Petri dish, and the added dose is 1 mL to 2 mL. After a stable film is formed, extract the lifting frame to make the molybdenum disulfide film lie flat on the sample, and place the sample on a heating table for heat treatment, heating to 70 °C and lasting for 3 min to 5 min to ensure that the liquid is completely evaporated, thereby forming the second layer of molybdenum disulfide film on the sample surface; Step 203: After placing the sample obtained in Step 202 on the lifting frame again, place the lifting frame into a glass Petri dish, and then add 20 mL of deionized water with a density of 995 kg·m -3 and 20 mL of n-hexane with a density of 655 kg·m -3 . When an obvious layered interface appears in the glass Petri dish, for the third time, use a pipette to slowly and continuously drip molybdenum disulfide ink into the glass Petri dish, and the added dose is 1 mL to 2 mL. After a stable film is formed, extract the lifting frame to make the molybdenum disulfide film lie flat on the sample, and place the sample on a heating table for heat treatment, heating to 70 °C and lasting for 3 min to 5 min to ensure that the liquid is completely evaporated, thereby forming the third layer of molybdenum disulfide film on the sample surface.

[0023] As a preferred embodiment, in step 201, when dropping molybdenum disulfide ink onto the glass Petri dish for the first time, it is dropped at the middle position of the glass Petri dish; in step 202, when dropping molybdenum disulfide ink onto the glass Petri dish for the second time, it is dropped at the upper left corner position of the glass Petri dish; in step 203, when dropping molybdenum disulfide ink onto the glass Petri dish for the third time, it is dropped at the lower right corner position of the glass Petri dish. The molybdenum disulfide ink is dropped three times at different positions (the center, upper left corner, and lower right corner of the glass Petri dish), introducing randomness through spatial non-uniformity, thereby significantly improving the performance of the PUF chip.

[0024] In the specific implementation process of step 3, electron beam lithography, ultraviolet lithography, extreme ultraviolet lithography, or nanoimprinting can be used for patterning. Taking ultraviolet lithography as an example, the specific implementation process of step 3 is as follows: Place the substrate on a spin coater, and spin coat using Nr9-3000P negative photoresist. The spin coating parameters are set as follows: the pre-rotation speed is 600 r / min for 10 s; then the acceleration is increased to 1000 r / min and further accelerated to 3000 r / min for 60 s, and finally the acceleration reaches 5000 r / min; Place the substrate spin-coated with photoresist on a heating platform for pre-baking. The heating temperature is set at 110 °C for 180 s. After heating, the substrate needs to be left standing in the dark for 20 min for re-absorbing water operation; Use a JB-Ⅷ contact lithography machine for ultraviolet lithography patterning. The source-drain electrodes and channel patterns are specifically as Figure 2 shown. Before operation, preheat the mercury lamp for 20 min. First, install the mask plate into the suction slot of the ultraviolet lithography machine, then place the pure silicon wafer processed in the above steps on the sample stage, slowly push it into the lithography machine, set the exposure time to 45 s, and take out the sample after exposure; Place the exposed sample on a heating platform for post-baking, set the temperature to 100 °C and the time to 60 s; Cool the sample for 10 min to room temperature, and then immerse it in RD6 developer for 10 s for development; After development, rinse with deionized water for 1 min and dry with a nitrogen gun.

[0025] In the specific implementation process of Step 4, on the silicon oxide substrate covered with a molybdenum disulfide thin film, first deposit 10 nm of metallic titanium at a rate of 0.01 nm / s, then deposit 50 nm of metallic palladium at a rate of 0.05 nm / s. Subsequently, place the sample on which the metal has been deposited into a glass petri dish containing acetone and soak it for 1 min to 3 min. Heat it using a heating stage with the temperature set at 50 °C. Gently rinse the heated sample with acetone, then rinse it with isopropyl alcohol to remove the acetone, and dry it with a nitrogen gun to obtain the final transistor PUF array. The optical micrograph of the channel of one transistor is as shown in Figure 3 shown.

[0026] Reference Figure 4 is the Raman characterization of the molybdenum disulfide thin film on a 300-nm silicon oxide substrate. It can be seen from Figure 4 that the molybdenum disulfide thin film prepared in this embodiment is molybdenum disulfide with a 2H-phase structure. Reference Figure 5 is the AFM characterization of the molybdenum disulfide thin film on a 300-nm silicon oxide substrate. It can be seen from Figure 5 that the thickness of the molybdenum disulfide thin film prepared in this embodiment is 7 nm. Reference Figure 6 is the SEM characterization of the molybdenum disulfide thin film on a 300-nm silicon oxide substrate. It can be seen from Figure 6 that the molybdenum disulfide thin film prepared in this embodiment has a high density and an uneven surface stacking distribution.

[0027] Reference Figure 7 is the test chart of the transfer characteristic curve of the transistor array. It can be seen from Figure 7 that each transistor in the transistor array has excellent performance, and when the gate voltage of the transistor is -100 V, the drain current Id is distributed between 0.1 mA and 1 mA and is different for each, showing a large difference. Thus, it can be seen that the method for preparing the transistor PUF in this embodiment not only has excellent performance and high stability, but also can play an important role in the fields of chip encryption, information security protection, etc.

[0028] The above are only the preferred embodiments of the present invention, and do not limit the protection scope of the present invention. Any equivalent structural transformation made under the inventive concept of the present invention, or direct / indirect application in other related technical fields, is included in the protection scope of the present invention.

Claims

1. A method for preparing a transistor PUF based on molybdenum disulfide, characterized in that: The steps include: Step 1, pre-treating the surface of the silicon oxide substrate to remove natural organic matter and other impurities on the surface; Step 2, based on liquid-liquid interface self-assembly, the molybdenum disulfide ink forms a continuous and uneven molybdenum disulfide film on the silicon oxide substrate; Step 3, performing patterning on the surface of the molybdenum disulfide film to obtain a pattern of source and drain electrodes; Step 4: deposit a titanium film and a palladium film on the silicon oxide substrate covered with the molybdenum disulfide film to complete the patterning of the source and drain electrodes to obtain a molybdenum disulfide transistor PUF array.

2. The method for preparing a transistor PUF based on molybdenum disulfide according to claim 1, characterized in that: In step 2, based on liquid-liquid interface self-assembly, a molybdenum disulfide thin film is formed on the silicon oxide substrate at least twice, thereby forming a continuous and non-uniform molybdenum disulfide thin film on the silicon oxide substrate.

3. The method for preparing a transistor PUF based on molybdenum disulfide according to claim 2, characterized in that: Step 2 specifically includes: Step 201, after placing the silicon oxide substrate on a customized lifting frame, the lifting frame is placed in a glass culture dish, and then deionized water and n-hexane are added. When a clear stratified interface appears in the glass culture dish, a pipette is used to slowly and continuously drop molybdenum disulfide ink in the glass culture dish for the first time. After a stable film is formed, the lifting frame is removed to spread the molybdenum disulfide film on the silicon oxide substrate, and the silicon oxide substrate is placed on a heating table for heating treatment to ensure that the liquid is completely evaporated, thereby forming a first layer of molybdenum disulfide film on the sample surface; Step 202, after placing the sample obtained in step 201 on the lifting frame again, the lifting frame is placed in a glass culture dish, and then deionized water and n-hexane are added. When a clear stratified interface appears in the glass culture dish, molybdenum disulfide ink is slowly and continuously added to the glass culture dish for the second time using a pipette. After a stable film is formed, the lifting frame is removed so that the molybdenum disulfide film is spread flat on the sample, and the sample is placed on a heating table for heating treatment to ensure that the liquid is completely evaporated, thereby forming a second layer of molybdenum disulfide film on the surface of the sample; Step 203, after placing the sample obtained in step 202 on the lifting frame again, the lifting frame is placed in a glass culture dish, and then deionized water and n-hexane are added. When a clear stratified interface appears in the glass culture dish, molybdenum disulfide ink is slowly and continuously added to the glass culture dish for the third time using a pipette. After a stable film is formed, the lifting frame is removed so that the molybdenum disulfide film is spread flat on the sample, and the sample is placed on a heating table for heating treatment to ensure that the liquid is completely evaporated, thereby forming a third layer of molybdenum disulfide film on the sample surface.

4. The method for preparing a transistor PUF based on molybdenum disulfide according to claim 3, characterized in that: In step 201, when the molybdenum disulfide ink is added to the glass culture dish for the first time, it is added to the middle position of the glass culture dish; In step 202, when the molybdenum disulfide ink is added to the glass culture dish for the second time, it is added to the upper left corner of the glass culture dish; In step 203, when molybdenum disulfide ink is added to the glass culture dish for the third time, it is added to the lower right corner of the glass culture dish.

5. The method for preparing a transistor PUF based on molybdenum disulfide according to any one of claims 1 to 4, characterized in that: In step 3, patterning is performed using electron beam lithography, ultraviolet lithography, extreme ultraviolet lithography or nanoimprinting.

6. The method for preparing a transistor PUF based on molybdenum disulfide according to any one of claims 1 to 4, characterized in that: In step 4, the process of depositing a titanium film and a palladium film on a silicon oxide substrate covered with a molybdenum disulfide film is as follows: First, 10 nm of metallic titanium is deposited at a rate of 0.01 nm / s, and then 50 nm of metallic palladium is deposited at a rate of 0.05 nm / s.

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