Gain-adjustable bionic photoreceptor based on substrate bias effect and preparation method thereof

Abstract

The invention discloses a gain-adjustable bionic photoreceptor based on a substrate bias effect and a preparation method thereof. The device comprises an MOS field effect transistor and a photodiode, a substrate of the MOS field effect transistor is in a suspended state, and the photodiode works through a photosensitive PN junction. Under the condition that proper bias voltage is applied, a conducting channel of the MOS transistor is formed. When light irradiates the device, the longitudinal PN junction injects photon-generated carriers into the substrate of the MOS transistor by using a built-in electric field, so that the potential of the substrate is changed, and the threshold voltage of the MOS transistor is reduced. Under the condition that the external bias voltage remains unchanged, the reduction of the threshold voltage of the MOS transistor causes the increase of the drain output current, and the increase of the photoresponse current of the device is realized. The photoreceptor can realize gain adjustment and has an efficient light response characteristic. Similar to a photoreceptor in a human retina, the device has adjustable gain and wide dynamic range of visible light spectrum. Meanwhile, the device is compatible with a standard CMOS technology, large-scale array integration can be achieved, and the device is expected to be applied to an intelligent robot visual system in the future.

Description

Technical Field

[0001] The present invention relates to the field of bionic vision technology, and particularly to a gain-adjustable bionic photoreceptor based on the body bias effect and a preparation method thereof. Background Art

[0002] In organisms, photoreceptors can precisely capture light signals, convert these signals into electrical signals, and finally transmit them to the brain for processing, thereby achieving visual perception. Inspired by studying the structures, functions, and signal transduction mechanisms of these biological photoreceptors, scientists began to explore how to apply these principles to artificial systems. With the development of bionics and optoelectronic technologies, the research on bionic photoreceptors has gradually emerged. The goal of bionic photoreceptors is to mimic the working principles of biological photoreceptors and design artificial devices that can efficiently and accurately sense light signals. These devices can not only simulate the visual perception process but also be widely applied in multiple fields such as light detection, image processing, optical communication, and sensors. In recent years, with the emergence of new materials (such as organic photosensitive materials, quantum dots, two-dimensional materials, etc.), the performance of bionic photoreceptors has been significantly improved. Although new materials have more excellent performance in some specific applications, silicon-based devices are still the mainstream materials in the current and future electronics industries due to their mature technology, low cost, wide application compatibility, and high integration. Therefore, the present invention aims to achieve a bionic photoreceptor with a wider spectral response range, higher photoelectric conversion efficiency, and lower power consumption based on standard microelectronic processes. Summary of the Invention

[0003] To achieve the above object, the present invention provides a gain-adjustable bionic photoreceptor based on the body bias effect and a preparation method thereof, which can achieve gain adjustment and a wide dynamic range of the visible light spectrum. In addition, the structure of the present invention is simple, compatible with standard microelectronic processes, easy to achieve large-scale integration and production, and has broad application prospects.

[0004] To achieve the above object, the technical solution of the present invention is: a gain-adjustable bionic photoreceptor based on the body bias effect; an N-type buried layer region (102) is provided on a P-type substrate (101); a first N-type deep well region (103), a P well region (104), and a second N-type deep well region (105) are sequentially provided on the N-type buried layer region (102) from left to right.

[0005] Among them, a first N+-heavily doped region (106) is provided on the first N-type deep well region (103); a second N+-heavily doped region (107), a polysilicon gate region (206), a third N+-heavily doped region (108), and a fourth N+-heavily doped region (109) are successively provided on the P-well region (104) from left to right; a fifth N+-heavily doped region (110) is provided on the second N-type deep well region (105); each N+-heavily doped region is separated from the adjacent N+-heavily doped region by a shallow trench isolation region.

[0006] The second N+-heavily doped region (107) is connected to the first electrode (301) through metal leads, the polysilicon gate region (206) is connected to the second electrode (302) through metal leads, the third N+-heavily doped region (108) is connected to the third electrode (303) through metal leads, the fourth N+-heavily doped region (109) is connected to the fourth electrode (304) through metal leads, and the first N+-heavily doped region (106) and the fifth N+-heavily doped region (110) are connected to the fifth electrode (305) through metal leads.

[0007] The P-well region (104), the second N+-heavily doped region (107), the polysilicon gate region (206), and the third N+-heavily doped region (108) form an NMOS structure, and the P-well region (104) and the fourth N+-heavily doped region (109) form a photosensitive PN junction; the photosensitive PN junction injects photo-generated carriers into the body of the NMOS through the built-in electric field, causing the threshold voltage of the NMOS to become smaller, thereby achieving a strong photocurrent gain.

[0008] When there is no light illumination, the drain current of the MOS is detected once. When there is light illumination, the photosensitive PN junction uses the built-in electric field to inject photo-generated carriers into the body of the MOS transistor, changing the substrate potential and causing the threshold voltage of the MOS transistor to become smaller. Under the condition that the externally applied bias voltage remains unchanged, the decrease in the threshold voltage of the MOS transistor will increase the drain output current of the transistor. At this time, the drain current is detected for the second time, and the difference between the two obtained drain currents is taken to obtain the photocurrent response of the device.

[0009] A preparation method of a gain-adjustable bionic photoreceptor based on the body bias effect includes the following steps:

[0010] Step 1: A thin silicon oxide layer is grown on the P-type substrate by dry oxidation with oxygen. The oxidation process is carried out at a temperature of about 900 °C, and the oxidation time is controlled within a specific range to ensure that the thickness of the silicon oxide layer is appropriate. The main function of this silicon oxide layer is to protect the surface of the silicon wafer, and at the same time, in subsequent process steps, by precisely controlling its thickness, the depth of doping is adjusted;

[0011] Step 2: Use micro - lithography technology to transfer the pattern on the N - type buried layer region mask plate to the wafer surface, forming a photoresist pattern in the N - type buried layer region. The photoresist is retained in the non - N - type buried layer region. Through high - energy phosphorus ion implantation, phosphorus ions are implanted into the N - type buried layer region of the wafer to form the N - type buried layer, and then the photoresist is removed.

[0012] Step 3: Through micro - lithography technology, transfer the patterns on the first and second N - type deep well region mask plates to the wafer, forming a photoresist pattern in the N - type deep well region. The photoresist is retained in the non - N - type deep well region; implant high - energy phosphorus ions to form the N - type deep well region, and then remove the photoresist.

[0013] Step 4: Coat a uniform layer of photoresist on the silicon wafer surface to form a photoresist layer. Define the first to fifth shallow trench isolation regions, and use a mask template to transfer the pattern to the photoresist layer through ultraviolet light exposure, forming a photoresist pattern. Through a dry etching process, remove the silicon oxide layer and part of the silicon material to etch and form a shallow trench structure. The etching depth is about 0.4μm, and the etching angle with the sidewall of the shallow trench is about 10°, ensuring that the structure of the shallow trench meets the design requirements. After the etching of the shallow trench structure is completed, use low - pressure chemical vapor deposition (LPCVD) technology to fill about 1.0μm thick silicon oxide in the trench. Finally, adopt chemical mechanical polishing technology to remove the excess silicon oxide material, ensuring the flatness of the silicon wafer surface and providing a flat surface substrate for subsequent process steps.

[0014] Step 5: Through micro - lithography technology, transfer the pattern on the P - well mask plate to the wafer, forming a photoresist pattern in the P - well. The photoresist is retained in the non - P - well region; implant high - energy boron ions to form a local P - well, and then remove the photoresist.

[0015] Step 6: Anneal the ion - implanted region. Adopt rapid thermal annealing technology to repair the damage generated during the ion implantation process and activate the dopants through efficient heat treatment. This process can effectively reduce the diffusion of dopants, thereby precisely controlling the doping concentration and the doping distribution in the shallow region. The annealing temperature is controlled between 1000℃ and 1300℃, and the duration is 10 to 60 seconds to ensure that the annealing process can achieve the expected effect while avoiding excessive diffusion and damage.

[0016] Step 7: Grow a thick gate oxide layer on the silicon wafer surface through dry oxidation, and control the oxidation temperature at about 900℃ to ensure the quality and uniformity of the gate oxide layer. Use LPCVD technology to deposit a polysilicon layer about 200nm thick as the gate material. Adopt photolithography and dry etching processes to etch the polysilicon material into the required gate shape, and then remove the photoresist.

[0017] Step 8: Coat the photoresist on the silicon wafer, define the first to fifth N+ heavily doped regions, use a mask and ultraviolet light to irradiate the photoresist, and expose to form a pattern. Inject heavily doped arsenic ions to form the N+ heavily doped regions, and remove the photoresist. Perform annealing treatment to repair the crystal damage on the silicon surface caused by ion implantation and eliminate the migration of impurities in the heavily doped regions.

[0018] The beneficial effects of the present invention are as follows:

[0019] 1. The photosensitive PN junction of the present invention is connected to the substrate of the NMOS structure. When light enters the photosensitive PN junction, the built-in electric field of the PN junction injects photo-generated carriers into the substrate of the NMOS transistor, changing the substrate potential and causing the threshold voltage of the NMOS transistor to become smaller. With the external bias voltage unchanged, the drain of the NMOS outputs a larger current, that is, the photo-response current of the device. By adjusting the gate voltage, the output gain can be regulated. As shown in the Figure 4 accompanying figure, when the gate voltage is 0V, the drain output gain is approximately 20, and when the gate voltage increases to 0.6V, the drain output gain can approach 10 6 . Therefore, this device can simulate the photoreceptors in the human retina to automatically adjust its sensitivity according to the change of ambient light intensity, so as to obtain the optimal visual experience under different lighting conditions.

[0020] 2. The manufacturing method of the present invention has a simple manufacturing process and convenient operation. The gain-adjustable bionic photoreceptor based on the body bias effect prepared does not violate the basic rules of layout design and does not use steps other than the standard BCD process. At the same time, it is easy to be compatible with the standard microelectronics process and is also easy to realize large-scale integration and production, with broad application prospects. Brief Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the embodiments.

[0022] Figure 1 It is the cross-sectional view and circuit connection diagram of the gain-adjustable bionic photoreceptor based on the body bias effect in the embodiment of the present invention;

[0023] Figure 2 It is the schematic diagram of the parasitic structure and the working principle diagram of the gain-adjustable bionic photoreceptor based on the body bias effect in the embodiment of the present invention.

[0024] Figure 3 It is the top view of the gain-adjustable bionic photoreceptor based on the body bias effect in the embodiment of the present invention;

[0025] Figure 4 It is the relationship diagram between the output gain and the gate voltage excitation of the gain-adjustable bionic photoreceptor based on the body bias effect in the embodiment of the present invention;

[0026] The figure includes: 1. P-type substrate, 2. N-type buried layer region, 3. First N-type deep well region, 4. P well region, 5. Second N-type deep well region, 6. First N+ heavily doped region, 7. Second N+ heavily doped region, 8. Third N+ heavily doped region, 9. Fourth N+ heavily doped region, 10. Fifth N+ heavily doped region, 11. Polysilicon gate region, 12. First shallow trench isolation region, 13. Second shallow trench isolation region, 14. Third shallow trench isolation region, 15. Fourth shallow trench isolation region, 16. Fifth shallow trench isolation region. Detailed implementation manners

[0027] The present invention will be described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0028] The object of the present invention is to provide a gain-adjustable bionic photoreceptor based on the body bias effect and its manufacturing method. The device injects photo-generated carriers into the body of the NMOS transistor through the built-in electric field of the photosensitive PN junction, changing the substrate potential. With the external bias voltage unchanged, a larger current is output at the drain of the NMOS. By adjusting the gate voltage, it can simulate the photoreceptor in the human retina to adjust its sensitivity according to the change of ambient light intensity. In addition, the manufacturing method of the device is simple, can be realized by using the existing standard microelectronic process, does not require additional process modification, and is easy to realize large-scale array integration.

[0029] To make the above objects, features and advantages of the present invention clearer, the present invention will be briefly introduced below in conjunction with the accompanying drawings and specific implementation manners. Obviously, the described embodiments are only part of the present invention, and other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0030] As Figure 1 and Figure 3 shown, the present invention provides a gain-adjustable bionic photoreceptor based on the body bias effect; an N-type buried layer region (102) is provided on a P-type substrate (101); a first N-type deep well region (103), a P well region (104), and a second N-type deep well region (105) are successively provided on the N-type buried layer region (102) from left to right. A first N+ heavily doped region (106) is provided on the first N-type deep well region (103); a second N+ heavily doped region (107), a polysilicon gate region (206), a third N+ heavily doped region (108), and a fourth N+ heavily doped region (109) are successively provided on the P well region (104) from left to right; a fifth N+ heavily doped region (110) is provided on the second N-type deep well region (105); each N+ heavily doped region is separated from the adjacent N+ heavily doped region by a shallow trench isolation region.

[0031] As Figure 2As shown, the P-well region (104), the second N+ heavily doped region (107), the polysilicon gate region (206), and the third N+ heavily doped region (108) form an NMOS structure, and the P-well region (104) and the fourth N+ heavily doped region (109) form a photosensitive PN junction; the photosensitive PN junction injects photo-generated carriers into the body of the NMOS through the built-in electric field, causing the threshold voltage of the NMOS to become smaller, thereby achieving a strong photocurrent gain. Figure 4 As shown, when the gate voltage is 0V, the drain output gain is approximately 20, and when the gate voltage increases to 0.6V, the drain output gain can approach 106. Therefore, this device can simulate the photoreceptors in the human retina to automatically adjust its sensitivity according to the change of ambient light intensity, so as to obtain an optimal visual experience under different lighting conditions.

[0032] The P-type substrate, N-type buried layer region, N-type deep well region, P-well region, polysilicon gate region, N+ heavily doped region, and shallow trench isolation region in the present invention can be realized by using existing standard microelectronic manufacturing processes, without additional masks and process modifications.

[0033] A method for preparing a gain-tunable bionic photoreceptor based on the body bias effect proposed by the present invention includes the following steps:

[0034] Step 1: Grow a thin silicon oxide layer on the P-type substrate by dry oxidation with oxygen. The oxidation process is carried out at a temperature of about 900°C, and the oxidation time is controlled within a specific range to ensure that the thickness of the silicon oxide layer is appropriate. The main function of this silicon oxide layer is to protect the surface of the silicon wafer, and at the same time, in subsequent process steps, by precisely controlling its thickness, the doping depth is adjusted;

[0035] Step 2: Use micro-lithography technology to transfer the pattern on the N-type buried layer region mask to the surface of the wafer to form a photoresist pattern in the N-type buried layer region. The photoresist is retained in the non-N-type buried layer region. Through high-energy phosphorus ion implantation, phosphorus ions are implanted into the N-type buried layer region of the wafer to form an N-type buried layer, and the photoresist is removed.

[0036] Step 3: Use micro-lithography technology to transfer the pattern on the first and second N-type deep well region masks to the wafer to form a photoresist pattern in the N-type deep well region, and the photoresist is retained in the non-N-type deep well region; inject high-energy phosphorus ions to form an N-type deep well region, and remove the photoresist.

[0037] Step Four: Coat a uniform layer of photoresist on the silicon wafer surface to form a photoresist layer. Define the first to fifth shallow trench isolation regions, and use a mask to transfer the pattern onto the photoresist layer through ultraviolet light exposure, forming a photoresist pattern. Through a dry etching process, remove the silicon oxide layer and part of the silicon material to etch and form a shallow trench structure. The etching depth is approximately 0.4 μm, and the angle between the etching angle and the sidewall of the shallow trench is approximately 10°, ensuring that the structure of the shallow trench meets the design requirements. After the etching of the shallow trench structure is completed, use low-pressure chemical vapor deposition (LPCVD) technology to fill the trench with approximately 1.0 μm thick silicon oxide. Finally, adopt chemical mechanical polishing technology to remove the excess silicon oxide material, ensuring the flatness of the silicon wafer surface and providing a flat surface substrate for subsequent process steps.

[0038] Step Five: Transfer the pattern on the P-well mask plate to the wafer through micro-lithography technology to form a photoresist pattern of the P-well. The photoresist is retained in the non-P-well regions; inject high-energy boron ions to form a local P-well, and remove the photoresist.

[0039] Step Six: Perform annealing treatment on the ion implantation region. Adopt rapid thermal annealing technology to repair the damage generated during the ion implantation process and activate the dopants through efficient heat treatment. This process can effectively reduce the diffusion of dopants, thereby precisely controlling the doping concentration and the doping distribution in the shallow region. The annealing temperature is controlled between 1000 °C and 1300 °C, and the duration is 10 to 60 seconds to ensure that the annealing process can achieve the expected effect while avoiding excessive diffusion and damage.

[0040] Step Seven: Grow a thick gate oxide layer on the silicon wafer surface through dry oxidation. The oxidation temperature is controlled at approximately 900 °C to ensure the quality and uniformity of the gate oxide layer. Use LPCVD technology to deposit a polysilicon layer with a thickness of approximately 200 nm as the gate material. Adopt lithography and dry etching processes to etch the polysilicon material into the required gate shape and remove the photoresist.

[0041] Step Eight: Coat the photoresist on the silicon wafer, define the first to fifth N+ heavily doped regions, use a mask and ultraviolet light to irradiate the photoresist, and expose to form a pattern. Inject heavily doped arsenic ions to form N+ heavily doped regions, and remove the photoresist. Perform annealing treatment to repair the crystal damage on the silicon surface caused by ion implantation and eliminate the migration of impurities in the heavily doped regions.

[0042] Where the present invention is not elaborated, they are all well-known technologies to those skilled in the art.

[0043] The above has described the embodiments of the present invention in detail, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions, and variations made to these embodiments based on the concept of the present invention on the basis of the prior art still fall within the protection scope of the present invention.

Claims

1. A gain-adjustable bionic photoreceptor based on the bias effect, characterized in that: An N-type buried layer region (102) is provided on a P-type substrate (101); A first N-type deep well region (103), a P-well region (104), and a second N-type deep well region (105) are sequentially arranged on the N-type buried layer region (102) from left to right; The first N-type deep well region (103) is provided with a first N+ heavily doped region (106); the P-well region (104) is provided with a second N+ heavily doped region (107), a polysilicon gate region (206), a third N+ heavily doped region (108), and a fourth N+ heavily doped region (109) from left to right; the second N-type deep well region (105) is provided with a fifth N+ heavily doped region (110); each N+ heavily doped region is separated from the other N+ heavily doped region by a shallow trench isolation region; The second N+ heavily doped region (107) is connected to the first electrode (301) through a metal lead, the polysilicon gate region (206) is connected to the second electrode (302) through a metal lead, the third N+ heavily doped region (108) is connected to the third electrode (303) through a metal lead, the fourth N+ heavily doped region (109) is connected to the fourth electrode (304) through a metal lead, and the first N+ heavily doped region (106) and the fifth N+ heavily doped region (110) are connected to the fifth electrode (305) through metal leads.

2. The gain-adjustable bionic photoreceptor based on the offset effect according to claim 1, characterized in that: The P well region (104), the second N+ heavily doped region (107), the polysilicon gate region (206), and the third N+ heavily doped region (108) constitute an NMOS structure; the P well region (104) and the fourth N+ heavily doped region (109) constitute a photosensitive PN junction; the photosensitive PN junction injects photogenerated carriers into the NMOS substrate through a built-in electric field, causing the NMOS threshold voltage to decrease, thereby achieving a strong photocurrent gain.

3. A bionic visual photoelectric sensor with pulse coding capability according to claim 2, characterized in that: When there is no light, the drain current of the MOS is detected once. When there is light, the photosensitive PN junction uses the built-in electric field to inject photogenerated carriers into the substrate of the MOS tube, changing the substrate potential and causing the MOS tube value voltage to decrease. When the external bias voltage remains unchanged, the reduction of the MOS tube threshold voltage will increase the drain output current of the transistor. At this time, the drain current is detected for the second time, and the difference between the two drain currents is taken to obtain the light response current of the device.

4. A method for preparing a gain-adjustable bionic photoreceptor based on the offset effect according to any one of claims 1 to 3, comprising the following steps: Step 1: A thin silicon oxide layer is grown on a P-type substrate by dry oxidation with oxygen. The oxidation process is carried out at a temperature of about 900°C and the oxidation time is controlled within a specific range to ensure that the thickness of the silicon oxide layer is appropriate. The main function of the silicon oxide layer is to protect the surface of the silicon wafer. At the same time, in the subsequent process steps, the depth of doping can be adjusted by precisely controlling its thickness. Step 2: Use micro-development technology to transfer the pattern on the mask of the N-type buried layer area to the wafer surface to form a photoresist pattern in the N-type buried layer area. The photoresist is retained in the non-N-type buried layer area. Through high-energy phosphorus ion implantation, phosphorus ions are implanted in the N-type buried layer area of ​​the wafer to form an N-type buried layer and remove the photoresist. Step 3: Transferring the patterns on the first and second N-type deep well region masks to the wafer by micro-development technology to form a photoresist pattern in the N-type deep well region, and retaining the photoresist in the non-N-type deep well region; High-energy phosphorus ions are injected to form an N-type deep well region and the photoresist is removed. Step 4: Coat a uniform layer of photoresist on the surface of the silicon wafer to form a photoresist layer. Define the first to fifth shallow trench isolation areas, and use a mask to transfer the pattern to the photoresist layer through ultraviolet light exposure to form a photoresist pattern. Through a dry etching process, remove the silicon oxide layer and part of the silicon material, and etch to form a shallow groove structure. The etching depth is about 0.4μm, and the angle between the etching angle and the side wall of the shallow groove is about 10°, ensuring that the structure of the shallow groove meets the design requirements. After the shallow groove structure is etched, use low-pressure chemical vapor deposition (LPCVD) technology to fill the groove with about 1.0μm thick silicon oxide. Finally, use chemical mechanical polishing technology to remove excess silicon oxide material to ensure that the surface of the silicon wafer is flat, providing a flat surface substrate for subsequent process steps. Step 5: Transfer the pattern on the P-well mask to the wafer through micro-development technology to form a P-well photoresist pattern, and retain the photoresist in the non-P-well area; High-energy boron ions are injected to form a local P-well and the photoresist is removed. Step 6: Anneal the ion implanted area. Rapid thermal annealing technology is used to repair the damage caused by the ion implantation process through efficient heat treatment and activate the dopants. This process can effectively reduce the diffusion of dopants, thereby accurately controlling the doping concentration and doping distribution in shallow areas. The annealing temperature is controlled between 1000°C and 1300°C, and the duration is 10 to 60 seconds to ensure that the annealing process can achieve the desired effect while avoiding excessive diffusion and damage. Step 7: Grow a thick gate oxide layer on the surface of the silicon wafer through dry oxidation. The oxidation temperature is controlled at about 900°C to ensure the quality and uniformity of the gate oxide layer. Use LPCVD technology to deposit a polysilicon layer of about 200nm thick as the gate material. Use photolithography and dry etching processes to etch the polysilicon material into the required gate shape and remove the photoresist. Step 8: Apply photoresist on the silicon wafer to define the first to fifth N+ heavily doped regions. Use a mask and ultraviolet light to irradiate the photoresist and expose it to form a pattern. Implant heavily doped arsenic ions to form N+ heavily doped regions and remove the photoresist. Annealing treatment repairs the crystal damage on the silicon surface caused by ion implantation and eliminates the migration of impurities in the heavily doped regions.

Images