Display device

Abstract

A display device is provided. The display device includes: a substrate including a display area and a peripheral area; a transistor in the display area; a pixel electrode connected to the transistor; a common electrode overlapping the pixel electrode; and an organic insulating layer between the common electrode and the substrate and overlapping at least a portion of the peripheral region, in which a thickness of a portion of the organic insulating layer overlapping the display region and a thickness of a portion of the organic insulating layer overlapping the peripheral region are different from each other, and the organic insulating layer includes a valley penetrating the organic insulating layer and overlapping the peripheral region.

Description

[0001] This application is a divisional application of the patent application with the application date of November 13, 2019, application number 201911104803.0, and invention name "display device". Technical Field

[0002] The embodiment relates to a display device. Background Art

[0003] The display device includes a display panel, and the display panel includes a light-emitting element located on a substrate and a circuit element for driving the light-emitting element. The display panel may include a packaging substrate to help prevent the penetration of external moisture or oxygen, thereby preventing the light-emitting element from being damaged due to moisture or oxygen.

[0004] The above information disclosed in this background art section is only used to enhance the understanding of the background of the invention. Therefore, it may include information that does not form the prior art known to those of ordinary skill in the art in this country. Summary of the Invention

[0005] The embodiment relates to a display device, which includes: a substrate including a display area and a peripheral area; a transistor located in the display area; a pixel electrode connected to the transistor; a common electrode stacked with the pixel electrode; and an organic insulating layer located between the common electrode and the substrate and stacked with at least a part of the peripheral area, wherein the thickness of the part of the organic insulating layer stacked with the display area and the thickness of the part of the organic insulating layer stacked with the peripheral area are different from each other, and the organic insulating layer includes a valley penetrating the organic insulating layer and stacked with the peripheral area.

[0006] The organic insulating layer stacked with the display area may have a first height, the organic insulating layer stacked with the peripheral area may have a second height, and the first height may be higher than the second height.

[0007] The first height may be approximately twice the second height.

[0008] The display device may further include a packaging layer located on the common electrode and stacked with the display area and the peripheral area, and the packaging layer may include a first inorganic layer and a second inorganic layer and an organic layer located between the first inorganic layer and the second inorganic layer.

[0009] Touch lines may be located on the packaging layer stacked with the peripheral area, and touch electrodes may be located on the packaging layer stacked with the display area.

[0010] The side of the packaging layer where the touch lines are provided and the side of the packaging layer where the touch electrodes are provided may have a step difference.

[0011] The organic layer may be provided in the valley.

[0012] The display device may further include a dam provided in the peripheral region, wherein the distance from the dam to the edge of the display region may be greater than the distance from the edge of the organic layer to the edge of the display region.

[0013] The transistor may further include: a semiconductor layer located on a substrate; a gate electrode stacked with the semiconductor layer; and a source electrode and a drain electrode connected to the semiconductor layer. The display device may further include a first connection member located on the drain electrode and connecting the pixel electrode and the drain electrode.

[0014] The organic insulating layer may include: a first organic insulating layer located between the source electrode and the first connection member and between the drain electrode and the first connection member; and a second organic insulating layer located between the first connection member and the pixel electrode.

[0015] One region of at least one of the first organic insulating layer and the second organic insulating layer that overlaps with the display region and another region that overlaps with the peripheral region may have a thickness difference.

[0016] An embodiment also relates to a display device, the display device including: a substrate including a display region and a peripheral region; a transistor located in the display region; an organic insulating layer located on the transistor; a light-emitting diode connected to the transistor; a packaging layer located on the light-emitting diode and including an organic layer; and a touch line and a touch electrode located on the packaging layer, wherein the organic insulating layer includes a valley overlapping with the peripheral region, the organic layer is provided in the valley, and there is a step difference between the organic insulating layer overlapping with the display region and the organic insulating layer overlapping with the peripheral region.

[0017] The transistor may further include: a semiconductor layer located on a substrate; a gate electrode stacked with the semiconductor layer; and a source electrode and a drain electrode connected to the semiconductor layer, wherein the display device may further include a first connection member located on the drain electrode and connecting the pixel electrode and the drain electrode.

[0018] The organic insulating layer may include: a first organic insulating layer located between the source electrode and the first connection member and between the drain electrode and the first connection member; and a second organic insulating layer located between the first connection member and the pixel electrode.

[0019] One region of at least one of the first organic insulating layer and the second organic insulating layer that overlaps with the peripheral region may be thinner than another region that overlaps with the display region.

[0020] The packaging layer may further include a first inorganic layer and a second inorganic layer, wherein the organic layer may be located between the first inorganic layer and the second inorganic layer.

[0021] The embodiment also relates to a display device, which includes: a substrate including a display area and a peripheral area; a semiconductor layer located on the substrate overlapping with the display area; a gate electrode overlapping with the semiconductor layer; a source electrode and a drain electrode connected to the semiconductor layer; a first connection member located on the drain electrode and connected to the drain electrode; a pixel electrode located on the first connection member and connected to the first connection member; an emission layer and a common electrode overlapping with the pixel electrode; an organic insulating layer located between the common electrode and the substrate and overlapping with at least a part of the peripheral area, wherein the organic insulating layer includes a valley overlapping with the peripheral area; and a power supply wiring disposed in the peripheral area and overlapping with the valley.

[0022] The display device may further include a second connection member located on the same layer as the first connection member and disposed in the peripheral area, and the second connection member may overlap with the valley.

[0023] The organic insulating layer may include: a first organic insulating layer located between the drain electrode and the first connection member; and a second organic insulating layer located between the first connection member and the pixel electrode, the first organic insulating layer may include a first valley, and the second organic insulating layer may include a second valley.

[0024] The display device may further include a packaging layer located on the common electrode, wherein the packaging layer may include a first inorganic layer, a second inorganic layer, and an organic layer located between the first inorganic layer and the second inorganic layer, and the organic layer is disposed in the second valley. Description of the Drawings

[0025] By describing the exemplary embodiments in detail with reference to the drawings, the features will become apparent to those skilled in the art. In the drawings: Figure 1 A schematic top view of a display device according to an exemplary embodiment is shown; Figure 2 Shows Figure 1 A schematic cross-sectional view taken along line AA' of Figure 3 Shows Figure 1 A schematic cross-sectional view taken along line AA' of Figure 4 Shows Figure 1 A schematic cross-sectional view taken along line AA' of Figure 5 Shows Figure 1 A schematic cross-sectional view taken along line AA' of Figure 6 A schematic equivalent circuit diagram of a pixel of a display device according to an exemplary embodiment is shown; and Figure 7 A schematic cross-sectional view of a pixel of a display device according to an exemplary embodiment is shown. Detailed Description of the Embodiment

[0026] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the example implementations to those skilled in the art. In the drawings, the dimensions of layers and regions may be exaggerated for clarity. Like reference numerals always denote like elements.

[0027] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, no intervening elements are present. The terms "on... " or "above... " mean positioned on or below a portion of an object and do not necessarily mean positioned on the upper side of the portion of the object based on a direction of gravity.

[0028] In addition, unless explicitly described to the contrary, the term "comprising" and its variants such as will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0029] In addition, in this specification, the phrase "in a plane" means viewing a target portion from the top, and the phrase "in a cross-section" means viewing a cross-section formed by vertically cutting the target portion from the side.

[0030] Hereinafter, reference will be made to Figure 1 and Figure 2 to describe a display device according to an exemplary embodiment. Figure 1 is a schematic top view of a display device according to an exemplary embodiment. Figure 2 is Figure 1 a schematic cross-sectional view taken along line AA' of

[0031] Referring to Figure 1 according to the present exemplary embodiment, a display device may include a driving unit that includes a display panel 10, a flexible printed circuit film 20 coupled to the display panel 10, and an IC chip 30.

[0032] The display panel 10 includes a display area DA corresponding to a screen for displaying an image (e.g., in a plane defined by an x-axis direction and a y-axis direction intersecting the x-axis direction) and a peripheral area PA provided at the periphery of the display area DA. In Figure 1 the inner side of the quadrilateral single-dot dash line () corresponds to the display area DA, and the outer side of the single-dot dash line corresponds to the peripheral area PA.

[0033] In the display area DA, pixels PX may be arranged in the form of, for example, a matrix. Signal lines such as scan lines (gate lines), light emission control lines, data lines, drive voltage lines, etc. may be provided in the display area DA. Each pixel PX may be connected to a scan line, a light emission control line, a data line, and a drive voltage line. Each pixel PX may receive a scan signal (gate signal), a light emission control signal, a data signal, and a drive voltage from the signal lines. Each pixel PX may include a light-emitting element, which may be an organic light-emitting diode.

[0034] The display area DA may include a touch portion for sensing a user's contact touch or non-contact touch.

[0035] In Figure 1 it, the display area DA is shown as a rounded quadrilateral as an example. The display area DA may have various shapes, such as a polygon, a circle, an ellipse, etc.

[0036] Circuits and / or signal lines may be provided in the peripheral area PA to generate and / or transmit various signals applied to the display area DA. In the present exemplary embodiment, a pad (or "bond pad") portion PP is provided in the peripheral area PA of the display panel 10, and pads are formed in the pad portion PP to receive external signals of the display panel 10. The pad portion PP may extend in a first direction (x-axis direction) along the periphery of one edge of the display panel 10. A flexible printed circuit film 20 may be bonded to the pad portion PP, and the pads of the flexible printed circuit film 20 may be electrically connected to the pads of the pad portion PP.

[0037] A driving unit for generating and / or processing various signals for driving the display panel 10 may be provided in the peripheral area PA. The driving unit may include: a data driver that applies a data signal to the data line; an emission driver (light emission driver) that applies an emission control signal (light emission control signal) to the emission control line (light emission control line); and a signal controller that controls the data driver, the scan driver, and the emission driver. The scan driver and the emission driver may be integrated with the display panel 10, or may be provided on the left and right sides or on one side of the display area DA. The data driver and the signal controller may be provided as an IC chip (driving IC chip) 30, and the IC chip 30 may be mounted in the peripheral area PA of the display panel 10. The IC chip 30 may be mounted in the flexible printed circuit film 20, and the IC chip 30 may be bonded to the display panel 10 and thus electrically connected to the display panel 10.

[0038] The display panel 10 may include an encapsulation layer EN that completely covers the display area DA. The encapsulation layer EN can prevent moisture or oxygen from penetrating into the display panel 10 by sealing the display area DA, for example, preventing moisture or oxygen from penetrating into the light-emitting elements. The edge of the encapsulation layer EN may be located between the edge of the display panel 10 and the display area DA.

[0039] A valley VA surrounding the display area DA may be provided in the peripheral area PA. The valley VA represents an area where the organic insulating layer (for example, the first organic insulating layer 181 described in detail below in connection with the first valley V1) is removed. The organic insulating layer may be vulnerable to moisture penetration. Therefore, in the valley VA where the organic insulating layer is removed, moisture penetrating along a part of the organic insulating layer can be prevented from entering the display area DA.

[0040] The valley VA may be provided along the edge of the display panel 10, for example, may be provided along the four edges of the display panel 10. The edge of the valley VA may be substantially parallel to the edge of the display panel 10.

[0041] The display panel 10 may include a bending region BR. The bending region BR may be provided in the peripheral area PA between the display area DA and the pad portion PP. The bending region BR may be provided to cross the display panel 10 in a first direction (x-axis direction). The display panel 10 may be bent with a predetermined radius of curvature with respect to a bending axis parallel to the first direction (x-axis direction) in the bending region BR. When the display panel 10 is a top-emission type, the pad portion PP and the flexible printed circuit film 20 provided farther from the display area DA than the bending region BR may be bent to be disposed behind the display panel 10. In an electronic device to which the display device is applied, the display panel 10 may be in such a bent state. The bending region BR may be bent with respect to one bending axis, or may be bent with respect to two or more bending axes. In the drawings, the bending region BR is provided in the peripheral area PA, but the bending region BR may be provided to cross the display area DA and the peripheral area PA, or may be provided in the display area DA.

[0042] Hereinafter, Figure 2 the cross-sectional structure of the display panel 10 according to an exemplary embodiment will be described in detail. Figure 2 A cross-section at the periphery of the left edge of the display panel 10 in an exemplary embodiment is schematically shown. The periphery of the right edge of the display panel 10 and the periphery of the left edge of the display panel 10 may be substantially symmetric to each other.

[0043] Referring to Figure 2 this, the display area DA will be described, and then the peripheral area PA will be described.

[0044] The substrate 110 includes a display area DA and a peripheral area PA, and a plurality of layers, wirings, and components are located in the display area DA. Although a plurality of pixels PX may be provided in the display area DA of the display panel 10, only one pixel PX will be shown in the drawings to avoid complexity. Additionally, each pixel PX may include, for example, a capacitor, a light-emitting element, and a plurality of transistors, but for clear explanation, the stacked structure of the display panel 10 will be described specifically with reference to one transistor and one light-emitting element (light-emitting diode) LED connected to the transistor.

[0045] The substrate 110 may be a flexible substrate or a rigid substrate. The substrate 110 may include a polymer (such as polyimide, polyamide, polycarbonate, polyethylene terephthalate, etc.) or glass, quartz, ceramic, etc.

[0046] The barrier layer 115 may be located on the substrate 110 and may help prevent the penetration of external moisture or impurities. The barrier layer 115 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), etc.

[0047] The buffer layer 120 may be located on the barrier layer 115. The buffer layer 120 may help block impurities and may reduce the stress applied to the substrate 110, and the impurities may diffuse from the substrate 110 into the semiconductor layer 130 during the process for forming the semiconductor layer 130. The buffer layer 120 may include an inorganic insulating material such as silicon oxide, silicon nitride, etc.

[0048] The semiconductor layer 130 may be located on the buffer layer 120. The semiconductor layer 130 may include a source region 131, a drain region 132, and a channel region 133 that overlaps with the gate electrode 124a. The source region 131 and the drain region 132 provided on opposite sides of the channel region 133 may both be doped with impurities. The semiconductor layer 130 may include polysilicon, amorphous silicon, or an oxide semiconductor.

[0049] The first insulating layer 141 including an inorganic insulating material (such as silicon oxide, silicon nitride, etc.) or an organic insulating material may be located on the semiconductor layer 130. The first insulating layer 141 may include a portion that serves as a first gate insulating layer.

[0050] The first gate conductor including the scan line and the gate electrode 124a of the transistor may be located on the first insulating layer 141. The first gate conductor may include a metal (such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), etc.) or their metal alloys.

[0051] The second insulating layer 142 may be located on the first insulating layer 141 and the first gate conductor. The second insulating layer 142 may include an inorganic insulating material (such as silicon oxide, silicon nitride, etc.) or an organic insulating material. The second insulating layer 142 includes a portion that serves as the second gate insulating layer.

[0052] A second gate conductor such as a storage line including the storage electrode 124b may be located on the second insulating layer 142. The second gate conductor may include a metal (such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), etc.) or an alloy of these metals.

[0053] The third insulating layer 160 may be located on the second gate conductor. The third insulating layer 160 may include an inorganic insulating material (such as silicon oxide, silicon nitride, etc.) or an organic insulating material.

[0054] A first data conductor that may include a data line, a driving voltage line, a power supply wiring 178, a source electrode 173 of a transistor, and a drain electrode 175 of the transistor may be located on the third insulating layer 160.

[0055] The source electrode 173 and the drain electrode 175 may be connected to the source region 131 and the drain region 132 of the semiconductor layer 130 through contact holes formed in the third insulating layer 160, the second insulating layer 142, and the first insulating layer 141, respectively.

[0056] The first data conductor may include a metal (such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), etc.) or an alloy of these metals. The first data conductor may be multilayer, such as titanium / aluminum / titanium (Ti / Al / Ti), titanium / copper / titanium (Ti / Cu / Ti), or molybdenum / aluminum / molybdenum (Mo / Al / Mo).

[0057] The gate electrode 124a, the source electrode 173, and the drain electrode 175 together with the semiconductor layer 130 form a transistor. In the transistor shown in the drawing, the gate electrode 124a is provided above the semiconductor layer 130, but the structure of the transistor may be modified differently.

[0058] The above-mentioned first organic insulating layer 181 may be located on the third insulating layer 160 and the first data conductor (i.e., on the power supply wiring 178, the source electrode 173, and the drain electrode 175). The first organic insulating layer 181 may include an organic insulating material (such as polyimide, acrylic polymer, silicone polymer, etc.) and may also include an inorganic insulating material.

[0059] As described in detail below, a part of the first organic insulating layer 181 located in the peripheral region PA may include a first valley V1 in which some of the first organic insulating layer 181 is removed.

[0060] A second data conductor that may include the first connection member 177, the driving control signal line 179, and the second connection member 188 may be located on the first organic insulating layer 181.

[0061] The first connection member 177 may connect the drain electrode 175 and the pixel electrode 191, which will be described below. The first connection member 177 reduces the resistance between the drain electrode 175 and the pixel electrode 191, so that a light-emitting element that can be driven at a high frequency and has high brightness can be provided.

[0062] The second organic insulating layer 182 may be located on the second data conductor and the first organic insulating layer 181. The second organic insulating layer 182 may include an organic insulating material and may include, for example, polyimide, acrylic polymer, etc.

[0063] The pixel electrode 191 of the light-emitting diode LED may be located on the second organic insulating layer 182. The pixel electrode 191 may be connected to the first connection member 177 through a contact hole formed in the second organic insulating layer 182 and may be connected to the drain electrode 175 through the first connection member 177.

[0064] The pixel electrode 191 may include a metal (such as silver (Ag), nickel (Ni), gold (Au), platinum (Pt), aluminum (Al), copper (Cu), aluminum-neodymium (AlNd), aluminum-nickel-lanthanum (AlNiLa), etc.) or their metal alloys. Optionally, the pixel electrode 191 may include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. The pixel electrode 191 may be multilayer, such as ITO / Ag / ITO, ITO / Al, etc.

[0065] The barrier rib 360 having an opening superimposed on the pixel electrode 191 may be located on the second organic insulating layer 182. The opening of the barrier rib 360 may define each pixel region. The barrier rib 360 may be used as a pixel defining layer. The barrier rib 360 may include an organic insulating material or an inorganic insulating material.

[0066] The emission layer 370 may be provided on the pixel electrode 191 so as to be superimposed on the opening defined by the barrier rib 360.

[0067] The common electrode 270 may be located on the emission layer 370. The common electrode 270 may be formed of a thin metal with a low work function, such as calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), etc., such that the common electrode 270 has the property of being light transmissive. The common electrode 270 may include a transparent conductive material, such as ITO, IZO, etc.

[0068] The pixel electrode 191, the emission layer 370, and the common electrode 270 of each pixel PX form a light-emitting diode LED, such as an organic light-emitting diode.

[0069] The encapsulation layer EN may be located on the common electrode 270 and may encapsulate the light-emitting diode LED to help prevent the penetration of external moisture or oxygen. The encapsulation layer EN may cover the entire area of the display region DA, and the edge of the encapsulation layer EN may be disposed in the peripheral region PA.

[0070] The encapsulation layer EN may include a structure in which one or more inorganic layers and one or more organic layers are stacked. In some example embodiments, the encapsulation layer EN may include a first inorganic layer 391, an organic layer 392, and a second inorganic layer 393. In the encapsulation layer EN, the first inorganic layer 391 and the second inorganic layer 393 may help prevent the penetration of moisture, etc., and the organic layer 392 may flatten the surface of the encapsulation layer EN (e.g., the top surface of the encapsulation layer EN).

[0071] The first inorganic layer 391 and the second inorganic layer 393 may include an inorganic insulating material, such as silicon oxide, silicon nitride, etc. The organic layer 392 may include an organic material, such as an acrylic resin, a methacrylic resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, and a perylene resin.

[0072] Although not shown in this specification, a polarization layer may be located on the encapsulation layer EN to reduce the reflection of external light.

[0073] The touch electrode TP for sensing touch may be located on the second inorganic layer 393 of the encapsulation layer EN. The touch electrode TP may be located between the encapsulation layer EN and the polarization layer. The touch electrode TP may be formed in the shape of a plurality of blocks and may include a transparent conductive material (such as ITO, etc.), or may include a metal mesh.

[0074] According to an example embodiment, the touch electrode TP may be directly located on the encapsulation layer EN instead of being attached to an additionally provided touch panel. Compared with the case of additionally manufacturing a touch panel and attaching the touch electrode to the touch panel, the process for forming the touch electrode TP may be simplified, and a light and thin display device may be provided.

[0075] Hereinafter, the components provided in the peripheral area PA will be described. The components provided in the peripheral area PA may be explained in conjunction with the components provided in the display area DA, and repeated explanations may be partially omitted.

[0076] The substrate 110, the barrier layer 115, the buffer layer 120, the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 respectively extending from the display area DA may be sequentially stacked in the peripheral area PA.

[0077] The edges of the first insulating layer 141, the edges of the second insulating layer 142, and the edges of the third insulating layer 160 may overlap each other. For example, the edges of the first insulating layer 141, the edges of the second insulating layer 142, and the edges of the third insulating layer 160 may be substantially aligned.

[0078] The edges of the first insulating layer 141, the edges of the second insulating layer 142, and the edges of the third insulating layer 160 may be provided inside the edge of the substrate 110. Therefore, the edges of the first insulating layer 141, the edges of the second insulating layer 142, and the edges of the third insulating layer 160 may be provided closer to the display area DA than the edge of the substrate 110.

[0079] In the peripheral area PA, a crack dam CD may be provided at the edges of the first insulating layer 141, the edges of the second insulating layer 142, and the edges of the third insulating layer 160. The crack dam CD may help prevent the spread of cracks that may occur in inorganic insulating layers such as the barrier layer 115 and the buffer layer 120 when the display panel 10 is cut corresponding to the edge of the substrate 110. The crack dam CD may be formed of an organic material. For example, it may be formed of the same material as at least one of the first organic insulating layer 181, the second organic insulating layer 182, and the barrier rib 360 in the same process.

[0080] The crack dam CD may cover at least one edge of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160. In another embodiment, the crack dam CD may not overlap with the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160.

[0081] The power supply wiring 178 may be located on a part of the third insulating layer 160 provided in the peripheral area PA. The power supply wiring 178 may be on the same layer as the source electrode 173 and the drain electrode 175 provided in the display area DA. The power supply wiring 178 may be formed of the same material as the first data conductor including the source electrode 173 and the drain electrode 175 in the same process.

[0082] The power supply wiring 178 may transmit a power supply voltage having a predetermined level that may be applied to the light-emitting diode LED, and may transmit, for example, a common voltage ELVSS (seeFigure 6 ). The power supply wiring 178 can be electrically connected to the pad portion PP through its first end portion and second end portion, and can surround the display area DA.

[0083] The first organic insulating layer 181 can be located on the power supply wiring 178 and the third insulating layer 160.

[0084] The first organic insulating layer 181 that overlaps with the peripheral area PA can include the above-described first valley V1. The first valley V1 represents an area from which the first organic insulating layer 181 is removed. The first valley V1 can block the movement path of moisture and the like introduced from outside the substrate 110 through the first organic insulating layer 181, so as to help prevent moisture from penetrating into the display area DA.

[0085] The first valley V1 can penetrate (e.g., completely penetrate) the first organic insulating layer 181. The first valley V1 can have a height substantially the same as the thickness of the first organic insulating layer 181.

[0086] The drive control signal line 179 and the second connection member 188 can be located on a part of the first organic insulating layer 181 that overlaps with the peripheral area PA. The drive control signal line 179 and the second connection member 188 can be on the same layer as the first connection member 177 provided in the display area DA. The drive control signal line 179 and the second connection member 188 can be formed by the same process as the first connection member 177, and can include the same material as the first connection member 177.

[0087] The drive control signal line 179 can transmit signals such as a vertical start signal, a clock signal, etc. and a signal providing a low voltage of a specific level to the scan driver and / or the light-emitting driver, and the scan driver and / or the light-emitting driver can be provided in the drive circuit area in the peripheral area PA.

[0088] The second connection member 188 can be located on the first organic insulating layer 181, and can be connected to the power supply wiring 178. A part of the first organic insulating layer 181 that overlaps with the power supply wiring 178 can be removed for the connection between the second connection member 188 and the power supply wiring 178.

[0089] The second organic insulating layer 182 can be located on the first organic insulating layer 181, the drive control signal line 179, and the second connection member 188.

[0090] The thickness of the second organic insulating layer 182 provided in the peripheral area PA may be different from the thickness of the second organic insulating layer 182 provided in the display area DA. The second organic insulating layer 182 superimposed on the display area DA may have a first height h1, and the second organic insulating layer 182 provided in the peripheral area PA may have a second height h2. In the present exemplary embodiment, the first height h1 may be higher than the second height h2. For example, the first height h1 may be approximately twice the second height h2. There may be a step difference between one side (e.g., the top surface) of the second organic insulating layer 182 provided in the peripheral area PA and one side (e.g., the top surface) of the second organic insulating layer 182 provided in the display area DA.

[0091] The second organic insulating layer 182 having a plurality of regions (each region having a different height) may be formed by a single process. For example, it may be formed by using a halftone mask.

[0092] The second organic insulating layer 182 may include a second valley V2. The second valley V2 represents an area from which the second organic insulating layer 182 is removed. The second valley V2 may block the movement path of moisture or foreign particles moving through the second organic insulating layer 182 or the first organic insulating layer 181 from the outside, thereby preventing external moisture or foreign particles from penetrating into the display area DA.

[0093] The second valley V2 may penetrate (e.g., completely penetrate) the second organic insulating layer 182 provided in the peripheral area PA. The height of the second valley V2 may be substantially the same as the thickness of the second organic insulating layer 182 provided in the peripheral area PA. The height of the second valley V2 may be the same as the second height h2.

[0094] In some exemplary embodiments, the first valley V1 and the second valley V2 may be superimposed on each other. The edges of the first valley V1 and the edges of the second valley V2 may be aligned while being superimposed on each other. When the first valley V1 and the second valley V2 are substantially superimposed on each other, they may be regarded as a single valley.

[0095] The third connection member 198 located on the same layer as the pixel electrode 191 may be located on the second organic insulating layer 182. The third connection member 198 and the pixel electrode 191 may be formed of the same material by the same process.

[0096] The third connection member 198 may be connected to the power supply wiring 178 through the second connection member 188. The third connection member 198 may be connected to the common electrode 270 superimposed on the display area DA. The power supply wiring 178 may be connected to the common electrode 270 through the third connection member 198 and the second connection member 188. When the power supply wiring 178 transmits the common voltage ELVSS as the power supply voltage, the common electrode 270 may receive the common voltage ELVSS.

[0097] The third connection member 198 on the second organic insulating layer 182 may have a patterned shape. In the present exemplary embodiment, the third connection member 198 and the driving control signal line 179 may not be substantially superimposed on each other in the z-axis direction. The driving control signal line 179 may also have a patterned shape and may be disposed in a region that does not overlap with the third connection member 198. The third connection member 198 and the driving control signal line 179 may be set to be misaligned or offset from each other. In a plan view, the third connection member 198 and the driving control signal line 179 may be disposed in a misaligned region and thus completely form a planar shape. Since the third connection member 198 and the driving control signal line 179 are misaligned, signals generated from below the touch line TL that are unnecessary can be shielded.

[0098] The third connection member 198 may be disposed in the first valley V1 and the second valley V2. The third connection member 198 may have a shape that penetrates the first organic insulating layer 181 and the second organic insulating layer 182. When the first valley V1 and the second valley V2 are filled with a material other than an organic material (such as the third connection member 198), moisture or foreign particles moving along the organic insulating layer can be prevented from penetrating into the display area DA.

[0099] At least one of the dams D1 and D2 may be disposed in the peripheral area PA. The dams D1 and D2 may be located on the third insulating layer 160.

[0100] The dams D1 and D2 can prevent a flowing organic material (such as a monomer used in the process of the organic layer 392 for forming the encapsulation layer EN) from overflowing. Thus, the edge of the organic layer 392 of the encapsulation layer EN can be substantially closer to the inside than the dams D1 and D2. For example, it may be disposed inside the first dam D1. The edge of the organic layer 392 may be located between the dams D1 and D2 and the display area DA. The edge of the organic layer 392 may be set to be closer to the display area DA than the edges of the dams D1 and D2.

[0101] The dams D1 and D2 may include at least one layer. The dams D1 and D2 may be formed by using an organic insulating layer, an inorganic insulating layer, or a barrier rib disposed in the display area DA.

[0102] The first dam D1 according to the exemplary embodiment may include one layer. In the present exemplary embodiment, the first dam D1 may be formed of the same material as the second organic insulating layer 182 by the same process. The first dam D1 may be formed of the same material as the barrier rib 360 by the same process.

[0103] The second dam D2 according to the exemplary embodiment may include a plurality of layers. The second dam D2 may include at least one of a layer formed of the same material as the first organic insulating layer 181 by the same process, a layer formed of the same material as the second organic insulating layer 182 by the same process, and a layer formed of the same material as the barrier rib 360 by the same process.

[0104] The encapsulation layer EN extending from the display area DA may be provided in the peripheral area PA. The first inorganic layer 391 and the second inorganic layer 393 included in the encapsulation layer EN may extend to near an edge of the peripheral area PA where the third insulating layer 160 is provided. The first inorganic layer 391 and the second inorganic layer 393 of the encapsulation layer EN may extend over the dams D1 and D2 so as to cover the dams D1 and D2. In the present exemplary embodiment, the contact area of the first inorganic layer 391 and the second inorganic layer 393 is increased, and thus, the bonding force between the first inorganic layer 391 and the second inorganic layer 393 can be increased.

[0105] An edge of the organic layer 392 may be located between the first dam D1 and the valleys V1 and V2. The organic layer 392 may be formed at a position not exceeding the first dam D1 while filling the valleys V1 and V2. The organic layer 392 may be provided in the valleys V1 and V2.

[0106] The organic layer 392 may be formed of an organic material such as a monomer or a reaction product thereof. The organic material may flow into the first valley V1 and the second valley V2 during the process for forming the organic layer 392. The height of the second valley V2 may be determined by the thickness of the second organic insulating layer 182. According to the exemplary embodiment, the thickness of the second organic insulating layer 182 provided in the peripheral area PA may be thinner than the thickness of the second organic insulating layer 182 provided in the display area DA, and thus the height of the second valley V2 can be reduced. Accordingly, the organic material provided during the process for forming the organic layer 392 may have an edge located between the first dam D1 and the valleys V1 and V2 while sufficiently filling the first valley V1 and the second valley V2. According to the present exemplary embodiment, the organic layer 392 may have a flat top surface.

[0107] Compared with the above-described exemplary embodiment, if the height of the second valley V2 in the peripheral region PA is substantially the same as the thickness of the second organic insulating layer 182 in the display region DA, a large amount of organic material may be required to fill the first valley V1 and the second valley V2. In the case where the height of the second valley V2 is equal to the first height h1, the organic material does not flow to the periphery of the first dam D1 after filling the first valley V1 and the second valley V2, or does not completely fill the first valley V1 and the second valley V2. Therefore, the top surface of the organic layer 392 is recessed, such that the organic layer 392 does not have a flat top surface. The touch line TL connected to the touch electrode TP may be located on the top surface of the organic layer 392. If the top surface of the organic layer 392 is not planarized, it is not easy to form the touch line TL, and a short circuit failure may occur.

[0108] Multiple touch lines TL connected to the touch electrode TP disposed in the display region DA may be located on the top surface of the encapsulation layer EN. The touch line TL is connected to the touch electrode TP and transmits a touch sensing signal. The touch line TL may be formed of the same material as the touch electrode TP by the same process, or may be formed of a different material from the touch electrode TP by a different process.

[0109] According to the present exemplary embodiment, the touch line TL disposed in the peripheral region PA and the touch electrode TP disposed in the display region DA may have a step difference. Therefore, one side of the encapsulation layer EN where the touch line TL is disposed and one side of the encapsulation layer EN where the touch electrode TP is disposed may have a step difference.

[0110] A protective film (not shown) may also be provided under the substrate 110. The protective film may be attached to the rear side of the display panel 10 by using an adhesive, or the protective film may be formed by a coating process without using an adhesive. The protective film may include plastics such as polyethylene terephthalate, polyethylene naphthalate, polyimide, polyethylene sulfide, etc.

[0111] Hereinafter, Figures 3 to 5 display devices according to various exemplary embodiments will be described respectively. Figure 3 is Figure 1 a cross-sectional view of an exemplary embodiment taken along line AA' of Figure 4 is Figure 1 a cross-sectional view of an exemplary embodiment taken along line AA' of Figure 5 is Figure 1 a cross-sectional view of an exemplary embodiment taken along line AA' of Figures 3 to 5 The components disposed in the display region DA shown in Figure 2 are the same as the components described with reference to

[0112] First, with reference toFigure 3 ,a base 110, a barrier layer 115, a buffer layer 120, a first insulating layer 141, a second insulating layer 142, and a third insulating layer 160 extending from the display area DA can be sequentially stacked in the peripheral area PA.

[0113] The first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 can be aligned at their edges. For example, the edges of the first insulating layer 141, the edges of the second insulating layer 142, and the edges of the third insulating layer 160 can overlap each other.

[0114] In the peripheral area PA, crack dams CD can be provided at the edges of the first insulating layer 141, the edges of the second insulating layer 142, and the edges of the third insulating layer 160. The crack dams CD can prevent the spread of cracks, which may occur in inorganic insulating layers such as the barrier layer 115 and the buffer layer 120 when the display panel 10 is cut corresponding to the edge of the base 110. The crack dams CD can be formed of an organic material or an inorganic material. For example, they can be formed of the same material as at least one of the first organic insulating layer 181, the second organic insulating layer 182, and the barrier ribs 360 in the same process.

[0115] The power supply wiring 178 can be located on a part of the third insulating layer 160 provided in the peripheral area PA. The power supply wiring 178 can be on the same layer as the source electrode 173 and the drain electrode 175 provided in the display area DA. The power supply wiring 178 can be formed of the same material as the first data conductor including the source electrode 173 and the drain electrode 175 in the same process.

[0116] The power supply wiring 178 can transmit a power supply voltage having a predetermined level that can be applied to the light-emitting diode LED, and can transmit, for example, a common voltage ELVSS.

[0117] The first organic insulating layer 181 is located on the power supply wiring 178 and the third insulating layer 160. The thickness of the first organic insulating layer 181 overlapping the peripheral area PA and the thickness of the first organic insulating layer 181 overlapping the display area DA can be different from each other. For example, the first organic insulating layer 181 overlapping the display area DA can have a third height h3, and the first organic insulating layer 181 overlapping the peripheral area PA can have a fourth height h4, and the third height h3 can be higher than the fourth height h4. For example, the third height h3 can be approximately twice the fourth height h4.

[0118] The first organic insulating layer 181 having multiple regions (each region having a different height) can be formed by a single process. For example, it can be formed by using a halftone mask.

[0119] The first organic insulating layer 181 superimposed on the peripheral area PA may include a first valley V1 in which the first organic insulating layer 181 is removed. The first valley V1 may block the movement path of moisture and the like introduced from outside the substrate 110 through the first organic insulating layer 181, so as to help prevent moisture from penetrating into the display area DA.

[0120] The height of the first valley V1 may be substantially the same as the thickness of the first organic insulating layer 181 provided in the peripheral area PA. The height of the first valley V1 may be substantially the same as the fourth height h4.

[0121] The drive control signal line 179 and the second connection member 188 may be located on the first organic insulating layer 181. The drive control signal line 179 and the second connection member 188 may be located on the same layer as the first connection member 177 provided in the display area DA. The drive control signal line 179 and the second connection member 188 may be formed by the same process as the first connection member 177 and may include the same material as the first connection member 177.

[0122] The second connection member 188 may be located on the first organic insulating layer 181 and may be connected to the power supply wiring 178. A part of the first organic insulating layer 181 superimposed on the power supply wiring 178 may be removed for the connection between the second connection member 188 and the power supply wiring 178.

[0123] The second organic insulating layer 182 may be located on the drive control signal line 179 and the second connection member 188. In various exemplary embodiments, the thickness of the second organic insulating layer 182 superimposed on the display area DA and the thickness of the second organic insulating layer 182 superimposed on the peripheral area PA may be substantially equal to each other. When the thickness of the second organic insulating layer 182 superimposed on the display area DA is the first height h1 and the thickness of the second organic insulating layer 182 superimposed on the peripheral area PA is the second height h2, the first height h1 and the second height h2 may be substantially equal to each other. Substantial equality not only indicates complete equality, but also indicates that there may be slight differences depending on, for example, process errors.

[0124] The second organic insulating layer 182 may include a second valley V2 in which the second organic insulating layer 182 is removed. The second valley V2 may block the movement path of moisture and the like introduced from outside the substrate 110 through the second organic insulating layer 182, so as to help prevent external moisture from penetrating into the display area DA.

[0125] In various exemplary embodiments, the first valley V1 and the second valley V2 may be superimposed on each other. The edges of the first valley V1 and the edges of the second valley V2 may be aligned while being superimposed on each other.

[0126] The third connection member 198 located on the same layer as the pixel electrode 191 may be located on the second organic insulating layer 182. The third connection member 198 may be connected to the power supply wiring 178 through the second connection member 188, and the third connection member 198 may be connected to the common electrode 270 overlapping the display area DA. The power supply wiring 178 may be connected to the common electrode 270 through the third connection member 198 and the second connection member 188. When the power supply wiring 178 transmits the common voltage ELVSS as the power supply voltage, the common electrode 270 may receive the common voltage ELVSS.

[0127] The third connection member 198 may be disposed in the first valley V1 and the second valley V2. The third connection member 198 may have a shape penetrating the first organic insulating layer 181 and the second organic insulating layer 182. When the first valley V1 and the second valley V2 are filled with a material other than the organic material (such as the third connection member 198), moisture or foreign particles can be prevented from penetrating into the display area DA.

[0128] At least one of the dams D1 and D2 may be disposed in the peripheral area PA. The dams D1 and D2 may be located on the third insulating layer 160.

[0129] The dams D1 and D2 may prevent the overflow of the organic material having fluidity (such as the monomer used in the process for forming the organic layer 392 of the encapsulation layer EN). The edge of the organic layer 392 of the encapsulation layer EN may be substantially closer to the inside than the dams D1 and D2. For example, it may be disposed inside the first dam D1. The edge of the organic layer 392 may be located between the dams D1 and D2 and the display area DA.

[0130] The encapsulation layer EN extending from the display area DA may be disposed in the peripheral area PA. The first inorganic layer 391 and the second inorganic layer 393 included in the encapsulation layer EN may extend to near the edge of the peripheral area PA where the third insulating layer 160 is provided.

[0131] The edge of the organic layer 392 included in the encapsulation layer EN may be located between the first dam D1 and the valleys V1 and V2. The organic layer 392 may be formed at a position close to the first dam D1 while filling the valleys V1 and V2.

[0132] The organic layer 392 may be formed of an organic material such as a monomer. The organic material may flow into the first valley V1 and the second valley V2 during the process for forming the organic layer 392. The height of the first valley V1 is determined by the thickness of the first organic insulating layer 181, and according to an exemplary embodiment, the thickness of the first organic insulating layer 181 provided in the peripheral region PA is thinner than the thickness of the first organic insulating layer 181 provided in the display region DA, so the height of the first valley V1 can be reduced. Therefore, the organic material provided during the process for forming the organic layer 392 may have an edge located between the first dam D1 and the valleys V1 and V2 while sufficiently filling the first valley V1 and the second valley V2. According to the present exemplary embodiment, the organic layer 392 and the encapsulation layer EN including the organic layer 392 may have a flat top surface.

[0133] Multiple touch lines TL connected to the touch electrode TP may be located on the top surface of the encapsulation layer EN. Since the touch lines TL are formed on a very flat top surface, they can be formed stably.

[0134] If the height of the first valley V1 is substantially the same as the thickness of the first organic insulating layer 181 provided in the display region DA, a large amount of organic material may be required to fill the first valley V1 and the second valley V2. In the case where the height of the first valley V1 is equal to the third height h3, the organic material may not be sufficient to flow to the periphery of the first dam D1, or may not completely fill the first valley V1 and the second valley V2. Therefore, the top surface of the organic layer 392 will be recessed, such that the organic layer 392 does not have a flat top surface. The touch lines TL connected to the touch electrode TP may be located on the top surface of the organic layer 392. If the top surface of the organic layer 392 is not planarized, it will not be easy to form the touch lines TL, and a short - circuit failure may occur.

[0135] Next, referring to Figure 4 , the substrate 110, the barrier layer 115, the buffer layer 120, the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 respectively extending from the display region DA may be sequentially stacked in the peripheral region PA.

[0136] In the peripheral region PA, crack dams CD may be provided at the edges of the first insulating layer 141, the edges of the second insulating layer 142, and the edges of the third insulating layer 160. The crack dams CD can prevent the spread of cracks that may occur in inorganic insulating layers such as the barrier layer 115 and the buffer layer 120 when the display panel 10 is cut corresponding to the edge of the substrate 110.

[0137] The power supply wiring 178 may be located on a part of the third insulating layer 160 provided in the peripheral area PA. The power supply wiring 178 may be on the same layer as the source electrode 173 and the drain electrode 175 provided in the display area DA. The power supply wiring 178 may be formed of the same material as the first data conductor including the source electrode 173 and the drain electrode 175 in the same process.

[0138] The power supply wiring 178 may transmit a power supply voltage having a predetermined level that can be applied to the light emitting diode LED, and may transmit, for example, a common voltage ELVSS.

[0139] The first organic insulating layer 181 may be located on the power supply wiring 178 and the third insulating layer 160. The thickness of the first organic insulating layer 181 provided in the peripheral area PA may be different from the thickness of the first organic insulating layer 181 provided in the display area DA. For example, the first organic insulating layer 181 superimposed on the display area DA may have a third height h3, and the first organic insulating layer 181 superimposed on the peripheral area PA may have a fourth height h4. In the present exemplary embodiment, the third height h3 may be higher than the fourth height h4. For example, the third height h3 may be approximately twice the fourth height h4.

[0140] The first organic insulating layer 181 having a plurality of regions (each region having a different height) may be formed by a single process. For example, it may be formed by using a halftone mask.

[0141] The first organic insulating layer 181 superimposed on the peripheral area PA may include a first valley V1 in which the first organic insulating layer 181 is removed.

[0142] The height of the first valley V1 may be substantially the same as the thickness of the first organic insulating layer 181 provided in the peripheral area PA. The height of the first valley V1 may be substantially the same as the fourth height h4.

[0143] The drive control signal line 179 and the second connection member 188 may be located on the first organic insulating layer 181. The drive control signal line 179 and the second connection member 188 may be on the same layer as the first connection member 177 provided in the display area DA. The drive control signal line 179 and the second connection member 188 may be formed by the same process as the first connection member 177 and may include the same material as the first connection member 177.

[0144] The second connection member 188 may be located on the first organic insulating layer 181 and may be connected to the power supply wiring 178. A part of the first organic insulating layer 181 superimposed on the power supply wiring 178 may be removed for the connection between the second connection member 188 and the power supply wiring 178.

[0145] The second organic insulating layer 182 may be located on the driving control signal lines 179 and the second connection member 188.

[0146] The thickness of the second organic insulating layer 182 that overlaps with the display area DA and the thickness of the second organic insulating layer 182 that overlaps with the peripheral area PA may be different from each other. The thickness of the second organic insulating layer 182 provided in the peripheral area PA may be less than the thickness of the second organic insulating layer 182 provided in the display area DA. The second organic insulating layer 182 that overlaps with the display area DA may have a first height h1, and the second organic insulating layer 182 provided in the peripheral area PA may have a second height h2. In the present exemplary embodiment, the first height h1 may be higher than the second height h2. For example, the first height h1 may be approximately twice the second height h2.

[0147] The second organic insulating layer 182 having a plurality of regions (each region having a different height) may be formed by a single process. For example, it may be formed by using a halftone mask.

[0148] The second organic insulating layer 182 may include a second valley V2. The height of the second valley V2 may be substantially the same as the thickness of the second organic insulating layer 182 provided in the peripheral area PA. For example, the second valley V2 may have a second height h2. The second valley V2 represents a region from which the second organic insulating layer 182 is removed.

[0149] In various exemplary embodiments, the first valley V1 and the second valley V2 may overlap with each other. The edges of the first valley V1 and the edges of the second valley V2 may be aligned while overlapping with each other.

[0150] The third connection member 198 located on the same layer as the pixel electrode 191 may be located on the second organic insulating layer 182. The third connection member 198 and the pixel electrode 191 may be formed of the same material by the same process.

[0151] The third connection member 198 may be connected to the power supply wiring 178 through the second connection member 188, and the third connection member 198 may be connected to the common electrode 270 that overlaps with the display area DA. The power supply wiring 178 may be connected to the common electrode 270 through the third connection member 198 and the second connection member 188. When the power supply wiring 178 transmits the common voltage ELVSS as the power supply voltage, the common electrode 270 may receive the common voltage ELVSS.

[0152] The third connecting member 198 may be disposed in the first valley V1 and the second valley V2. The third connecting member 198 may have a shape that penetrates the first organic insulating layer 181 and the second organic insulating layer 182. When the first valley V1 and the second valley V2 are filled with a material other than the organic material (such as the third connecting member 198), moisture or foreign particles can be prevented from penetrating into the display area DA.

[0153] The encapsulation layer EN may include a first inorganic layer 391, an organic layer 392, and a second inorganic layer 393. In the present exemplary embodiment, the edge of the organic layer 392 may be located between the first dam D1 and the valleys V1 and V2. The organic layer 392 may be formed at a position adjacent to the first dam D1 while filling the valleys V1 and V2.

[0154] The organic layer 392 may be formed of an organic material such as a monomer. The organic material may flow into the first valley V1 and the second valley V2 during the process for forming the organic layer 392. The height of the first valley V1 may be determined by the thickness of the first organic insulating layer 181, and the height of the second valley V2 may be determined by the thickness of the second organic insulating layer 182. According to the present exemplary embodiment, the thickness of the first organic insulating layer 181 provided in the peripheral area PA is thinner than the thickness of the first organic insulating layer 181 provided in the display area DA, so the height of the first valley V1 can be reduced. Similarly, the thickness of the second organic insulating layer 182 provided in the peripheral area PA is thinner than the thickness of the second organic insulating layer 182 provided in the display area DA, so the height of the second valley V2 can be reduced. Therefore, the organic material provided during the process for forming the organic layer 392 may have an edge located between the first dam D1 and the valleys V1 and V2 while sufficiently filling the first valley V1 and the second valley V2. According to the present exemplary embodiment, the organic layer 392 may have a flat top surface.

[0155] A plurality of touch lines TL connected to the touch electrode TP may be located on the top surface of the encapsulation layer EN.

[0156] When the heights of the first valley V1 and the second valley V2 are substantially the same as the thicknesses of the first organic insulating layer 181 and the second organic insulating layer 182 provided in the display area DA, a large amount of organic material may be required to fill the first valley V1 and the second valley V2. In the case where the heights of the first valley V1 and the second valley V2 are equal to the third height h3 and the first height h1, the organic material may not be sufficient to flow to the periphery of the first dam D1, or may not completely fill the first valley V1 and the second valley V2. Therefore, the top surface of the organic layer 392 may be recessed, such that the organic layer 392 does not have a flat top surface. The touch lines TL connected to the touch electrode TP may be located on the top surface of the organic layer 392. If the top surface of the organic layer 392 is not planarized, it may not be easy to form the touch lines TL, and a short circuit failure may occur.

[0157] Next, with reference to Figure 5 , the base 110, the barrier layer 115, the buffer layer 120, the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 respectively extending from the display area DA can be sequentially stacked in the peripheral area PA.

[0158] In the peripheral area PA, crack dams CD can be provided at the edges of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160. The crack dams CD can prevent the spread of cracks, which may occur in inorganic insulating layers such as the barrier layer 115 and the buffer layer 120 when the display panel 10 is cut corresponding to the edge of the base 110. The crack dams CD can be formed of an organic material. For example, they can be formed of the same material as at least one of the first organic insulating layer 181, the second organic insulating layer 182, and the barrier ribs 360 by the same process.

[0159] The power supply wiring 178 can be located on a part of the third insulating layer 160 provided in the peripheral area PA. The power supply wiring 178 can be on the same layer as the source electrode 173 and the drain electrode 175 provided in the display area DA. The power supply wiring 178 can be formed of the same material as the first data conductor including the source electrode 173 and the drain electrode 175 in the same process.

[0160] The power supply wiring 178 can transmit a power supply voltage having a predetermined level that can be applied to the light-emitting diode LED, and can transmit, for example, a common voltage ELVSS.

[0161] The first organic insulating layer 181 can be located on the power supply wiring 178 and the third insulating layer 160.

[0162] The first organic insulating layer 181 superimposed on the peripheral area PA can include a first valley V1 in which the first organic insulating layer 181 is removed. The first valley V1 can block the movement of moisture introduced through the first organic insulating layer 181 to help prevent moisture from penetrating into the display area DA.

[0163] The power supply wiring 178 according to the present exemplary embodiment can extend toward the display area DA. For example, the power supply wiring 178 can be partially superimposed on the first valley V1. The first valley V1 can expose the power supply wiring 178 partially.

[0164] The driving control signal line 179 and the second connection member 188 may be located on the first organic insulating layer 181. The driving control signal line 179 and the second connection member 188 may be located on the same layer as the first connection member 177 provided in the display area DA. The driving control signal line 179 and the second connection member 188 may be formed by the same process as the first connection member 177 and may include the same material as the first connection member 177.

[0165] The second connection member 188 may be located on the first organic insulating layer 181 and may be connected to the power supply wiring 178. A part of the first organic insulating layer 181 that overlaps with the power supply wiring 178 may be removed for the connection between the second connection member 188 and the power supply wiring 178. In an embodiment, the second connection member 188 may be connected to the power supply wiring 178 through the first valley V1, and in an exemplary embodiment, this part of the first organic insulating layer 181 may not be removed.

[0166] The second connection member 188 may be disposed in the first valley V1. The second connection member 188 may extend toward the display area DA while filling the first valley V1. The second connection member 188 may be connected to the power supply wiring 178 through the first valley V1.

[0167] The second organic insulating layer 182 may be located on the driving control signal line 179 and the second connection member 188. The second organic insulating layer 182 may include a second valley V2 in which the second organic insulating layer 182 is removed.

[0168] In various exemplary embodiments, the first valley V1 and the second valley V2 may overlap each other. The first valley V1 and the second valley V2 may be aligned at their edges while overlapping each other.

[0169] The third connection member 198 located on the same layer as the pixel electrode 191 may be located on the second organic insulating layer 182. The third connection member 198 and the pixel electrode 191 may be formed of the same material by the same process.

[0170] The third connection member 198 may be connected to the power supply wiring 178 through the second connection member 188. The third connection member 198 may be connected to the common electrode 270 that overlaps with the display area DA. The power supply wiring 178 may be connected to the common electrode 270 through the third connection member 198 and the second connection member 188. When the power supply wiring 178 transmits the common voltage ELVSS as the power supply voltage, the common electrode 270 may receive the common voltage ELVSS.

[0171] The third connection member 198 may be disposed in the first valley V1 and the second valley V2. The third connection member 198 may have a shape that penetrates the first organic insulating layer 181 and the second organic insulating layer 182. The third connection member 198 may contact the second connection member 188 in the first valley V1 and the second valley V2. The third connection member 198 is connected to the second connection member 188 through the second valley V2, and the second connection member 188 is connected to the power supply wiring 178 through the first valley V1, so that the common voltage ELVSS can be transmitted.

[0172] The first valley V1 and the second valley V2 may be mainly filled with materials other than organic materials, such as the second connection member 188 and the third connection member 198. Therefore, moisture or foreign particles can be prevented from penetrating into the display area DA through the first valley V1 and the second valley V2.

[0173] At least one of the dams D1 and D2 may be disposed in the peripheral area PA. The dams D1 and D2 can prevent the overflow of the organic material having fluidity, such as the monomer used in the process of forming the organic layer 392 of the encapsulation layer EN. Therefore, the edge of the organic layer 392 of the encapsulation layer EN can be substantially closer to the inside than the dams D1 and D2. For example, it can be disposed inside the first dam D1.

[0174] The edge of the organic layer 392 may be located between the dams D1 and D2 and the display area DA. The edge of the organic layer 392 may be located between the first dam D1 and the valleys V1 and V2. The organic layer 392 may extend to a position adjacent to the first dam D1 while filling the valleys V1 and V2.

[0175] The organic layer 392 may be formed of an organic material such as a monomer. The organic material may flow into the first valley V1 and the second valley V2 during the process of forming the organic layer 392. In the present exemplary embodiment, the first valley V1 is in a state filled with the second connection member 188, and the second valley V2 is in a state filled with the third connection member 198. Therefore, the organic material provided during the process of forming the organic layer 392 may have an edge located between the first dam D1 and the valleys V1 and V2, and the first valley V1 and the second valley V2 can be sufficiently filled even with a small amount of organic material. The organic layer 392 formed on such a structure may have a flattened top surface.

[0176] Multiple touch lines TL connected to the touch electrode TP may be located on the top surface of the encapsulation layer EN.

[0177] Hereinafter, reference will be made to Figure 6 and Figure 7 describe the display area of the display device according to the present exemplary embodiment. Figure 6 is a circuit diagram of one pixel of the display device according to the present exemplary embodiment, Figure 7Schematic cross-sectional view of a pixel of a display device according to an exemplary embodiment.

[0178] First, referring to Figure 6 , the pixel PX may be an area divided by a plurality of signal lines 121, 171, and 172. The pixel PX may be the smallest unit for displaying an image. The display device displays an image by using a plurality of pixels PX.

[0179] The signal lines 121, 171, and 172 may include a plurality of gate lines 121 that transmit gate signals (or scan signals), a plurality of data lines 171 that transmit data signals, and a plurality of driving voltage lines (first driving voltage lines) 172 that transmit a driving voltage ELVDD. In the present exemplary embodiment, the data lines 171 and the driving voltage lines 172 are included in a data conductor, and the gate lines 121 will be referred to as gate conductors.

[0180] The gate lines 121 may extend substantially in the row direction and be substantially parallel to each other, and the vertical portions of the data lines 171 and the driving voltage lines 172 may extend substantially in the column direction and be substantially parallel to each other.

[0181] Each pixel PX may include a switching thin film transistor Qs, a driving thin film transistor Qd, a storage capacitor Cst, and a light emitting diode LED. Each pixel PX may also include a transistor and a capacitor for compensating the current supplied to the light emitting diode LED.

[0182] In the present exemplary embodiment, the switching thin film transistor Qs transmits the data signal applied to the data line 171 to the driving thin film transistor Qd in response to a scan signal applied to the gate line 121. The driving thin film transistor Qd has an output current I LD , and the magnitude of this output current I LD varies according to the voltage applied between the control terminal and the output terminal. The storage capacitor Cst is charged with an electric charge corresponding to the data signal applied to the control terminal of the driving thin film transistor Qd, and maintains this electric charge even after the switching thin film transistor Qs is turned off.

[0183] In the present exemplary embodiment, the light emitting diode LED includes an anode connected to the output terminal of the driving thin film transistor Qd and a cathode connected to a power supply wiring 178 (see Figures 2 to 5 ) that transmits a common voltage ELVSS. The light emitting diode LED displays an image by changing its intensity according to the output current I LD of the driving thin film transistor Qd.

[0184] Next, referring to Figure 7 , the interlayer structure of the region provided with the storage capacitor, the driving thin film transistor (referred to as "transistor" in the following) etc. will be described. References may be omitted in the following descriptionFigure 2 Repeated descriptions of similar features are provided.

[0185] The barrier layer 115 may be located on the substrate 110 to help prevent the penetration of externally introduced moisture or foreign particles. The buffer layer 120 may be located on the barrier layer 115. The buffer layer 120 may block impurities and may reduce the stress applied to the substrate 110, and the impurities may diffuse from the substrate 110 to the semiconductor layer 130 during the process for forming the semiconductor layer 130. Each of the barrier layer 115 and the buffer layer 120 may include an inorganic insulating material such as silicon oxide, silicon nitride, etc.

[0186] The semiconductor layer 130 may be located on the buffer layer 120. The semiconductor layer 130 may include a source region 131, a drain region 132, and a channel region 133 that overlaps with the gate electrode 124a. In the present exemplary embodiment, the source region 131 and the drain region 132 are respectively provided on opposite sides of the channel region 133 and are doped with impurities. The semiconductor layer 130 may include polysilicon, amorphous silicon, or an oxide semiconductor.

[0187] The first insulating layer 141 including an inorganic insulating material (such as silicon oxide, silicon nitride, etc.) or an organic insulating material may be located on the semiconductor layer 130. The first insulating layer 141 may also be referred to as the first gate insulating layer.

[0188] The first gate conductor including the scan line and the gate electrode 124a of the transistor may be located on the first insulating layer 141.

[0189] The second insulating layer 142 may be located on the first insulating layer 141 and the first gate conductor. The second insulating layer 142 may include an inorganic insulating material (such as silicon oxide, silicon nitride, etc.) or an organic insulating material. The second insulating layer 142 may also be referred to as the second gate insulating layer.

[0190] The second gate conductor such as the storage line including the storage electrode 124b may be located on the second insulating layer 142. The gate electrode 124a and the storage electrode 124b may form the storage capacitor Cst described with reference to Figure 6 the description.

[0191] The third insulating layer 160 may be located on the second gate conductor. The third insulating layer 160 may include an inorganic insulating material (such as silicon oxide, silicon nitride, etc.) or an organic insulating material.

[0192] The first data conductor including the data line 171, the first driving voltage line 172, and the source electrode 173 and the drain electrode 175 of the transistor may be located on the third insulating layer 160.

[0193] Each of the source electrode 173 and the drain electrode 175 may be connected to the source region 131 and the drain region 132 of the semiconductor layer 130 through contact holes formed in the third insulating layer 160, the second insulating layer 142, and the first insulating layer 141, respectively.

[0194] In the present exemplary embodiment, the gate electrode 124a, the source electrode 173, and the drain electrode 175 together with the semiconductor layer 130 form a transistor. In the transistor shown in the drawings, the gate electrode 124a is disposed above the semiconductor layer 130, but the structure of the transistor may be modified differently.

[0195] The first organic insulating layer 181 may be located on the third insulating layer 160 and the first data conductor. The first organic insulating layer 181 may include an organic insulating material, for example, may include polyimide, acrylic polymer, silicone polymer, etc.

[0196] The second data conductor including the first connection member 177 and the second driving voltage line 177b may be located on the first organic insulating layer 181.

[0197] The first connection member 177 may connect the drain electrode 175 and the pixel electrode 191. The second driving voltage line 177b may be connected to the first driving voltage line 172 and may transmit a driving voltage. The second driving voltage line 177b may reduce resistance by being connected to the first driving voltage line 172, and may provide a display panel with high brightness and high frequency.

[0198] In the present exemplary embodiment, the second organic insulating layer 182 is located on the second data conductor and the first organic insulating layer 181. The second organic insulating layer 182 may include an organic insulating material, and may include, for example, polyimide, acrylic polymer, etc.

[0199] The pixel electrode 191 of the light-emitting diode LED may be located on the second organic insulating layer 182. The pixel electrode 191 may be connected to the first connection member 177 through a contact hole formed in the second organic insulating layer 182, and may be connected to the drain electrode 175 through the first connection member 177.

[0200] The barrier rib 360 having an opening overlapping with the pixel electrode 191 may be located on the second organic insulating layer 182. The opening of the barrier rib 360 may define each pixel region. The barrier rib 360 may be referred to as a pixel defining layer. The barrier rib 360 may include an organic insulating material or an inorganic insulating material.

[0201] In the present exemplary embodiment, the emission layer 370 is located on the pixel electrode 191 overlapping with the opening of the barrier rib 360, and the common electrode 270 is located on the emission layer 370.

[0202] In the present exemplary embodiment, a pixel electrode 191, an emission layer 370, and a common electrode 270 of each pixel PX form a light-emitting diode LED such as an organic light-emitting diode. According to the light-emitting direction of the light-emitting diode LED, the display device may have a structure of any one of a front display type, a rear display type, and a single-panel dual-display type.

[0203] Above the common electrode 270, as previously referred to Figure 2 and described, an encapsulation layer EN and a touch electrode TP may be sequentially provided.

[0204] By summarizing and reviewing, instead of sealing the light-emitting element by using an encapsulation substrate, an encapsulation layer may be formed on the light-emitting element, which may reduce the weight of the display panel and lower the possibility of damaging the display panel. Most of the display panel may be a display area for displaying an image, but a specific area of the display panel (for example, an edge area of the display panel) may be a peripheral area where a driving circuit, signal lines, etc. are provided.

[0205] The exemplary embodiment may provide a display panel in which an organic layer of the encapsulation layer provided in the peripheral area may have a flat top surface. Accordingly, a touch line formed on the encapsulation layer may be stably formed. Accordingly, a display device having improved reliability may be provided. The exemplary embodiment may provide a display device in which a top surface of the encapsulation layer (for example, an organic layer included in the encapsulation layer) provided in the peripheral area may be made flat, which may contribute to enabling a touch line to be formed on the encapsulation layer.

[0206] <Description of symbols> DA: Display area PA: Peripheral area 110: Substrate 191: Pixel electrode 270: Common electrode.

[0207] Exemplary embodiments have been disclosed herein. Although specific terms have been employed, they are used in a general and descriptive sense only and are to be construed, not for purposes of limitation. In some instances, it will be apparent to those of ordinary skill in the art from the time of filing of this application that, unless otherwise specifically stated, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display device, the display device comprises: a substrate including a display area and a peripheral area; a transistor in the display area; a first electrode electrically connected to the transistor; a second electrode stacked with the first electrode; an organic insulating layer between the first electrode and the substrate and stacked with at least a part of the peripheral area, a via penetrating the organic insulating layer and stacked with the peripheral area; a first metal layer under the organic insulating layer and stacked with the via; and a second metal layer and a third metal layer, at least partially disposed in the via, wherein the first metal layer and the second metal layer are in direct contact with each other, and the second metal layer and the third metal layer are in direct contact with each other.

2. The display device according to claim 1, wherein the transistor comprises: a semiconductor layer on the substrate; a gate electrode stacked with the semiconductor layer; and a source electrode and a drain electrode connected to the semiconductor layer, wherein the display device further comprises a first connection member on the drain electrode and connecting the first electrode and the drain electrode.

3. The display device according to claim 2, wherein the first metal layer and the source electrode are disposed in the same layer.

4. The display device according to claim 2, wherein the second metal layer and the first connection member are disposed in the same layer.

5. The display device according to claim 2, wherein the third metal layer and the first electrode are disposed in the same layer.

6. The display device according to claim 2, wherein the organic insulating layer comprises: a first organic insulating layer between the source electrode and the first connection member and between the drain electrode and the first connection member; and a second organic insulating layer between the first connection member and the first electrode.

7. The display device according to claim 6, wherein a part of the first organic insulating layer is disposed between the first metal layer and the second metal layer.

8. The display device according to claim 6, wherein a part of the second organic insulating layer is disposed between the second metal layer and the third metal layer.

9. The display device according to claim 1, wherein the display device further comprises a packaging layer on the second electrode and stacked with the display area and the peripheral area, and the packaging layer comprises: a first inorganic layer and a second inorganic layer; and an organic layer between the first inorganic layer and the second inorganic layer.

10. The display device according to claim 9, the display device further comprises: a touch line on the packaging layer, the touch line stacked with the peripheral area; and a touch electrode on the packaging layer, the touch electrode stacked with the display area.

11. The display device according to claim 10, wherein a side of the packaging layer where the touch line is disposed and a side of the packaging layer where the touch electrode is disposed have a step difference.

12. The display device according to claim 9, wherein the organic layer is disposed in the via.

13. The display device according to claim 9, wherein the display device further comprises a dam provided in the peripheral region, wherein, the distance from the dam to the edge of the display region is greater than the distance from the edge of the organic layer to the edge of the display region.

14. The display device according to claim 6, wherein, the organic insulating layer comprises: the first organic insulating layer, including a first valley; and the second organic insulating layer, including a second valley.

15. The display device according to claim 14, wherein the display device further comprises a packaging layer provided on the second electrode, wherein, the packaging layer comprises: a first inorganic layer and a second inorganic layer; and an organic layer provided between the first inorganic layer and the second inorganic layer, and the organic layer is provided in the second valley.

16. The display device according to claim 1, wherein, the thickness of the portion of the organic insulating layer overlapping with the display region and the thickness of the portion of the organic insulating layer overlapping with the peripheral region are different from each other.

17. A display device, the display device comprises: a substrate, including a display region and a peripheral region; a transistor in the display region; a first electrode electrically connected to the transistor; a second electrode overlapping with the first electrode; a light-emitting layer between the first electrode and the second electrode; and an organic insulating layer between the first electrode and the transistor and overlapping with at least a part of the peripheral region, wherein the transistor comprises a semiconductor layer on the substrate, a gate electrode overlapping with the semiconductor layer, and a source electrode and a drain electrode connected to the semiconductor layer, and wherein a first thickness of the organic insulating layer provided in the display region is greater than a second thickness of the organic insulating layer provided in the peripheral region.

18. The display device according to claim 17, wherein the display device further comprises: a first connection member between the drain electrode and the first electrode, wherein the organic insulating layer overlaps with the first connection member, and the organic insulating layer is in direct contact with the first connection member.

19. The display device according to claim 17, wherein the display device further comprises: a valley penetrating the organic insulating layer and overlapping with the peripheral region.

20. The display device according to claim 19, wherein, the display device further comprises a packaging layer on the second electrode and overlapping with the display region and the peripheral region, and the packaging layer comprises: a first inorganic layer and a second inorganic layer; and an organic layer between the first inorganic layer and the second inorganic layer.

21. The display device according to claim 20, wherein, the valley overlaps with the organic layer of the packaging layer.

22. The display device according to claim 20, wherein the display device further comprises: a touch line provided on the packaging layer, the touch line overlapping with the peripheral region, and at least one touch line in the touch lines overlaps with the valley.

23. The display device according to claim 19, wherein the display device further comprises: A metal layer, which is disposed on the same layer as the first electrode, and the metal layer is disposed on a side surface of the valley.

24. The display device according to claim 23, wherein the metal layer is in direct contact with a first inorganic layer of the encapsulation layer.

25. The display device according to claim 18, wherein the organic insulating layer includes: a first organic insulating layer between the source electrode and the first connection member and between the drain electrode and the first connection member; and a second organic insulating layer between the first connection member and the first electrode.

26. A display device, the display device comprising: a substrate including a display area and a peripheral area; a transistor in the display area; a light-emitting diode connected to the transistor; an organic insulating layer between the transistor and the light-emitting diode; and a touch sensing layer disposed on the light-emitting diode, wherein the touch sensing layer includes touch electrodes and touch lines, and a first thickness of the organic insulating layer overlapping with the touch electrodes is different from a second thickness of the organic insulating layer overlapping with the touch lines.

27. The display device according to claim 26, wherein the first thickness of the organic insulating layer overlapping with the touch electrodes is greater than the second thickness of the organic insulating layer overlapping with the touch lines.

28. The display device according to claim 26, wherein the transistor includes a semiconductor layer on the substrate, a gate electrode overlapping with the semiconductor layer, and a source electrode and a drain electrode connected to the semiconductor layer, and the light-emitting diode includes a first electrode, a light-emitting layer, and a second electrode.

29. The display device according to claim 28, the display device further comprising: a first connection member disposed between the drain electrode and the first electrode.

30. The display device according to claim 29, wherein the organic insulating layer includes a first organic insulating layer between the source electrode and the first connection member and between the drain electrode and the first connection member.

31. The display device according to claim 30, wherein a first thickness of the first organic insulating layer overlapping with the touch electrodes is different from a second thickness of the first organic insulating layer overlapping with the touch lines.

32. The display device according to claim 30, wherein the first thickness of the first organic insulating layer overlapping with the touch electrodes is greater than the second thickness of the first organic insulating layer overlapping with the touch lines.

33. The display device according to claim 29, wherein the organic insulating layer includes a second organic insulating layer between the first connection member and the first electrode.

34. The display device according to claim 33, wherein a first thickness of the second organic insulating layer overlapping with the touch electrodes is different from a second thickness of the second organic insulating layer overlapping with the touch lines.

35. The display device according to claim 33, wherein the first thickness of the second organic insulating layer overlapping with the touch electrodes is greater than the second thickness of the second organic insulating layer overlapping with the touch lines.

36. The display device according to claim 29, wherein, the organic insulating layer includes: a first organic insulating layer between the source electrode and the first connection member and between the drain electrode and the first connection member; and a second organic insulating layer between the first connection member and the first electrode.

37. The display device according to claim 36, wherein, a first thickness of the first organic insulating layer stacked with the touch electrode is different from a second thickness of the first organic insulating layer stacked with the touch line, and a first thickness of the second organic insulating layer stacked with the touch electrode is different from a second thickness of the second organic insulating layer stacked with the touch line.

38. The display device according to claim 36, wherein, a first thickness of the first organic insulating layer stacked with the touch electrode is greater than a second thickness of the first organic insulating layer stacked with the touch line, and a first thickness of the second organic insulating layer stacked with the touch electrode is greater than a second thickness of the second organic insulating layer stacked with the touch line.

39. The display device according to claim 26, the display device further comprises: a valley penetrating the organic insulating layer and overlapping with the peripheral region.

40. The display device according to claim 39, wherein, the valley is wider at the top of the organic insulating layer than at the bottom of the organic insulating layer, and the bottom of the valley directly contacts the electrical insulating layer.

41. The display device according to claim 39, wherein, the light-emitting diode includes a first electrode, a light-emitting layer, and a second electrode.

42. The display device according to claim 41, the display device further comprises: a metal layer disposed on the same layer as the first electrode, wherein the metal layer is disposed on a side surface of the valley.

43. The display device according to claim 39, the display device further comprises: a packaging layer on the light-emitting diode and overlapping with the display region and the peripheral region.

44. The display device according to claim 43, wherein, the touch line is disposed on the packaging layer, the touch line overlaps with the peripheral region, and at least one touch line of the touch lines overlaps with the valley.

45. The display device according to claim 43, wherein, the packaging layer includes: a first inorganic layer and a second inorganic layer; and an organic layer between the first inorganic layer and the second inorganic layer, and the valley overlaps with the organic layer of the packaging layer.

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