Organic light emitting diode display

Abstract

An organic light emitting diode display is disclosed. The organic light emitting diode display includes a substrate; and a pixel disposed on the substrate; wherein the pixel includes: an organic light emitting element; and a driving transistor applying a current to the organic light emitting element; the driving transistor includes: a first gate electrode; and a semiconductor layer including a channel, in which a first gate electrode of the driving transistor is arranged between the semiconductor layer of the driving crystal and the substrate, in which an overlapping layer of the driving transistor is arranged between the substrate and the first gate electrode of the driving transistor, and in which the overlapping layer of the driving transistor is arranged between the substrate and the first gate electrode of the driving transistor. The first gate electrode and the overlapping layer are arranged in a region between the semiconductor layer of the driving transistor and the substrate, and the first gate electrode and the overlapping layer overlap in the region between the semiconductor layer of the driving transistor and the substrate in a plan view.

Description

[0001] This application is a divisional application of a patent application for an invention titled "Organic Light-Emitting Diode Display Device" with an application date of June 27, 2019 and an application number of 201910564788.1.

[0002] Cross-reference to Related Applications

[0003] This application claims priority to Korean Patent Application No. 10-2018-0074950, filed with the Korean Intellectual Property Office on June 28, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] Exemplary embodiments of the present invention relate to an organic light-emitting diode display. Background Art

[0005] Organic light-emitting diode displays have self-emitting characteristics. Since organic light-emitting diode displays do not require a separate light source, they can have a relatively small thickness and weight, unlike liquid crystal displays. In addition, organic light-emitting diode displays exhibit high-quality characteristics such as low power consumption, high brightness, and high response speed.

[0006] Generally, an organic light-emitting diode display includes a substrate, a plurality of thin film transistors positioned on the substrate, a plurality of insulating layers disposed between wirings constituting the thin film transistors, and an organic light-emitting element connected to the thin film transistors. Summary of the Invention

[0007] Exemplary embodiments of the present invention reduce the thickness of the display device and improve the display device by, for example, removing or reducing transient image persistence, although there are protrusions formed in the polycrystalline semiconductor layer of the display device.

[0008] According to an exemplary embodiment, an organic light-emitting diode display includes a substrate; and pixels disposed on the substrate; wherein each pixel includes: an organic light-emitting element; and a driving transistor that applies current to the organic light-emitting element; wherein the driving transistor includes: a first gate electrode; and a semiconductor layer including a channel, wherein the first gate electrode of the driving transistor is disposed between the semiconductor layer of the driving transistor and the substrate, wherein an overlapping layer of the driving transistor is disposed between the substrate and the first gate electrode of the driving transistor, and wherein the first gate electrode and the overlapping layer are disposed in a region between the semiconductor layer of the driving transistor and the substrate, and in a plan view, the first gate electrode and the overlapping layer overlap in the region between the semiconductor layer of the driving transistor and the substrate.

[0009] According to an exemplary embodiment, an organic light emitting diode display includes a substrate; pixels disposed on the substrate; scan lines; data lines; driving voltage lines; and initialization voltage lines, wherein the scan lines, data lines, driving voltage lines, and initialization voltage lines are connected to the pixels, and wherein each pixel includes: an organic light emitting element; a first switching transistor connected to the scan line; a driving transistor that applies current to the organic light emitting element; and a compensation transistor that compensates for the operation of the driving transistor, wherein the driving transistor includes: a bottom gate electrode; and a semiconductor layer including a channel, and wherein the compensation transistor includes: a semiconductor layer including a channel; a first gate electrode disposed on the semiconductor layer of the compensation transistor; and a second gate electrode disposed under the semiconductor layer of the compensation transistor, and wherein the bottom gate electrode of the driving transistor is disposed between the semiconductor layer of the driving transistor and the substrate.

[0010] According to an exemplary embodiment, an organic light emitting diode display includes a substrate, pixels disposed on the substrate, scan lines, data lines, driving voltage lines, and initialization voltage lines. The scan lines, data lines, driving voltage lines, and initialization voltage lines are connected to the pixels. Each pixel includes an organic light emitting element, a first switching transistor connected to the scan line, a driving transistor that applies current to the organic light emitting element, and a compensation transistor that compensates for the operation of the driving transistor. The driving transistor includes a first gate electrode and a polycrystalline semiconductor layer, the first gate electrode is disposed on the substrate, and the polycrystalline semiconductor layer is disposed on the first gate electrode and includes a first electrode, a second electrode, and a channel. The compensation transistor includes a polycrystalline semiconductor layer and a first gate electrode, the polycrystalline semiconductor layer includes a first electrode, a second electrode, and a channel, and the first gate electrode is disposed on the polycrystalline semiconductor layer of the compensation transistor.

[0011] In an exemplary embodiment, the driving transistor further includes a second gate electrode disposed on the polycrystalline semiconductor layer of the driving transistor.

[0012] In an exemplary embodiment, the second gate electrode of the driving transistor receives a driving voltage flowing to the driving voltage line.

[0013] In an exemplary embodiment, the driving transistor further includes an overlap layer disposed between the substrate and the first gate electrode of the driving transistor.

[0014] In an exemplary embodiment, the driving voltage flowing to the driving voltage line is applied to the overlap layer.

[0015] In an exemplary embodiment, the organic light emitting diode display further includes a driving voltage applying unit that applies a driving voltage to the overlap layer and the second gate electrode of the driving transistor.

[0016] In an exemplary embodiment, the organic light emitting diode display further includes a second switching transistor. The first switching transistor is connected to a scan line and a data line, and the second switching transistor is connected to the scan line and a first gate electrode of the driving transistor.

[0017] In an exemplary embodiment, the first switching transistor includes a polycrystalline semiconductor layer and a first gate electrode. The polycrystalline semiconductor layer includes a first electrode, a second electrode, and a channel, and the first gate electrode is disposed on the polycrystalline semiconductor layer of the first switching transistor.

[0018] In an exemplary embodiment, the first switching transistor further includes a second gate electrode disposed under the polycrystalline semiconductor layer of the first switching transistor. A driving voltage flowing to a driving voltage line is applied to the second gate electrode of the first switching transistor.

[0019] In an exemplary embodiment, the first switching transistor includes a gate electrode and a polycrystalline semiconductor layer. The gate electrode is disposed on a substrate, and the polycrystalline semiconductor layer is disposed on the gate electrode of the first switching transistor and includes a first electrode, a second electrode, and a channel.

[0020] In an exemplary embodiment, the second switching transistor includes a polycrystalline semiconductor layer and a first gate electrode. The polycrystalline semiconductor layer includes a first electrode, a second electrode, and a channel, and the first gate electrode is disposed on the polycrystalline semiconductor layer of the second switching transistor.

[0021] In an exemplary embodiment, the second switching transistor further includes a second gate electrode disposed under the polycrystalline semiconductor layer of the second switching transistor. The second gate electrode of the second switching transistor receives a driving voltage flowing to a driving voltage line.

[0022] In an exemplary embodiment, the first switching transistor includes a polycrystalline semiconductor layer and a first gate electrode. The polycrystalline semiconductor layer includes a first electrode, a second electrode, and a channel, and the first gate electrode is disposed on the polycrystalline semiconductor layer of the first switching transistor.

[0023] In an exemplary embodiment, the first switching transistor further includes a second gate electrode disposed under the polycrystalline semiconductor layer of the first switching transistor. The second gate electrode of the first switching transistor receives a driving voltage flowing to a driving voltage line.

[0024] In an exemplary embodiment, the driving transistor further includes an overlapping layer disposed between the substrate and the first gate electrode of the driving transistor. The overlapping layer receives a driving voltage, and the overlapping layer is electrically connected to the second gate electrode of the second switching transistor so that the driving voltage is applied to the second gate electrode of the second switching transistor.

[0025] In an exemplary embodiment, the organic light emitting diode display further includes a driving voltage applying unit. The driving transistor further includes a second gate electrode disposed on the polycrystalline semiconductor layer of the driving transistor, and the driving voltage applying unit applies a driving voltage to the overlapping layer and the second gate electrode of the driving transistor.

[0026] In an exemplary embodiment, the second switching transistor includes a gate electrode and a polycrystalline semiconductor layer. The gate electrode is disposed on a substrate, and the polycrystalline semiconductor layer is disposed on the gate electrode of the second switching transistor and includes a first electrode, a second electrode, and a channel.

[0027] In an exemplary embodiment, the compensation transistor initializes the first gate electrode of the driving transistor.

[0028] In an exemplary embodiment, the compensation transistor further includes a second gate electrode disposed under the polycrystalline semiconductor layer of the compensation transistor. The second gate electrode of the compensation transistor receives the driving voltage flowing to the driving voltage line.

[0029] According to an exemplary embodiment, an organic light emitting diode display includes a substrate, pixels disposed on the substrate, scan lines, data lines, a driving voltage line, and an initialization voltage line. The scan lines, data lines, driving voltage line, and initialization voltage line are connected to the pixels. The pixels include an organic light emitting element, a first switching transistor connected to the scan line, a driving transistor that applies current to the organic light emitting element, and a compensation transistor that compensates for the operation of the driving transistor. The driving transistor includes a first gate electrode, a polycrystalline semiconductor layer, and a second gate electrode. The first gate electrode is disposed on the substrate, the polycrystalline semiconductor layer is disposed on the first gate electrode and includes a first electrode, a second electrode, and a channel, and the second gate electrode is disposed on the polycrystalline semiconductor layer of the driving transistor. The compensation transistor includes a polycrystalline semiconductor layer and a first gate electrode. The polycrystalline semiconductor layer includes a first electrode, a second electrode, and a channel, and the first gate electrode is disposed on the polycrystalline semiconductor layer of the compensation transistor. The compensation transistor does not include a second gate electrode disposed under the polycrystalline semiconductor layer of the compensation transistor.

[0030] According to an exemplary embodiment of the present invention, although protrusions may be formed in the polycrystalline semiconductor layer, since the gate electrode of the driving transistor is disposed under the polycrystalline semiconductor layer, the thickness of the gate insulating layer can be reduced and the thickness of the display device can be reduced. Moreover, since the gate electrode of the driving transistor is disposed under the polycrystalline semiconductor layer, if the thickness of the gate insulating layer is reduced, the characteristics (hysteresis) of the driving transistor are reduced so that no transient ghosting occurs in the displayed image. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0032] Figure 1 It is an equivalent circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0033] Figure 2 It is a timing diagram of signals applied to a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0034] Figure 3 It is a cross-sectional view of a plurality of transistors included in a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0035] Figure 4 It is a view schematically showing the structure of an overlying layer caused by protrusions generated in a polycrystalline semiconductor layer.

[0036] Figure 5 It is an equivalent circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0037] Figure 6 It is a cross-sectional view of a plurality of transistors included in a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0038] Figure 7 It is an equivalent circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0039] Figure 8 It is a cross-sectional view of a plurality of transistors included in a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0040] Figure 9 It is a cross-sectional view of a plurality of transistors included in a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0041] Figure 10 It is an equivalent circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0042] Figure 11 It is a cross-sectional view of a plurality of transistors included in a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0043] Figure 12 It is an equivalent circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0044] Figure 13 It is a cross-sectional view of a plurality of transistors included in a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0045] Figure 14 A cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0046] Figure 15 A cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment. Detailed Description

[0047] Hereinafter, exemplary embodiments of the present invention will be described more fully with reference to the accompanying drawings. In the entire drawings, like reference numerals denote like elements.

[0048] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

[0049] Spatial relative terms such as "beneath", "below", "lower", "under", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that, in addition to the orientation shown in the figures, the spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figures is turned over, an element described as "below", "beneath", or "under" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can include both an orientation of above and below.

[0050] It should be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another, and these elements are not limited by these terms. Thus, a "first" element in an exemplary embodiment can be described as a "second" element in another exemplary embodiment.

[0051] Unless otherwise clearly stated in the context, the description of each feature or aspect within an exemplary embodiment is generally considered applicable to other similar features or aspects in other exemplary embodiments.

[0052] Refer to Figures 1 to 3 A description of an organic light emitting diode display according to an exemplary embodiment.

[0053] Figure 1It is an equivalent circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment. Figure 2 It is a timing diagram of signals applied to a pixel of an organic light emitting diode display according to an exemplary embodiment. Figure 3 It is according to an exemplary embodiment (for example, Figure 1 the exemplary embodiment shown in) a cross-sectional view of a plurality of transistors included in a pixel of an organic light emitting diode display.

[0054] Referring to Figure 1 , the pixel PX of the organic light emitting diode display includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to signal lines 127, 151, 152, 153, 158, 171, 172, and 741, a storage capacitor Cst, and an organic light emitting diode OLED.

[0055] Referring to Figure 3 , the driving transistor T1 includes a gate electrode G1 (referred to as a driving gate electrode) disposed below the polycrystalline semiconductor layer. The polycrystalline semiconductor layer includes a first electrode S1, a second electrode D1, and a channel disposed therebetween. In contrast, in the other transistors T2 to T7, the gate electrodes G2, G3, G4, G5, G6, and G7 are disposed on the polycrystalline semiconductor layer. In Figure 3 , G4, G5, G6, and G7 are shown as G, S4, S5, S6, and S7 are shown as S, and D4, D5, D6, and D7 are shown as D. In the driving transistor T1, different from the gate electrodes G2, G3, G4, G5, G6, and G7 of the other transistors T2 to T7 that may be affected by the protrusions of the polycrystalline semiconductor layer, the gate electrode G1 is not affected by the protrusions of the polycrystalline semiconductor layer. In the exemplary embodiment, the main function of supplying current to the organic light emitting diode OLED is completed using the driving transistor T1, and the other transistors T2 to T7 only perform the function of preparing or initializing the operation of the driving transistor T1. As a result, the influence on the display quality caused by the protrusions of the polycrystalline semiconductor layer can be reduced.

[0056] Referring to Figure 1 and Figure 3 , the driving transistor T1 that supplies current to the organic light emitting diode OLED further includes an overlapping layer M1 and a second gate electrode G1-2 that overlaps the overlapping layer M1. For convenience of illustration, Figure 1The overlapping layer M1 is not shown. According to an exemplary embodiment, the overlapping layer M1 may be omitted. The second gate electrode G1-2 is disposed on a side opposite to the gate electrode G1 of the driving transistor T1, with a semiconductor layer in which a channel of the driving transistor T1 is formed disposed therebetween. The overlapping layer M1 is disposed under the gate electrode G1 of the driving transistor T1. The second gate electrode G1-2 and the overlapping layer M1 are electrically connected to each other, and a driving voltage ELVDD is applied thereto. A predetermined voltage (driving voltage ELVDD) is applied to the second gate electrode G1-2 such that the second gate electrode G1-2 does not function as a gate electrode of a transistor. As Figure 3 shown in, the second gate electrode G1-2 is disposed on the channel of a polycrystalline semiconductor layer including a first electrode S1, a second electrode D1, and a channel disposed therebetween.

[0057] A pixel PX according to an exemplary embodiment includes a total of seven transistors T1 to T7.

[0058] The seven transistors T1 to T7 include a driving transistor T1 that supplies current to the organic light emitting diode OLED, and also include a second transistor T2 connected to a scan line 151 and a data line 171 and providing a data voltage Dm in the pixel PX. A third transistor T3 is also connected to the scan line 151. The second transistor T2 and the third transistor T3 connected to the scan line 151 may each be referred to as a switching transistor. Other transistors for operating the organic light emitting diode OLED may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and each of these transistors may be referred to as a compensation transistor.

[0059] The plurality of signal lines 127, 151, 152, 153, 158, 171, 172, and 741 may include a scan line 151, a previous scan line 152, a light emission control line 153, a bypass control line 158, a data line 171, a driving voltage line 172, an initialization voltage line 127, and a common voltage line 741. The bypass control line 158 may be a part of the previous scan line 152 or may be electrically connected to the previous scan line 152.

[0060] The scan line 151 is connected to a gate driver and transmits a scan signal Sn to the second transistor T2 and the third transistor T3. The previous scan line 152 is connected to a gate driver and transmits a previous scan signal Sn-1 applied to a pixel PX disposed at a previous stage to the fourth transistor T4. The light emission control line 153 is connected to a light emission controller and transmits a light emission control signal EM that controls the time when the organic light emitting diode OLED emits light to the fifth transistor T5 and the sixth transistor T6. The bypass control line 158 transmits a bypass signal GB to the seventh transistor T7, and according to an exemplary embodiment, may transmit the same signal as the previous scan signal Sn-1.

[0061] The data line 171 is a wiring for transmitting the data voltage Dm generated from the data driver. The luminance emitted by the organic light-emitting diode OLED (also referred to as an organic light-emitting device) changes according to the data voltage Dm. The driving voltage line 172 applies the driving voltage ELVDD, the initialization voltage line 127 transmits the initialization voltage Vint for initializing the driving transistor T1, and the common voltage line 741 applies the common voltage ELVSS. The voltages applied to the driving voltage line 172, the initialization voltage line 127, and the common voltage line 741 may be predetermined voltages, respectively.

[0062] Next, a detailed description of the plurality of transistors will be given.

[0063] The driving transistor T1 controls the magnitude of the output current according to the applied data voltage Dm, and the output driving current Id is applied to the organic light-emitting diode OLED. As a result, the luminance of the organic light-emitting diode OLED is controlled according to the data voltage Dm. For this purpose, the first electrode S1 (also referred to as an input terminal) of the driving transistor T1 is arranged to receive the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5. The first electrode S1 of the driving transistor T1 is also connected to the second electrode D2 of the second transistor T2, thereby also receiving the data voltage Dm. The second electrode D1 (also referred to as an output terminal) is arranged to output a current toward the organic light-emitting diode OLED and is connected to the anode of the organic light-emitting diode OLED via the sixth transistor T6. The gate electrode G1 is connected to one electrode (the second storage electrode E2) of the storage capacitor Cst. Accordingly, the voltage of the gate electrode G1 changes according to the voltage stored in the storage capacitor Cst, and as a result, the driving current Id output by the driving transistor T1 changes. The gate electrode G1 is arranged between the polycrystalline semiconductor layer and the substrate, and thus is arranged below the polycrystalline semiconductor layer. Moreover, the second gate electrode G1-2 is arranged on the polycrystalline semiconductor layer and directly receives the driving voltage ELVDD. The driving voltage ELVDD is also applied to the overlapping layer M1 electrically connected to the second gate electrode G1-2, and the overlapping layer M1 is arranged between the gate electrode G1 and the substrate. The second gate electrode G1-2 causes the characteristics (threshold voltage value) of the driving transistor T1 to drift due to the driving voltage ELVDD in the channel region (the region between the second electrode D1 and the first electrode S1) of the polycrystalline semiconductor layer, so that the characteristics of the driving transistor T1 are improved.

[0064] In pixel PX, the second transistor T2 receives the data voltage Dm. The gate electrode G2 is connected to the scan line 151, and the first electrode S2 is connected to the data line 171. The second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the first electrode S1 of the driving transistor T1. The gate electrode G2 is disposed on the polycrystalline semiconductor layer where the channel of the second transistor T2 is disposed.

[0065] The third transistor T3 transmits the compensation voltage (voltage Dm + Vth) obtained by changing the data voltage Dm by the driving transistor T1 to the second storage electrode E2 of the storage capacitor Cst. The gate electrode G3 of the third transistor T3 is connected to the scan line 151. The first electrode S3 of the third transistor T3 is connected to the second electrode D1 of the driving transistor T1, and the second electrode D3 of the third transistor T3 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. The third transistor T3 is turned on according to the scan signal Sn transmitted through the scan line 151. When turned on, the third transistor T3 connects the gate electrode G1 and the second electrode D1 of the driving transistor T1, and connects the second electrode D1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G3 is disposed on the polycrystalline semiconductor layer where the channel of the third transistor T3 is disposed.

[0066] The fourth transistor T4 functions to initialize the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G4 of the fourth transistor T4 is connected to the previous scan line 152, and the first electrode S4 is connected to the initialization voltage line 127. The second electrode D4 of the fourth transistor T4 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 via the second electrode D3 of the third transistor T3. The fourth transistor T4 transmits the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst according to the previous scan signal Sn-1 transmitted through the previous scan line 152. Accordingly, the gate voltage of the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint may be a voltage capable of turning on the driving transistor T1 by having a low voltage value. The gate electrode G4 is disposed on the polycrystalline semiconductor layer where the channel of the fourth transistor T4 is disposed.

[0067] The fifth transistor T5 has a function of transmitting a driving voltage ELVDD to the driving transistor T1. The gate electrode G5 is connected to the emission control line 153, and the first electrode S5 is connected to the driving voltage line 172. The second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1. The gate electrode G5 is disposed on the polycrystalline semiconductor layer in which the channel of the fifth transistor T5 is disposed.

[0068] The sixth transistor T6 has a function of transmitting the driving current Id output from the driving transistor T1 to the organic light-emitting diode OLED. The gate electrode G6 is connected to the emission control line 153, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1. The second electrode D6 of the sixth transistor T6 is connected to the anode of the organic light-emitting diode OLED. The gate electrode G6 is disposed on the polycrystalline semiconductor layer in which the channel of the sixth transistor T6 is disposed.

[0069] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the emission control signal EM transmitted through the emission control line 153. When the driving voltage ELVDD is transmitted to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, the driving transistor T1 outputs the driving current Id according to the voltage of the gate electrode G1 of the driving transistor T1 (for example, the voltage of the second storage electrode E2 of the storage capacitor Cst). The output driving current Id is transmitted to the organic light-emitting diode OLED through the sixth transistor T6. When the current Ioled flows to the organic light-emitting diode OLED, the organic light-emitting diode OLED emits light.

[0070] The seventh transistor T7 has a function of initializing the anode of the organic light-emitting diode OLED. The gate electrode G7 is connected to the bypass control line 158, the first electrode S7 is connected to the anode of the organic light-emitting diode OLED, and the second electrode D7 is connected to the initialization voltage line 127. The bypass control line 158 may be connected to the previous scan line 152, and the bypass signal GB is applied with a signal having the same timing as the previous scan signal Sn-1. In an exemplary embodiment, the bypass control line 158 is not connected to the previous scan line 152 and may transmit a signal independent of the previous scan signal Sn-1. When the seventh transistor T7 is turned on according to the bypass signal GB, the initialization voltage Vint is applied to the anode of the organic light-emitting diode OLED for initialization. The gate electrode G7 is disposed on the polycrystalline semiconductor layer in which the channel of the seventh transistor T7 is disposed.

[0071] The pixel PX further includes a storage capacitor Cst. The data voltage Dm passes through the driving transistor T1 and is applied to the storage capacitor Cst to be stored.

[0072] The first storage electrode E1 of the storage capacitor Cst is connected to the driving voltage line 172, and the second storage electrode E2 is connected to the gate electrode G1 of the driving transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. As a result, the second storage electrode E2 determines the voltage of the gate electrode G1 of the driving transistor T1 (the gate-source voltage Vgs of the driving transistor T1), the data voltage Dm is applied to the second storage electrode E2 through the second electrode D3 of the third transistor T3, and the initialization voltage Vint is applied to the second storage electrode E2 through the second electrode D4 of the fourth transistor T4.

[0073] The pixel PX further includes an organic light-emitting diode OLED. The anode of the organic light-emitting diode OLED is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7, and the cathode is connected to the common voltage line 741 for transmitting the common voltage ELVSS.

[0074] In Figure 1 the exemplary embodiment, the pixel circuit includes seven transistors T1 to T7 and one capacitor Cst. However, the pixel circuit is not limited thereto. For example, according to the exemplary embodiment, the number of transistors, the number of capacitors, and their connections can be changed differently.

[0075] The organic light-emitting diode display includes a display area for displaying an image, and the pixels PX are arranged in various forms (such as a matrix) in the display area.

[0076] Now refer to Figure 1 and Figure 2 to describe the operation of a pixel of the organic light-emitting diode display according to the exemplary embodiment.

[0077] During the initialization period, the previous scan signal Sn-1 at a low level is supplied to the pixel PX through the previous scan line 152. Accordingly, the fourth transistor T4 receiving the previous scan signal Sn-1 is turned on, and the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst through the fourth transistor T4. As a result, the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint is a low voltage so that the driving transistor T1 can be turned on.

[0078] During the initialization period, the bypass signal GB at a low level is also applied to the seventh transistor T7. Accordingly, the seventh transistor T7 receiving the bypass signal GB is turned on so that the initialization voltage Vint is applied to the anode of the organic light-emitting diode OLED through the seventh transistor T7. As a result, the anode of the organic light-emitting diode OLED is also initialized.

[0079] Next, during a data writing period (hereinafter referred to as a writing period), a scanning signal Sn at a low level is supplied to the pixel PX through the scanning line 151. The second transistor T2 and the third transistor T3 are turned on by the scanning signal Sn at a low level.

[0080] When the second transistor T2 is turned on, the data voltage Dm is input to the first electrode S1 of the driving transistor T1 after passing through the second transistor T2.

[0081] Moreover, during the data writing period, the third transistor T3 is turned on, and as a result, the second electrode D1 of the driving transistor T1 is electrically connected to the gate electrode G1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G1 and the second electrode D1 of the driving transistor T1 are connected in a diode-like connection. Further, during the initialization period, a low voltage (initialization voltage Vint) is applied to the gate electrode G1 of the driving transistor T1 so that the driving transistor T1 is in an on state. As a result, the data voltage Dm input to the first electrode S1 of the driving transistor T1 passes through the channel of the driving transistor T1 and is output from the second electrode D1, and then is stored in the second storage electrode E2 of the storage capacitor Cst through the third transistor T3. In this case, the voltage applied to the second storage electrode E2 changes according to the threshold voltage Vth of the driving transistor T1, and when the data voltage Dm is applied to the first electrode S1 of the driving transistor T1 and the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1, the voltage output to the second electrode D1 may have a value (Vgs + Vth). Here, the voltage Vgs is the difference between the voltage applied to the gate electrode G1 and the first electrode S1 of the driving transistor T1, and thus has a value (Dm - Vint). Therefore, the voltage output from the second electrode D1 and stored in the second storage electrode E2 may have a value (Dm - Vint + Vth).

[0082] Next, during the light emission period, the light emission control signal EM supplied from the light emission control line 153 has a low level value so that the fifth transistor T5 and the sixth transistor T6 are turned on.

[0083] Since the fifth transistor T5 and the sixth transistor T6 are turned on, a driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1, and the second electrode D1 of the driving transistor T1 is connected to the organic light-emitting diode OLED. A driving current Id is generated according to the voltage difference between the voltage of the gate electrode G1 of the driving transistor T1 and the voltage of the first electrode S1 (e.g., the driving voltage ELVDD). The driving current Id of the driving transistor T1 can have a value proportional to the square of the value (Vgs - Vth). Here, the value Vgs is the same as the voltage difference applied to the two terminals of the storage capacitor Cst, and the value Vgs is (Vg - Vs), so it has a value (Dm - Vint + Vth - ELVDD). Here, when the value (Vgs - Vth) is obtained by subtracting the value Vth, the value (Dm - Vint - ELVDD) is obtained. That is, the driving current Id of the driving transistor T1 has a value independent of the threshold voltage Vth of the driving transistor T1.

[0084] Therefore, although the driving transistors T1 arranged in each pixel PX have different threshold voltages Vth due to process variations, the output current of each driving transistor T1 can be constant, thereby improving its non-uniformity characteristics.

[0085] In the driving transistor T1, the gate electrode G1 is formed under the polycrystalline semiconductor layer. As a result, even if protrusions are formed in the polycrystalline semiconductor layer, the driving transistor T1 can operate correctly regardless of the protrusions (e.g., the protrusions do not have a negative impact on the driving transistor T1), and constant characteristics are obtained. As a result, the display device can be free from display defects such as transient afterimages.

[0086] In the above equation, in the case of a P-type transistor using a polycrystalline semiconductor layer, the value Vth can have a value slightly greater than 0 or a negative value. Moreover, the expressions of + and - can be changed according to the direction of calculating the voltage. However, one thing that does not change is that the driving current Id, which is the output current of the driving transistor T1, can have a value independent of the threshold voltage Vth.

[0087] When the above light-emitting period ends, the initialization period starts again and the same operation is repeated from the beginning.

[0088] For the first and second electrodes of the multiple transistors T1, T2, T3, T4, T5, T6, and T7, depending on the application direction of the voltage or current, one can be the source electrode S, and the other can be the drain electrode D.

[0089] According to an exemplary embodiment, when the seventh transistor T7 in the initialization period initializes the anode of the organic light-emitting diode OLED, it is also possible to prevent a small amount of leakage current from the driving transistor T1 from flowing toward the organic light-emitting diode OLED. In this case, the small amount of current is discharged as a bypass current Ibp to the initialization voltage Vint terminal through the seventh transistor T7. As a result, since the organic light-emitting diode OLED does not emit unnecessary light, black-gray can be more clearly displayed and the contrast can also be improved. In this case, the bypass signal GB may be a signal having a timing different from that of the previous scan signal Sn-1. According to an exemplary embodiment, the seventh transistor T7 may be omitted.

[0090] In addition, in the pixel PX of the above operation, when the driving voltage ELVDD is applied to the second gate electrode G1-2 of the driving transistor T1, the characteristics (threshold voltage) of the driving transistor T1 drift, so that the display quality is improved.

[0091] Next, refer to Figure 3 A cross-sectional structure of a transistor included in an organic light-emitting diode display is described.

[0092] Figure 3 A cross-sectional view of a plurality of transistors included in one pixel of an organic light-emitting diode display is shown. From left to right, a driving transistor T1, a third transistor T3, and a second transistor T2 are shown, followed by fourth to seventh transistors T4 to T7. The cross-sections of the fourth to seventh transistors T4 to T7 are the same. Therefore, for convenience of explanation, these cross-sections are combined and shown as one. In this regard, in Figure 3 G corresponds to G4 to G7, D corresponds to D4 to D7, and S corresponds to S4 to S7.

[0093] According to an exemplary embodiment, the organic light-emitting diode display includes substrates 110 and 110-1 such as plastic or polyimide (PI), and barrier layers 111 and 111-1 disposed on the substrates 110 and 110-1, respectively. The substrates 110 and 110-1 may be collectively referred to as a substrate, and the barrier layers 111 and 111-1 may be collectively referred to as a barrier layer. According to an exemplary embodiment, the substrate and the barrier layer may be formed in the same number, and different from those shown in Figure 3 they may include only one pair, or may be formed in three or more pairs. The barrier layers 111 and 111-1 may be formed to reduce the influence on the flexible substrates 110 and 110-1 when forming the overlying layer.

[0094] Now, a cross-section of the driving transistor T1 is described.

[0095] The overlapping layer M1 is disposed on the upper barrier layer 111, and the overlapping layer M1 is covered by the buffer layer 112. The gate electrode G1 is formed on the buffer layer 112, and the gate electrode G1 is covered by the first gate insulating layer 141. The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S1, a second electrode D1, and a channel disposed therebetween.

[0096] The polycrystalline semiconductor layer is covered by the second gate insulating layer 142, and the second gate electrode G1-2 is formed on the second gate insulating layer 142. The second gate electrode G1-2 is covered by the interlayer insulating layer 160.

[0097] Data conductors are formed on the interlayer insulating layer 160. The data conductors include data lines 171 and drive voltage lines 172 for transmitting the drive voltage ELVDD.

[0098] The drive voltage line 172 includes a drive voltage application portion C-1, and the drive voltage application portion C-1 is connected to the second gate electrode G1-2 and the overlapping layer M1 through openings respectively exposing the second gate electrode G1-2 and the overlapping layer M1. The drive voltage application portion C-1 may be a part where the drive voltage line 172 extends or only a part of the electrical connection.

[0099] The gate electrode G1 and the second gate electrode G1-2 are disposed above and below the channel of the drive transistor T1. In an exemplary embodiment, the gate electrode G1 and the second gate electrode G1-2 may have a width corresponding to (e.g., substantially equal to) the width of the channel. However, in an exemplary embodiment, as Figure 3 shown, a structure is shown in which the gate electrode G1 extends toward the third transistor T3 (e.g., toward the right in Figure 3 such that the gate electrode G1 disposed below the channel is connected to the second electrode D3 of the third transistor T3. In an exemplary embodiment, except for this extended portion, the gate electrode G1 has a width corresponding to (e.g., substantially equal to) the width of the channel of the drive transistor T1.

[0100] When doping the polycrystalline semiconductor layer, the second gate electrode G1-2 can be used as a mask. As a result, the width of the second gate electrode G1-2 can conform to the width of the channel. According to an exemplary embodiment, since the drive transistor T1 includes the second gate electrode G1-2 and the overlapping layer M1 as the part for receiving the drive voltage ELVDD, the overlapping layer M1 can be omitted.

[0101] The drive transistor T1 has a bottom gate (e.g., the second gate electrode G1-2), and the drive voltage ELVDD is applied to the second gate electrode G1-2, thereby causing the characteristics of the channel to drift. As a result, according to an exemplary embodiment, by using the bottom gate, it is possible to reduce or eliminate protrusions (see Figure 4)defects caused thereby.

[0102] Next, a cross-section of the third transistor T3 will be described.

[0103] The buffer layer 112 is disposed on the upper barrier layer 111, and the first gate insulating layer 141 is disposed on the buffer layer 112.

[0104] The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S3, a second electrode D3, and a channel disposed therebetween.

[0105] The polycrystalline semiconductor layer is covered by the second gate insulating layer 142, and the gate electrode G3(151) is formed on the second gate insulating layer 142. The gate electrode G3(151) is covered by the interlayer insulating layer 160.

[0106] A connection portion 71 is formed on the interlayer insulating layer 160. The connection portion 71 electrically connects the second electrode D3 of the third transistor T3 and the gate electrode G1 of the driving transistor T1 through openings respectively exposing the second electrode D3 of the third transistor T3 and the gate electrode G1 of the driving transistor T1. Since the output of the driving transistor T1 changes according to the voltage of the gate electrode G1, the voltage output to the second electrode D3 of the third transistor T3 affects the output of the driving transistor T1.

[0107] The gate electrode G3(151) is disposed on the channel of the third transistor T3 and has a width corresponding to (e.g., substantially equal to) the width of the channel. When doping the polycrystalline semiconductor layer, the gate electrode G3(151) can be used as a mask.

[0108] As described above, different from the driving transistor T1, in the exemplary embodiment, the third transistor T3 has a top gate and does not include a bottom gate. Therefore, different from the driving transistor T1, in the exemplary embodiment, the third transistor T3 does not include a structure that causes the characteristics of the channel to drift.

[0109] Next, a cross-section of the second transistor T2 will be described.

[0110] The buffer layer 112 is disposed on the upper barrier layer 111, and the first gate insulating layer 141 is disposed on the buffer layer 112.

[0111] The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S2, a second electrode D2, and a channel disposed therebetween.

[0112] The polycrystalline semiconductor layer is covered by the second gate insulating layer 142, and the gate electrode G2(151) is formed on the second gate insulating layer 142. The gate electrode G2(151) is covered by the interlayer insulating layer 160.

[0113] The data line 171 is formed on the interlayer insulating layer 160. The data line 171 is connected to the first electrode S2 of the second transistor T2 through an opening exposing the first electrode S2 of the second transistor T2. When the second transistor T2 is turned on, a data voltage Dm is input to the corresponding pixel PX.

[0114] The gate electrode G2 (151) is disposed on the channel of the second transistor T2 and has a width corresponding to (e.g., substantially equal to) the width of the channel. When doping the polycrystalline semiconductor layer, the gate electrode G2 (151) can be used as a mask.

[0115] As described above, in the exemplary embodiment, different from the driving transistor T1, the second transistor T2 has a top gate and does not include a bottom gate. Therefore, in the exemplary embodiment, the second transistor T2 does not include a structure that causes the characteristics of the channel to drift.

[0116] Hereinafter, the fourth transistor T4 to the seventh transistor T7 included in the pixel PX are grouped and described. The first electrode of each of the fourth transistor T4 to the seventh transistor T7 is indicated by S, its second electrode is indicated by D, and its gate electrode is indicated by G.

[0117] The buffer layer 112 is disposed on the upper barrier layer 111, and the first gate insulating layer 141 is disposed on the buffer layer 112. The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S, a second electrode D, and a channel disposed therebetween.

[0118] The polycrystalline semiconductor layer is covered by the second gate insulating layer 142, and the gate electrode G is formed on the second gate insulating layer 142. The gate electrode G is covered by the interlayer insulating layer 160.

[0119] The fourth transistor T4 to the seventh transistor T7 have Figure 1 the connection relationship shown in, and are disposed in the pixel PX.

[0120] The gate electrode G is disposed on the channels of the fourth transistor T4 to the seventh transistor T7 and has a width corresponding to (e.g., substantially equal to) the width of the channels. When doping the polycrystalline semiconductor layer, the gate electrode G can be used as a mask.

[0121] As described above, in the exemplary embodiment, the fourth transistor T4 to the seventh transistor T7 also have a top gate and do not include a bottom gate. As a result, in the exemplary embodiment, the fourth transistor T4 to the seventh transistor T7 do not include a structure that causes the characteristics of the channel to drift.

[0122] In the organic light emitting diode display having the above structure, the driving transistor T1 that performs the main operation only in the pixel PX has a bottom gate (a gate electrode disposed under the polycrystalline semiconductor layer), and the remaining transistors have a top gate (a gate electrode disposed on the polycrystalline semiconductor layer) and do not have a bottom gate.

[0123] The polycrystalline semiconductor layer is formed by forming a semiconductor layer of amorphous silicon and irradiating the semiconductor layer with a laser for crystallization. Protrusions may be formed in the polycrystalline semiconductor layer during the crystallization step, and reference is made to Figure 4 A description is given of an extended cross section in a structure using a top gate.

[0124] Figure 4 is a view schematically showing the structure of an overlying layer caused by protrusions generated in the polycrystalline semiconductor layer.

[0125] Figure 4 The cross-sectional view in shows a structure using a top gate in the driving transistor T1. Two gate layers GL1 and GL2 are formed on the polycrystalline semiconductor layer Poly.

[0126] The polycrystalline semiconductor layer Poly having protrusions is disposed on the substrate 110. The protrusions formed in the polycrystalline semiconductor layer Poly are formed as protrusions protruding in the first gate insulating layer 141 and the second gate insulating layer 142 and the two gate layers GL1 and GL2 disposed thereon. As a result, charges accumulate on the protrusions of the gate layers GL1 and GL2, and the thicknesses of the first gate insulating layer 141 and the second gate insulating layer 142 become thinner, such that the insulation aspect may be damaged. To prevent insulation breakdown, the thicknesses of the first gate insulating layer 141 and the second gate insulating layer 142 should be thick enough, and as a result, there is a limit in reducing the thickness of the display device.

[0127] However, in an exemplary embodiment according to the present invention, the gate electrode G1 of the driving transistor T1 is formed under the protrusions of the polycrystalline semiconductor layer (bottom gate), and as a result, the influence of the protrusions is reduced or eliminated. That is, even if the thickness of the first gate insulating layer 141 is made thinner, sufficient insulation characteristics can be obtained.

[0128] Different from the driving transistor T1, the second transistor T2 to the seventh transistor T7 have a top gate structure (for example, they do not include a bottom gate), and the gate electrodes are disposed on the polycrystalline semiconductor layer including the protrusions. However, the second transistor T2 to the seventh transistor T7 do not play a main role in supplying current to the organic light emitting diode OLED, and therefore, the display quality is not particularly affected by the protrusions corresponding to the second transistor T2 to the seventh transistor T7. However, in an exemplary embodiment, at least some of the second transistor T2 to the seventh transistor T7 may have a bottom gate structure to further improve the display characteristics.

[0129] In Figures 1 to 3 the exemplary embodiment, the characteristics of the driving transistor T1 are drifted by forming only the second gate electrode G1-2 receiving the driving voltage ELVDD in the driving transistor T1. However, the exemplary embodiment of the present invention is not limited thereto. For example, according to the exemplary embodiment, at least some of the second transistor T2 to the seventh transistor T7 may include a second gate electrode receiving the driving voltage ELVDD. Compared with using only the second gate electrode G1-2 in the driving transistor T1, using the second gate electrode in some of the second transistor T2 to the seventh transistor T7 may increase the complexity and cost of the display device, but may further improve the display characteristics.

[0130] Next, referring to Figure 5 and Figure 6 an exemplary embodiment further including a second gate electrode G2-2 receiving the driving voltage ELVDD applied to the second transistor T2 will be described.

[0131] Figure 5 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment. Figure 6 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment (e.g., Figure 5 the exemplary embodiment shown in

[0132] Compared with the circuit diagram of Figure 1 in the circuit diagram of Figure 5 the second transistor T2 further includes a second gate electrode G2-2, and the second gate electrode G2-2 is connected to the driving voltage line 172. Accordingly, the second gate electrode G2-2 receives the driving voltage ELVDD, and as a result, in addition to the channel characteristics of the driving transistor T1, the channel characteristics of the second transistor T2 also drift.

[0133] Compared with the cross-sectional view of Figure 3 in the cross-sectional view of Figure 6 the second transistor T2 further includes a second gate electrode G2-2, and further includes a driving voltage applying unit C-2 for applying the driving voltage ELVDD to the second gate electrode G2-2.

[0134] Referring to Figure 5 and Figure 6 for convenience of explanation, further description of the previously described elements may be omitted.

[0135] Now, the cross-section of the second transistor T2 will be described in detail.

[0136] The buffer layer 112 is disposed on the upper barrier layer 111, and the second gate electrode G2-2 is disposed on the buffer layer 112. The second gate electrode G2-2 is covered by the first gate insulating layer 141.

[0137] A polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S2, a second electrode D2, and a channel disposed therebetween.

[0138] The polycrystalline semiconductor layer is covered by the second gate insulating layer 142, and the gate electrode G2(151) is formed on the second gate insulating layer 142. The gate electrode G2(151) is covered by the interlayer insulating layer 160.

[0139] The data line 171 and the drive voltage application unit C-2 are formed on the interlayer insulating layer 160. The data line 171 is connected to the first electrode S2 of the second transistor T2 through an opening exposing the first electrode S2 of the second transistor T2. When the second transistor T2 is turned on, the data voltage Dm is input to the corresponding pixel PX. The drive voltage application unit C-2 is connected to the second gate electrode G2-2 of the second transistor T2 through an opening exposing the second gate electrode G2-2. The drive voltage application unit C-2 applies the drive voltage ELVDD to the second gate electrode G2-2. As a result, the channel characteristics of the second transistor T2 drift.

[0140] The gate electrode G2(151) is disposed on the channel of the second transistor T2 and has a width corresponding to (e.g., substantially equal to) the width of the channel. When doping the polycrystalline semiconductor layer, the gate electrode G2(151) can be used as a mask.

[0141] As described above, the second transistor T2 includes a top gate. Additionally, in Figure 5 and Figure 6 the exemplary embodiment, a second gate electrode G2-2 for receiving the drive voltage ELVDD is additionally included so that the channel characteristics of the second transistor T2 also drift.

[0142] However, the structure of the second transistor T2 is not limited thereto, and according to the exemplary embodiment, the second transistor T2 can be formed with a bottom gate, and the second gate electrode G2-2 can be formed as a top gate. In this case, the gate electrode G2(151) can be formed under the polycrystalline semiconductor layer so that it is connected to the scan line 151, and the second gate electrode G2-2 can be formed on the polycrystalline semiconductor layer so that the drive voltage ELVDD is applied.

[0143] Next, with reference to Figure 7 and Figure 8 an exemplary embodiment including a second gate electrode G3-2 for receiving the drive voltage ELVDD applied to the third transistor T3 is described.

[0144] Figure 7 is an equivalent circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment. Figure 8 is a cross-sectional view of a plurality of transistors included in a pixel of an organic light emitting diode display according to an exemplary embodiment (e.g., Figure 7 the exemplary embodiment shown in

[0145] Compared with the circuit diagram of Figure 1 , in the circuit diagram of Figure 7 , the third transistor T3 further includes a second gate electrode G3-2, and the second gate electrode G3-2 is connected to the driving voltage line 172. Accordingly, the second gate electrode G3-2 receives the driving voltage ELVDD, and as a result, in addition to the channel characteristics of the driving transistor T1, the channel characteristics of the third transistor T3 also drift.

[0146] Compared with the cross-sectional view of Figure 1 , in the cross-sectional view of Figure 8 , the third transistor T3 further includes a second gate electrode G3-2, and also includes a driving voltage applying unit C-3 for applying the driving voltage ELVDD to the second gate electrode G3-2.

[0147] Referring to Figure 7 and Figure 8 , for convenience of explanation, further description of the previously described elements may be omitted.

[0148] Now, a cross-section of the third transistor T3 will be described in detail.

[0149] The buffer layer 112 is disposed on the upper barrier layer 111, and the second gate electrode G3-2 is disposed on the buffer layer 112. The second gate electrode G3-2 is covered by the first gate insulating layer 141.

[0150] The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S3, a second electrode D3, and a channel disposed therebetween.

[0151] The polycrystalline semiconductor layer is covered by the second gate insulating layer 142, and the gate electrode G3 (151) is formed on the second gate insulating layer 142. The gate electrode G3 (151) is covered by the interlayer insulating layer 160.

[0152] The connection part 71 and the driving voltage applying unit C-3 are formed on the interlayer insulating layer 160.

[0153] The connection portion 71 electrically connects the second electrode D3 of the third transistor T3 and the gate electrode G1 of the driving transistor T1 through openings that respectively expose the second electrode D3 of the third transistor T3 and the gate electrode G1 of the driving transistor T1. Since the output of the driving transistor T1 changes according to the voltage of the gate electrode G1, the voltage output to the second electrode D3 of the third transistor T3 affects the output of the driving transistor T1.

[0154] The driving voltage application portion C-3 is connected to the second gate electrode G3-2 of the third transistor T3 through an opening that exposes the second gate electrode G3-2. The driving voltage application portion C-3 applies the driving voltage ELVDD to the second gate electrode G3-2. As a result, the channel characteristics of the third transistor T3 shift.

[0155] The gate electrode G3 (151) is disposed on the channel of the third transistor T3 and has a width corresponding to (e.g., substantially equal to) the width of the channel. When doping the polycrystalline semiconductor layer, the gate electrode G3 (151) can be used as a mask.

[0156] As described above, the third transistor T3 includes a top gate. Additionally, in Figure 7 and Figure 8 exemplary embodiments, a second gate electrode G3-2 that receives the driving voltage ELVDD is additionally included so that the channel characteristics of the third transistor T3 also shift.

[0157] However, the structure of the third transistor T3 is not limited thereto, and according to an exemplary embodiment, the third transistor T3 may be formed with a bottom gate, and the second gate electrode G3-2 may be formed as a top gate. In this case, the gate electrode G3 (151) is formed under the polycrystalline semiconductor layer so that it is connected to the scan line 151, and the second gate electrode G3-2 is formed on the polycrystalline semiconductor layer to receive the driving voltage ELVDD.

[0158] Next, a method for applying the driving voltage ELVDD to the second gate electrode G3-2 of the third transistor T3 will be described with reference to Figure 9 .

[0159] Figure 9 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0160] Figure 9 The cross-sectional structure of each of the transistors T1 to T7 in Figure 8 is substantially the same as the cross-sectional structure in Figure 8 . However, different from the exemplary embodiment shown in Figure 9In the exemplary embodiment shown, a driving voltage application unit C-3 for applying a driving voltage ELVDD to the second gate electrode G3-2 of the third transistor T3 is omitted.

[0161] In contrast, in Figure 9 the exemplary embodiment shown, the second gate electrode G3-2 of the third transistor T3 receives the driving voltage ELVDD from an overlapping layer M1 disposed below the driving transistor T1.

[0162] For example, in Figure 9 an overlapping layer M1 is disposed below the driving transistor T1 and further includes a portion M1-1 extending below the third transistor T3. The overlapping layer M1 is directly connected to the second gate electrode G3-2 of the third transistor T3 through an opening exposing the extending portion M1-1 of the overlapping layer M1. Since the overlapping layer M1 receives the driving voltage ELVDD through the driving voltage application unit C-1, the driving voltage ELVDD is also applied to the second gate electrode G3-2 of the third transistor T3.

[0163] Compared with the exemplary embodiment shown in Figure 8 in the exemplary embodiment shown in Figure 9 the structure on the interlayer insulating layer 160 is simplified, and the structure below the polycrystalline semiconductor layer (e.g., below the gate electrode G1 of the driving transistor T1) is more complex. Transistors using a polycrystalline semiconductor layer usually use a top-gate type and generally have a more complex structure when an organic light-emitting diode OLED made of a pixel electrode, an organic emission layer, and a common electrode is disposed on the transistor.

[0164] Accordingly, in the exemplary embodiment shown in Figure 9 the structure below the relatively simple polycrystalline semiconductor layer (e.g., below the gate electrode G1 of the driving transistor T1) becomes more complex, and the structure of the upper region (on the interlayer insulating layer 160) is simplified.

[0165] Since the area of the pixel PX becomes smaller at high resolution, a simple structure on the interlayer insulating layer 160 as in Figure 9 may be advantageous in some cases.

[0166] Next, with reference to Figure 10 and Figure 11 an exemplary embodiment of the exemplary embodiment combined with Figures 5 to 8 will be described.

[0167] Figure 10 is an equivalent circuit diagram of a pixel of an organic light-emitting diode display according to an exemplary embodiment. Figure 11 is according to an exemplary embodiment (e.g., Figure 10Cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment).

[0168] Referring to Figure 10 and Figure 11 For convenience of explanation, further description of the previously described elements may be omitted.

[0169] Figure 10 and Figure 11 The exemplary embodiment of Figure 5 and Figure 6 also includes a second gate electrode G2-2 that receives the driving voltage ELVDD applied to the second transistor T2 (as in the exemplary embodiments of Figure 7 and Figure 8 ), and also includes a second gate electrode G3-2 that receives the driving voltage ELVDD applied to the third transistor T3 (as in the exemplary embodiments of

[0170] Compared with the circuit diagram of Figure 1 in the circuit diagram of Figure 10 the second transistor T2 also includes a second gate electrode G2-2, and the third transistor T3 also includes a second gate electrode G3-2. As a result, the second gate electrode G2-2 of the second transistor T2 is connected to the driving voltage line 172, and the second gate electrode G3-2 of the third transistor T3 is also connected to the driving voltage line 172. This structure causes the channel characteristics of the second transistor T2 and the third transistor T3 to drift.

[0171] In the cross-sectional view of Figure 11 the features of Figure 6 and Figure 8 are shown together. For example, compared with the cross-sectional view of Figure 3 the second transistor T2 also includes a second gate electrode G2-2, and the third transistor T3 also includes a second gate electrode G3-2. In addition, there is also a driving voltage applying unit C-2 that applies the driving voltage ELVDD to the second gate electrode G2-2 of the second transistor T2 and a driving voltage applying unit C-3 that applies the driving voltage ELVDD to the second gate electrode G3-2 of the third transistor T3.

[0172] Figure 11 The exemplary embodiment of

[0173] As described above, the second transistor T2 and the third transistor T3 include top gates. However, according to an exemplary embodiment, the second transistor T2 and the third transistor T3 may also be formed with bottom gates, and the second gate electrodes G2-2 and G3-2 may be formed as top gates. In this case, the gate electrodes G2 and G3 may be formed under the polysilicon semiconductor layer to be connected to the scan line 151, and the second gate electrodes G2-2 and G3-2 may be formed on the polysilicon semiconductor layer to receive the driving voltage ELVDD.

[0174] Next, with reference to Figure 12 and Figure 13 an exemplary embodiment including a second gate electrode G4-2 that receives the driving voltage ELVDD applied to the fourth transistor T4 will be described.

[0175] Figure 12 is an equivalent circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment. Figure 13 is a cross-sectional view of a plurality of transistors included in a pixel of an organic light emitting diode display according to an exemplary embodiment (e.g., the exemplary embodiment shown in Figure 12 ).

[0176] With reference to Figure 12 and Figure 13 , for convenience of explanation, further description of the previously described elements may be omitted.

[0177] Compared with the circuit diagram of Figure 1 , in the circuit diagram of Figure 12 , the fourth transistor T4 further includes a second gate electrode G4-2, and the second gate electrode G4-2 is connected to the driving voltage line 172. Accordingly, the second gate electrode G4-2 receives the driving voltage ELVDD, and as a result, the channel characteristics of the fourth transistor T4 shift.

[0178] Compared with the cross-sectional view of Figure 3 , in the cross-sectional view of Figure 13 , the fourth transistor T4 further includes a second gate electrode G4-2, and further includes a driving voltage application unit C-4 that applies the driving voltage ELVDD to the second gate electrode G4-2.

[0179] Now, the cross-section of the fourth transistor T4 will be described in detail.

[0180] The buffer layer 112 is disposed on the upper barrier layer 111, and the second gate electrode G4-2 is disposed on the buffer layer 112. The second gate electrode G4-2 is covered by the first gate insulating layer 141.

[0181] The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S4, a second electrode D4, and a channel disposed therebetween.

[0182] The polycrystalline semiconductor layer is covered by a second gate insulating layer 142, and a gate electrode G4 is formed on the second gate insulating layer 142. The gate electrode G4 is covered by an interlayer insulating layer 160.

[0183] A driving voltage application unit C-4 is formed on the interlayer insulating layer 160. The driving voltage application unit C-4 is connected to the second gate electrode G4-2 of the second transistor T4 through an opening exposing the second gate electrode G4-2. The driving voltage application unit C-4 applies a driving voltage ELVDD to the second gate electrode G4-2. As a result, the channel characteristics of the fourth transistor T4 drift.

[0184] The gate electrode G4 is disposed on the channel of the fourth transistor T4 and has a width corresponding to (e.g., substantially equal to) the width of the channel. When doping the polycrystalline semiconductor layer, the gate electrode G4 can be used as a mask.

[0185] As described above, the fourth transistor T4 includes a top gate. However, in an exemplary embodiment, a second gate electrode G4-2 for receiving the driving voltage ELVDD is additionally formed so that the channel characteristics of the fourth transistor T4 also drift.

[0186] However, the structure of the fourth transistor T4 is not limited thereto, and according to an exemplary embodiment, the fourth transistor T4 may include a bottom gate, and the second gate electrode G4-2 may be formed as a top gate. In this case, the gate electrode G4 may be formed under the polycrystalline semiconductor layer, and the second gate electrode G4-2 may be formed on the polycrystalline semiconductor layer to receive the driving voltage ELVDD.

[0187] Exemplary embodiments may be provided that include the characteristics of the above exemplary embodiments Figure 12 and Figure 13 (also including the second gate electrode G4-2 for receiving the driving voltage ELVDD applied to the fourth transistor T4). For example, in addition to Figure 12 and Figure 13 of the exemplary embodiments, the second transistor T2 may further include a second gate electrode G2-2 for receiving the driving voltage ELVDD, or the third transistor T3 may further include a second gate electrode G3-2 for receiving the driving voltage ELVDD. Moreover, the second gate electrodes G2-2 and G3-2 for receiving the driving voltage ELVDD may be included in both the second transistor T2 and the third transistor T3.

[0188] In an exemplary embodiment, the fifth transistor T5 to the seventh transistor T7 may also include a second gate electrode for receiving the driving voltage ELVDD.

[0189] In the above exemplary embodiment, only the driving transistor T1 uses a bottom gate structure (the gate electrode is disposed under the polycrystalline semiconductor layer), and the other transistors T2 to T7 use a top gate structure (the gate electrode is disposed on the polycrystalline semiconductor layer).

[0190] However, according to an exemplary embodiment, the bottom gate structure can be used in transistors other than the driving transistor T1 so that the influence on the characteristics of the transistors other than the driving transistor T1 caused by the protrusion of the polycrystalline semiconductor layer can be reduced.

[0191] Next, refer to Figure 14 An exemplary embodiment in which the second transistor T2 and the third transistor T3 have a bottom gate structure will be described.

[0192] Figure 14 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0193] In Figure 14 the exemplary embodiment of Figure 3 different from the exemplary embodiment of

[0194] First, the cross-section of the second transistor T2 will be described.

[0195] A buffer layer 112 is disposed on the upper barrier layer 111, and a gate electrode G2(151) is disposed on the buffer layer 112. The gate electrode G2(151) is covered by a first gate insulating layer 141.

[0196] A polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S2, a second electrode D2, and a channel disposed therebetween.

[0197] The polycrystalline semiconductor layer is covered by a second gate insulating layer 142, and an interlayer insulating layer 160 is formed on the second gate insulating layer 142.

[0198] A data line 171 is formed on the interlayer insulating layer 160. The data line 171 is connected to the first electrode S2 of the second transistor T2 through an opening exposing the first electrode S2 of the second transistor T2. When the second transistor T2 is turned on, a data voltage Dm is input to the corresponding pixel PX.

[0199] The gate electrode G2 of the second transistor T2 is disposed under the polycrystalline semiconductor layer so that it has a bottom gate structure, and the gate electrode G2 has a width corresponding to (e.g., substantially equal to) the width of the channel. Also, since the gate electrode G2 is disposed under the polycrystalline semiconductor layer, a mask can be separately utilized when doping the polycrystalline semiconductor layer.

[0200] In Figure 14 an exemplary embodiment, the second transistor T2 does not separately include a structure for drifting the channel characteristics, and according to the exemplary embodiment, a driving voltage ELVDD can be received, and a second gate electrode disposed on the polycrystalline semiconductor layer can be formed.

[0201] Next, a cross-section of the third transistor T3 will be described.

[0202] A buffer layer 112 is disposed on the upper barrier layer 111, and a gate electrode G3(151) is disposed on the buffer layer 112. The gate electrode G3(151) is covered by a first gate insulating layer 141.

[0203] A polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S3, a second electrode D3, and a channel disposed therebetween.

[0204] The polycrystalline semiconductor layer is covered by a second gate insulating layer 142, and an interlayer insulating layer 160 is formed on the second gate insulating layer 142.

[0205] A connection portion 71 is formed on the interlayer insulating layer 160. The connection portion 71 electrically connects the second electrode D3 of the third transistor T3 and the gate electrode G1 of the driving transistor T1 through openings respectively exposing the second electrode D3 of the third transistor T3 and the gate electrode G1 of the driving transistor T1. Since the output of the driving transistor T1 changes according to the voltage of the gate electrode G1, the voltage output to the second electrode D3 of the third transistor T3 affects the output of the driving transistor T1.

[0206] The gate electrode G3 of the third transistor T3 is disposed under the polycrystalline semiconductor layer so that it has a bottom gate structure, and the gate electrode G3 has a width corresponding to (e.g., substantially equal to) the width of the channel. Since the gate electrode G3 is disposed under the polycrystalline semiconductor layer, a mask can be separately utilized when doping the polycrystalline semiconductor layer.

[0207] In Figure 14 an exemplary embodiment, the third transistor T3 does not separately include a structure for drifting the channel characteristics, and according to the exemplary embodiment, a driving voltage ELVDD can be received, and a second gate electrode disposed on the polycrystalline semiconductor layer can be formed.

[0208] With Figure 14Unlike the exemplary embodiments, only one of the second transistor T2 and the third transistor T3 includes a bottom gate structure. Also, in an exemplary embodiment, one of the fourth transistor T4 to the seventh transistor T7 may have a bottom gate structure.

[0209] In addition to this structure, at least one of the second transistor T2 to the seventh transistor T7 may further include a second gate electrode that receives a driving voltage ELVDD.

[0210] In the above exemplary embodiment, the driving transistor T1 includes a second gate electrode G1-2 on a polycrystalline semiconductor layer while having a bottom gate structure. However, according to an exemplary embodiment, the second gate electrode G1-2 may be omitted. Now refer to Figure 15 Describe this structure.

[0211] Figure 15 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0212] Unlike Figure 1 the exemplary embodiment of Figure 15 in the driving transistor T1 of the exemplary embodiment of

[0213] Now describe Figure 15 the cross-section of the driving transistor T1 according to the exemplary embodiment of

[0214] An overlap layer M1 is disposed on the upper barrier layer 111, and the overlap layer M1 is covered by a buffer layer 112. A gate electrode G1 is formed on the buffer layer 112, and the gate electrode G1 is covered by a first gate insulating layer 141. A polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S1, a second electrode D1, and a channel disposed therebetween.

[0215] The polycrystalline semiconductor layer is covered by a second gate insulating layer 142, and an interlayer insulating layer 160 is disposed on the second gate insulating layer 142.

[0216] A driving voltage application unit C-1 is formed on the interlayer insulating layer 160. The driving voltage application unit C-1 is connected to the overlap layer M1 through an opening that exposes the overlap layer M1. Also, the driving voltage application unit C-1 is connected to a driving voltage line 172 so that a driving voltage ELVDD flows. As a result, the driving voltage ELVDD is also applied to the overlap layer M1. The driving voltage application unit C-1 may be a part extending from the driving voltage line 172 or only a part that is electrically connected.

[0217] The gate electrode G1 is disposed below the channel of the driving transistor T1, and the gate electrode G1 has a width corresponding (e.g., substantially equal) to the width of the channel. Figure 15 A structure is shown in which the gate electrode G1 extends to the right to connect to the second electrode D3 of the third transistor T3, and except for the extended portion, its width corresponds (e.g., substantially equal) to the width of the channel.

[0218] In Figure 15 the driving transistor T1, a second gate electrode is not formed on the polycrystalline semiconductor layer so that a mask can be utilized separately when doping the polycrystalline semiconductor layer. According to an exemplary embodiment, the structure of the driving voltage application unit C-1 can be formed by covering the shape of the channel of the driving transistor T1 so that an exemplary embodiment without using a mask can be achieved.

[0219] According to an exemplary embodiment, the overlapping layer M1 can be omitted.

[0220] In each exemplary embodiment described herein, wirings and electrodes disposed at the same layer can be formed of the same material. Layers disposed on the second gate insulating layer 142 can be formed of the same material and can be formed by using one mask. Moreover, each layer disposed on the upper barrier layer 111, disposed on the buffer layer 112, disposed on the first gate insulating layer 141, and disposed on the interlayer insulating layer 160 can be formed of the same material.

[0221] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments of the present invention, those of ordinary skill in the art will understand that various changes in form and detail can be made without departing from the scope and spirit of the present invention as defined in the appended claims.

Claims

1. An organic light emitting diode display, comprising: a substrate; and pixels disposed on the substrate; wherein, the pixels comprise: an organic light emitting element; and a driving transistor that applies a current to the organic light emitting element; wherein, the driving transistor comprises: a first gate electrode; and a semiconductor layer including a channel, wherein, the first gate electrode of the driving transistor is disposed between the semiconductor layer of the driving transistor and the substrate, wherein, an overlap layer of the driving transistor is disposed between the substrate and the first gate electrode of the driving transistor, and wherein, the first gate electrode and the overlap layer are disposed in a region between the semiconductor layer of the driving transistor and the substrate, and in a plan view, the first gate electrode overlaps the overlap layer in the region between the semiconductor layer of the driving transistor and the substrate.

2. The organic light emitting diode display according to claim 1, further comprising: a scan line; a data line; a driving voltage line that transmits a driving voltage; and an initialization voltage line, wherein, the scan line, the data line, the driving voltage line, and the initialization voltage line are connected to the pixels.

3. The organic light emitting diode display according to claim 2, wherein, the driving voltage is applied to the overlap layer of the driving transistor.

4. The organic light emitting diode display according to claim 2, wherein, the pixel further comprises: a first switching transistor connected to the scan line and the data line; and a second switching transistor connected to the scan line and the first gate electrode of the driving transistor.

5. The organic light emitting diode display according to claim 4, wherein, the driving transistor has a bottom gate structure having the first gate electrode of the driving transistor disposed below the semiconductor layer of the driving transistor.

6. The organic light emitting diode display according to claim 5, wherein, the first switching transistor and the second switching transistor have a top gate structure, and wherein, the top gate structure has a gate electrode disposed on the semiconductor layer including the channel.

7. The organic light emitting diode display according to claim 6, wherein, at least one of the first switching transistor and the second switching transistor includes a second overlap layer disposed between the substrate and the semiconductor layer, and wherein, the driving voltage is applied to the second overlap layer.

8. The organic light emitting diode display according to claim 7, wherein, both the first switching transistor and the second switching transistor respectively have the second overlap layer.

9. The organic light emitting diode display according to claim 6, further comprising at least one compensation transistor for compensating for the operation of the driving transistor, wherein, the at least one compensation transistor has the top gate structure.

10. The organic light emitting diode display according to claim 9, wherein, At least one of the compensation transistors includes a third overlapping layer disposed between the substrate and the semiconductor layer, and wherein, the driving voltage is applied to the third overlapping layer.

11. The organic light emitting diode display according to claim 5, wherein, the first switching transistor and the second switching transistor each have the bottom gate structure.

12. The organic light emitting diode display according to claim 11, further comprising at least one compensation transistor that compensates for the operation of the driving transistor, wherein, the at least one compensation transistor has a top gate structure, and wherein, the top gate structure has a gate electrode disposed on the semiconductor layer including the channel.

13. The organic light emitting diode display according to claim 1, wherein, the semiconductor layer includes polycrystalline semiconductor.

14. The organic light emitting diode display according to claim 1, wherein, the driving transistor further includes a second gate electrode disposed on the semiconductor layer of the driving transistor.

15. An organic light emitting diode display, comprising: a substrate; a pixel disposed on the substrate; a scan line; a data line; a driving voltage line; and an initialization voltage line, wherein, the scan line, the data line, the driving voltage line and the initialization voltage line are connected to the pixel, wherein, the pixel includes: an organic light emitting element; a first switching transistor connected to the scan line; a driving transistor that applies current to the organic light emitting element; and a compensation transistor that compensates for the operation of the driving transistor, wherein, the driving transistor includes: a bottom gate electrode; and a semiconductor layer including a channel, wherein, the compensation transistor includes: a semiconductor layer including a channel; a first gate electrode disposed on the semiconductor layer of the compensation transistor; and a second gate electrode disposed below the semiconductor layer of the compensation transistor, wherein, the bottom gate electrode of the driving transistor is disposed between the semiconductor layer of the driving transistor and the substrate.

16. The organic light emitting diode display according to claim 15, wherein, the driving transistor further includes: a top gate electrode disposed on the semiconductor layer of the driving transistor.

17. The organic light emitting diode display according to claim 16, wherein, the top gate electrode of the driving transistor receives a driving voltage.

18. The organic light emitting diode display according to claim 17, wherein, the driving transistor further includes: an overlapping layer disposed between the substrate and the bottom gate electrode of the driving transistor.

19. The organic light emitting diode display according to claim 18, wherein, the driving voltage flowing to the driving voltage line is applied to the overlapping layer.

20. The organic light emitting diode display according to claim 19, further comprising: A driving voltage applying unit that applies the driving voltage to the overlapping layer and the top gate electrode of the driving transistor.

21. The organic light emitting diode display according to claim 15, wherein, the pixel further includes: a second switching transistor, wherein the first switching transistor is connected to the scan line and the data line, and the second switching transistor is connected to the scan line and the driving transistor.

22. The organic light emitting diode display according to claim 21, wherein, the first switching transistor includes: a semiconductor layer including a channel; and a first gate electrode disposed on the semiconductor layer of the first switching transistor.

23. The organic light emitting diode display according to claim 22, wherein, the first switching transistor further includes: a second gate electrode disposed under the semiconductor layer of the first switching transistor.

24. The organic light emitting diode display according to claim 21, wherein, the first switching transistor includes: a gate electrode disposed on the substrate; and a semiconductor layer disposed on the gate electrode of the first switching transistor, and the semiconductor layer includes a channel.

25. The organic light emitting diode display according to claim 21, wherein, the second switching transistor includes: a semiconductor layer including a channel; and a first gate electrode disposed on the semiconductor layer of the second switching transistor.

26. The organic light emitting diode display according to claim 25, wherein, the second switching transistor further includes: a second gate electrode disposed under the semiconductor layer of the second switching transistor.

27. The organic light emitting diode display according to claim 26, wherein, the first switching transistor includes: a semiconductor layer including a channel; and a first gate electrode disposed on the semiconductor layer of the first switching transistor.

28. The organic light emitting diode display according to claim 27, wherein, the first switching transistor further includes: a second gate electrode disposed under the semiconductor layer of the first switching transistor.

29. The organic light emitting diode display according to claim 26, wherein, the driving transistor further includes: an overlapping layer disposed between the substrate and the bottom gate electrode of the driving transistor, wherein the overlapping layer receives a driving voltage, and the overlapping layer is electrically connected to the second gate electrode of the second switching transistor so that the driving voltage is applied to the second gate electrode of the second switching transistor.

30. The organic light emitting diode display according to claim 29, further includes: a driving voltage applying unit, wherein the driving transistor further includes a top gate electrode disposed on the semiconductor layer of the driving transistor, and The driving voltage applying unit applies the driving voltage to the overlapping layer and the top gate electrode of the driving transistor.

31. The organic light emitting diode display according to claim 21, wherein, the second switching transistor includes: a gate electrode disposed on the substrate; and a semiconductor layer disposed on the gate electrode of the second switching transistor, and the semiconductor layer includes a channel.

32. The organic light emitting diode display according to claim 15, wherein, the compensation transistor initializes the bottom gate electrode of the driving transistor.

33. The organic light emitting diode display according to claim 15, wherein, the driving transistor further includes a top gate electrode disposed on the semiconductor layer of the driving transistor.

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