Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device. The array substrate comprises at least one terminal group (C) located in the binding area (BB), and the terminal group (C) is provided with a plurality of terminals (3) which are sequentially arranged in the second direction; the at least one connecting line group (D) and the data line (2) are located on the same side of the substrate (1) and located in the binding area (BB), the connecting line group (D) comprises a plurality of connecting lines (4), one end of each connecting line (4) is electrically connected with the data line (2), the other end of each connecting line (4) is electrically connected with the terminal (3), and the connecting lines (4) of the same connecting line group (D) are electrically connected to the same terminal group (C); in the connection line group (D), a plurality of connection lines (4) located on at least one side of the terminal group (C) are provided with a plurality of wiring regions (CX) in the second direction, the line widths (W) of the connection lines (4) in the same wiring region (CX) are substantially equal, and the line widths (W) of the connection lines (4) in the wiring regions (CX) are sequentially reduced in the direction from the connection line (4) on the outermost edge of the connection line group (D) to the terminal group (C).

Description

Array substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] With the development of information technology, electronic devices have become widely used in people's daily lives. Liquid crystal displays (LCDs), as the most widely used flat-panel displays, occupy a key position in display panels. Currently, the notebook market is increasingly pursuing low cost and high display performance, requiring optimized display screen design. The cost of source chips for display screens is relatively high. Most current products use a single-gate design. Adopting a dual-gate design would reduce the number of source chips used per screen by half, significantly reducing the initial cost of the product. However, existing dual-gate design products can exhibit poor display quality, such as black blocks or split-screen display (as shown in the dashed box in Figure 1).

[0003] Summary of the Invention

[0004] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate has a display area and a binding area located on one side of the display area, wherein the array substrate includes:

[0005] substrate;

[0006] a plurality of data lines, located on one side of the substrate, located in the display area, and extending along a first direction;

[0007] at least one terminal group, located on the same side of the substrate as the data line and located in the binding area, the terminal group comprising a plurality of terminals sequentially arranged along the second direction;

[0008] at least one connecting wire group, located on the same side of the substrate as the data line and located in the binding area, the connecting wire group comprising a plurality of connecting wires, one end of each connecting wire being electrically connected to the data line and the other end being electrically connected to the terminal, and the connecting wires of the same connecting wire group being electrically connected to the same terminal group;

[0009] Among them, in the connecting wire group, multiple connecting wires located on at least one side of the terminal group are arranged in multiple wiring areas along the second direction, the line widths of the connecting wires in the same wiring area are roughly equal, and the line widths of the connecting wires in each wiring area decrease in the direction from the connecting wire at the outermost edge of the connecting wire group to the terminal group.

[0010] In a possible implementation manner, the line spacing of the connecting lines in each wiring area decreases in a direction from the connecting lines at the outermost edge to the terminal group.

[0011] In a possible implementation manner, the line width W and line spacing S of a single connecting line in the wiring area satisfy the following relationship:

[0012] Among them, k represents the order of the wiring areas in the direction from the edge of the connecting wire group to the terminal group, f represents the number of the wiring areas in the direction from the edge of the connecting wire group to the terminal group, m is the display resolution of the array substrate along the second direction, n is the number of the terminal groups, and G represents the maximum width of the wiring area in the first direction.

[0013] In a possible implementation, the line width W and line spacing S of the connecting lines further satisfy the following relationship:

[0014] In a possible implementation manner, the line width difference of the connection lines in any two adjacent wiring areas is equal.

[0015] In a possible implementation manner, the number of the connecting wires in each wiring area increases in a direction from the outermost connecting wire in the connecting wire group to the terminal group.

[0016] In a possible implementation manner, in a direction from the outermost connecting wire in the connecting wire group to the terminal group, lengths of the wiring regions in the second direction are equal or increase.

[0017] In a possible implementation manner, in the second direction, the number H of the connecting lines in the wiring area farthest from the terminal group satisfies the following relationship:

[0018] Wherein, f represents the number of the wiring areas in the direction from the edge of the connecting wire group to the terminal group, m is the display resolution of the array substrate along the second direction, and n is the number of the terminal groups.

[0019] In a possible implementation manner, in a direction from the outermost connection line to the terminal group, the number of the connection lines in adjacent wiring areas increases sequentially by H.

[0020] In a possible implementation manner, in a direction from the outermost connection line to the terminal group, a length d of each wiring area in the second direction satisfies the following relationship: d=H*P;

[0021] Wherein, P represents the width of the sub-pixel on the array substrate in the second direction.

[0022] In a possible implementation, the wiring area includes: a first sub-wiring area, and a second sub-wiring area located on a side of the first sub-wiring area facing the display area; the connecting line extends along the first direction in the second sub-wiring area;

[0023] In a direction from the outermost connection line to the terminal group, a ratio of the second sub-wiring area to the wiring area in which it is located gradually decreases.

[0024] In a possible implementation manner, the line resistance R of the outermost connecting line is fmax Satisfies the following relationship:

[0025] Among them, R aa represents the resistance of the data line, R fmin represents the resistance of the connection line extending between the terminal group and the display area along the first direction.

[0026] In a possible embodiment, the array substrate further includes a connection area located between adjacent wiring areas, the connection area including connection traces electrically connected one-to-one with at least some of the connection lines in the adjacent wiring areas, and the connection traces intersect with an extension direction of the connection lines.

[0027] In a possible implementation manner, an angle α formed by the connecting trace and the second direction and away from the terminal group ranges from 30° to 65°.

[0028] In one possible embodiment, the line width of the connecting trace is the same as the line width of the connecting line in the adjacent wiring area away from the terminal group; the line spacing of the connecting trace is the same as the line spacing of the connecting line in the adjacent wiring area away from the terminal group.

[0029] In a possible implementation manner, in a direction from the outermost connection line to the terminal group, the minimum widths of at least two adjacent wiring areas in the first direction increase.

[0030] In a possible implementation manner, at least a portion of the connection line electrically connected to the data line is curved; at least a portion of the connection line electrically connected to the terminal group is curved.

[0031] In a possible implementation manner, the shape of the connection line at the portion electrically connected to the data line includes: an S-shaped curve, a bow shape, or a broken line shape.

[0032] In one possible embodiment, the connecting line includes: a main connecting line, a first auxiliary connecting line electrically connected to the data line, and a second auxiliary connecting line electrically connected to the terminal; the main connecting line is provided with a first compensation part at the position where it is connected to the first auxiliary connecting line, and the main connecting line is provided with a second compensation part at the position where it is connected to the second auxiliary connecting line.

[0033] In a possible implementation, the array substrate further includes: a plurality of dummy gate driving units located at the periphery of the display area, and a plurality of floating transistors electrically connected to output ends of the dummy gate driving units.

[0034] In one possible embodiment, the array substrate further includes: a plurality of first transistors located in the display area; in the second direction, the density of the floating transistors is approximately equal to the density of the first transistors in the display area; in the first direction, the density of the floating transistors in the binding area is greater than the density of the first transistors in the display area.

[0035] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0036] An embodiment of the present disclosure further provides a display device, which includes the display panel provided in the embodiment of the present disclosure and also includes a control chip, and the control chip is bound and electrically connected to the terminal group. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic diagram of a Block defect;

[0038] FIG2 is a timing diagram of a conventional single pixel during a 1H charging period;

[0039] FIG3 is a schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0040] FIG4 is an enlarged schematic diagram of the dotted frame S1 in FIG3 ;

[0041] FIG5A is an enlarged schematic diagram of the dotted frame Q1 in FIG4 ;

[0042] FIG5B is an enlarged schematic diagram of FIG5A at the dotted frame Q2;

[0043] FIG5C is an enlarged schematic diagram of the dotted frame S2 in FIG4 ;

[0044] FIG5D is an enlarged schematic diagram of FIG5C at the dotted frame S3;

[0045] FIG5E is a schematic cross-sectional view of FIG5C taken along dotted line EF;

[0046] FIG6A is another enlarged schematic diagram of the dashed box S2 in FIG4 ;

[0047] FIG6B is a schematic cross-sectional view of FIG6A taken along dotted line EF;

[0048] FIG6C is an enlarged schematic diagram of a connecting line in FIG6A ;

[0049] FIG7 is a partial schematic diagram of the connection line provided by an embodiment of the present disclosure at the connection point with the data line;

[0050] FIG8 is a partial schematic diagram of the connection between the connecting wire and the terminal group provided by an embodiment of the present disclosure;

[0051] FIG9 is a partially enlarged schematic diagram of FIG7 at the dotted frame S4;

[0052] FIG10 shows the range of the connection line resistance shown in FIG9 ;

[0053] FIG11 is an enlarged schematic diagram of the position of the dotted frame S6 in FIG7 and the position of the dotted frame S7 in FIG8;

[0054] FIG12 is a schematic diagram showing the distribution of gate drive units in a related design;

[0055] FIG13 is a schematic diagram of a floating transistor provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0057] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0058] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0059] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0060] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0061] Existing dual-gate display devices have multiple ICs (for example, two ICs), which increases the distance between the far end of the panel and the ICs. This leads to a significant difference in impedance between the far end and the near end, resulting in black blocks between the ICs or poor screen splitting. Alternatively, to reduce the overall length of the printed circuit board (PCB), the leftmost and rightmost ICs on the panel edge are moved toward the center, which can also cause these block defects.

[0062] Figure 1 illustrates a common block defect. The center of the IC facing the display is brighter, while the farther away from the IC, the darker it gets. Furthermore, the distance between the two ICs causes a noticeable block or split screen in the center of the display area (AA). This is primarily due to the impedance difference between the near and far ends of the fan-out traces, which leads to inconsistent loading on the data lines in the center and on either side of the IC. This results in significant differences in the charging rate of each pixel, leading to varying brightness levels and ultimately, a block defect. Specifically, Figure 2 shows a typical timing diagram for a single pixel within a 1H charging period. Here, t1 is the data line delay, which is primarily related to the impedance and capacitance of the panel load. t2 is the effective charging time. t3 is the time from the gate signal turning off to the data signal turning off. As can be seen, a larger t1 value shortens the effective charging time t2, resulting in a lower pixel charging rate. Therefore, t1 is a critical parameter that must be strictly controlled.

[0063] The Data line delay time satisfies the following relationship:

[0064] t1 = R*C, where R represents the resistance of the data line and C represents the capacitance of each data line.

[0065] From the above formula, we can see that since the number of pixels in each column is consistent, the capacitance C of each data line in the display area is consistent. The underside of the panel typically uses an alternating wiring design to prevent cross-capacitance. Therefore, the capacitance of each data line can be considered consistent. The resistance R of each data line can also be considered consistent within the display area, since the number of pixels in each column is consistent. Therefore, the difference in resistance R between each data line is primarily reflected in the fan-out wiring area. Due to the current demand for low-cost, narrow-bezel, and narrow PCBs, specifically halving the number of ICs can halve IC costs, which increases wiring distances and leads to greater impedance differences between the near and far ends. Narrower bezels reduce fan-out wiring space, resulting in thinner traces, which also increases the impedance difference between the near and far ends. Shorter PCB lengths and closer IC placement to the center of the panel also increase the impedance difference between the near and far ends. Therefore, innovative design and optimized design methods for the existing fan-out wiring area are urgently needed to address display defects.

[0066] In view of this, an embodiment of the present disclosure provides an array substrate, as shown in Figures 3, 4, 5A-5E, and 6A-6C, wherein Figure 4 is an enlarged schematic diagram of Figure 3 at the dotted frame S1, Figure 5A is an enlarged schematic diagram of Figure 4 at the dotted frame Q1, Figure 5B is an enlarged schematic diagram of Figure 5A at the dotted frame Q2, Figure 5C is an enlarged schematic diagram of Figure 4 at the dotted frame S2, Figure 5D is an enlarged schematic diagram of Figure 5C at the dotted frame S3, Figure 5E is a cross-sectional schematic diagram of Figure 5C at the dotted line EF, Figure 6A is another enlarged schematic diagram of Figure 4 at the dotted frame S2, Figure 6B is a cross-sectional schematic diagram of Figure 6A at the dotted line EF, and Figure 6C is an enlarged schematic diagram of a connecting line in Figure 6A, comprising a display area AA and a binding area BB located on one side of the display area AA, wherein the array substrate includes:

[0067] Substrate 1;

[0068] A plurality of data lines 2 are located on one side of the substrate 1, in the display area AA, and extend along a first direction X;

[0069] At least one terminal group C is located on the same side of the substrate 1 as the data line 2 and in the bonding area BB. The terminal group C includes a plurality of terminals 3 arranged sequentially along the second direction Y. Specifically, the terminals of the array substrate terminal group C can be subsequently bonded to the terminals of the control chip IC in a one-to-one correspondence.

[0070] At least one connecting wire group D is located on the same side of the substrate 1 as the data line 2 and is located in the bonding area BB. The connecting wire group D includes a plurality of connecting wires 4. One end of the connecting wire 4 is electrically connected to the data line 2 and the other end is electrically connected to the terminal 3. The connecting wires 4 in the same connecting wire group D are all electrically connected to the same terminal group C. Specifically, the connecting wires 4 electrically connected to one terminal group C can be regarded as one connecting wire group D.

[0071] In the connection line group D, the plurality of connection lines 4 located on at least one side of the terminal group C are arranged in a plurality of wiring areas CX along the second direction Y. The line widths W of the connection lines 4 in the same wiring area CX are substantially equal, and the line widths W of the connection lines 4 in each wiring area CX decrease in the direction from the outermost connection line 4 in the connection line group D to the terminal group C (in the direction from arrow Z1 to arrow Z2 in FIG. 3 or FIG. 4 ). Specifically, the line widths W of the connection lines 4 in each wiring area CX may decrease sequentially. Specifically, for example, as shown in Figure 4, the area between the display area AA and the terminal group C is divided in sequence from the connecting line 4 at the outermost edge of the connecting line group D to the terminal group C: the first wiring area CX1, the second wiring area CX2, the third wiring area CX3, the fourth wiring area CX4, and the fifth wiring area CX5, wherein the line width of the connecting line 4 in the first wiring area CX1 is greater than the line width of the connecting line 4 in the second wiring area CX2; the line width of the connecting line 4 in the second wiring area CX2 is greater than the line width of the connecting line 4 in the third wiring area CX3; the line width of the connecting line 4 in the third wiring area CX3 is greater than the line width of the connecting line 4 in the fourth wiring area CX4; the line width of the connecting line 4 in the fourth wiring area CX4 is greater than the line width of the connecting line 4 in the fifth wiring area CX5.

[0072] In the disclosed embodiment, the connecting line 4 between the display area AA and the terminal group C is divided into several wiring areas CX, and the line width W of the connecting line 4 in the same wiring area CX is roughly equal. In addition, in the direction from the connecting line 4 at the outermost edge of the connecting line group D to the terminal group C, the line width W of the connecting line 4 in each wiring area CX decreases successively, that is, the line width of the distal connecting line 4 is increased, thereby reducing the resistance of the distal connecting line 4, reducing the resistance difference between the distal connecting line 4 and the proximal connecting line 4, making the line resistance of the connecting line 4 at each position roughly the same, and improving the poor display of black blocks or split-screen display.

[0073] It should be noted that, when the display panel is provided with only one terminal group C, the direction from the connecting wire 4 at the outermost edge of the connecting wire group D to the terminal group C may refer to the direction from the outer edge of the display panel to the terminal group C; when two display panels are provided, the direction from the connecting wire 4 at the outermost edge of the connecting wire group D to the terminal group C may refer to the direction from the middle of the display panel to the terminal group C.

[0074] In one possible implementation, the line spacing S of the connecting wires 4 in each wiring area CX decreases in a direction from the outermost connecting wire 4 in the connecting wire group D to the terminal group C. Specifically, the line spacing S of the connecting wires 4 in each wiring area CX may decrease sequentially in a direction from the outermost connecting wire 4 in the connecting wire group D to the terminal group C.

[0075] In the embodiment of the present disclosure, the farther away from the terminal group C, the fewer the number of connecting wires 4, the larger the wiring space along the first direction X, and the larger the line width W and line spacing S of the connecting wires 4 can be designed; the closer to the terminal group C, the more the number of connecting wires 4, the smaller the wiring space along the first direction X, and the smaller the line width W and line spacing S of the connecting wires 4 need to be designed. By making the line width W of the connecting wires 4 in each wiring area CX decrease in the direction from the outermost edge of the connecting wire group D to the terminal group C and the line spacing S of the connecting wires 4 in each wiring area CX decrease in sequence, the space of each wiring area CX can be effectively utilized, the line width W of the distal connecting wire 4 can be increased, the resistance of the distal connecting wire 4 can be reduced, the resistance difference between the distal connecting wire 4 and the proximal connecting wire 4 can be reduced, and the poor display of black blocks or split screen display can be improved.

[0076] In one possible embodiment, as shown in Figures 5C-5E , the connection lines 4 may be arranged using a double-layer metal routing, for example, alternating between a gate layer (Gate) and a data layer (SD). In another possible embodiment, as shown in Figures 6A-6C , the connection lines 4 may be arranged using a single-layer metal routing, for example, either a gate layer (Gate) or a data layer (SD).

[0077] It should be noted that Figure 4 is only a schematic illustration of dividing the area between the display area AA and the terminal group C, and between the left edge and the left terminal group C, into five wiring areas CX. In specific implementation, the area between the display area AA and the terminal group C can also be set with other numbers of wiring areas CX. For example, it can be divided into 4 wiring areas CX; for another example, it can also be divided into 5 wiring areas CX; for another example, it can also be divided into 6 wiring areas CX; for another example, it can also be divided into 7 wiring areas CX; for another example, it can also be divided into 8 wiring areas CX; for another example, it can also be divided into 9 wiring areas CX; for another example, it can also be divided into 10 wiring areas CX.

[0078] In a possible implementation, with reference to FIG. 5C to FIG. 5E and FIG. 6A to FIG. 6C , the line width W and line spacing S of a single connecting line 4 in the wiring area CX satisfy the following relationship:

[0079] Among them, k represents the order of the wiring areas CX in the direction from the edge of the connecting line group D to the terminal group D (that is, the corresponding nth segment of the wiring areas, for example, in Figure 4, the order corresponding to the leftmost wiring area CX can be 1, and the order corresponding to the rightmost wiring area CX can be 5), which can be a constant of 1 to 10, f represents the number of wiring areas CX in the direction from the edge of the connecting line group D to the terminal group D, which can be a constant of 4 to 10, m is the display resolution of the array substrate along the second direction Y, n is the number of terminal groups C, G represents the maximum width of the wiring area in the first direction X, that is, the distance value in the first direction X between the connecting line 4 farthest from the lower edge of the array substrate (the lower edge can be the edge of the array substrate closest to the terminal group C in the first direction X) and the connecting line 4 closest to the array substrate.

[0080] Specifically, the display resolution of the array substrate along the second direction Y may refer to the resolution in pixel units, where a pixel unit may include three sub-pixels of red, green, and blue. That is, if m is the display resolution of the array substrate along the second direction Y, then the number of data lines 2 may be 3m.

[0081] In a possible implementation, with reference to FIG. 5C to FIG. 5E and FIG. 6A to FIG. 6C , the line width W and line spacing S of the connecting line 4 further satisfy the following relationship:

[0082] In this way, during the display panel manufacturing process, when the frame sealant between the sealed array substrate and the opposing substrate is UV-cured, the relationship between the line width W and the line spacing S can meet the transmittance requirements when curing the frame sealant, avoiding the line width and line spacing being too large or too small, which affects the curing effect of the frame sealant.

[0083] In one possible embodiment, the difference in line width W between the connecting lines 4 of any two adjacent wiring regions CX is equal. Specifically, for example, the difference in line width W between the connecting lines 4 of the first wiring region CX1 and the second wiring region CX2 is 0.5 μm, and the difference in line width between the connecting lines 4 of the third wiring region CX3 and the fourth wiring region CX4 is also 0.5 μm.

[0084] In a possible implementation manner, the difference in line width W between the connection lines 4 of any two adjacent wiring areas CX is ≥0.5 um.

[0085] Specifically, for example, the line width of the connecting line 4 in the first wiring area CX1 is 4.0μm~10μm, the line width of the connecting line 4 in the second wiring area CX2 is 3.5μm~8.0μm, the line width of the connecting line 4 in the third wiring area CX3 is 3.0μm~5.5μm, the line width of the connecting line 4 in the fourth wiring area CX4 is 2.5μm~4.5μm, and the line width of the connecting line 4 in the fifth wiring area CX5 is 2.0μm~4μm.

[0086] In a possible implementation, in a direction from the outermost connection line 4 in the connection line group D to the terminal group C, the number of connection lines 4 in each wiring area CX is equal or increases.

[0087] In a possible implementation, in the second direction Y, the number H of the connecting wires 4 in the wiring area CX farthest from the terminal group C satisfies the following relationship:

[0088] Wherein, f represents the number of wiring areas CX in the direction from the edge of the connecting line group D to the terminal group D, m is the display resolution of the array substrate along the second direction Y, and n is the number of the terminal groups C.

[0089] In a possible implementation, the number of connection lines 4 in adjacent wiring areas CX increases sequentially by H from the outermost connection line 4 in the connection line group D to the terminal group C. Specifically, the value of H is generally designed to be 60-200.

[0090] In one possible embodiment, as shown in FIG4 , the length of each wiring area CX in the second direction Y increases from the outermost connection line 4 to the terminal group C. Specifically, the length of each wiring area CX in the second direction Y may increase sequentially from the outermost connection line 4 to the terminal group C.

[0091] Specifically, in the direction from the outermost connection line 4 in the connection line group D to the terminal group C, the length d of each wiring area CX in the second direction Y satisfies the following relationship:

[0092] d=H*P, where P represents the width of the sub-pixel on the array substrate in the second direction Y. Specifically, the length d of the wiring area CX in the second direction Y can be designed to be in the range of 5 mm to 20 mm.

[0093] In one possible embodiment, as shown in Figures 4 and 5C , the wiring area CX includes a first sub-wiring area CXA and a second sub-wiring area CXB located on the side of the first sub-wiring area CXA facing the display area AA. Connecting lines 4 extend in the second sub-wiring area CXB along a first direction X. The ratio of the second sub-wiring area CXB to the wiring area CX in which it resides gradually decreases from the outermost connecting lines 4 to the terminal group C. For example, as shown in Figure 3 , the entire leftmost first wiring area CX1 is distributed with connecting lines 4 extending in the first direction X. Within this first wiring area CX1, the ratio of the second sub-wiring area CXB to the first wiring area CX1 in which it resides can be 100%. Meanwhile, within the rightmost fifth wiring area CX5, only a portion of the area is distributed with connecting lines 4 extending in the first direction X. Within this fifth wiring area CX5, the ratio of the second sub-wiring area CXB to the fifth wiring area CX5 in which it resides can be, for example, 80%.

[0094] In a possible embodiment, the line resistance R of the outermost connecting line 4 is fmax Satisfies the following relationship:

[0095] Among them, R aa Represents the resistance of data line 2, R fmin represents the resistance of the connection line 4 extending between the terminal group C and the display area AA along the first direction X. This ensures that the resistance difference between the distal connection line 4 and the proximal connection line 4 is ≤35%. Consequently, when displaying an image, the grayscale difference can be kept below the grayscale difference discernible to the human eye (the human eye can generally discern a difference of two grayscales (1 grayscale ≈ 12mV), meaning a voltage difference of 24mV is visible).

[0096] Specifically, the resistance difference percentage ΔR between the distal connection line and the proximal connection line satisfies the following relationship:

[0097] R=R aa +R fanout ; Among them, R max is the resistance value of the panel remote connection line 4 (corresponding to the connection line 4 near Z1 in FIG4 ), R min is the resistance value of the connecting wire 4 just above the terminal group C. aa is the resistance value of the data line in the panel display area (the resistance value on each data line is usually the same), R fanout The resistance of the connection line between the panel display area and terminal group C (control design is required). The following table shows the charging voltage simulation values ​​of different screens corresponding to the resistance difference of a certain display product:

[0098] As can be seen from the table above, when designing the traces between the panel display area and terminal group C, the impedance difference between the near and far ends must be ΔR ≤ 35% to prevent block failure.

[0099] In one possible embodiment, as shown in conjunction with Figures 5C-5E and 6A-6C, the array substrate further includes a connection region M located between adjacent wiring regions CX. The connection region M includes connection traces M0 that are electrically connected one-to-one to at least some of the connection lines 4 in the adjacent wiring regions CX. The connection traces M0 intersect with the extension direction of the connection lines 4. Specifically, as shown in conjunction with Figures 5A and 5B, some connection lines 4 may not pass through the connection traces M0 to enter the adjacent wiring region CX. For example, in Figure 5B, the bottommost connection line 4 may not bend, but may only change in width before entering the adjacent wiring region CX.

[0100] In one possible embodiment, as shown in Figures 5C-5E and 6A-6C, the minimum distance between the end of the same connecting trace M0 near the terminal group C and the display area AA is greater than the minimum distance between the end away from the terminal group C and the display area AA. In other words, the connecting trace M0 is an inclined line, with the lower end closer to the terminal group C.

[0101] Specifically, as shown in Figure 6C, the angle α formed by the connecting trace M0 and the second direction Y and away from the terminal group C can range from 30° to 65°. Specifically, for example, it can be 30°, 35°, 40°, 45°, 50°, 55°, 60°, or 65°.

[0102] Specifically, as shown in Figure 6C, the line width W0 of the connecting trace M0 can be the same as the line width W0 of the connecting line 4 in the adjacent wiring area CX away from the terminal group C; the line spacing S of the connecting trace M0 can be the same as the line spacing S of the connecting line 4 in the adjacent wiring area CX away from the terminal group C.

[0103] In one possible embodiment, as shown in FIG5A , the minimum width J of at least two adjacent wiring regions CX in the first direction X increases in the direction from the outermost connection line 4 to the terminal group C. That is, as shown in FIG4 , for example, the minimum width J of the second wiring region CX2 in the first direction X is greater than the minimum width J of the first wiring region CX1 in the first direction X; and for another example, the minimum width J of the third wiring region CX3 in the first direction X is greater than the minimum width J of the second wiring region CX2 in the first direction X.

[0104] It should be noted that, since each wiring area CX has a new connection line 4 added on the side facing the display area A, the minimum width J of the wiring area CX in the first direction X can be the width of the wiring area CX close to the previous connection area M (the previous connection area M is the connection area adjacent to the wiring area CX and away from the terminal group C), as shown in FIG5A , that is, the distance value in the first direction X between the first new connection line 4 added to the wiring area CX and the connection line 4 closest to the lower edge of the display panel (that is, the lowest connection line 4 in FIG5A ).

[0105] It is understood that, in conjunction with FIG5A , the number of connection lines 4 in the wiring area CX may include the number of connection lines 4 newly added in the connecting area M adjacent to the wiring area CX and away from the terminal group C. For example, as shown in FIG5A , the number of connection lines 4 in the wiring area CX on the right side also includes the two connection lines 4 newly added in the connecting area M on its left side.

[0106] In one possible embodiment, referring to Figures 7, 8, 9, and 10, Figure 9 may be a partially enlarged schematic diagram of Figure 7 at the dashed box S4 or Figure 8 at the dashed box S5. Figure 10 illustrates the resistance ranges of the data lines and the connecting wires connected to the data lines shown in Figure 9. The abscissa of Figure 10 represents the order of the data lines and the connecting wires connected to the data lines, and the ordinate represents the resistance of the data lines and the connecting wires connected to the data lines. As shown in Figure 7, the connecting wire 4 is curved at least partially where it is electrically connected to the data line 2. As shown in Figure 8, the connecting wire 4 is curved at least partially where it is electrically connected to the terminal group C. In the disclosed embodiment, the curved shape of the connecting wire 4 at least partially where it is electrically connected to the data line 2 and / or the curved shape of the connecting wire 4 at least partially where it is electrically connected to the terminal group C effectively reduces the resistance difference between two adjacent connecting wires 4, ensuring uniform resistance changes without sudden changes. Specifically, the resistance difference ΔR between two adjacent connecting wires 4 is ≤ 1%, preventing display-related defects.

[0107] In a possible implementation, the shape of the connection line 4 at the portion electrically connected to the data line 2 includes: an S-shaped curve, a bow shape, or a broken line shape.

[0108] Specifically, the line width W of the connecting line 4 in the bow-shaped area can be designed to be 2.0 μm to 8.0 μm, and the line spacing S is usually designed to be 4.0 μm to 10.0 μm.

[0109] In a possible embodiment, refer to Figure 11, wherein the left side of Figure 11 can be an enlarged schematic diagram of Figure 7 at the position of the dotted box S6, and the right side of Figure 11 can be an enlarged schematic diagram of Figure 8 at the position of the dotted box S7, the connecting line 4 includes: a main connecting line 40, a first auxiliary connecting line 41 electrically connected to the data line 2, and a second auxiliary connecting line 42 electrically connected to the terminal 3; the main connecting line 40 is provided with a first compensation part 51 at the position where it is connected to the first auxiliary connecting line 41 (such as the dotted box SA), and the main connecting line 40 is provided with a second compensation part 52 at the position where it is connected to the second auxiliary connecting line 42 (such as the dotted box SB). In the embodiment of the present disclosure, a first compensation portion 51 is provided at the position where the main connecting line 40 is connected to the first auxiliary connecting line 41, and a second compensation portion 52 is provided at the position where the main connecting line 40 is connected to the second auxiliary connecting line 42. This can avoid the situation where, when the connecting line 4 is patterned, the area around the connecting line 4 in the dotted box SA, SB, and SC is a light-transmitting area exposed by the mask plate. When the metal routing line width is designed to be small (for example, ≤4μm), the line width in the dotted box SA, SB, and SC area is very thin due to the excessive exposure, which may lead to a broken line.

[0110] Specifically, the first compensation portion 51 can be located on the side of the main connecting line 40 facing the display area AA, and the second compensation portion 52 can be located on the side of the main connecting line 40 facing the terminal group C. Specifically, for the connecting line 4 located inside the wiring area CX, the first compensation portion 51 or the second compensation portion 52 can be set on one side of the connecting line 4 (such as the dotted boxes SA and SB in Figure 11). For the connecting line 4 located at the edge of the wiring area CX, the first compensation portion 51 or the second compensation portion 52 can be set on both sides of the connecting line 4 (such as the dotted box SC in Figure 11).

[0111] Specifically, for the dotted box SA, SB, and SC areas, the line width b1 of the added first compensation part 51 (or the second compensation part 52) ​​can be 0.7μm to 1.5μm, and the routing distance corner spacing b2 after adding the first compensation part 51 (or the second compensation part 52) ​​can be 3.0μm to 7μm.

[0112] In the related art, as shown in Figure 12, it can be seen that the output terminal Output of the gate drive unit GOA in this row is both the reset terminal Reset of the gate drive unit GOA in the previous row and the input terminal Input of the gate drive unit GOA in the next row, so their waveforms affect each other. In order to reset the last row of gate drive units GOA (n), a virtual (Dummy) gate drive unit GOA (DG) design is provided, but the virtual gate drive unit Dummy GOA is not connected to the display area (Active Area, AA), that is, there is no AA area load. However, since the virtual gate drive unit Dummy GOA has no display area pixel unit to connect to, the load of these rows of virtual gate drive units Dummy GOA will be inconsistent with the load of the gate drive unit GOA in the normal area.

[0113] In view of this, referring to FIG13 , the array substrate of the embodiment of the present disclosure includes: a plurality of virtual gate drive units DG located at the periphery of the display area AA, and also includes: a plurality of floating transistors DT (Dummy TFT) electrically connected to the output terminal Output of the virtual gate drive unit DG. In the embodiment of the present disclosure, the array substrate also includes: a plurality of floating transistors DT electrically connected to the output terminal Output of the virtual gate drive unit DG, which can make the load on the output terminal Output of the virtual gate drive unit DG basically consistent with the load on the output terminal Output of the normal gate drive unit GOA. Moreover, without setting pixels, only designing floating transistors DT can greatly reduce the space of the display panel on the first side X, thereby reducing the bottom frame of the display panel; adding the floating transistor DT design can ensure that the density of the gate pattern, source and drain pattern, and active layer pattern outside the display area is consistent with that inside the display area. The consistency makes the film formation around the display area uniform, especially for oxide transistor display panel products, which can effectively improve the poor conductivity problem around the display area caused by uneven source and drain patterns; moreover, adding a floating transistor DT design can also effectively prevent static electricity at the terminal group C and other positions at the bottom of the display panel from entering the display area and burning the transistor, resulting in a short circuit between the power line and the data line (i.e., DGS failure) or a source-drain short circuit. In the embodiment of the present disclosure, since static electricity will be preferentially introduced into the floating transistor DT position, the source and drain on the floating transistor DT will be short-circuited, but this short circuit will not cause any actual impact.

[0114] In one possible embodiment, the array substrate further includes: a plurality of first transistors T1 located in the display area AA; in the second direction, the density of the floating transistors DT is substantially equal to the density of the first transistors T1 in the display area AA, thereby ensuring that the load on the output terminal Output of the virtual gate driver unit DG is substantially consistent with the load on the output terminal Output of the normal gate driver unit GOA; in the first direction X, the density of the floating transistors DT in the binding area BB is greater than the density of the first transistors T1 in the display area AA, thereby reducing the space of the display panel in the first direction X, thereby reducing the bottom frame of the display panel.

[0115] Specifically, the size of the floating transistor DT at the output end of the virtual gate driving unit DG is consistent with the design size of the transistor in the display area (that is, the source and drain pattern shape and size of the floating transistor DT are consistent with the source and drain pattern shape and size of the transistor in the display area; the gate pattern shape and size of the floating transistor DT are consistent with the gate pattern shape and size of the transistor in the display area; the active layer pattern shape and size of the floating transistor DT are consistent with the active layer pattern shape and size of the transistor in the display area).

[0116] Specifically, the number of floating transistors DT connected to the output end of each virtual gate driving unit DG is consistent with the number of transistors DT connected to the output end of the display area gate driving unit DG.

[0117] Specifically, the distance between two adjacent upper and lower gate lines connected to the output terminal of the virtual gate driving unit DG may be 5 μm to 10 μm, and may be smaller than the distance between two adjacent gate lines in the display area.

[0118] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0119] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel as provided in the embodiment of the present disclosure, and also includes a control chip IC, and the control chip IC is bound and electrically connected to the terminal group C.

[0120] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0121] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, comprising a display area and a binding area located on one side of the display area, wherein: The array substrate comprises: substrate; A plurality of data lines are located on one side of the substrate, located in the display area, and extending along a first direction; at least one terminal group, located on the same side of the substrate as the data line and located in the binding area, the terminal group having a plurality of terminals arranged in sequence along the second direction; At least one connection line group is located on the same side of the substrate as the data line and is located in the binding area, the connection line group includes a plurality of connection lines, one end of the connection line is electrically connected to the data line, and the other end is electrically connected to the terminal, and the connection lines of the same connection line group are all electrically connected to the same terminal group; Among them, in the connecting wire group, multiple connecting wires located on at least one side of the terminal group are arranged in multiple wiring areas along the second direction, the line widths of the connecting wires in the same wiring area are roughly equal, and the line widths of the connecting wires in each wiring area decrease in the direction from the connecting wire at the outermost edge of the connecting wire group to the terminal group.

2. The array substrate according to claim 1, wherein: In a direction from the outermost connection line in the connection line group to the terminal group, the line spacing of the connection lines in each wiring area decreases.

3. The array substrate according to claim 1 or 2, wherein: The line width W and line spacing S of a single connecting line in the wiring area satisfy the following relationship: Among them, k represents the order of the wiring areas in the direction from the edge of the connecting wire group to the terminal group, f represents the number of the wiring areas in the direction from the edge of the connecting wire group to the terminal group, m is the display resolution of the array substrate along the second direction, n is the number of the terminal groups, and G represents the maximum width of the wiring area in the first direction.

4. The array substrate according to claim 3, wherein: The line width W and line spacing S of the connecting line also satisfy the following relationship:

5. The array substrate according to any one of claims 1 to 4, wherein: The line width difference of the connection lines in any two adjacent wiring areas is equal.

6. The array substrate according to any one of claims 1 to 5, wherein: In a direction from the outermost connection wire in the connection wire group to the terminal group, the number of the connection wires in each wiring area increases.

7. The array substrate according to any one of claims 1 to 6, wherein: In the direction from the outermost connection line in the connection line group to the terminal group, the lengths of the wiring areas in the second direction are equal or increase.

8. The array substrate according to claim 6 or 7, wherein: In the second direction, the number H of the connection lines in the wiring area farthest from the terminal group satisfies the following relationship: Among them, f represents the number of the wiring areas in the direction from the edge of the connecting line group to the terminal group, m is the display resolution of the array substrate along the second direction, and n is the number of the terminal groups.

9. The array substrate according to claim 8, wherein: In the direction from the outermost connection line to the terminal group, the number of the connection lines in adjacent wiring areas increases sequentially by H.

10. The array substrate according to claim 8 or 9, wherein: In the direction from the outermost connection line to the terminal group, the length d of each wiring area in the second direction satisfies the following relationship: d=H*P; Wherein, P represents the width of the sub-pixel on the array substrate in the second direction.

11. The array substrate according to any one of claims 1 to 10, wherein: The wiring area includes: a first sub-wiring area, and a second sub-wiring area located on a side of the first wiring area facing the display area; the connection line extends along the first direction in the second sub-wiring area; In the direction from the outermost connection line to the terminal group, the ratio of the second sub-wiring area to the wiring area in which it is located gradually decreases.

12. The array substrate according to any one of claims 1 to 11, wherein: The line resistance R of the outermost edge of the connecting line fmax Satisfies the following relationship: in, Raa represents the resistance of the data line, R fmin represents the resistance of the connection line extending between the terminal group and the display area along the first direction.

13. The array substrate according to any one of claims 1 to 12, wherein: The array substrate further includes a connection area between adjacent wiring areas, wherein the connection area includes connection traces electrically connected one-to-one with at least some of the connection traces in the adjacent wiring areas, and the connection traces intersect with an extension direction of the connection traces.

14. The array substrate according to claim 13, wherein: The angle α formed by the connecting line and the second direction and away from the terminal group is in the range of 30° to 65°.

15. The array substrate according to claim 13 or 14, wherein: The line width of the connecting trace is the same as the line width of the connecting line in the adjacent wiring area away from the terminal group; the line spacing of the connecting trace is the same as the line spacing of the connecting line in the adjacent wiring area away from the terminal group.

16. The array substrate according to any one of claims 1 to 15, wherein: In the direction from the outermost connection line to the terminal group, the minimum widths of at least two adjacent wiring areas in the first direction increase.

17. The array substrate according to any one of claims 1 to 16, wherein: The shape of at least a part of the connecting line where it is electrically connected to the data line is curved; the shape of at least a part of the connecting line where it is electrically connected to the terminal group is curved.

18. The array substrate according to claim 17, wherein: The shape of the connection line at the portion where it is electrically connected to the data line includes: an S-shaped curve, a bow shape, or a broken line shape.

19. The array substrate according to any one of claims 1 to 18, wherein: The connecting line includes: a main connecting line, a first auxiliary connecting line electrically connected to the data line, and a second auxiliary connecting line electrically connected to the terminal; the main connecting line is provided with a first compensation part at a position where it is connected to the first auxiliary connecting line, and the main connecting line is provided with a second compensation part at a position where it is connected to the second auxiliary connecting line.

20. The array substrate according to any one of claims 1 to 19, wherein: The array substrate further comprises: a plurality of dummy gate driving units located at the periphery of the display area, and a plurality of floating transistors electrically connected to output ends of the dummy gate driving units.

21. The array substrate according to claim 20, wherein: The array substrate also includes: a plurality of first transistors located in the display area; in the second direction, the density of the floating transistors is substantially equal to the density of the first transistors in the display area; in the first direction, the density of the floating transistors in the binding area is greater than the density of the first transistors in the display area.

22. A display panel, wherein: Comprising the array substrate as described in any one of claims 1-21.

23. A display device, wherein: It includes the display panel as claimed in claim 22, and also includes a control chip, wherein the control chip is bound and electrically connected to the terminal group.

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