Indication of quality for random numerical value generation

Abstract

One or more examples relate to generating a quality indication for a randomly generated value or more generally a random value generator. An example apparatus can include a memory and a logic circuit. Such a memory is used to receive and store a previously randomly generated value and a currently randomly generated value. Such logic circuitry is to: determine a relationship between the previously randomly generated value and the currently randomly generated value; and generate an indication of the quality of the current randomly generated value in response at least in part to the determined relationship between the previously randomly generated value and the current randomly generated value.

Description

[0001] Priority Claim

[0002] This application claims the benefit of the filing date of U.S. Patent Application Serial No. 18 / 053,458, entitled "INDICATION OF QUALITY FOR RANDOM NUMBER GENERATION", filed on November 8, 2022, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] One or more examples generally relate to random number generation, and more particularly to logic circuitry for increasing the entropy of random number generation. Background Art

[0004] Random number generators are electronic components that exist in many applications. For example, random number generators specifically exist in security components of applications involving data exchange (such as: automotive, industrial, Internet of Things, electronic metering, and point of sale). Brief Description of the Drawings

[0005] To easily identify the discussion of any particular element or action, the most significant digit in the reference numeral refers to the figure number in which that element was first introduced.

[0006] Figure 1 is a block diagram depicting an apparatus for generating an indication of the quality of a randomly generated value according to one or more examples.

[0007] Figure 2 is a functional block diagram depicting a system for conditioning the output of a random number generator according to one or more examples.

[0008] Figure 3A is a functional block diagram depicting a random number generator according to one or more examples.

[0009] Figure 3B is a functional block diagram depicting an arrangement of a random number generator and an output conditioner according to one or more examples.

[0010] Figure 4 is a functional block diagram depicting an output conditioner for generating an indication as to whether a string distance between two values (i.e., randomly generated values) meets or exceeds a threshold.

[0011] Figure 5 is a functional block diagram depicting an output conditioner that gates the supply of randomly generated values in response to an indication as to whether a string distance between two values (i.e., randomly generated values) meets or exceeds a threshold.

[0012] Figure 6 is a functional block diagram depicting an output regulator that applies a correction to a randomly generated value in response to detecting a threshold number of failed attempts to generate the randomly generated value.

[0013] Figure 7 is a flowchart depicting a process for generating an indication of the quality of a randomly generated value according to one or more examples.

[0014] Figure 8 is a flowchart depicting a process for determining a relationship between a current randomly generated value and a previous randomly generated value according to one or more examples.

[0015] Figure 9 is a flowchart depicting a process for determining a string distance between a current randomly generated value and a previous randomly generated value according to one or more examples.

[0016] Figure 10 is a flowchart depicting an example of a process for applying a correction to a randomly generated value in response to detecting a threshold number of failed attempts to generate the randomly generated value.

[0017] Figure 11 is a block diagram of a circuit that may be used in some examples to implement various functions, operations, actions, processes, and / or methods disclosed herein. Detailed Description

[0018] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific examples in which the disclosure may be practiced. The examples are described in sufficient detail to enable those of ordinary skill in the art to practice the disclosure. However, other examples may be utilized and structural, material, and process changes may be made without departing from the scope of the disclosure.

[0019] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations of examples for describing the disclosure. In some cases, for the convenience of the reader, similar structures or components in the various figures may retain the same or similar numbers; however, the similarity of the numbers does not necessarily mean that the structures or components are the same in terms of size, composition, configuration, or any other property.

[0020] The following description may include examples to help enable a person of ordinary skill in the art to practice the disclosed examples. The use of the terms "exemplary", "such as", and "for example" means that the relevant description is illustrative, and although the scope of the present disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the examples or the scope of the present disclosure to the specified components, steps, features, functions, etc.

[0021] It should be readily understood that the components of the examples, as generally described herein and illustrated in the figures, can be arranged and designed in a variety of different configurations. Accordingly, the following description of the various examples is not intended to limit the scope of the present disclosure, but merely represents the various examples. Although aspects of these examples may be presented in the figures, the figures are not necessarily drawn to scale unless specifically indicated.

[0022] In addition, the specific embodiments shown and described are only examples and should not be construed as the only way to implement the present disclosure, unless otherwise indicated herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure with unnecessary detail. On the contrary, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise indicated herein. Additionally, the block definitions and the partitioning of logic between various blocks are examples of a specific embodiment. It will be apparent to a person of ordinary skill in the art that the present disclosure can be practiced with many other partitioning solutions. In most cases, details regarding timing considerations, etc. have been omitted, where such details are not required to obtain a full understanding of the present disclosure and are within the capabilities of a person of ordinary skill in the relevant art.

[0023] A person of ordinary skill in the art will understand that any of a variety of different techniques and methodologies can be used to represent information and signals. For clarity of presentation and description, some of the figures may illustrate a signal as a single signal. A person of ordinary skill in the art should understand that a signal can represent a signal bus, where the bus can have a variety of bit widths, and the present disclosure can be implemented on any number of data signals, including a single data signal.

[0024] The various illustrative logical blocks, modules, logics, and circuits described in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a dedicated processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor (also referred to herein as a host processor or simply a host) may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. When a general purpose computer is configured to execute the computing instructions (e.g., software code) associated with the examples of the present disclosure, the general purpose computer including the processor is considered a special purpose computer.

[0025] Examples may be described in accordance with processes depicted as flowcharts, process schematics, structural diagrams, or block diagrams. Although a flowchart may describe operational actions as a sequential process, many of these actions may be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of the actions may be rearranged. The processes herein may correspond to methods, threads, functions, procedures, subroutines, subprograms, other structures, or combinations thereof. In addition, the methods disclosed herein may be implemented by hardware, software, or both. If implemented in software, the functions may be stored or transmitted as one or more instructions or code on a computer-readable medium. The computer-readable medium includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.

[0026] Any reference in this document to elements using terms such as “first,” “second,” etc. does not limit the number or order of those elements, unless such limitations are expressly stated. Instead, these terms may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, a reference to a first element and a second element does not mean that only two elements can be present, or that the first element must precede the second element in some manner. In addition, unless otherwise specified, a group of elements may include one or more elements.

[0027] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the extent to which the given parameter, property, or condition is satisfied with a minor degree of variance that would be understood by one of ordinary skill in the art, such as, for example, within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied to at least 90%, at least 95%, or even at least 99%.

[0028] In this description, the terms "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as "coupled" to another element, then the element may be in direct physical or electrical contact, or there may be intervening elements or layers. In contrast, when an element is described as "directly coupled" to another element, then there are no intervening elements or layers. The terms "on" and "connected" in this description may be used interchangeably with the term "coupled" and have the same meaning, unless otherwise expressly indicated or the context would otherwise indicate to one of ordinary skill in the art.

[0029] Various applications of a random number generator have different requirements for randomness, and the level of randomness is referred to as "entropy". As used herein, the "quality" of a random number generator or a randomly generated number may be understood as an indication of its entropy. It may be desirable for a random number generator or an electronic device utilizing a random number generator to include circuitry for generating an indication of the quality of a randomly generated number or, more generally, of the random number generator.

[0030] The disclosed indication of quality may be used to adjust the output of a random number generator, such as: increasing the entropy of a randomly generated number or the random number generator, storing the random number generator and making it available to an observer of the random number generator, providing a randomly generated number to indicate quality, or combinations thereof, but not limited thereto.

[0031] As a non-limiting example, the disclosed indication of quality may be used to identify, for example, multiple instances of the same number or insufficiently different numbers generated by one or more random number generators in a system that obtains randomly generated numbers from multiple random number generators. As a non-limiting example, the disclosed indication of quality may be used to track and identify a random number generator that does not exhibit sufficient entropy (e.g., as represented by a predetermined threshold entropy). In various examples, the value of the threshold entropy may be user-configurable, e.g., set and optionally reset by the user.

[0032] Figure 1 is a block diagram depicting apparatus 100 for generating an indication of the quality of a randomly generated number according to one or more examples. Apparatus 100 includes a memory 102 coupled to a logic circuit 108.

[0033] The memory 102 includes one or more non-transitory computer-readable memories for respectively receiving and storing a previously randomly generated value 104 and a currently randomly generated value 106. In one or more examples, the previously randomly generated value 104 and the currently randomly generated value 106 are strings of one or more numbers (e.g., integers or floating-point numbers, but not limited thereto) generated in response to a random number generation process. The respective random number generation processes in response to which the previously randomly generated value 104 and the currently randomly generated value 106 are generated may be the same or different. Additionally, the same random number generator or different random number generators may be utilized to generate the previously randomly generated value 104 and the currently randomly generated value 106. In one or more examples, the previously randomly generated value 104 is generated before (i.e., earlier in time) the currently randomly generated value 106.

[0034] In one or more examples, the previously randomly generated value 104 and the currently randomly generated value 106 may have been generated consecutively, or one or more intermediate randomly generated values may have been generated between them. In one or more examples, the previously randomly generated value 104 may be the most recently randomly generated value provided to a user (e.g., read by the user, but not limited thereto).

[0035] The logic circuit 108 includes one or more combinational logic circuits for determining a relationship 112 (″the determined relationship 112″) between the previously randomly generated value 104 and the currently randomly generated value 106, and for generating an indication 110 of the quality of the currently randomly generated value 106 at least partially in response to the determined relationship 112. In one or more examples, the determined relationship 112 may indicate the degree of sameness between the corresponding previously randomly generated value 104 and the currently randomly generated value 106. In one or more examples, the degree of sameness may be used as an indication of the magnitude of the entropy of the currently randomly generated value 106.

[0036] One or more examples generally relate to regulating the output of a random number generator by generating and providing an indication 110 of quality associated with the currently randomly generated value 106.

[0037] Figure 2 is a functional block diagram depicting a system 200 for regulating the output of a random number generator according to one or more examples. The system 200 includes a random number generator 202 and an output regulator 204.

[0038] The random number generator 202 generates random numbers, such as the random numbers provided as the output 206 of the random number generator 202 in the system 200. Non-limiting examples of random number generators include noise sources coupled to the input of a string generator. Non-limiting examples of noise sources include analog noise sources (such as resistors and amplifiers) for generating sufficient amplitude to drive an analog-to-digital converter, digital noise sources (such as one or more variable or fixed frequency ring oscillators), or combinations thereof.

[0039] The output regulator 204 adjusts the output 206 of the random number generator 202 at least in part in response to an indication 210 of the quality of the number generated by the random number generator 202, and this adjustment is represented by Figure 2 the adjusted output 208 in. As described herein, adjusting the output of a random number generator may include, but is not limited to: providing a value along with the randomly generated number, where the value represents the quality of the randomly generated number; or filtering the output of the random number generator to allow only randomly generated numbers with an associated indication of quality that meets or exceeds a quality threshold to pass. In one or more examples, the output regulator 204 may include Figure 1 the logic circuit 108 or device 100 of to generate an indication 210 of quality.

[0040] In one or more examples, the disclosed output regulator may be coupled to the output of the random number generator, for example, as in Figure 1 and Figure 3B the depicted examples. Additionally or alternatively, the disclosed output regulator may be within the random number generator, and more specifically, within the string generator of the random number generator as in Figure 3A the depicted examples.

[0041] Figure 3A is a functional block diagram of a random number generator 300a according to one or more examples, the random number generator including a string generator (here an N-bit string generator 304), the string generator including an output regulator 204.

[0042] The random number generator 300a may include a digital noise source 302 and an N-bit string generator 304. The digital noise source 302 generates a digital noise signal 306 at least in part in response to a control signal 308. In one or more examples, the digital noise source 302 is an entropy source for random number generation. Any suitable digital entropy source may be used for the digital noise source 302, including but not limited to digital entropy generators (such as variable or fixed frequency ring oscillators, but not limited thereto) or digital entropy generators that utilize computational entropy.

[0043] A non-limiting example of a digital noise source utilizing computational entropy is a coupled or cross-coupled linear feedback shift register (LFSR) pair clocked by a variable or fixed frequency ring oscillator. In the case of a cross-coupled LFSR pair, the shift value in the respective LFSR is utilized to modify a bus clock that clocks the variable frequency ring oscillator of the other LFSR in the pair that does not clock the respective LFSR.

[0044] In one or more examples, the output 306 of the digital noise source 302 can be a one-bit or multi-bit signal (e.g., generated by one or more variable or fixed frequency ring oscillators, but not limited thereto). The N-bit string generator 304 generates an N-bit string in response to the stream of the one-bit or multi-bit signal output 306, wherein the randomly generated value 310 is the generated N-bit string.

[0045] Optionally, N-bit string generator 304 may generate control signal 308 at least partially in response to modified clock signal 316 and a previous digital noise signal of digital noise signal 306 generated by digital noise source 302. An optional feedback loop may be used to increase entropy in the output of digital noise source 302.

[0046] The N-bit string generator 304 includes an output conditioner 204 for conditioning an output 310 of the N-bit string generator 304. In various examples, the output conditioner 204 may condition the output 310 by providing an indication of quality (e.g., the indication of quality 110, but not limited thereto) to the output 310 or providing an indication of the quality of intermediate randomly generated numerical values ​​determined by the N-bit string generator 304, and the N-bit string generator 304 may select or discard intermediate randomly generated numerical values ​​(as discussed below) to generate the output 310 based at least in part on the indication of quality provided by the output conditioner 204.

[0047] Figure 3B is a block diagram depicting an arrangement in which an input of an output regulator 204 is coupled to receive an output 314 of an N-bit string generator 312, which N-bit string generator may optionally be part of the logic circuitry of a random value generator 300b, or may optionally be separate from the logic circuitry of the random value generator 300b, in a separate logic circuit.

[0048] Figure 4 , Figure 5 and Figure 6 Depicted include Figure 2 An example of an output regulator 204 is shown.

[0049] Figure 4is a functional block diagram depicting an output regulator 400 that generates an indication 414 as to whether a string distance between two values (i.e., randomly generated values) meets or exceeds a threshold value.

[0050] The output regulator 400 includes a calculator 404 and a comparator 402. The calculator 404 is configured to calculate a string distance 410 between a previously randomly generated value 406 and a currently randomly generated value 408. The comparator 402 is configured to generate an indication 414 that is an indication of the relationship between a string distance threshold 412 and the string distance 410. The indication 414 is another indication of the state of the currently randomly generated value 408. In this case, a value of the string distance 410 that is equal to or greater than the string distance threshold 412 value may correspond to a first state of the currently randomly generated value 408, and a value of the string distance 410 that is less than the string distance threshold 412 value may correspond to a second different state of the currently randomly generated value 408.

[0051] In one or more examples, the value of the string distance threshold 412 may be a set value 418 that is provided by a user and stored at an optional memory 416 (which may be the same or different memory as Figure 1 memory 102). In one or more examples, the value of the string distance threshold 412 may be programmable or hard-coded at the output regulator 400.

[0052] Figure 5 is a functional block diagram depicting an output regulator 500 according to one or more examples that gates the supply of randomly generated values in response to an indication 514 as to whether a string distance between two values (i.e., randomly generated values) meets or exceeds a threshold value. The output regulator 500 is Figure 2 a non-limiting example of the output regulator 204.

[0053] The output regulator 500 includes a calculator 504, a comparator 502, and a register 516. The calculator 504 is configured to calculate a string distance 510 between a currently randomly generated value 508 and a previously randomly generated value 506. The comparator 502 is configured to generate an indication 514 of the state of the currently randomly generated value 508 at least in part in response to the string distance 510 and the string distance threshold 512.

[0054] The register 516 is configured to sample and save the currently randomly generated value 508 at least in part in response to the indication 514 of the state of the currently randomly generated value 508.

[0055] As a non - limiting example, the value of the string distance threshold 512 can represent a predetermined minimum acceptable string distance between the currently randomly generated value 508 and a previously randomly generated value 506. In this case, when the value of the string distance 510 meets or exceeds the value of the string distance threshold 512, the register 516 can sample and save the currently randomly generated value 508. When the indication 514 indicates that the value of the indication of quality 110 meets or exceeds the value of the string distance threshold 512, the indication 518 can be asserted to indicate that a valid random value is stored at the register 516 and is available for reading by the user. When the indication 514 indicates that the value of the indication of quality 110 does not meet or exceed the value of the string distance threshold 512, the indication 518 can be de - asserted to indicate that neither a valid value is stored at the register 516 nor is it available for reading by the user.

[0056] Figure 6 is a functional block diagram depicting an output regulator 600 according to one or more examples, the output regulator being for applying a transformation (e.g., correction) to a randomly generated value in response to detecting a threshold number of failed attempts to generate the randomly generated value. The output regulator 600 is Figure 2 a non - limiting example of the output regulator 204.

[0057] The output regulator 600 includes a comparator 602, a calculator 604, a timer 620, a corrector 622, and a register 616.

[0058] The calculator 604 is for calculating the string distance 610 between the currently randomly generated value 608 and a previously randomly generated value 606. The comparator 602 is for generating an indication 614 of the status of the currently randomly generated value 608 in at least partial response to a comparison of the string distance 610 and the string distance threshold 612.

[0059] The timer 620 is for generating a value of time 632 that represents the duration (e.g., the number of clock cycles of an optional clock signal 624 or the number of counted randomly generated values, but not limited to this) since the last indication 614 generated by the comparator 602, the last indication indicating that the calculated value of the string distance 610 exceeds the value of the string distance threshold 612.

[0060] The corrector 622 is for generating an output 618 that includes: a transformed currently randomly generated value in at least partial response to detecting that the time 632 generated by the timer 620 exceeds the value of a timeout threshold 630; or the currently randomly generated value 608 in at least partial response to detecting that the value of the time 632 generated by the timer 620 is reset before exceeding the value of the timeout threshold 630. The corrector 622 can also generate an indication 628 that is an indication of the quality of the randomly generated value 626.

[0061] Non-limiting examples of algorithms for transforming randomly generated values include a bitwise exclusive OR (XOR) operation on each bit and every bit of a previously randomly generated value that meets quality requirements. For each bit and every bit, one input to the XOR is driven by the bit of the previously randomly generated value, and the other input to the XOR is driven by the output of timer 620. In the case of a timeout event, the newly randomly generated value is the "negation" of the previously randomly generated value, and thus is the maximum hamming distance between the value generated by the XOR operation and the previously generated random value. In various examples, the XOR operation can be applied to fewer than each bit and every bit of the previously randomly generated value, as long as the XOR operation is applied to a sufficient number of bits to equal or be greater than the value of the string distance threshold 612. In one or more examples, the number of bits to which the XOR operation can be applied can be variable, as long as a sufficient number of bits are applied to equal or be greater than the value of the string distance threshold 612.

[0062] Register 616 is used to store the output 618 of corrector 622 and to provide a randomly generated value 626 that is either the currently randomly generated value 608 or a transformed version of the currently randomly generated value 608.

[0063] Figure 7 is a flowchart depicting process 700 for generating an indication of the quality of a randomly generated value according to one or more examples. As a non-limiting example, process 700 can be performed by logic circuit 108 in cooperation with the values of a previously randomly generated value 104 and a currently randomly generated value 106 stored at memory 102 to generate an indication of quality.

[0064] In operation 702, process 700 determines the relationship between the previously randomly generated value and the currently randomly generated value. As discussed above, the determined relationship is an indication of the entropy of the currently randomly generated value.

[0065] In operation 704, process 700 generates an indication of the quality of the currently randomly generated value at least in part in response to the determined relationship between the previously randomly generated value and the currently randomly generated value.

[0066] In one or more examples, string distance is used as an indication of the entropy of a randomly generated value, and more specifically as the string distance between the currently generated random value and the previously generated random value. String distance is a value that represents the degree of similarity between two symbol strings. In one or more examples, similarity can be determined at the bit level, the symbol level, or a combination thereof. In various examples, any suitable algorithm can be utilized to determine string distance.

[0067] Figure 8is a flowchart depicting a process 800 for determining a relationship between a currently randomly generated value and a previously randomly generated value according to one or more examples.

[0068] In operation 802, process 800 determines a string distance between the previously randomly generated value and the currently randomly generated value. More specifically, process 800 may generate a value representing the string distance between the previously randomly generated value and the currently randomly generated value. This value may be a numerical value.

[0069] In operation 804, process 800 determines a relationship between the determined string distance and a string distance threshold. The string distance threshold represents a target or desired minimum similarity level between the currently randomly generated value and the previously randomly generated value. In various examples, the value representing the string distance threshold may be a predetermined value set by a user (e.g., a user of device 100, but not limited thereto).

[0070] In optional operation 806, process 800 optionally sets the value of the string distance threshold by the user.

[0071] In operation 808, process 800 uses the determined relationship between the determined string distance and the string distance threshold for the relationship between the previously randomly generated value and the currently randomly generated value determined by the relationship determination logic.

[0072] In optional operation 810, process 800 generates an indication with a first value that represents the determined string distance being greater than or equal to the value of the string distance threshold.

[0073] In optional operation 812, process 800 generates an indication with a second value that represents the determined string distance being less than the string distance threshold.

[0074] Figure 9 is a flowchart depicting a process 900 for determining a string distance between a currently randomly generated value and a previously randomly generated value according to one or more examples.

[0075] In operation 902, process 900 executes a string distance algorithm to determine the string distance between the previously randomly generated value and the currently randomly generated value.

[0076] In optional operation 904, process 900 optionally performs a string distance algorithm by performing one or more of the following: Hamming distance algorithm, Levenshtein distance algorithm, full Damerau-Levenshtein distance algorithm, restricted Damerau-Levenshtein distance algorithm, longest common substring distance algorithm, q-gram distance algorithm, cosine distance algorithm, Jaccard distance algorithm, Jaro distance algorithm, or Jaro-Winkler distance algorithm.

[0077] Figure 10 is a flowchart depicting an example of process 1000 for applying a correction to a randomly generated value in response to detecting a threshold number of failed attempts to generate a randomly generated value.

[0078] In operation 1002, process 1000 determines the relationship between a previously randomly generated value and the current randomly generated value.

[0079] In optional operation 1004, process 1000 detects a timeout condition at least in part in response to determining that the value of a timer counter exceeds a timeout threshold value. In one or more examples, process 1000 determines whether the number of consecutively randomly generated values meets or exceeds a hard-coded or configurable threshold, and if so, detects a timeout condition.

[0080] In operation 1006, process 1000 performs a transformation of the current randomly generated value at least in part in response to the timeout condition. In one or more examples, process 1000 applies a bitwise XOR with the previously randomly generated value. The first input to the XOR circuit is driven by a timer, and the second input to the XOR circuit is driven by the bits of the previously randomly generated value.

[0081] In operation 1008, process 1000 generates an indication of the quality of the modified randomly generated value obtained at least in part in response to the performed transformation of the current randomly generated value.

[0082] Those skilled in the art will appreciate that the functional elements (e.g., functions, operations, actions, processes, and / or methods) of the examples disclosed herein may be implemented in any suitable hardware, software, firmware, or combination thereof. Figure 11 Illustrates non-limiting examples of specific implementations of the functional elements disclosed herein. In some examples, some or all of the functional elements disclosed herein may be performed by hardware specifically configured to perform that functional element.

[0083] Figure 11FIG. 1100 is a block diagram of a circuit 1100 that may be used to implement various functions, operations, actions, processes, and / or methods disclosed herein. Circuit 1100 includes one or more processors 1102 (sometimes referred to herein as "processor 1102") operatively coupled to one or more data storage devices (sometimes referred to herein as "storage 804"). Storage 1104 includes machine-executable code 1106 stored thereon, and processor 1102 includes logic circuitry 1108. Machine-executable code 1106 includes information describing functional elements that may be implemented (e.g., executed) by logic circuitry 1108. Logic circuitry 1108 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 1106. When the functional elements described by machine-executable code 1106 are executed, circuit 1100 should be considered to be specialized hardware configured to execute the functional elements disclosed herein. In some examples, processor 1102 may be configured to execute the functional elements described by machine-executable code 1106 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

[0084] When implemented by logic circuitry 1108 of processor 1102, machine-executable code 1106 is configured to cause processor 1102 to be adapted to perform the operations of the examples disclosed herein, including output conditioning or generating an indication of quality as described herein. As a non-limiting example, machine-executable code 1106 may be configured to cause processor 1102 to be adapted to perform some or all of one or more of the following operations: process 700, process 800, process 900, or process 1000.

[0085] Also as a non-limiting example, machine-executable code 1106 may be configured to cause processor 1102 to be adapted to perform some or all of the features, functions, or operations disclosed herein for one or more of the following: logic circuitry 108, memory 102; random number generator 202 or output conditioner 204; digital noise source 302; N-bit string generator 304; calculator 404, comparator 402, or memory 416; calculator 504, comparator 502, register 516; calculator 604, comparator 602, timer 620, corrector 622, or register 616.

[0086] The processor 1102 may include a general-purpose processor, a dedicated processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof, which are designed to execute the functions disclosed herein. A general-purpose computer including a processor is considered a dedicated computer, and the general-purpose computer is configured to execute functional elements corresponding to machine-executable code 1106 (e.g., software code, firmware code, hardware description) related to the examples of the present disclosure. Note that the general-purpose processor (which may also be referred to as the host processor or simply the host herein) may be a microprocessor, but in an alternative, the processor 1102 may include any conventional processor, controller, microcontroller, or state machine. The processor 1102 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration.

[0087] In some examples, the storage device 1104 includes volatile data storage devices (e.g., random access memory (RAM)), non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), etc.). In some examples, the processor 1102 and the storage device 1104 may be implemented as a single device (e.g., a semiconductor device product, a system-on-chip (SOC), etc.). In some examples, the processor 1102 and the storage device 1104 may be implemented as separate devices.

[0088] In some examples, the machine-executable code 1106 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by the storage device 1104, directly accessed by the processor 1102, and executed by the processor 1102 using at least the logic circuit 1108. Also as a non-limiting example, the computer-readable instructions may be stored on the storage device 1104, transferred to a memory device (not shown) for execution, and executed by the processor 1102 using at least the logic circuit 1108. Thus, in some examples, the logic circuit 1108 includes the logic circuit 1108 that can be configured electrically.

[0089] In some examples, the machine-executable code 1106 can describe hardware (e.g., circuitry) to be implemented in the logic circuitry 1108 to perform functional elements. The hardware can be described at any of a variety of levels of abstraction ranging from low-level transistor layouts to high-level description languages. At a high level of abstraction, a hardware description language (HDL) can be used, such as the IEEE standard hardware description language (HDL). As a non-limiting example, Verilog, SystemVerilog, or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL) can be used.

[0090] The HDL description can be converted to a description at any of a variety of other levels of abstraction as needed. As a non-limiting example, a high-level description can be converted to a logic-level description such as Register Transfer Language (RTL), gate-level (GL) description, layout-level description, or mask-level description. As a non-limiting example, the micro-operations to be performed by the hardware logic circuitry (e.g., gates, flip-flops, registers, but not limited to) of the logic circuitry 1108 can be described in RTL and then converted to a GL description by a synthesis tool, and the GL description can be converted to a layout-level description by placement and routing tools, which corresponds to the physical layout of an integrated circuit, discrete gates or transistor logic, discrete hardware components, or a combination thereof of a programmable logic device. Thus, in some examples, the machine-executable code 1106 can include HDL, RTL, GL description, mask-level description, other hardware descriptions, or any combination thereof.

[0091] In examples where the machine-executable code 1106 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage device 1104) can be configured to implement the hardware description described by the machine-executable code 1106. As a non-limiting example, the processor 1102 can include a programmable logic device (e.g., FPGA or PLC), and the logic circuitry 1108 can be controlled electrically to implement the circuitry corresponding to the hardware description as the logic circuitry 1108. Also as a non-limiting example, the logic circuitry 1108 can include hardwired logic fabricated by a manufacturing system (not shown, but including the storage device 1104) according to the hardware description of the machine-executable code 1106.

[0092] Regardless of whether the machine-executable code 1106 includes computer-readable instructions or a hardware description, the logic circuitry 1108 is adapted to perform the functional elements described by the machine-executable code 1106 when implementing the functional elements of the machine-executable code 1106. Note that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0093] As used in this disclosure, the term "combination" involving multiple elements can include any combination of all the elements or various different sub - combinations of some of the elements. For example, the phrase "A, B, C, D, or combinations thereof" can refer to any one of A, B, C, or D; the combination of each of A, B, C, and D; and any sub - combination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0094] The terms used in this disclosure and particularly in the appended claims (e.g., the body of the appended claims, but not limited thereto) are generally intended to be "open - ended" terms (e.g., the term "comprising" should be interpreted as "comprising but not limited to", the term "having" should be interpreted as "having at least", but not limited thereto). As used herein, the term "each" means some or all. As used herein, the term "every" means all.

[0095] Additionally, if a specific number of introduced claim recitations is intended, such intent will be explicitly recited in the claim, and in the absence of such recitation, there is no such intent. For example, as an aid to understanding, the following appended claims may contain the use of introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim recitation introduced by the indefinite article "a" or "an" limits any particular claim containing such introduced claim recitation to an embodiment containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and the indefinite article, such as "a" or "an" (e.g., "a" and / or "an" can be interpreted to mean "at least one" or "one or more", but not limited thereto); the same is true for the use of the definite article to introduce a claim recitation.

[0096] Furthermore, even if a specific number of the introduced claim recitations is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the unmodified recitation "two recitations" in the absence of other modifying components is intended to mean at least two recitations, or two or more recitations, but not limited thereto). Additionally, in those cases where a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, generally such construction is intended to include only A, only B, only C, both A and B, both A and C, both B and C, or A, B, and C, etc.

[0097] In addition, any discrete word or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, any one of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B". As used herein, "each" means some or all, and "each and every" means all.

[0098] Although the present invention has been described herein with respect to certain illustrated embodiments, those of ordinary skill in the art will recognize and understand that the present invention is not so limited. On the contrary, many additions, deletions, and modifications may be made to the illustrated embodiments and the described embodiments without departing from the scope of the present invention as claimed hereinafter and its legal equivalents. In addition, features from one embodiment may be combined with features from another embodiment while still being included within the scope of the present invention contemplated by the inventors.

[0099] Non-limiting example embodiments of the present disclosure may include:

[0100] Example 1: An apparatus, the apparatus comprising: a memory for receiving and storing a previously randomly generated value and a currently randomly generated value; and a logic circuit for: determining a relationship between the previously randomly generated value and the currently randomly generated value; and generating an indication of the quality of the currently randomly generated value at least in part in response to the determined relationship between the previously randomly generated value and the currently randomly generated value.

[0101] Example 2: The apparatus according to Example 1, wherein the logic circuit is for: determining a string distance between the previously randomly generated value and the currently randomly generated value; determining a relationship between the determined string distance and a string distance threshold; and using the determined relationship between the determined string distance and the string distance threshold for the relationship between the previously randomly generated value and the currently randomly generated value.

[0102] Example 3: The apparatus according to any one of Examples 1 and 2, wherein the logic circuit is for: generating the indication of quality having a first value indicating a first relationship between the determined string distance and the string distance threshold; and generating the indication of quality having a second value indicating a second relationship between the determined string distance and the string distance threshold.

[0103] Example 4: The apparatus according to any one of Examples 1 to 3, wherein the first relationship is that the value of the determined string distance is less than the value of the string distance threshold.

[0104] Example 5: The apparatus according to any one of Examples 1 to 4, wherein the second relationship is that the value of the determined string distance is greater than or equal to the value of the string distance threshold.

[0105] Example 6: The apparatus according to any one of Examples 1 to 5, wherein the value of the string distance threshold is user-configurable.

[0106] Example 7: The apparatus according to any one of Examples 1 to 6, wherein the logic circuit is configured to: execute a string distance algorithm to determine the string distance between the previously randomly generated numerical value and the currently randomly generated numerical value.

[0107] Example 8: The apparatus according to any one of Examples 1 to 7, wherein the string distance algorithm includes one or more of the following: Hamming distance algorithm, Levenshtein distance algorithm, full Damerau-Levenshtein distance algorithm, restricted Damerau-Levenshtein distance algorithm, longest common substring distance algorithm, q-gram distance algorithm, cosine distance algorithm, Jaccard distance algorithm, Jaro distance algorithm, or Jaro-Winkler distance algorithm.

[0108] Example 9: The apparatus according to any one of Examples 1 to 8, the apparatus comprising: another memory for storing a timeout threshold, wherein the logic circuit is configured to: detect a timeout condition at least in part in response to a relationship between a timer count and the timeout threshold; and transform the currently randomly generated numerical value at least in part in response to detecting the timeout condition.

[0109] Example 10: The apparatus according to any one of Examples 1 to 9, wherein the logic circuit is configured to detect the timeout condition at least in part in response to determining that the value of the timer count exceeds the value of the timeout threshold.

[0110] Example 11: The apparatus according to any one of Examples 1 to 10, wherein the logic circuit is configured to generate an indication of the quality of the modified currently randomly generated numerical value obtained at least in part in response to the transformation performed on the currently randomly generated numerical value.

[0111] Example 12: A method, the method comprising: determining a relationship between a previously randomly generated numerical value and a currently randomly generated numerical value; and generating an indication of the quality of the currently randomly generated numerical value at least in part in response to the determined relationship between the previously randomly generated numerical value and the currently randomly generated numerical value.

[0112] Example 13: The method according to Example 12, the method comprising: receiving a string distance threshold; determining a string distance between the previously randomly generated value and the currently randomly generated value; determining a relationship between the determined string distance and the string distance threshold; and determining the relationship between the previously randomly generated value and the currently randomly generated value at least in part in response to the determined relationship between the determined string distance and the string distance threshold.

[0113] Example 14: The method according to any one of Examples 12 and 13, the method comprising: generating the indication having a first value, the first value representing a value where the determined string distance is greater than or equal to the string distance threshold; and generating the indication having a second value, the second value representing a value where the determined string distance is less than the string distance threshold.

[0114] Example 15: The method according to any one of Examples 12 to 14, wherein the value of the string distance threshold is user-configurable.

[0115] Example 16: The method according to any one of Examples 12 to 15, the method comprising: performing a string distance algorithm to determine the string distance between the previously randomly generated value and the currently randomly generated value.

[0116] Example 17: The method according to any one of Examples 12 to 16, wherein performing the string distance algorithm includes performing one or more of the following: Hamming distance algorithm, Levenshtein distance algorithm, full Damerau-Levenshtein distance algorithm, restricted Damerau-Levenshtein distance algorithm, longest common substring distance algorithm, q-gram distance algorithm, cosine distance algorithm, Jaccard distance algorithm, Jaro distance algorithm, or Jaro-Winkler distance algorithm.

[0117] Example 18: The method according to any one of Examples 12 to 17, the method comprising: transforming the currently randomly generated value at least in part in response to a timeout condition.

[0118] Example 19: The method according to any one of Examples 12 to 18, the method comprising: detecting the timeout condition at least in part in response to determining that a value of a timer counter exceeds a value of a timeout threshold.

[0119] Example 20: The method according to any one of Examples 12 to 19, wherein generating the indication of the quality of the currently randomly generated value includes: generating an indication of the quality of a modified currently randomly generated value obtained at least in response to a transformation performed at least in response to the currently randomly generated value.

[0120] Example 21: A system, the system comprising: a random value generator; and an output regulator for regulating the output of the random value generator at least in response to an indication of the quality of a value generated by the random value generator.

[0121] Example 22: The system according to Example 21, wherein the random value generator includes: a digital noise source for generating a digital noise signal at least in response to a control signal; and an n-bit string generator for generating the control signal at least in response to a modified clock signal and a previous digital noise signal generated by the digital noise source.

[0122] Example 23: The system according to any one of Examples 21 and 22, wherein the n-bit string generator includes the output regulator.

[0123] Example 24: The system according to any one of Examples 21 to 23, wherein the output regulator is coupled to the output of the n-bit string generator of the random value generator.

[0124] Example 25: The system according to any one of Examples 21 to 24, wherein the output regulator includes: a calculator for calculating a string distance at least in response to a currently randomly generated value and a previous randomly generated value; and a comparator for generating a regulated output including an indication of the state of the currently randomly generated value at least in response to a comparison of the calculated string distance with a string distance threshold.

[0125] Example 26: The system according to any one of Examples 21 to 25, wherein the output regulator includes: a calculator for calculating a string distance at least in response to a currently randomly generated value and a previous randomly generated value; a comparator for generating an indication of the state of the currently randomly generated value at least in response to a comparison of the calculated string distance with a string distance threshold; and a register for sampling and storing the currently randomly generated value in response to the indication of the state of the currently randomly generated value.

[0126] Example 27: The system according to any one of Examples 21 to 26, wherein the output regulator comprises: a calculator configured to calculate a string distance at least in part in response to a currently randomly generated value and a previously randomly generated value; a comparator configured to generate an indication of the state of the currently randomly generated value at least in part in response to a comparison of the calculated string distance with a string distance threshold; a timer configured to generate a value indicative of the duration since the last indication generated by the comparator, the last indication corresponding to the calculated string distance exceeding the string distance threshold; a corrector configured to: output a transformed currently randomly generated value at least in part in response to detecting that the value generated by the timer exceeds a timeout threshold value; or output the currently randomly generated value at least in part in response to detecting that the value generated by the timer is reset before exceeding the timeout threshold; and a register configured to store the output of the corrector.

[0127] Example 28: The system according to any one of Examples 21 to 27, wherein the corrector is configured to generate an indication of the quality of the output stored at the register.

[0128] The embodiments of the present disclosure described above and illustrated in the accompanying drawings do not limit the scope of the present disclosure, which is covered by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of the present disclosure. Indeed, various modifications of the present disclosure, such as alternative useful combinations of the elements described, will be apparent to those skilled in the art from the specification. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. An apparatus, the apparatus comprises: a memory for receiving and storing a previously randomly generated value and a currently randomly generated value; and a logic circuit for: determining a relationship between the previously randomly generated value and the currently randomly generated value; and generating an indication of the quality of the currently randomly generated value at least in part in response to the determined relationship between the previously randomly generated value and the currently randomly generated value.

2. The apparatus according to claim 1, wherein the logic circuit is for: determining a string distance between the previously randomly generated value and the currently randomly generated value; determining a relationship between the determined string distance and a string distance threshold; and using the determined relationship between the determined string distance and the string distance threshold for the relationship between the previously randomly generated value and the currently randomly generated value.

3. The apparatus according to claim 2, wherein the logic circuit is for: generating the indication of quality having a first value, the first value indicating a first relationship between the determined string distance and the string distance threshold; and generating the indication of quality having a second value, the second value indicating a second relationship between the determined string distance and the string distance threshold.

4. The apparatus according to claim 3, wherein the first relationship is that the value of the determined string distance is less than the value of the string distance threshold.

5. The apparatus according to claim 3, wherein the second relationship is that the value of the determined string distance is greater than or equal to the value of the string distance threshold.

6. The apparatus according to claim 2, wherein the value of the string distance threshold is user-configurable.

7. The apparatus according to claim 2, wherein the logic circuit is for: executing a string distance algorithm to determine the string distance between the previously randomly generated value and the currently randomly generated value.

8. The apparatus according to claim 7, wherein the string distance algorithm comprises one or more of the following: Hamming distance algorithm, Levenshtein distance algorithm, full Damerau-Levenshtein distance algorithm, restricted Damerau-Levenshtein distance algorithm, longest common substring distance algorithm, q-gram distance algorithm, cosine distance algorithm, Jaccard distance algorithm, Jaro distance algorithm or Jaro-Winkler distance algorithm.

9. The apparatus according to claim 1, the apparatus comprises: another memory for storing a timeout threshold, wherein the logic circuit is for: detecting a timeout condition at least in part in response to a relationship between a timer count and the timeout threshold; and transforming the currently randomly generated value at least in part in response to detecting the timeout condition.

10. The apparatus according to claim 9, wherein the logic circuit is for detecting the timeout condition at least in part in response to determining that the value of the timer count exceeds the value of the timeout threshold.

11. The apparatus according to claim 9, wherein the logic circuit is configured to generate an indication of the quality of a modified currently randomly generated value obtained at least in response to a transformation performed on the currently randomly generated value.

12. A method, the method comprising: determining a relationship between a previously randomly generated value and a currently randomly generated value; and generating an indication of the quality of the currently randomly generated value at least in response to the determined relationship between the previously randomly generated value and the currently randomly generated value.

13. The method according to claim 12, the method comprising: receiving a string distance threshold; determining a string distance between the previously randomly generated value and the currently randomly generated value; determining a relationship between the determined string distance and the string distance threshold; and determining the relationship between the previously randomly generated value and the currently randomly generated value at least in response to the determined relationship between the determined string distance and the string distance threshold.

14. The method according to claim 13, the method comprising: generating the indication having a first value, the first value representing a value where the determined string distance is greater than or equal to the string distance threshold; and generating the indication having a second value, the second value representing a value where the determined string distance is less than the string distance threshold.

15. The method according to claim 13, wherein the value of the string distance threshold is user-configurable.

16. The method according to claim 13, the method comprising: performing a string distance algorithm to determine the string distance between the previously randomly generated value and the currently randomly generated value.

17. The method according to claim 16, wherein performing the string distance algorithm comprises performing one or more of the following: Hamming distance algorithm, Levenshtein distance algorithm, full Damerau-Levenshtein distance algorithm, restricted Damerau-Levenshtein distance algorithm, longest common substring distance algorithm, q-gram distance algorithm, cosine distance algorithm, Jaccard distance algorithm, Jaro distance algorithm, or Jaro-Winkler distance algorithm.

18. The method according to claim 12, the method comprising: performing a transformation of the currently randomly generated value at least in response to a timeout condition.

19. The method according to claim 18, the method comprising: detecting the timeout condition at least in response to determining that a value of a timer counter exceeds a value of a timeout threshold.

20. The method according to claim 18, wherein generating the indication of the quality of the currently randomly generated value comprises: generating an indication of the quality of a modified currently randomly generated value obtained at least in response to a transformation performed on the currently randomly generated value.

21. A system, the system comprising: a random value generator; and An output regulator for regulating the output of the random number generator at least in part in response to an indication of the quality of a value generated by the random number generator.

22. The system according to claim 21, wherein the random number generator comprises: a digital noise source for generating a digital noise signal at least in part in response to a control signal; and an n-bit string generator for generating the control signal at least in part in response to a modified clock signal and a previous digital noise signal generated by the digital noise source.

23. The system according to claim 22, wherein the n-bit string generator comprises the output regulator.

24. The system according to claim 22, wherein the output regulator is coupled to the output of the n-bit string generator of the random number generator.

25. The system according to claim 21, wherein the output regulator comprises: a calculator for calculating a string distance at least in part in response to a currently randomly generated value and a previously randomly generated value; and a comparator for generating a regulated output comprising an indication of the state of the currently randomly generated value at least in part in response to a comparison of the calculated string distance with a string distance threshold.

26. The system according to claim 21, wherein the output regulator comprises: a calculator for calculating a string distance at least in part in response to a currently randomly generated value and a previously randomly generated value; a comparator for generating an indication of the state of the currently randomly generated value at least in part in response to a comparison of the calculated string distance with a string distance threshold; and a register for sampling and storing the currently randomly generated value in response to the indication of the state of the currently randomly generated value.

27. The system according to claim 21, wherein the output regulator comprises: a calculator for calculating a string distance at least in part in response to a currently randomly generated value and a previously randomly generated value; a comparator for generating an indication of the state of the currently randomly generated value at least in part in response to a comparison of the calculated string distance with a string distance threshold; a timer for generating a value indicative of the duration since the last indication generated by the comparator, the last indication corresponding to the calculated string distance exceeding the string distance threshold; a corrector for: outputting a transformed currently randomly generated value at least in part in response to detecting that the value generated by the timer exceeds a timeout threshold value; or outputting the currently randomly generated value at least in part in response to detecting that the value generated by the timer is reset before exceeding the timeout threshold; and a register for storing the output of the corrector.

28. The system according to claim 27, wherein the corrector generates an indication of the quality of the output stored at the register.

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