Apparatus having pulse width controlled vector matrix multiplication unit of capacitive element and control method thereof

Abstract

The invention relates to an arrangement of pulse width controlled vector matrix multiplication cells, in which an input module is connected to word lines of a matrix consisting of non-volatile memory elements, and which has an output module comprising an amplifier having an inverting input, and a method for controlling said arrangement, and to a method for controlling said arrangement, in which the input module is connected to the word lines of the matrix consisting of non-volatile memory elements. And a feedback coupling capacitor and a parallel switch. It is an object of the invention to improve energy efficiency using an improved analog comparator of a double ramp approach. This object is achieved in that the non-volatile memory component consists of an adjustable capacitor (10), and the input module comprises a switch (11) connecting the voltage ramp generator (12) to the word line (3), which switch can be controlled by the input pulse width, and an amplifier in the output module with a feedback coupling capacitance, which amplifier can be controlled by the input pulse width. The amplifier works as a non-inverting amplifier (7) together with an adjustable capacitor (10) of the matrix, and a reference for the second phase is connected to the inverting input of the amplifier, the reference consisting of a reference capacitor (13) and an inverse voltage ramp generator (14) connected thereto.

Description

Technical Field

[0001] The present invention relates to an apparatus for a pulse-width-controlled vector matrix multiplication unit as described in the preamble of claim 1.

[0002] The present invention also relates to a method for controlling an apparatus as described in any one of claims 1 to 9. Background Art

[0003] In recent years, there has been increasing interest in performing analog vector matrix multiplication through memory cells, where the memory cells represent the multiplicand. The memory cells are arranged in a matrix form and represent coefficients, and input values are applied on horizontal lines (i.e., word lines), which are the word lines. The accumulation operation is usually performed according to Kirchhoff’s law, where the output currents of the memory cells are summed up.

[0004] This type of apparatus is mainly applied to the calculation of artificial neural networks or the solution of differential equations.

[0005] One option is to use non-volatile memories, such as resistive memory devices (e.g., “In-memory computing with resistive switching devices” by Ielmini et al. in Nature Electronics in 2018). In this option, Ohm's law is used for multiplication operations. For example, a voltage is applied to the word lines of the matrix, and the total current output from the bit lines of the matrix is measured.

[0006] According to this method, to perform analog vector matrix multiplication, it is necessary to convert digital data into analog input signals for the word lines, and convert the analog output signals into digital data for the bit lines, so that the multiplication unit can be combined with traditional digital processing.

[0007] In the patent EP3523805B1 by Demasius et al. and the paper “Energy-efficient memcapacitor devices for neuromorphic computing” published in Nature Electronics in 2021, in addition to the above-mentioned resistive non-volatile memories, capacitive non-volatile memories are also proposed. These are based on the principle that the capacitance of a capacitor can be freely adjusted, and this capacitance can be stored in a non-volatile manner. Compared with resistive elements, capacitive elements have advantages because capacitive elements consume almost no static current and have a high signal-to-noise ratio. Therefore, when the signal quality is comparable to that of resistive elements, a lower readout voltage can be used, thereby reducing the dynamic energy consumption.

[0008] For this purpose, there are several options for digital-to-analog converters and analog-to-digital converters (ADCs): parallel converters, successive approximation register (SAR)-ADCs, or integrating converters. In analog vector matrix multipliers, parallel converters or SAR ADCs are mostly used (refer to "Memory Devices and A / D Interfaces: Design Tradeoffs in Mixed-Signal Accelerators for Machine Learning Applications" by Caselli et al. in IEEE 2022). If high-speed conversion is required, parallel converters have an advantage; if energy efficiency is crucial, SAR ADCs have an advantage. However, both of these ADCs have the drawback of requiring a large amount of space, and for SAR ADCs, complex digital control logic is also needed. However, for a matrix with analog storage components, bit lines are arranged in a dense pattern, and in order to outperform digital circuits, it is beneficial if the ADCs connected to the bit lines also adopt a compact design. This is particularly important in cases where design rules related to integrated circuit design must be complied with (e.g., the minimum gap requirements between transistors and metal conductors), where in a dense layout, the more complex and larger the ADC circuit, the more difficult it is to comply with these rules.

[0009] In the patent document with the patent number US11409045B2, a ramp-type ADC is used in combination with a resistive element. The patent document with the patent number US11409045B2 describes integrating the output current of the bit line, or the patent document with the patent number US2021271732A1 describes converting the output current of the bit line into a voltage through an inverting amplifier. Then this voltage is compared with a ramp signal and converted into a pulse width through an analog comparator. The pulse width is converted into a binary signal through a counter.

[0010] An ADC operating using a dual-ramp method includes an integration stage (the first stage) in which the bit line current is integrated, and then a de-integration stage (the second stage) in which the charged state of the integrator is cleared. The time interval required for the integrator to be restored to the initial voltage is converted into a pulse width through a comparator and counted again. An exemplary embodiment with a current source for a resistive non-volatile memory is proposed in the patent application US2020234111A1. Compared with a single-ramp ADC, the advantage of a dual-ramp ADC is the reduction of the integration capacitance, and the aging and temperature dependence are significantly reduced. However, this application does not explain the use of capacitive non-volatile memories, which have the advantage of significantly reducing energy consumption because these memories can no longer be used as current sources to operate.

[0011] The use of programmable capacitive non-volatile memories is disclosed in the paper "Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing" by Luo et al. published in IEEE Transactions on Circuits and Systems in 2022, where the accumulated charge is integrated by an operational amplifier. The publication also includes the design of a reference capacitor array, however, it is used to solve the problem of having a restrictive dynamic (on / off) ratio. The publication does not mention a dual-ramp ADC with an integration phase and a discharge phase.

[0012] In patent application US20220027130A1, a device is disclosed that has an integrator on the bit line and incorporates capacitors for representing a weighted matrix. The input value can also be applied to the word line in a pulse-width encoded manner, where a constant voltage pulse or a current pulse is assumed to be used. The patent application also discloses the use of an integration phase and a discharge phase. These two phases are implemented based on a constant voltage applied to a conductance or based on a current source, where in the discharge phase, a reference conductance or a reference current source is used.

[0013] The above patent application US20220027130A1 does not describe converting the input pulse width into a variable voltage value (only relates to a digital-time converter), nor does it describe any capacitive non-volatile memory that can be programmed as an analog capacitance value. Instead, constant reference capacitors are connected in parallel through switches, so that various weighted states can be achieved. The disadvantage of this arrangement is that representing multiple states requires a large amount of space, and each memory cell includes at least one capacitor and one switch. In addition, according to this patent, the integration of capacitive weighting is performed over multiple pulses, which results in high energy consumption. The proposed integration and discharge by means of a current source or a conductance also result in high energy consumption.

[0014] This patent disclosure represents the closest prior art.

[0015] The analog comparator in a ramp-type ADC can be, for example, another operational amplifier circuit or differential amplifier as described in patent application US2020234111A1. However, such amplifiers have the disadvantage of requiring static current consumption, and this type of ADC has no further advantage in terms of energy efficiency. Another option is a dynamic latch-based comparator. However, this comparator requires 256 switches, for example, when dealing with 8-bit values, which results in high dynamic power consumption. In the paper "An Ultra-Low-Energy Analog Comparator for A / D Converters in CMOS Image Sensors" by Jendernalik et al. published in Circuits Syst Signal Process in 2017, an energy-saving comparator for image sensors was proposed, which is characterized by generating dynamic current consumption only at the switching time points. For this purpose, an input transistor is used, which generates a discharge current for a charging capacitor based on the gate-source voltage difference, and once the threshold voltage of the input transistor is exceeded, the switching of the relevant output transistor is performed. The disadvantage of this comparator is that there are significant performance fluctuations in the characteristics of the input transistor under the influence of temperature and manufacturing process conditions. Summary of the Invention

[0016] Accordingly, an object of the present invention is to develop a device for an analog vector matrix multiplication unit employing a capacitive non-volatile storage component, where a dual-ramp analog-to-digital converter (ADC) is suitable for this purpose, and an improved analog comparator using the dual-ramp method enhances the energy efficiency.

[0017] According to the present invention, to achieve this object, the network weights consist of programmable non-volatile adjustable capacitors, an additional time-to-voltage converter is arranged in the downstream circuit of the digital-to-time converter, and a reference capacitor is provided for performing a discharge phase with a reference voltage ramp.

[0018] The non-volatile storage component consists of adjustable capacitors, and the input module includes a switch connecting a voltage ramp generator to the word line, where the switch is configured to be controlled by an input pulse width, and an amplifier with a feedback coupling capacitor in the output module, which operates as a non-inverting amplifier together with the adjustable capacitors in the matrix, and the capacitances of the adjustable capacitors are accumulated, where the output voltage of the amplifier is determined by the capacitance ratio, and the reference for the second stage is connected to the inverting input of the amplifier, which is provided by a reference capacitor and a reverse voltage ramp generator connected to this reference capacitor.

[0019] This means that the adjustable capacitor (C m) is connected in parallel with the non-inverting input of the amplifier, and the adjustable capacitors form the elements of the matrix. The adjustable capacitors are connected via word lines to a voltage ramp generator controlled by an input pulse, such that the voltage ramp has different lengths across the adjustable capacitors. Thus, the output voltage of the inverting amplifier is determined by the input ramp voltage (V ramp ) and the integrating capacitor (C int ) as follows:

[0020]

[0021] In the second stage, after the first input ramp, a reverse ramp applied through a reference capacitor cancels the previously generated output voltage, and the relationship is as follows:

[0022]

[0023] The duration of this second stage is determined by a comparator and corresponds to the output pulse width.

[0024] In another advantageous embodiment, the matrix consists of differential elements, each differential element having a positive adjustable capacitor and a negative adjustable capacitor, and the positive and negative adjustable capacitors are connected to a common bit line and have respective word lines, each word line being associated with a respective switch in the input module, these switches being connected to voltage ramps in opposite directions and controllable by the same input pulse width.

[0025] Thus, the weights of the neural network are divided into positive and negative values, each positive and negative value having a separate word line, and in each case, voltage ramps in opposite directions are applied such that the subtraction operation is performed within the matrix itself, which represents an advantage over the prior art where subtraction calculations are typically implemented using a differential amplifier on two separate bit lines. Expressed by a formula, the output voltage of the amplifier can be represented by the positive voltage ramp (V ramp，+ ) and the negative voltage ramp (V ramp，- ), as well as the positive adjustable capacitor (C m，+ ) and the negative adjustable capacitor (C m，- ) as:

[0026]

[0027] According to one embodiment, the reverse voltage ramp is connected to one or more additional switches configured such that if the input pulse widths have different signs, the direction of the reverse voltage ramp can be interchanged.

[0028] In this way, for example, both a negative voltage ramp and a positive voltage ramp can be connected to a positive adjustable capacitor, or conversely to a negative adjustable capacitor. Thus, by combining positive and negative adjustable capacitors, four-quadrant multiplication can be achieved in a matrix. In another embodiment, another offset capacitor is connected to the inverting input of the amplifier, and this another offset capacitor is connected to another voltage ramp, thereby achieving an offset of the amplifier output voltage. The purpose of this arrangement is to ensure that the amplifier always operates within a limited voltage range. If the amplifier starts in a lower voltage range in the first stage, it cannot provide the ability to cover the negative voltage range. For this purpose, an additional offset capacitor is connected to the input of the amplifier, and a voltage ramp is applied. Thus, an offset of the initial output voltage is achieved, enabling the negative voltage range to be covered.

[0029] In another embodiment, one comparator input is connected to a capacitor, which is also connected to a voltage ramp generator through a switch, where the switch is configured to be controlled by the comparator output, and the other comparator input is connected to the output of the amplifier.

[0030] Typical comparators have an offset voltage. In addition, amplifiers generally also have an offset voltage, which depends on the selected amplifier topology. This offset voltage varies with temperature and also with the manufacturing process. Especially in the comparator structure selected here (the next embodiment), the threshold voltage of the input transistors will vary significantly. As a result of the comparator switching at different time points, the change in the offset voltage will cause the output pulse width of the comparator to change. In this embodiment, a device is described that samples the offset voltages of the comparator and the amplifier by connecting a voltage ramp to a capacitor, thereby performing a subtraction operation.

[0031] In another advantageous embodiment, the comparator consists of an input transistor, where one input of the comparator is connected to the source terminal, the other input of the comparator is connected to the gate terminal of the input transistor, the drain terminal of the input transistor is connected to a capacitor (optionally, it can be the stray capacitance of the transistor), and is connected to the gate terminal of another output transistor, where the capacitor and the output of the output transistor are configured such that they can be precharged before the comparison stage.

[0032] Finally, the comparator consists of an input transistor that generates a discharge current that depends on the differential voltage between the two inputs (the gate terminal and the source terminal). This discharge current discharges the capacitance connected to the gate terminal of the output transistor, and this capacitance causes the output transistor to switch from a certain point onwards, which corresponds to the end of the output pulse width. For example, if the differential voltage (V GS ) at the input exceeds the threshold voltage (V T ), then this time point is reached:

[0033] V GS ≥V T

[0034] The advantage of this comparator is that the dynamic power consumption only occurs in a one-time manner at the switching time point. This is the difference between this comparator and other dynamic comparators. However, the threshold voltage undergoes significant variations, which can be addressed by the previous embodiments.

[0035] According to another embodiment, a counter is connected to the output of the comparator. The output pulse width is thus converted into a binary number. According to another embodiment, the output of the comparator is connected to a conversion table, which is configured to be controlled by a clock pulse generator. The advantage of this arrangement is that, compared to a binary counter, any number can be entered in the conversion table, thereby compensating for any non-linear errors. It is also conceivable to map non-linear activation functions, such as ReLU or Sigmoid, into a conversion table of this type.

[0036] Embodiments of the method will be described in more detail below:

[0037] According to an advantageous embodiment, in a first stage, a voltage ramp is applied to the bit lines of a matrix controlled by an input pulse width, and the capacitances of the non-volatile tunable capacitors of the matrix are accumulated along the bit lines. And in a second stage, via a reference capacitor, a reverse voltage ramp is applied to the inverting input of an amplifier, and the comparator outputs a pulse width until the output voltage of the inverting amplifier is restored to the initial voltage. Finally, in the first stage, the voltage ramp on the input side is converted into an output voltage ramp on the amplifier through the following capacitance ratio relationship:

[0038]

[0039] Subsequently, in the second stage, this ramp is cancelled by the reference capacitor:

[0040]

[0041] Since the slope and endpoints of the output voltage ramp of the amplifier can vary according to the stored tunable capacitance and the input pulse width, but the ramp in the second stage always remains constant, the time point at which the inverting amplifier returns to its initial voltage will be different. This time point is determined by the comparator and output in the form of a pulse width.

[0042] According to another embodiment of the method, the word lines of the positive tunable capacitors and the word lines of the negative tunable capacitors are charged with a reverse voltage ramp, but the voltage ramp of the word lines of the corresponding matrix elements composed of the positive tunable capacitors and the negative tunable capacitors is controlled by the same input pulse width.

[0043] According to another embodiment of the method, the reverse voltage ramp is interchanged such that, in the case where the input signal has a different sign, the reverse voltage ramp is applied to the word lines of the positive and negative tunable capacitors. This enables four-quadrant multiplication since both positive and negative input values are now possible. Thus, the subtraction operation of the positive and negative elements of the matrix has been completed within the matrix itself, which is advantageous compared to implementations involving differential amplifiers as differential amplifiers require significantly more space.

[0044] According to another embodiment of the method, a voltage ramp is connected to one input of a comparator and simultaneously charges the capacitor, and the voltage ramp is interrupted immediately when switching the comparator output, and the capacitor stores the sampled offset voltage. In this way, temperature and process fluctuations are compensated for.

[0045] According to another embodiment of the method, in a first stage, the capacitor and the output of the output transistor are pre-charged with a reset signal, and in a second stage, the capacitor is discharged through an input transistor controlled by the voltage difference between two inputs, and once the threshold voltage of the input transistor is exceeded, the output transistor performs a switch.

[0046] The use of a comparator of this form enables significantly lower power consumption since dynamic power consumption only occurs at the switching time points. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The following shows advantageous embodiments:

[0048] Figure 1 : shows an overview of a memory matrix having an input module and an output module;

[0049] Figure 2 : shows the operating mode of the output module;

[0050] Figure 3 : shows the offset voltage sampling by a comparator

[0051] Figure 4 : shows the circuit diagram of a possible comparator. DETAILED DESCRIPTION

[0052] In Figure 1A matrix with a non-volatile storage component (4) and its connected input module (1) and output module (6) is shown. These modules are respectively connected to word lines (4) and bit lines (5). In the matrix (4), adjustable capacitors (10) are employed, which are divided into positive capacitors (15) and negative capacitors (16). The adjustable capacitors (10) are accumulated along the bit lines (5). A voltage ramp (12) is applied to the word lines, and for the positive capacitors (15) and negative capacitors (16), this voltage ramp presents opposite slopes. The length (duration) of the voltage ramp is controlled by a switch (11) and an input pulse width (2) in the input module.

[0053] In Figure 2 the output module is shown in more detail, where, for illustrative purposes, the positive capacitors (15) and negative capacitors (16) of the input module and the switches (11) of the capacitors are labeled. The adjustable capacitors (10) are accumulated along the bit lines and combined with an inverting amplifier (7) and a feedback coupling capacitor (8) to form an inverting amplifier, whose output voltage depends on the capacitance value of the adjustable capacitors (10) and the input pulse width (2). In the second stage, a reverse voltage ramp (14) is applied to another reference capacitor (13) until the previously established output voltage is canceled, and the ramp length is output in the form of a pulse width by a comparator (9). An offset voltage can also be introduced into the amplifier (7) through an offset capacitor (17) and another voltage ramp (18). This is particularly suitable if positive and negative voltages are to be output.

[0054] In Figure 3 the sampling of the offset voltage is shown: For this purpose, one input terminal (19) of the comparator is connected to a capacitor (20), which is charged through a voltage ramp (22). This charging is controlled by the output (23) of the comparator and a switch (21). Once the comparator (9) performs a switch, that is, the voltage ramp (22) reaches the offset voltage, and this offset voltage is stored on the capacitor (20). Since subtraction is performed on the two inputs, this offset voltage is fed into the comparison stage, thereby generating an output pulse in this comparison stage.

[0055] Figure 4 A favorable embodiment of the comparator is shown. Conventional comparators either have static current consumption or high dynamic current consumption. The present invention uses a comparator with low dynamic energy consumption, where energy consumption only occurs at the switching time points (except for leakage current). The capacitor (26) is pre-charged with a reset signal (28) and then discharged through an input transistor (25), where the discharge amplitude depends on the differential value of the input signal applied to the gate terminal and the source terminal of the input transistor (25). Once the threshold voltage of the input transistor (25) is exceeded, the output transistor (27) performs a switch.

[0056] Reference Numerals

[0057] 1 – Input Module

[0058] 2 – Input Pulse

[0059] 3 – Word Line

[0060] 4 – Matrix of Non-Volatile Memory Elements

[0061] 5 – Bit Line

[0062] 6 – Output Module

[0063] 7 – Amplifier

[0064] 8 – Feedback Coupling Capacitor

[0065] 9 – Comparator

[0066] 10 – Tunable Capacitor

[0067] 11 – Switch of Input Module

[0068] 12 – Voltage Ramp (Generator)

[0069] 13 – Reference Capacitor

[0070] 14 – Reverse Voltage Ramp of Reference

[0071] 15 – Positive Tunable Capacitor

[0072] 16 – Negative Tunable Capacitor

[0073] 17 – Offset Capacitor

[0074] 18 – Voltage Ramp of Offset Capacitor

[0075] 19 – Input Terminal of First Comparator

[0076] 20 – Capacitor of Comparator

[0077] 21 – Switch of Comparator

[0078] 22 – Voltage Ramp Generator of Comparator

[0079] 23 – Output Terminal of Comparator

[0080] 24 – Input Terminal of Second Comparator

[0081] 25 – Input Transistor

[0082] 26 – Capacitor in Comparator

[0083] 27 – Output Transistor

[0084] 28 – Reset Signal

Claims

1. A device of a vector matrix multiplication unit with pulse width control, comprising: A digital-time converter, which is connected to a reference time, the digital-time converter is configured to receive a digital input signal, and output a signal that is proportional to the digital input signal and modulated over a time interval; A memory; An output interface, which is connected to the matrix of the memory, the output interface is configured to receive the memory weighted output signal, and output a digital value that is at least proportional to the reference time; And A time-digital converter; Wherein the device is configured to perform a two-stage process, the two-stage process includes a first accumulation stage, and a second stage that is a reference discharge stage, the first accumulation step has the initial conditions of the reference discharge stage of the second step; It is characterized in that The network weights are composed of programmable non-volatile adjustable capacitors; Another time-voltage converter is arranged in the downstream circuit of the digital-time converter; and A reference capacitor is provided for performing the discharge stage with a reference voltage ramp.

2. The device according to claim 1, It is characterized in that, The time-voltage converter includes a reference voltage ramp generator and a switch, the switch is controlled by an input pulse width, one switch terminal of the switch is connected to the reference voltage ramp generator, and the second switch terminal of the switch is connected to the input terminal of the matrix.

3. The device according to claim 1 or 2, It is characterized in that, The matrix uses differential elements, each differential element has a positive adjustable capacitor (15) and a negative adjustable capacitor (16), and the positive adjustable capacitor and the negative adjustable capacitor are connected to a common bit line (5) and each positive adjustable capacitor and negative adjustable capacitor has its own word line (3), each word line (3) is associated with its own switch (11) in the input module, the switch is connected to voltage ramps (12) with opposite directions and can be controlled by the same input pulse width (2).

4. The device according to any one of claims 1 to 3, It is characterized in that, The reverse voltage ramp (14) is connected to one or more additional switches, the switches are configured such that if the input pulse width (2) has different signs, the reverse voltage ramp (14) can be interchanged.

5. The device according to any one of claims 1 to 4, It is characterized in that, Another offset capacitor (17) is connected to the inverting input terminal of the amplifier (7), the offset capacitor (17) is connected to another voltage ramp (18), so as to realize the offset of the amplifier output voltage.

6. The device according to any one of claims 1 to 5, It is characterized in that, One comparator input terminal (19) is connected to a capacitor (20), the capacitor (20) is also connected to a voltage ramp generator (22) through a switch (21), wherein the switch is configured to be controlled by the comparator output terminal (23), and the other comparator input terminal (24) is connected to the output terminal of the amplifier (7).

7. The device according to any one of claims 1 to 6, It is characterized in that, The comparator (9) consists of an input transistor (25), where one input terminal of the comparator is connected to the source terminal, the other input terminal of the comparator is connected to the gate terminal of the input transistor (25), the drain terminal of the input transistor (25) is connected to a capacitor (26), which can optionally also be the parasitic capacitance of the transistor, and the drain terminal of the input transistor (25) is connected to the gate of another output transistor (27), where the output terminals of the capacitor (26) and the output transistor (27) are configured such that they can be precharged before the comparison stage.

8. The device according to any one of claims 1 to 7, characterized in that a counter is connected to the output terminal of the comparator.

9. The device according to any one of claims 1 to 8, characterized in that the output terminal of the comparator is connected to a conversion table, which is configured to be controlled by a clock pulse generator.

10. A method for controlling the device according to any one of claims 1 to 9, characterized in that in a first stage, a voltage ramp (12) is applied to the bit lines (5) of the matrix, the voltage ramp (12) is controlled by an input pulse width (2), and the capacitance of the non-volatile adjustable capacitors (10) in the matrix is accumulated along the bit lines (5); in a second stage, a reverse voltage ramp (12) is applied to the inverting input terminal of the amplifier (7) through a reference capacitor (17), and the comparator (9) outputs a pulse width until the output voltage of the inverting amplifier (7) returns to the initial voltage.

11. The method according to claim 2, characterized in that the word lines (3) of the positive adjustable capacitors (15) and the word lines (3) of the negative adjustable capacitors (16) are charged with a reverse voltage ramp (12), but the voltage ramp (12) of the word lines (3) of the corresponding matrix elements composed of the positive and negative adjustable capacitors is controlled by the same input pulse width (2).

12. The method according to claim 3, characterized in that the reverse voltage ramp (12) can be interchanged such that, in the case of different signs of the input signal (2), the reverse voltage ramp is applied to the word lines of the positive and negative adjustable capacitors.

13. The method according to claim 5, characterized in that the voltage ramp (12) is connected to a comparator input terminal (19), the voltage ramp (12) simultaneously charges a capacitor (20), and the voltage ramp (12) is immediately interrupted when the switching of the comparator output terminal (23) is performed, and the capacitor (20) stores the sampled offset voltage.

14. The method according to claim 6, characterized in that in a first stage, the output terminals of the capacitor (26) and the output transistor (27) are precharged with a reset signal (28), in a second stage, the capacitor (26) is discharged through the input transistor (25) controlled by the voltage difference between the two input terminals, and once the threshold voltage of the input transistor (25) is exceeded, the output transistor (27) performs switching.

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