Display device and manufacturing method thereof

Abstract

The display device may include a substrate including pixel regions each including a first region and a second region; and a pixel disposed in each of the pixel regions. The pixel may include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer sequentially stacked on the substrate; a power wiring disposed on the substrate; a pixel circuit unit including a transistor disposed in the first region on the substrate and electrically connected to the power wiring; and a light emitting unit including a first alignment electrode, a second alignment electrode, and a third alignment electrode spaced apart from each other in the second region on the substrate, and a light emitting device disposed between the first alignment electrode, the second alignment electrode, and the third alignment electrode. At least one of the first to fifth insulating layers may be disposed under the first alignment electrode, the second alignment electrode, and the third alignment electrode. The at least one of the first to fifth insulating layers may include an inorganic insulating layer.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a display device and a method of manufacturing a display device. Background Art

[0002] In recent years, with the increasing interest in information display, research and development of display devices have been continuously carried out. Summary of the Invention

[0003] Technical Problem

[0004] Various embodiments of the present disclosure may provide a display device having improved reliability.

[0005] In addition, various embodiments of the present disclosure relate to a method of manufacturing a display device.

[0006] Technical Solution

[0007] Embodiments of the present disclosure may provide a display device including: a substrate including a pixel region, each of the pixel regions including a first region and a second region; and pixels disposed in each of the pixel regions. The pixels may include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer stacked in sequence on the substrate; a power line disposed on the substrate; a pixel circuit component disposed in the first region and including a transistor disposed on the substrate and electrically connected to the power line; and an emission component disposed in the second region and including a first alignment electrode, a second alignment electrode, and a third alignment electrode disposed on the substrate at spaced positions from each other, and a light-emitting element disposed between the first alignment electrode, the second alignment electrode, and the third alignment electrode. At least one of the first insulating layer to the fifth insulating layer may be disposed below the first alignment electrode to the third alignment electrode. The at least one of the first insulating layer to the fifth insulating layer may include an inorganic insulating layer.

[0008] In an embodiment, the first alignment electrode, the second alignment electrode, and the third alignment electrode may be formed of a third conductive layer disposed on the third insulating layer. Each of the first insulating layer, the second insulating layer, and the third insulating layer may include an inorganic insulating layer.

[0009] In an embodiment, the power lines may include a first power line and a second power line. The first power line is configured to be supplied with a voltage of a first driving power source, and the second power line is configured to be supplied with a voltage of a second driving power source different from the voltage of the first driving power source. The first power line may include a first vertical power line formed of a first conductive layer provided on a substrate, a first horizontal power line formed of a fourth conductive layer provided on a fourth insulating layer, and a first dummy power line integrally formed with the first horizontal power line and extending in a direction different from that of the first horizontal power line. The second power line may include a second vertical power line formed of the first conductive layer, a second horizontal power line formed of the fourth conductive layer, and a second dummy power line integrally formed with the second horizontal power line and extending in a direction different from that of the second horizontal power line.

[0010] In an embodiment, the emitting assembly may further include a first floating pattern spaced apart from the first alignment electrode, a second floating pattern spaced apart from the second alignment electrode, and a third floating pattern spaced apart from the third alignment electrode. The first floating pattern may be electrically connected to the first horizontal power line, and the second floating pattern and the third floating pattern may be electrically connected to the second horizontal power line.

[0011] In an embodiment, the transistor may include an active pattern provided on a first insulating layer, a gate electrode provided on the active pattern, a source electrode electrically connected to a first end of the active pattern, and a drain electrode electrically connected to a second end of the active pattern, and a second insulating layer is interposed between the active pattern and the gate electrode. The gate electrode may be formed of a second conductive layer provided on the second insulating layer.

[0012] In an embodiment, the pixel may further include: an emission region and a non-emission region, in which light is emitted from a light-emitting element in the emission region, and the non-emission region surrounds the emission region; and a first bank provided in the non-emission region and including an opening corresponding to the emission region. The emission region may be located in the second region.

[0013] In an embodiment, in at least the emission region, the first conductive layer and the second conductive layer may not be provided below the first alignment electrode, the second alignment electrode, and the third alignment electrode.

[0014] In an embodiment, in at least the emission region, the third alignment electrode, the first alignment electrode, and the second alignment electrode may be arranged in the listed order in a first direction. The light-emitting element may include: a first light-emitting element provided between the first alignment electrode and the second alignment electrode and including a first end and a second end facing each other; and a second light-emitting element provided between the first alignment electrode and the third alignment electrode and including a first end and a second end facing each other.

[0015] In an embodiment, the emission assembly may further include a first electrode, a second electrode, and an intermediate electrode formed of a fifth conductive layer disposed on the fifth insulating layer and disposed spaced apart from each other. The first electrode may be disposed on a first side of the first alignment electrode and electrically connected to a first end of the first light-emitting element. The second electrode may be disposed on the third alignment electrode and electrically connected to a second end of the second light-emitting element. The intermediate electrode may be disposed on the second alignment electrode and electrically connected to a second end of the first light-emitting element, and may be disposed on a second side of the first alignment electrode and electrically connected to a first end of the second light-emitting element.

[0016] In an embodiment, the pixel circuit assembly may further include a storage capacitor electrically connected to the transistor, and a connection pattern electrically connected to one electrode of the storage capacitor and formed of a fourth conductive layer. The connection pattern may be located in the first region. The first electrode may extend into the first region and be electrically connected to the connection pattern through a first contact portion passing through the fifth insulating layer.

[0017] In an embodiment, the emission assembly may further include a bridge wire disposed in a non-emission region and integrally formed with and electrically connected to the second electrode. The bridge wire may include a protruding portion that protrudes in a second direction different from the first direction and is electrically connected to the second power line through a second contact portion passing through the fifth insulating layer.

[0018] In an embodiment, the display device may further include a pad region in which pads electrically connected to the pixels are disposed. The pads may include a first pad electrode formed of a fourth conductive layer and a second pad electrode formed of a fifth conductive layer. The first pad electrode and the second pad electrode may be electrically connected to each other through a pad contact hole passing through the fifth insulating layer.

[0019] In an embodiment, the pixel may further include: a second bank disposed above the first bank in the second region; a color conversion layer surrounded by the second bank and disposed above the light-emitting element; and a color filter disposed on the color conversion layer.

[0020] In an embodiment, the first vertical power line, the first horizontal power line, and the first dummy power line may be electrically connected to each other. The second vertical power line, the second horizontal power line, and the second dummy power line may be electrically connected to each other.

[0021] In an embodiment, the first dummy power line may overlap the first vertical power line in a plan view. The first horizontal power line may extend from the first dummy power line in the first direction.

[0022] The second dummy power line may overlap the second vertical power line in a plan view. The second horizontal power line may extend from the second dummy power line in the first direction.

[0023] Embodiments of the present disclosure may provide a display device including a first sub-pixel, a second sub-pixel, and a third sub-pixel that are disposed adjacent to each other and each include a first region and a second region. Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer, which are sequentially stacked on a substrate; power lines disposed on the substrate and including a first power line and a second power line, the first power line configured to be supplied with a voltage of a first driving power source, and the second power line spaced apart from the first power line and configured to be supplied with a voltage of a second driving power source; a pixel circuit assembly disposed in the first region and including a transistor disposed on the substrate and electrically connected to the power lines, and a storage capacitor electrically connected to the transistor; and an emission assembly disposed in the second region and including first alignment electrodes, second alignment electrodes, and third alignment electrodes disposed on the substrate in pairs at spaced positions from each other, and a light-emitting element disposed between the first alignment electrodes, the second alignment electrodes, and the third alignment electrodes. At least one of the first insulating layer to the fifth insulating layer may be disposed below the first alignment electrode to the third alignment electrode, and the at least one of the first insulating layer to the fifth insulating layer may include an inorganic insulating layer.

[0024] In an embodiment, the second region may include an emission region where light is emitted from the light-emitting element. In at least the emission region, a conductive layer may not be disposed below the first alignment electrode, the second alignment electrode, and the third alignment electrode.

[0025] In an embodiment, the light-emitting element may include: a first light-emitting element disposed between the first alignment electrode and the second alignment electrode and including a first end and a second end facing each other; and a second light-emitting element disposed between the first alignment electrode and the third alignment electrode and including a first end and a second end facing each other. The emission assembly may further include a first electrode, a second electrode, and an intermediate electrode disposed on the fifth insulating layer and spaced apart from each other.

[0026] In an embodiment, the emission assembly may further include a bridge wiring located in the second region and electrically connected to the second electrode of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel. The bridge wiring may include a protruding portion that extends from the second region to the first region and is electrically connected to the second power line.

[0027] Embodiments of the present disclosure may provide a method of manufacturing a display device, the method including: forming pixels on a substrate in each of pixel regions, each pixel region including a first region and a second region. Forming the pixels may include: forming a first insulating layer, a second insulating layer, and a third insulating layer on the substrate; forming first alignment lines, second alignment lines, and third alignment lines spaced apart from each other on the third insulating layer in the second region; forming a fourth insulating layer on the first alignment lines, second alignment lines, and third alignment lines, the fourth insulating layer including contact holes through which a region of each of the first alignment lines, second alignment lines, and third alignment lines is exposed; forming a first horizontal power line and a second horizontal power line on the fourth insulating layer in the second region, the first horizontal power line being electrically connected to the first alignment line and the second horizontal power line being electrically connected to the second alignment line and the third alignment line; forming a fifth insulating layer on the first horizontal power line and the second horizontal power line; aligning a first light-emitting element on the fifth insulating layer between a first alignment electrode and a second alignment electrode, and aligning a second light-emitting element on the fifth insulating layer between the first alignment electrode and a third alignment electrode; forming a first electrode on a first end of the first light-emitting element, forming an intermediate electrode on a second end of the first light-emitting element and a first end of the second light-emitting element, and forming a second electrode on a second end of the second light-emitting element; and forming alignment electrodes and floating patterns arranged to be spaced apart from each other by removing a part of each of the first alignment line, second alignment line, and third alignment line in the second region.

[0028] In an embodiment, each of the first insulating layer, second insulating layer, and third insulating layer located under the first alignment line, second alignment line, and third alignment line may include an inorganic insulating layer.

[0029] Advantageous Effects

[0030] In an embodiment, each pixel region (or each sub-pixel region) may be divided into a first region and a second region, a pixel circuit is provided in the first region, and an emission component is provided in the second region. The insulating layer provided under the alignment electrode located in at least the second region may be formed of an inorganic insulating layer. Except for the insulating layer, an additional conductive layer (or an additional conductive pattern) is not provided under the alignment electrode, so that the alignment electrode may have a flat surface.

[0031] Therefore, the alignment electrode may be reduced or prevented from being affected by the step difference caused by the components provided under the alignment electrode. Accordingly, the step coverage of the alignment electrode may be improved.

[0032] Since the step coverage of the alignment electrode is improved, the alignment accuracy of the light-emitting element aligned on the alignment electrode may be increased. Accordingly, the number of light-emitting elements that can be used as effective light sources may be increased, so that the light output efficiency of each pixel (or each sub-pixel) may be improved.

[0033] Therefore, a display device with improved reliability and a method of manufacturing the display device can be provided.

[0034] The effects of the present disclosure are not limited by the foregoing, and various other effects are expected herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic perspective view showing a light-emitting element according to an embodiment.

[0036] Figure 2 is a schematic view showing Figure 1 of the light-emitting element in cross section.

[0037] Figure 3 is a schematic plan view showing a display device according to an embodiment.

[0038] Figure 4 is a schematic view showing Figure 3 of the display panel in cross section.

[0039] Figure 5 is a schematic circuit diagram showing the electrical connection relationship of components included in each of the pixels shown in Figure 3

[0040] Figure 6 is a schematic plan view showing a pixel according to an embodiment.

[0041] Figure 7 is a schematic view showing a pixel in which some components have been omitted Figure 6

[0042] Figure 8 is a schematic view showing Figure 6 of the first sub-pixel in plan view.

[0043] Figure 9 is a schematic plan view showing a pixel before the alignment electrode and the corresponding floating pattern are electrically separated Figure 6

[0044] Figure 10 is a schematic cross-sectional view taken along line II-II' of Figure 8

[0045] Figures 11 to 14 is a schematic cross-sectional view taken along line III-III' of Figure 8

[0046] Figure 15 is a schematic cross-sectional view taken along line IV-IV' of Figure 8 ​​​​​​

[0047] Figure 16 is a schematic cross-sectional view taken along line I-I’ Figure 3 thereof.

[0048] Figures 17 to 24 is a diagram for describing a method of manufacturing a first sub-pixel according to an embodiment, and is a schematic cross-sectional view corresponding to Figure 8 line II-II’ thereof.

[0049] Figure 25 and Figure 26 show a first sub-pixel according to an embodiment, and are a schematic cross-sectional view corresponding to Figure 8 line III-III’ thereof. DETAILED DESCRIPTION

[0050] Since the present disclosure allows various changes and multiple embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to a specific practice mode, and it will be understood that all changes, equivalents, and alternatives that do not depart from the technical scope of the present disclosure are included in the present disclosure.

[0051] Throughout the present disclosure, in various drawings and embodiments of the present disclosure, the same reference numerals denote the same parts. For clarity of illustration, the dimensions of the elements in the drawings may be exaggerated. It will be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0052] It will also be understood that, as used in this specification, the terms "comprises", "comprising", "has", etc. specify the presence of the stated features, wholes, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof. Further, in a case where a first portion such as a layer, film, region, or plate is disposed on a second portion, the first portion may not only be directly disposed on the second portion, but a third portion may be interposed therebetween. Further, in a case where a first portion such as a layer, film, region, or plate is formed on a second portion, the surface of the second portion on which the first portion is formed is not limited to the upper surface of the second portion, but may include other surfaces such as the side surface or the lower surface of the second portion. Conversely, in a case where a first portion such as a layer, film, region, or plate is below a second portion, the first portion may not only be directly below the second portion, but a third portion may be interposed therebetween.

[0053] It will be understood that where an element (e.g., a first element) is referred to as being “coupled” / “coupled to” / “connected” / “connected to” another element (e.g., a second element) (operatively or communicatively), the first element may be directly coupled or connected to the second element, or may be coupled or connected to the second element via another element (e.g., a third element). Conversely, it will be understood that where an element (e.g., a first element) is referred to as being “directly” “coupled” / “directly coupled to” another element (e.g., a second element), or “directly” “connected” / “directly connected to” another element (e.g., a second element), no other element (e.g., a third element) intervenes between the element and the said another element.

[0054] Embodiments of the present disclosure and the required details are described with reference to the accompanying drawings so as to describe the present disclosure in detail such that those of ordinary skill in the art to which the present disclosure pertains can easily practice the present disclosure. In addition, the singular forms may also include the plural forms as long as they are not specifically mentioned in the sentence.

[0055] Figure 1 is a schematic perspective view showing a light-emitting element LD according to an embodiment. Figure 2 is showing Figure 1 a schematic cross-sectional view of the light-emitting element LD.

[0056] Referring to Figure 1 and Figure 2 , the light-emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may be implemented as an emission stack (or referred to as a “stack pattern”) formed by sequentially stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. The type and / or shape of the light-emitting element LD are not limited to Figure 1 the type and / or shape of the embodiment shown therein.

[0057] The light-emitting element LD can be formed in a shape extending in one direction. If the direction in which the light-emitting element LD extends is defined as the longitudinal direction, the light-emitting element LD can have a first end EP1 and a second end EP2 that are opposite to each other with respect to the longitudinal direction. One of the first semiconductor layer 11 and the second semiconductor layer 13 can be disposed on the first end EP1 of the light-emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 can be disposed on the second end EP2 of the light-emitting element LD. For example, the second semiconductor layer 13 can be disposed on the first end EP1 of the light-emitting element LD, and the first semiconductor layer 11 can be disposed on the second end EP2 of the light-emitting element LD.

[0058] The light-emitting element LD can be provided in various shapes. For example, as Figure 1 shown, the light-emitting element LD can have a rod-shaped, bar-shaped, or columnar shape that is long with respect to the longitudinal direction (e.g., having an aspect ratio greater than 1). Alternatively, the light-emitting element LD can have a rod-shaped, bar-shaped, or columnar shape that is short with respect to the longitudinal direction (e.g., having an aspect ratio less than 1). As another option, the light-emitting element LD can have a rod-shaped, bar-shaped, or columnar shape with an aspect ratio of 1.

[0059] The light-emitting element LD can include a light-emitting diode (LED) manufactured to have ultra-small dimensions, for example, having a diameter D and / or a length L corresponding to a range from the nanoscale (or nanometer scale) to the micrometer scale (or micrometer scale).

[0060] When the light-emitting element LD is long with respect to the longitudinal direction (e.g., having an aspect ratio greater than 1), the diameter D of the light-emitting element LD can be in the range of about 0.5 μm to 6 μm, and its length L can be in the range of about 1 μm to 10 μm. However, the diameter D and the length L of the light-emitting element LD are not limited thereto. The dimensions of the light-emitting element LD can be changed to meet the requirements (or design conditions) of the lighting device or the self-emitting display device to which the light-emitting element LD is applied.

[0061] The first semiconductor layer 11 can include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 can include an n-type semiconductor layer that includes at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and is doped with a first conductive dopant (or n-type dopant) such as Si, Ge, or Sn. However, the constituent material of the first semiconductor layer 11 is not limited thereto, and various other materials can be used to form the first semiconductor layer 11.

[0062] The active layer 12 may be disposed on the first semiconductor layer 11 and have a single quantum well structure or a multi - quantum well structure. For example, in the case where the active layer 12 has a multi - quantum well structure, the active layer 12 may be formed by periodically repeating the stacking of a barrier layer, a strain - enhancing layer, and a well layer provided as a unit. However, the structure of the active layer 12 is not limited to the structure of the foregoing embodiments.

[0063] The active layer 12 can emit light in a wavelength range from 400 nm to 900 nm and has a double - heterostructure. In an embodiment, a cladding layer doped with a conductive dopant may be formed above or below the active layer 12 with respect to the longitudinal direction of the light - emitting element LD. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, a material such as AlGaN or InAlGaN may be used to form the active layer 12, and various other materials may be used to form the active layer 12. The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0064] If an electric field having a certain voltage or a voltage greater than a certain voltage is applied between opposite ends of the light - emitting element LD, the light - emitting element LD can emit light by coupling electron - hole pairs in the active layer 12. Since the light emission of the light - emitting element LD can be controlled based on the foregoing principle, the light - emitting element LD can be used as a light source (or light - emitting source) for various light - emitting devices and pixels of a display device.

[0065] The second semiconductor layer 13 may be disposed on the second surface of the active layer 12 and include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p - type semiconductor layer. For example, the second semiconductor layer 13 may include a p - type semiconductor layer including at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductive dopant (or p - type dopant) such as Mg, Zn, Ca, Sr, or Ba. However, the material used to form the second semiconductor layer 13 is not limited thereto, and various other materials may be used to form the second semiconductor layer 13.

[0066] The first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses with respect to the longitudinal direction of the light - emitting element LD. For example, with respect to the longitudinal direction of the light - emitting element LD, the first semiconductor layer 11 may have a thickness greater than the thickness of the second semiconductor layer 13. Thus, the active layer 12 of the light - emitting element LD may be disposed at a position closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11.

[0067] Although Figure 1 and Figure 2It is shown that each of the first semiconductor layer 11 and the second semiconductor layer 13 is formed as a single layer, but the present disclosure is not limited thereto. In an embodiment, depending on the material of the active layer 12, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include one or more layers, such as a cladding layer and / or a tensile strain barrier reduction (TSBR) layer. The TSBR layer may be a strain release layer provided between semiconductor layers having different lattice structures, and thus may be used as a buffer layer to reduce the difference in lattice constants. Although the TSBR layer may be formed of a p-type semiconductor layer such as p-GaInP, p-AlInP, or p-AlGaInP, the present disclosure is not limited thereto.

[0068] In an embodiment, in addition to including the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the light-emitting element LD may further include a contact electrode (hereinafter referred to as "first contact electrode") provided above the second semiconductor layer 13. Further, in an embodiment, the light-emitting element LD may further include an additional contact electrode (hereinafter referred to as "second contact electrode") provided on one end of the first semiconductor layer 11.

[0069] Each of the first contact electrode and the second contact electrode may be an ohmic contact electrode, but the present disclosure is not limited thereto. In an embodiment, each of the first contact electrode and the second contact electrode may be a Schottky contact electrode. The first contact electrode and the second contact electrode may include a conductive material. For example, the first contact electrode and the second contact electrode may include an opaque metal such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and their oxides or alloys, which may be used alone or in combination, but the present disclosure is not limited thereto. In an embodiment, the first contact electrode and the second contact electrode may further include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). Here, zinc oxide (ZnO x ) may be zinc oxide (ZnO) and / or zinc peroxide (ZnO 2 ).

[0070] The materials included in the first contact electrode and the second contact electrode may be the same as or different from each other. The first contact electrode and the second contact electrode may be substantially transparent or semi-transparent.

[0071] In an embodiment, the light-emitting element LD may further include an insulating layer 14. However, depending on the embodiment, the insulating layer 14 may be omitted, or the insulating layer 14 may be provided to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0072] The insulating layer 14 can prevent the active layer 12 from short - circuiting due to contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, the insulating layer 14 can minimize the surface defects of the light - emitting element LD, thereby improving the lifespan and emission efficiency of the light - emitting element LD. In the case where a plurality of light - emitting elements LD are arranged in close contact with each other, the insulating layer 14 can prevent an undesired short - circuit from occurring between the light - emitting elements LD. The presence or absence of the insulating layer 14 is not limited as long as it can prevent the active layer 12 from short - circuiting with external conductive materials.

[0073] The insulating layer 14 can be arranged to surround the entire outer circumferential surface of the emission stack including the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0074] Although in the foregoing embodiment, the insulating layer 14 is described as surrounding the entire outer circumferential surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the present disclosure is not limited thereto. In an embodiment, in the case where the light - emitting element LD includes a first contact electrode, the insulating layer 14 can surround the entire corresponding outer circumferential surfaces of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the first contact electrode. In an embodiment, the insulating layer 14 may not surround the entire outer circumferential surface of the first semiconductor layer 11, or may only surround a part of the outer circumferential surface of the first semiconductor layer 11 and not surround another part of the outer circumferential surface of the first semiconductor layer 11. In addition, in an embodiment, in the case where the first contact electrode is provided on the first end EP1 of the light - emitting element LD and the second contact electrode is provided on the second end EP2 of the light - emitting element LD, the insulating layer 14 allows at least one region of each of the first contact electrode and the second contact electrode to be exposed.

[0075] The insulating layer 14 can include a transparent insulating material. Various materials having insulating properties can be used as the material of the insulating layer 14.

[0076] The insulating layer 14 can have a single - layer structure or a multi - layer structure including a double - layer structure. For example, in the case where the insulating layer 14 is formed of a double - layer structure including a first layer and a second layer stacked in sequence, the first layer and the second layer can be made of different materials (or substances) and formed by different processes. According to an embodiment, the first layer and the second layer can include the same material and be formed by a continuous process.

[0077] In an embodiment, the light - emitting element LD can be implemented as a light - emitting pattern having a core - shell structure.

[0078] The light - emitting element LD can be used as a light - emitting source (or light source) for various display devices. The light - emitting element LD can be manufactured by a surface - treatment process.

[0079] The light-emitting component including the above-described light-emitting element LD can be used not only for a display device but also for various electronic devices that require a light source.

[0080] Figure 3 FIG. 4 is a schematic plan view showing a display device DD according to an embodiment. Figure 4 FIG. 5 is a schematic cross-sectional view showing Figure 3 the display panel DP of FIG. 4.

[0081] In FIGS. 4 Figure 3 and Figure 4 for convenience, the display device DD is schematically shown. For example, the structure of the display panel DP provided in the display device DD is shown centered on the display area DA where an image is displayed.

[0082] Referring to Figures 1 to 4 FIG. 4, the display device DD may include a substrate SUB, pixels PXL provided in the display area DA of the substrate SUB and each including at least one light-emitting element LD, a driver provided in the substrate SUB and configured to drive the pixels PXL, and a line component for electrically connecting the pixels PXL to the driver.

[0083] According to the method of driving the light-emitting element LD, the display device DD can be classified into a passive matrix type display device and an active matrix type display device. For example, when the display device DD is implemented as an active matrix type display device, each of the pixels PXL may include a driving transistor configured to control the amount of current to be supplied to the light-emitting element LD, and a switching transistor configured to transmit a data signal to the driving transistor.

[0084] The display panel DP (or the display device DD) may include a substrate SUB and pixels PXL provided in the display area DA of the substrate SUB. Each of the pixels PXL may include at least one light-emitting element LD.

[0085] The substrate SUB may include a transparent insulating material that allows light to pass through. The substrate SUB may be a rigid substrate or a flexible substrate.

[0086] For example, the rigid substrate may be at least one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystallized glass substrate.

[0087] The flexible substrate may be a plastic substrate or a film substrate including a polymer organic material. For example, the flexible substrate SUB may include at least one of the following: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetyl cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0088] One region of the substrate SUB can be set as a display region DA in which pixels PXL are provided, and another region of the substrate SUB can be set as a non-display region NDA. For example, the substrate SUB can include a display region DA and a non-display region NDA provided around the periphery (or adjacent to) the display region DA, and the display region DA includes a plurality of pixel regions PXA in which corresponding pixels PXL are provided.

[0089] The non-display region NDA can be provided on at least one side of the display region DA. The non-display region NDA can surround the periphery (or edge) of the display region DA. A line component electrically connected to the pixel PXL and a part of a driver electrically connected to the line component and configured to drive the pixel PXL can be provided in the non-display region NDA.

[0090] The non-display region NDA can be a region in which certain lines (e.g., fan-out lines LP) electrically connected to the pixel PXL to drive the pixel PXL, pads PD, and / or internal circuits are provided.

[0091] In an embodiment, the non-display region NDA can include a fan-out region FTA and a pad region PDA.

[0092] The pad region PDA can be a region of the non-display region NDA in which a pad component PDP is located, and can be set to be most adjacent to the periphery (or edge) of the non-display region NDA. The fan-out region FTA can be another region of the non-display region NDA in which fan-out lines LP (i.e., parts of the line component) are located, and can be provided in the non-display region NDA adjacent to the display region DA. For example, the fan-out region FTA can be a region of the non-display region NDA provided between the pad region PDA and the display region DA. In an embodiment, the non-display region NDA can include an electrostatic protection circuit region in which an electrostatic protection circuit is provided, and the electrostatic protection circuit is electrically connected to a signal line provided in the display region DA and configured to prevent electrostatic occurrence. The electrostatic protection circuit region can be a region of the non-display region NDA between the display region DA and the fan-out region FTA, but is not limited thereto.

[0093] The pad component PDP can be provided in the pad region PDA. The fan-out lines LP as parts of the line component can be provided in the fan-out region FTA.

[0094] The fan-out lines LP can be electrically connected to the pixel PXL such that certain signals applied from the driver can be transmitted to the pixel PXL. The fan-out lines LP can be provided in the fan-out region FTA and electrically connect the driver to the pixel PXL.

[0095] The pad assembly PDP may include a pad PD. The pad PD may supply (or transmit) drive power voltage and signals for driving pixels PXL and / or internal circuits disposed in the display area DA. In an embodiment, when the driver is mounted in the non-display area NDA of the substrate SUB, the pad assembly PDP may overlap with the output pad of the driver and be supplied with signals output from the driver.

[0096] Each of the pixels PXL may be disposed in a pixel area PXA. In an embodiment, the pixels PXL may be arranged in the display area DA in various arrangements such as, for example, a stripe arrangement, but the present disclosure is not limited thereto.

[0097] Each of the pixels PXL may include a pixel circuit layer PCL, a display element layer DPL, and a package layer ENC disposed on the substrate SUB.

[0098] A pixel circuit (refer to "PXC" in Figure 5 ), disposed on the substrate SUB and including transistors, signal lines electrically connected to the transistors, and an insulating layer may be disposed in the pixel circuit layer PCL. Each of the transistors has a structure in which, for example, a semiconductor pattern, a gate electrode, a first terminal, and a second terminal are sequentially stacked with an insulating layer interposed therebetween. The semiconductor pattern may include amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon, an organic semiconductor, and / or an oxide semiconductor. Although each of the gate electrode, the first terminal (or source electrode), and the second terminal (or drain electrode) may include at least one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), the present disclosure is not limited thereto.

[0099] The display element layer DPL may include a light-emitting element layer LDL and an optical layer LCL.

[0100] The light-emitting element layer LDL may be disposed on the substrate SUB. In an embodiment, the light-emitting element layer LDL may be disposed on the same surface as the pixel circuit layer PCL and may be spaced apart from the pixel circuit layer PCL without overlapping the pixel circuit layer PCL. An emission assembly (refer to "EMU" in Figure 5 ), including a light-emitting element LD configured to emit light, may be disposed in the light-emitting element layer LDL. A first electrode and a second electrode electrically connected to the light-emitting element LD may be disposed in the emission assembly EMU.

[0101] The optical layer LCL may convert light emitted from the light-emitting element layer LDL and traveling in the upward direction (or the third direction DR3) of the substrate SUB into light having excellent color reproducibility and then emit the converted light. The optical layer LCL may include a color filter layer and a color conversion layer.

[0102] The encapsulation layer ENC can be disposed on the display element layer DPL (or the optical layer LCL). The encapsulation layer ENC can reduce the step difference caused by the components located thereunder (e.g., the optical layer LCL), and can prevent external air, water, etc. from penetrating the display element layer DPL. The encapsulation layer ENC can include a material capable of absorbing and / or blocking light to prevent external light from being introduced into the display element layer DPL. For example, the encapsulation layer ENC can include a black matrix, but is not limited thereto.

[0103] Figure 5 is a schematic circuit diagram showing the electrical connection relationship of the components included in each of the pixels PXL shown in Figure 3 The electrical connection relationship of the components included in each of the pixels PXL shown in

[0104] For example, Figure 5 shows the electrical connection relationship of the components included in the pixel PXL that can be used in an active matrix display device according to an embodiment. Here, the connection relationship of the components of each of the pixels PXL is not limited thereto.

[0105] Referring to Figures 1 to 5 , the pixel PXL can include an emission component EMU configured to generate light having a luminance corresponding to a data signal. In addition, the pixel PXL can include a pixel circuit PXC configured to drive the emission component EMU.

[0106] For example, the emission component EMU can include a first electrode PE1 (or a first pixel electrode), a second electrode PE2 (or a second pixel electrode), and a light-emitting element LD electrically connected between the first electrode PE1 and the second electrode PE2. The first electrode PE1 is electrically connected to a first driving power source VDD through the pixel circuit PXC and a first power line PL1, and the second electrode PE2 is electrically connected to a second driving power source VSS through a second power line PL2. The first driving power source VDD and the second driving power source VSS can have different potentials to allow the light-emitting element LD to emit light. For example, the first driving power source VDD can be set as a high-potential power source, while the second driving power source VSS can be set as a low-potential power source.

[0107] In an embodiment, the emission component EMU can include at least one series group. Each series group can include a pair of electrodes (e.g., two electrodes), and at least one light-emitting element LD electrically connected between the pair of electrodes in a forward direction. Here, the number of series groups forming the emission component EMU and the number of light-emitting elements LD forming each series group are not particularly limited. For example, the number of light-emitting elements LD forming the corresponding series groups can be the same or different from each other. The number of light-emitting elements LD in each series group is not particularly limited.

[0108] For example, the emission assembly EMU may include a first series group SET1 and a second series group SET2. The first series group SET1 includes at least one first light-emitting element LD1, and the second series group SET2 includes at least one second light-emitting element LD2.

[0109] The first series group SET1 may include a first electrode PE1, an intermediate electrode CTE (or a bridging electrode), and at least one first light-emitting element LD1 electrically connected between the first electrode PE1 and the intermediate electrode CTE. Each first light-emitting element LD1 may be electrically connected between the first electrode PE1 and the intermediate electrode CTE in a forward direction. For example, the first end EP1 of the first light-emitting element LD1 may be electrically connected to the first electrode PE1. The second end EP2 of the first light-emitting element LD1 may be electrically connected to the intermediate electrode CTE.

[0110] The second series group SET2 may include the intermediate electrode CTE, a second electrode PE2, and at least one second light-emitting element LD2 electrically connected between the intermediate electrode CTE and the second electrode PE2. Each second light-emitting element LD2 may be electrically connected between the intermediate electrode CTE and the second electrode PE2 in a forward direction. For example, the first end EP1 of the second light-emitting element LD2 may be electrically connected to the intermediate electrode CTE. The second end EP2 of the second light-emitting element LD2 may be electrically connected to the second electrode PE2.

[0111] The first electrode (e.g., the first electrode PE1) of the emission assembly EMU may be the anode of the emission assembly EMU. The last electrode (e.g., the second electrode PE2) of the emission assembly EMU may be the cathode of the emission assembly EMU.

[0112] In the case where the light-emitting elements LD are electrically connected in a series-parallel structure, compared with the case where the same number of light-emitting elements LD are only electrically connected in parallel with each other, the power efficiency can be improved. In addition, in a pixel PXL in which the light-emitting elements LD are connected in a series-parallel structure, sufficient brightness can be expressed by some series stages of the light-emitting elements LD, so that the probability of black dot defects occurring in the pixel PXL can be reduced. However, the present disclosure is not limited thereto. The emission assembly EMU may be formed by electrically connecting the light-emitting elements LD only in series. Alternatively, the emission assembly EMU may be formed by electrically connecting the light-emitting elements LD only in parallel.

[0113] Each of the light-emitting elements LD may include a first end EP1 (e.g., p-type end) and a second end EP2 (e.g., n-type end). The first end EP1 is electrically connected to a first driving power source VDD via at least one electrode (e.g., the first electrode PE1), a pixel circuit PXC, a first power line PL1, etc. The second end EP2 is electrically connected to a second driving power source VSS via at least one additional electrode (e.g., the second electrode PE2), a second power line PL2, etc. For example, the light-emitting element LD may be electrically connected between the first driving power source VDD and the second driving power source VSS in a forward direction. The light-emitting element LD electrically connected in the forward direction may form an effective light source of the emission assembly EMU.

[0114] In an embodiment, in addition to including the light-emitting elements LD forming corresponding effective light sources, the emission assembly EMU may further include at least one reverse light-emitting element LDr.

[0115] The light-emitting elements LD of the emission assembly EMU may emit light with a brightness corresponding to the driving current supplied to them through the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply a driving current corresponding to the gray-scale value of the corresponding frame data to the emission assembly EMU. The driving current supplied to the emission assembly EMU may be divided into multiple parts flowing into the corresponding light-emitting elements LD. Therefore, each of the light-emitting elements LD may emit light with a brightness corresponding to the current applied to it, such that the emission assembly EMU may emit light with a brightness corresponding to the driving current.

[0116] The pixel circuit PXC may be electrically connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, if the pixel PXL is disposed at the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the pixel PXL may be electrically connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In addition, the pixel circuit PXC may be electrically connected to the i-th control line CLi and the j-th sensing line SENj of the display area DA.

[0117] The pixel circuit PXC may include a first transistor T1, a second transistor T2, and a third transistor T3, and a storage capacitor Cst.

[0118] The first transistor T1 may be a driving transistor configured to control a driving current to be applied to the emission assembly EMU, and the first transistor T1 may be electrically connected between a first driving power supply VDD and the emission assembly EMU. For example, a first terminal of the first transistor T1 may be electrically connected to the first driving power supply VDD through a first power line PL1. A second terminal of the first transistor T1 may be electrically connected to a second node N2. A gate electrode of the first transistor T1 may be electrically connected to a first node N1. The first transistor T1 may control the amount of the driving current applied to the emission assembly EMU from the first driving power supply VDD through the second node N2 in response to a voltage applied to the first node N1. In an embodiment, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode, and the present disclosure is not limited thereto. In an embodiment, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0119] The second transistor T2 may be a switching transistor that selects and activates a pixel PXL in response to a scan signal, and the second transistor T2 may be electrically connected between a data line Dj (e.g., the j-th data line) and the first node N1. A first terminal of the second transistor T2 may be electrically connected to the data line Dj. A second terminal of the second transistor T2 may be electrically connected to the first node N1 (or the gate electrode of the first transistor T1). A gate electrode of the second transistor T2 may be electrically connected to a scan line Si (e.g., the i-th scan line). The first terminal and the second terminal of the second transistor T2 are different terminals, and for example, if the first terminal is a drain electrode, the second terminal may be a source electrode.

[0120] When a scan signal having a gate-on voltage (e.g., a high-level voltage) is provided from the scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj to the first node N1. The first node N1 may be a point where the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are electrically connected to each other. The second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0121] The third transistor T3 can obtain a sensing signal through the sensing line SENj (e.g., the j-th sensing line) by electrically connecting the first transistor T1 to the sensing line SENj, and use the sensing signal to detect characteristics of the pixel PXL, such as the threshold voltage of the first transistor T1. Information about the characteristics of the pixel PXL can be used to convert image data so that the deviation of characteristics between pixels PXL can be compensated. The second terminal of the third transistor T3 can be electrically connected to the second terminal of the first transistor T1. The first terminal of the third transistor T3 can be electrically connected to the sensing line SENj. The gate electrode of the third transistor T3 can be electrically connected to the control line CLi (e.g., the i-th control line). In addition, the first terminal of the third transistor T3 can also be electrically connected to an initialization power supply. The third transistor T3 can be an initialization transistor configured to initialize the second node N2 and can be turned on when a sensing control signal is provided from the control line CLi so that the voltage of the initialization power supply can be transmitted to the second node N2. Therefore, the upper electrode UE (or the second storage electrode) of the storage capacitor Cst electrically connected to the second node N2 can be initialized.

[0122] The storage capacitor Cst can include a lower electrode LE (or the first storage electrode) and an upper electrode UE (or the second storage electrode). The lower electrode LE can be electrically connected to the first node N1. The upper electrode UE can be electrically connected to the second node N2. The storage capacitor Cst can be charged with a data voltage corresponding to the data signal to be provided to the first node N1 during one frame period. Therefore, the storage capacitor Cst can store a voltage corresponding to the difference between the voltage of the gate electrode of the first transistor T1 and the voltage of the second node N2.

[0123] Although Figure 5 an embodiment in which all of the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors is shown, the present disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 can be changed to a P-type transistor. In an embodiment, the emission component EMU can be electrically connected between the first driving power supply VDD and the pixel circuit PXC.

[0124] The structure of the pixel circuit PXC can be changed in various ways.

[0125] In an embodiment, for ease of explanation, the lateral direction (or the X-axis direction) in the plan view will be represented by the first direction DR1, the longitudinal direction (or the Y-axis direction) in the plan view will be represented by the second direction DR2, and the vertical direction in the cross-sectional view will be represented by the third direction DR3.

[0126] Figure 6 is a schematic plan view showing a pixel PXL according to an embodiment. Figure 7is a schematic plan view of a pixel PXL in which some components are omitted. Figure 6 of the pixel PXL. Figure 8 is a schematic plan view showing Figure 6 of the first sub-pixel SPX1. Figure 9 is a schematic plan view of the pixel PXL before the alignment electrode ALE is electrically separated from the corresponding floating patterns FTP1, FTP2, and FTP3. Figure 6 of the pixel PXL.

[0127] In Figures 6 to 9 not only the components in the pixel PXL but also the regions in which these components are provided (or located) may be included in the definition of the term "pixel PXL".

[0128] Referring to Figures 1 to 9 the pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0129] The first sub-pixel SPX1 may be located in the first sub-pixel region SPXA1 of the pixel region PXA. The second sub-pixel SPX2 may be located in the second sub-pixel region SPXA2 of the pixel region PXA. The third sub-pixel SPX3 may be located in the third sub-pixel region SPXA3 of the pixel region PXA.

[0130] Each of the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 may include a first region A1 and a second region A2. For example, each of the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 may include a first region A1 and a second region A2 that are separated from each other in the second direction DR2. The pixel circuit PXC (or pixel circuit components) of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be provided in the first region A1. The emission component EMU of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be provided in the second region A2. In addition, the second region A2 in which the emission component EMU is provided may include the emission region of the corresponding sub-pixel. For example, the second region A2 of the first sub-pixel SPX1 may include a first emission region EMA1. The second region A2 of the second sub-pixel SPX2 may include a second emission region EMA2. The second region A2 of the third sub-pixel SPX3 may include a third emission region EMA3.

[0131] The pixel region PXA may include a non-emitting region NEA adjacent to (or surrounding the perimeter of) the first emitting region EMA1, a non-emitting region NEA adjacent to (or surrounding the perimeter of) the second emitting region EMA2, and a non-emitting region NEA adjacent to (or surrounding the perimeter of) the third emitting region EMA3.

[0132] Signal lines of the pixel circuit PXC electrically connected to each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be disposed in the pixel region PXA. For example, an initialization power line IPL, data lines D1, D2, and D3, a power line PL, a scan line SC, etc. may be disposed in the pixel region PXA, but the present disclosure is not limited thereto.

[0133] The scan line SC may be selectively provided with a scan signal and a sensing control signal. The scan line SC may extend in a first direction DR1. The scan line SC may be formed of a fourth conductive layer C4. The fourth conductive layer C4 may be formed of a single layer or multiple layers made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and their oxides or alloys.

[0134] The scan line SC may be electrically connected to a second transistor T2 included in the pixel circuit PXC included in each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 through corresponding contact holes. For example, the scan line SC may be electrically connected to a second gate electrode GE2 of the second transistor T2 included in the pixel circuit PXC of the first sub-pixel SPX1, may be electrically connected to a second gate electrode GE2 of the second transistor T2 included in the pixel circuit PXC of the second sub-pixel SPX2, and may be electrically connected to a second gate electrode GE2 of the second transistor T2 included in the pixel circuit PXC of the third sub-pixel SPX3.

[0135] In addition, the scan line SC may be electrically connected to a third transistor T3 included in the pixel circuit PXC included in each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 through corresponding contact holes. For example, the scan line SC may be electrically connected to a third gate electrode GE3 of the third transistor T3 included in the pixel circuit PXC of the first sub-pixel SPX1, may be electrically connected to a third gate electrode GE3 of the third transistor T3 included in the pixel circuit PXC of the second sub-pixel SPX2, and may be electrically connected to a third gate electrode GE3 of the third transistor T3 included in the pixel circuit PXC of the third sub-pixel SPX3.

[0136] The second gate electrode GE2 and the third gate electrode GE3 may be formed of a second conductive layer C2. The second conductive layer C2 may include the same material as that of the fourth conductive layer C4, or may include one or more suitable (or selected) materials among the materials listed as the constituent materials of the fourth conductive layer C4, but the present disclosure is not limited thereto.

[0137] The scan line SC may supply a scan signal to the second transistor T2 of the pixel circuit PXC of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 during the driving period of the light-emitting element LD, and may supply a sensing control signal to the third transistor T3 of the pixel circuit PXC of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 during the sensing period.

[0138] The data lines D1, D2, and D3 may include a first data line D1, a second data line D2, and a third data line D3 that extend in the second direction DR2 and are arranged in the first direction DR1. A data signal may be applied to each of the first data line D1, the second data line D2, and the third data line D3.

[0139] The first data line D1 may be electrically connected to the second transistor T2 of the pixel circuit PXC of the first sub-pixel SPX1. The second data line D2 may be electrically connected to the second transistor T2 of the pixel circuit PXC of the second sub-pixel SPX2. The third data line D3 may be electrically connected to the second transistor T2 of the pixel circuit PXC of the third sub-pixel SPX3. Each of the first data line D1, the second data line D2, and the third data line D3 may be formed of a first conductive layer C1. The first conductive layer C1 may include the same material as that of the fourth conductive layer C4, or may include one or more suitable materials among the materials listed as the constituent materials of the fourth conductive layer C4, but the present disclosure is not limited thereto.

[0140] The power line PL may include a first power line PL1 and a second power line PL2.

[0141] The first power line PL1 may be supplied with the voltage of the first driving power source VDD. The first power line PL1 may include a first vertical power line PL1a, a first horizontal power line PL1b, and a first dummy power line PL1c.

[0142] The first vertical power line PL1a may extend in the second direction DR2 and may be formed by the first conductive layer C1. The first horizontal power line PL1b may extend in the first direction DR1 and may be formed by the fourth conductive layer C4. The first dummy power line PL1c may be formed by the fourth conductive layer C4 and may extend in the second direction DR2 and overlap with the first vertical power line PL1a. The first dummy power line PL1c may be integrally formed with the first horizontal power line PL1b. In this case, the first dummy power line PL1c may be a region of the first horizontal power line PL1b. In an embodiment, the first horizontal power line PL1b may be arranged in a shape extending (or protruding) from the first dummy power line PL1c in the first direction DR1.

[0143] The first vertical power line PL1a formed by the first conductive layer C1 and the first dummy power line PL1c (or the first horizontal power line PL1b) formed by the fourth conductive layer C4 may be electrically connected to each other through corresponding contact holes. Thus, the first vertical power line PL1a, the first dummy power line PL1c, and the first horizontal power line PL1b may be electrically connected to each other. The mutually electrically connected first vertical power line PL1a, first horizontal power line PL1b, and first dummy power line PL1c may have a mesh structure.

[0144] The first dummy power line PL1c may be electrically connected through a corresponding contact hole to a first additional conductive pattern ACP1 provided in a different layer. The first additional conductive pattern ACP1 may be formed by the second conductive layer C2 and extend in the second direction DR2 to overlap with the first dummy power line PL1c. The first dummy power line PL1c may be electrically connected through a corresponding contact hole to the first additional conductive pattern ACP1 provided in a different layer, thereby forming a double-layer structure. Thus, the line resistance of the first dummy power line PL1c may be reduced.

[0145] The second power line PL2 may be supplied with the voltage of the second driving power source VSS. The second power line PL2 may include a second vertical power line PL2a, a second horizontal power line PL2b, and a second dummy power line PL2c.

[0146] The second vertical power line PL2a can extend in the second direction DR2 and can be formed by the first conductive layer C1. The second vertical power line PL2a can extend in the first direction DR1 and can be formed by the fourth conductive layer C4. The second dummy power line PL2c can be formed by the fourth conductive layer C4 and can extend in the second direction DR2 and overlap with the second vertical power line PL2a. The second dummy power line PL2c can be integrally formed with the second horizontal power line PL2b. In this case, the second dummy power line PL2c can be a region of the second horizontal power line PL2b. In an embodiment, the second horizontal power line PL2b can be arranged in a shape extending (or protruding) from the second dummy power line PL2c in the first direction DR1.

[0147] The second vertical power line PL2a formed by the first conductive layer C1 and the second dummy power line PL2c (or the second horizontal power line PL2b) formed by the fourth conductive layer C4 can be electrically connected to each other through corresponding contact holes. Therefore, the second vertical power line PL2a, the second dummy power line PL2c, and the second horizontal power line PL2b can be electrically connected to each other. The second vertical power line PL2a, the second horizontal power line PL2b, and the second dummy power line PL2c that are electrically connected to each other can have a mesh structure.

[0148] The second dummy power line PL2c can be electrically connected through a corresponding contact hole to a second additional conductive pattern ACP2 provided in a different layer. The second additional conductive pattern ACP2 can be formed by the second conductive layer C2 and extends in the second direction DR2 to overlap with the second dummy power line PL2c. Since the second dummy power line PL2c is electrically connected through a corresponding contact hole to the second additional conductive pattern ACP2 located in a different layer, the line resistance of the second dummy power line PL2c can be reduced.

[0149] In addition, the second vertical power line PL2a can be electrically connected through a corresponding contact hole to a dummy pattern DMP provided in a different layer. The dummy pattern DMP can be formed by the fourth conductive layer C4 and can overlap with a region of the second vertical power line PL2a. The dummy pattern DMP can be electrically connected through a corresponding contact hole to a third additional conductive pattern ACP3 provided in a different layer. The third additional conductive pattern ACP3 can be formed by the second conductive layer C2 and can overlap with the dummy pattern DMP. The second vertical power line PL2a can be electrically connected to the third additional conductive pattern ACP3 and the dummy pattern DMP provided in different layers, thereby forming a multi-layer structure. Therefore, the line resistance of the second vertical power line PL2a can be reduced.

[0150] The initialization power line IPL can extend in the second direction DR2. The initialization power line IPL can be located in each of the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3, and can be set to be spaced apart from the corresponding data line. The initialization power line IPL can be formed of the first conductive layer C1. The initialization power line IPL can be the sensing line SENj Figure 5 described. The initialization power line IPL can be supplied with the voltage of the initialization power supply. The initialization power line IPL in each of the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 can be electrically connected to the third transistor T3 included in the pixel circuit PXC of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 through the fourth connection pattern CNP4.

[0151] The fourth connection pattern CNP4 can be formed of the fourth conductive layer C4, and can be electrically connected to the initialization power line IPL through the corresponding contact hole. The fourth connection pattern CNP4 can be electrically connected to the third transistor T3 of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 through the corresponding contact hole.

[0152] The pixel circuit PXC of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0153] The pixel circuit PXC of the first sub-pixel SPX1, the pixel circuit PXC of the second sub-pixel SPX2, and the pixel circuit PXC of the third sub-pixel SPX3 can have substantially the same or similar structure. Hereinafter, the pixel circuit PXC of the first sub-pixel SPX1 will be described as a representative example. The description of the pixel circuit PXC of the first sub-pixel SPX1 will replace the description of the pixel circuit PXC of the second sub-pixel SPX2 and the pixel circuit PXC of the third sub-pixel SPX3.

[0154] The pixel circuit PXC of the first sub-pixel SPX1 can be located in the first region A1 of the first sub-pixel region SPXA1. For example, the first transistor T1, the second transistor T2, the third transistor T3, and the storage capacitor Cst can be located in the first region A1 of the first sub-pixel region SPXA1.

[0155] The first transistor T1 can include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, and a first drain electrode DE1.

[0156] The first gate electrode GE1 can be electrically connected to the first connection pattern CNP1 through a contact hole. The first gate electrode GE1 can be formed of the second conductive layer C2.

[0157] The first connection pattern CNP1 can be formed of the fourth conductive layer C4. The first end of the first connection pattern CNP1 can be electrically connected to the first gate electrode GE1 through a corresponding contact hole. The second end of the first connection pattern CNP1 can be electrically connected to the second source electrode SE2 through a corresponding contact hole. The first gate electrode GE1 and the second source electrode SE2 can be electrically connected to each other through the first connection pattern CNP1.

[0158] Each of the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 can be configured by a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. Each of the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 can be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the first source electrode SE1 and the first drain electrode DE1 can be doped with impurities and have conductivity. The first active pattern ACT1 can be formed of an intrinsic semiconductor layer not doped with impurities.

[0159] The first active pattern ACT1 can be located under the first gate electrode GE1 formed of the second conductive layer C2 and can overlap with the first gate electrode GE1. The first active pattern ACT1 can form the channel region of the first transistor T1.

[0160] The first source electrode SE1 can be electrically connected to the first end of the first active pattern ACT1. The first source electrode SE1 can be doped with impurities during an impurity doping process performed after the second conductive layer C2 is formed and thus can have conductivity. The first source electrode SE1 can be electrically connected to the third connection pattern CNP3 through a corresponding contact hole.

[0161] The third connection pattern CNP3 can be formed of the fourth conductive layer C4. The first end of the third connection pattern CNP3 can be electrically connected to the first source electrode SE1 through a corresponding contact hole. The second end of the third connection pattern CNP3 can be electrically connected to the bottom metal pattern BML through a corresponding contact hole. In addition, the second end of the third connection pattern CNP3 can be electrically connected to the third source electrode SE3 of the third transistor T3. The first source electrode SE1, the bottom metal pattern BML, and the third source electrode SE3 can be electrically connected to each other through the third connection pattern CNP3.

[0162] In an embodiment, the third connection pattern CNP3 may be electrically connected to the emission component EMU of the first sub-pixel SPX1 through the first contact portion CNT1. For example, the third connection pattern CNP3 may be electrically connected to the first electrode PE1 through the first contact portion CNT1.

[0163] The bottom metal pattern BML may be formed of the first conductive layer C1. The bottom metal pattern BML may be electrically connected to the third connection pattern CNP3 through a corresponding contact hole. The bottom metal pattern BML may be electrically connected to the first source electrode SE1 through the third connection pattern CNP3. Accordingly, the driving range of the voltage to be provided to the first gate electrode GE1 may be increased. In addition, since the bottom metal pattern BML is electrically connected to the first source electrode SE1, the bottom metal pattern BML may be prevented from floating. In an embodiment, the bottom metal pattern BML may extend from the first region A1 to the second region A2. The bottom metal pattern BML extending to the second region A2 may be electrically connected to the upper electrode UE of the storage capacitor Cst through a corresponding contact hole. Accordingly, the same signal may be provided to the bottom metal pattern BML and the upper electrode UE. The bottom metal pattern BML extending to the second region A2 may overlap with the lower electrode LE of the storage capacitor Cst, such that the capacitance of the storage capacitor Cst may be further increased.

[0164] The first drain electrode DE1 may be electrically connected to the second end of the first active pattern ACT1. In addition, the first drain electrode DE1 may also be electrically connected to the first horizontal power line PL1b through a corresponding contact hole.

[0165] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0166] The second gate electrode GE2 may be electrically connected to the scan line SC through a corresponding contact hole. The second gate electrode GE2 may overlap with the second active pattern ACT2.

[0167] Each of the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be configured of a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. Each of the second source electrode SE2 and the second drain electrode DE2 may be doped with impurities and have conductivity. The second active pattern ACT2 may be formed of an intrinsic semiconductor layer not doped with impurities.

[0168] The second active pattern ACT2 may be located below the second gate electrode GE2 formed of the second conductive layer C2 and may overlap with the second gate electrode GE2. The second active pattern ACT2 may form the channel region of the second transistor T2.

[0169] The second source electrode SE2 may be electrically connected to the first end of the second active pattern ACT2. The second source electrode SE2 may be doped with impurities during an impurity doping process performed after forming the second conductive layer C2, and may thus have conductivity. The second source electrode SE2 may be electrically connected to the first connection pattern CNP1 through a corresponding contact hole.

[0170] The second drain electrode DE2 may be electrically connected to the second end of the second active pattern ACT2. The second drain electrode DE2 may be doped with impurities during an impurity doping process performed after forming the second conductive layer C2, and may thus have conductivity. The second drain electrode DE2 may be electrically connected to the second connection pattern CNP2 through a corresponding contact hole.

[0171] The second connection pattern CNP2 may be formed of a fourth conductive layer C4. The first end of the second connection pattern CNP2 may be electrically connected to the second drain electrode DE2 through a corresponding contact hole. The second end of the second connection pattern CNP2 may be electrically connected to the first data line D1 formed of the first conductive layer C1 through a corresponding contact hole. The second drain electrode DE2 and the first data line D1 may be electrically connected to each other through the second connection pattern CNP2.

[0172] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3.

[0173] The third gate electrode GE3 may be electrically connected to the scan line SC through a corresponding contact hole. The third gate electrode GE3 may overlap with the third active pattern ACT3.

[0174] Each of the third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be configured of a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. Each of the third source electrode SE3 and the third drain electrode DE3 may be doped with impurities and have conductivity. The third active pattern ACT3 may be formed of an intrinsic semiconductor layer that is not doped with impurities.

[0175] The third active pattern ACT3 may be located below the third gate electrode GE3 formed of the second conductive layer C2 and may overlap with the third gate electrode GE3. The third active pattern ACT3 may form the channel region of the third transistor T3.

[0176] The third source electrode SE3 may be electrically connected to the first end of the third active pattern ACT3. The third source electrode SE3 may be doped with impurities during an impurity doping process performed after forming the second conductive layer C2, and may thus have conductivity. The third source electrode SE3 may be electrically connected to the third connection pattern CNP3 through a corresponding contact hole.

[0177] The third drain electrode DE3 may be electrically connected to the second end of the third active pattern ACT3. The third drain electrode DE3 may be doped with impurities during an impurity doping process performed after forming the second conductive layer C2, and may thus have conductivity. The third drain electrode DE3 may be electrically connected to the fourth connection pattern CNP4 through a corresponding contact hole.

[0178] The storage capacitor Cst may include a lower electrode LE and an upper electrode UE.

[0179] The lower electrode LE may be arranged in a shape extending from the second source electrode SE2 to the second region A2. In an embodiment, the lower electrode LE may be integrally formed with the second source electrode SE2. The lower electrode LE may be configured of a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc., and may have conductivity after being doped with impurities.

[0180] The upper electrode UE may be formed of the fourth conductive layer C4, and may extend in the second direction DR2 in the second region A2. The upper electrode UE may be arranged to overlap the lower electrode LE, and may be electrically connected to the bottom metal pattern BML through a corresponding contact hole. The upper electrode UE may be electrically connected to the first electrode PE1 of the emission assembly EMU through the third connection pattern CNP3 electrically connected to the bottom metal pattern BML.

[0181] The emission assembly EMU of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include a light-emitting element LD located in the second region A2 of the corresponding sub-pixel. In addition, the emission assembly EMU of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include an electrode PE, an intermediate electrode CTE, and an alignment electrode ALE electrically connected to the light-emitting element LD. The first bank BNK1 may be provided in the non-emission region NEA of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0182] The first bank BNK1 may be a pixel defining layer that is a structure defining (or separating) a first emission area EMA1, a second emission area EMA2, and a third emission area EMA3. For example, the first bank BNK1 may be a structure defining the emission area of each of adjacent sub-pixels. The first bank BNK1 may define the position where the light-emitting element LD is provided (or input) during the process of providing (or inputting) the light-emitting element LD into each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. For example, since the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3 are separated (or defined) by the first bank BNK1, a mixed solution (e.g., ink) including a target amount and / or type of the light-emitting element LD may be provided (or input) into the corresponding emission area.

[0183] In an embodiment, the first bank BNK1 may include at least one light-blocking material and / or a reflective material (or a scattering material) so as to prevent a light leakage defect in which light (or light rays) leaks between adjacent sub-pixels. In an embodiment, the first bank BNK1 may include a transparent material (or substance). The transparent material may include, for example, a polyamide resin, a polyimide resin, etc., but the present disclosure is not limited thereto. In an embodiment, in order to improve the efficiency of the light emitted from each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, a separate reflective layer may be provided and / or formed on the first bank BNK1.

[0184] The first bank BNK1 may include an opening OP in the pixel area PXA, and components disposed below it are exposed through the opening OP. In an embodiment, each of the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3 may correspond to the opening OP of the first bank BNK1.

[0185] Since the first bank BNK1 is disposed in the non-emission area NEA between the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3, the area of the pixel area PXA to which the light-emitting element LD is to be provided (or input) may be determined. Therefore, in the step of providing the light-emitting element LD to the pixel PXL, it is possible to prevent the light-emitting element LD from being provided to an undesired area, and the light-emitting element LD can be effectively provided to each of the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3. Therefore, it is possible to prevent the light-emitting element LD from being wasted unnecessarily. The manufacturing cost of the display device DD (or the pixel PXL) can be reduced.

[0186] The electrode separation area ESA can be set in the non-emission area NEA of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The electrode separation area ESA can be an area where the alignment electrode ALE in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 is separated from the corresponding floating pattern.

[0187] The emission components EMU of the first sub-pixel SPX1, the emission components EMU of the second sub-pixel SPX2, and the emission components EMU of the third sub-pixel SPX3 can have substantially the same or similar structures. Hereinafter, the emission component EMU of the first sub-pixel SPX1 will be described as a representative example. The description of the emission component EMU of the first sub-pixel SPX1 will replace the descriptions of the emission components EMU of the second sub-pixel SPX2 and the third sub-pixel SPX3.

[0188] The emission component EMU of the first sub-pixel SPX1 can include an electrode PE and an intermediate electrode CTE disposed in at least the first emission area EMA1, a light-emitting element LD electrically connected to the electrode PE and the intermediate electrode CTE, and an alignment electrode ALE disposed at positions corresponding to the electrode PE and the intermediate electrode CTE. For example, the emission component EMU of the first sub-pixel SPX1 can include a first electrode PE1 (or first pixel electrode), a second electrode PE2 (or second pixel electrode), an intermediate electrode CTE (or bridging electrode), a light-emitting element LD, and a first alignment electrode ALE1, a second alignment electrode ALE2, and a third alignment electrode ALE3 disposed in at least the first emission area EMA1. Each of the electrode PE, the intermediate electrode CTE, and / or the alignment electrode ALE can be changed in terms of quantity, shape, size, arrangement structure, etc. in various ways according to the structure of the first sub-pixel SPX1.

[0189] In an embodiment, based on one surface of the substrate SUB on which the first sub-pixel SPX1 is disposed, the alignment electrode ALE, the light-emitting element LD, the electrode PE, and / or the intermediate electrode CTE can be disposed in the listed order, but the present disclosure is not limited thereto. The positions and formation orders of the electrode patterns forming the emission component EMU can be changed in various ways. Below will refer to Figures 10 to 15 Describe the stacked structure (or cross-sectional structure) of the first sub-pixel SPX1.

[0190] The alignment electrodes ALE may be disposed in at least the first emission region EMA1, and may be spaced apart from each other in the first direction DR1 in the first emission region EMA1, and each may extend in the second direction DR2. In an embodiment, the alignment electrodes ALE may include a third alignment electrode ALE3, a first alignment electrode ALE1, and a second alignment electrode ALE2 arranged to be spaced apart from each other in the first direction DR1.

[0191] During the process of manufacturing the display device DD (or pixel PXL), each of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 may be separated from the corresponding power line PL by removing a part thereof after the light-emitting element LD is aligned in the first emission region EMA1. For example, the first alignment electrode ALE1 may be electrically separated from the second horizontal power line PL2b by removing a region of the first alignment electrode ALE1 located in the electrode separation region ESA after the light-emitting element LD is aligned in the first emission region EMA1. The second alignment electrode ALE2 may be electrically separated from the first horizontal power line PL1b by removing a region of the second alignment electrode ALE2 located in the electrode separation region ESA after the light-emitting element LD is provided and aligned in the first emission region EMA1. The third alignment electrode ALE3 may be electrically separated from the first horizontal power line PL1b by removing a region of the third alignment electrode ALE3 located in the electrode separation region ESA after the light-emitting element LD is provided and aligned in the first emission region EMA1.

[0192] The first alignment electrode ALE1 may be formed to be integrally connected to the first floating pattern FTP1 during the process of manufacturing the display device DD (or pixel PXL), thereby forming the first alignment line ALL1, as Figure 9 shown. The first floating pattern FTP1 may be electrically connected to the second horizontal power line PL2b through the first contact hole CH1. During the process of aligning the light-emitting element LD, a first alignment signal may be provided to the first alignment line ALL1 through the second horizontal power line PL2b. After the process of aligning the light-emitting element LD is completed, a part of the first alignment line ALL1 around the first contact hole CH1 located in the non-emission region NEA may be removed (or the first alignment line ALL1 may be cut off), thereby interrupting the electrical connection between the first alignment line ALL1 and the second horizontal power line PL2b. For example, the first alignment line ALL1 may be divided into the first alignment electrode ALE1 and the first floating pattern FTP1 by cutting off the first alignment line ALL1 in the electrode separation region ESA located around the first floating pattern FTP1.

[0193] The second alignment electrode ALE2 can be formed integrally connected to the second floating pattern FTP2 during the process of manufacturing the display device DD, thereby forming the second alignment line ALL2, as Figure 9 shown. The second floating pattern FTP2 can be electrically connected to the first horizontal power line PL1b through the second contact hole CH2. During the process of aligning the light-emitting element LD, a second alignment signal can be provided to the second alignment line ALL2 through the first horizontal power line PL1b. After the process of aligning the light-emitting element LD is completed, a part of the second alignment line ALL2 around the second contact hole CH2 located in the non-emission area NEA can be removed (or the second alignment line ALL2 can be cut off), thereby interrupting the electrical connection between the second alignment line ALL2 and the first horizontal power line PL1b. For example, the second alignment line ALL2 can be divided into the second alignment electrode ALE2 and the second floating pattern FTP2 by cutting off the second alignment line ALL2 in the electrode separation area ESA located around the second floating pattern FTP2.

[0194] The third alignment electrode ALE3 can be formed integrally connected to the third floating pattern FTP3 during the process of manufacturing the display device DD, thereby forming the third alignment line ALL3, as Figure 9 shown. The third floating pattern FTP3 can be electrically connected to the first horizontal power line PL1b through the third contact hole CH3. During the process of aligning the light-emitting element LD, a second alignment signal can be provided to the third alignment line ALL3 through the first horizontal power line PL1b. After the process of aligning the light-emitting element LD is completed, a part of the third alignment line ALL3 around the third contact hole CH3 located in the non-emission area NEA can be removed (or the third alignment line ALL3 can be cut off), thereby interrupting the electrical connection between the third alignment line ALL3 and the first horizontal power line PL1b. For example, the third alignment line ALL3 can be divided into the third alignment electrode ALE3 and the third floating pattern FTP3 by cutting off the third alignment line ALL3 in the electrode separation area ESA located around the third floating pattern FTP3.

[0195] The aforementioned first alignment signal and second alignment signal can be signals each having a voltage difference and / or a phase difference that enables the light-emitting element LD to be aligned between the first alignment line ALL1, the second alignment line ALL2, and the third alignment line ALL3. At least one of the first alignment signal and the second alignment signal can be an AC signal, but the present disclosure is not limited thereto.

[0196] In an embodiment, the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3, and the first floating pattern FTP1, the second floating pattern FTP2, and the third floating pattern FTP3 may be formed of a third conductive layer C3. For example, the third conductive layer C3 may be a conductive layer among the conductive layers formed on the substrate SUB and located between the second conductive layer C2 and the fourth conductive layer C4. In the first emission region EMA1 located in the second region A2, other conductive layers (e.g., the first conductive layer C1, the second conductive layer C2, and a semiconductor pattern having conductivity) may not be located under the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3.

[0197] In a plan view, the third alignment electrode ALE3, the first alignment electrode ALE1, and the second alignment electrode ALE2 may be arranged in the first direction DR1 in the listed order in the first emission region EMA1. The third alignment electrode ALE3 and the second alignment electrode ALE2 may face each other, and the first alignment electrode ALE1 may be interposed therebetween.

[0198] Each of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 may be set in the form of a bar having a constant width at least in the first emission region EMA1, but the present disclosure is not limited thereto.

[0199] In an embodiment, each of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 may be floating rather than being electrically connected to any electrode. In this case, during the process of driving the light-emitting element LD, the electrical influence of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 on the first electrode PE1, the second electrode PE2, and the intermediate electrode CTE may be reduced or prevented.

[0200] Although at least two to several tens of light-emitting elements LD may be aligned and / or disposed in the first emission region EMA1 (or the first sub-pixel region SPXA1), the number of the light-emitting elements LD is not limited thereto.

[0201] The light-emitting element LD can be disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2, and between the first alignment electrode ALE1 and the third alignment electrode ALE3. In a plan view, each of the light-emitting elements LD may include a first end EP1 and a second end EP2 that are located on respective opposite ends (or face each other) of the light-emitting element LD in its longitudinal direction (e.g., in the first direction DR1). In an embodiment, a second semiconductor layer 13 including a p-type semiconductor layer may be disposed on the first end EP1 (or p-type end), and a first semiconductor layer 11 including an n-type semiconductor layer may be disposed on the second end EP2 (or n-type end). The light-emitting elements LD may be electrically connected in parallel to each other between the first alignment electrode ALE1 and the second alignment electrode ALE2, and between the first alignment electrode ALE1 and the third alignment electrode ALE3.

[0202] The light-emitting elements LD may be disposed at positions spaced apart from each other and aligned substantially parallel to each other. The distance by which the light-emitting elements LD are spaced apart from each other is not particularly limited. In an embodiment, the light-emitting elements LD may be disposed adjacent to each other to form a group, and the light-emitting elements LD may be spaced apart from each other at a fixed interval to form a group. The light-emitting elements LD may be aligned with an uneven density in one direction.

[0203] The light-emitting element LD may be input (or provided) to the first emission area EMA1 (or the opening OP of the first bank BNK1) by an inkjet printing scheme, a slot coating scheme, or various other schemes. For example, the light-emitting element LD may be mixed with a volatile solvent and then input (or provided) to the first emission area EMA1 by an inkjet printing scheme or a slot coating scheme.

[0204] The light-emitting element LD may include a first light-emitting element LD1 and a second light-emitting element LD2.

[0205] The first light-emitting element LD1 may be disposed between the first side (e.g., the right side) of the first alignment electrode ALE1 and the second alignment electrode ALE2, and is electrically connected to the first electrode PE1 and the intermediate electrode CTE. The second light-emitting element LD2 may be disposed between the second side (e.g., the left side) of the first alignment electrode ALE1 and the third alignment electrode ALE3, and is electrically connected to the intermediate electrode CTE and the second electrode PE2.

[0206] A plurality of first light-emitting elements LD1 and a plurality of second light-emitting elements LD2 may be provided. The first end EP1 of each of the first light-emitting elements LD1 may be electrically connected to the first electrode PE1. The second end EP2 of each of the first light-emitting elements LD1 may be electrically connected to the intermediate electrode CTE. The first end EP1 of each of the second light-emitting elements LD2 may be electrically connected to the intermediate electrode CTE.

[0207] The second end EP2 of each of the second light-emitting elements LD2 may be electrically connected to the second electrode PE2.

[0208] The first light-emitting elements LD1 may be electrically connected in parallel to each other between the first electrode PE1 and the intermediate electrode CTE. The second light-emitting elements LD2 may be electrically connected in parallel to each other between the intermediate electrode CTE and the second electrode PE2.

[0209] The electrode PE and the intermediate electrode CTE may be provided in at least the first emission region EMA1, and each may be provided at positions corresponding to at least one alignment electrode ALE and at least one light-emitting element LD. For example, each electrode PE and each intermediate electrode CTE may be formed on the corresponding alignment electrode ALE and the corresponding light-emitting element LD so as to overlap the alignment electrode ALE and the light-emitting element LD, and thus may be electrically connected to at least the light-emitting element LD.

[0210] The electrode PE may include a first electrode PE1 and a second electrode PE2 spaced apart from each other.

[0211] The first electrode PE1 (“first pixel electrode” or “anode”) may be formed on the first side of the first alignment electrode ALE1 and on the corresponding first end EP1 of the first light-emitting element LD1, and thus may be electrically connected to the corresponding first end EP1 of the first light-emitting element LD1. The first electrode PE1 may have a bar shape with a constant width in its extending direction (e.g., the second direction DR2).

[0212] The second electrode PE2 (“second pixel electrode” or “cathode”) may be formed on the third alignment electrode ALE3 and on the corresponding second end EP2 of the second light-emitting element LD2, and thus is electrically connected to the corresponding second end EP2 of the second light-emitting element LD2. The second electrode PE2 may have a bar shape with a constant width in its extending direction (e.g., the second direction DR2).

[0213] The intermediate electrode CTE may be formed on the second alignment electrode ALE2 and on the corresponding second end EP2 of the first light-emitting element LD1, and thus may be electrically connected to the corresponding second end EP2 of the first light-emitting element LD1. In addition, the intermediate electrode CTE may be formed on the second side of the first alignment electrode ALE1 and on the corresponding first end EP1 of the second light-emitting element LD2, and thus may be electrically connected to the corresponding first end EP1 of the second light-emitting element LD2. For this purpose, the intermediate electrode CTE may have a bent shape. For example, the intermediate electrode CTE may have a bent or curved structure at the boundary between the region where at least one first light-emitting element LD1 is provided and the region where at least one second light-emitting element LD2 is provided.

[0214] The first electrode PE1, the intermediate electrode CTE, and the second electrode PE2 may be arranged to be spaced apart from each other in the first emission region EMA1. The first electrode PE1, the intermediate electrode CTE, and the second electrode PE2 may be formed of the fifth conductive layer C5.

[0215] In the foregoing solution, the light-emitting element LD may be connected to each other in a desired shape by using the first electrode PE1, the intermediate electrode CTE, and the second electrode PE2. For example, the first light-emitting element LD1 and the second light-emitting element LD2 may be electrically connected in series to each other in sequence by using the first electrode PE1, the intermediate electrode CTE, and the second electrode PE2.

[0216] In an embodiment, the first electrode PE1 may extend to the first region A1 and be electrically connected to the third connection pattern CNP3 through the first contact portion CNT1. The first contact portion CNT1 may be formed by opening a part of at least one insulating layer provided between the first electrode PE1 formed of the fifth conductive layer C5 and the third connection pattern CNP3 formed of the fourth conductive layer C4. A part of the third connection pattern CNP3 may be exposed through the first contact portion CNT1.

[0217] In an embodiment, the second electrode PE2 may be integrally formed with a bridge wiring BRL provided between pixels PXL in different rows. The bridge wiring BRL may be formed of the fifth conductive layer C5.

[0218] The bridge wiring BRL may extend in the first direction DR1 and be integrally formed with and connected to the second electrode PE2. In addition, the bridge wiring BRL may be integrally formed with the second electrode PE2 of each of the second sub-pixel SPX2 and the third sub-pixel SPX3. The second electrode PE2 of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may branch off from the bridge wiring BRL in the second direction DR2 and extend to the second region A2 of the corresponding sub-pixel. Since the bridge wiring BRL and the second electrode PE2 of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are electrically connected to each other, the second electrode PE2 of the first sub-pixel SPX1, the second electrode PE2 of the second sub-pixel SPX2, and the second electrode PE2 of the third sub-pixel SPX3 may be electrically connected to each other.

[0219] The bridge wiring BRL may include a protruding portion PRP protruding toward the first region A1 in the second direction DR2 in a non-emitting region NEA between the second sub-pixel SPX2 and the third sub-pixel SPX3. The protruding portion PRP may be integrally formed with the bridge wiring BRL and is a region of the bridge wiring BRL. The protruding portion PRP may be electrically connected to the third additional conductive pattern ACP3 through the second contact portion CNT2. The second contact portion CNT2 may be formed by opening a part of at least one insulating layer located between the protruding portion PRP (or the bridge wiring BRL) formed by the fifth conductive layer C5 and the third additional conductive pattern ACP3 formed by the second conductive layer C2. A part of the third additional conductive pattern ACP3 may be exposed through the second contact portion CNT2.

[0220] As described above, since the third additional conductive pattern ACP3 is electrically connected to the second vertical power line PL2a through the dummy pattern DMP, the protruding portion PRP (or the bridge wiring BRL) may be electrically connected to the second vertical power line PL2a. Therefore, the second electrode PE2 of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be electrically connected to the second vertical power line PL2a, and thus electrically connected to the second driving power source VSS.

[0221] In an embodiment, the first electrode PE1 may be the anode of the emission component EMU of the first sub-pixel SPX1. The second electrode PE2 may be the cathode of the emission component EMU.

[0222] Hereinafter, it will be mainly referred to Figures 10 to 15 to describe the stacked structure (or cross-sectional structure) of the first sub-pixel SPX1 according to the foregoing embodiment.

[0223] Figure 10 is a schematic cross-sectional view taken along Figure 8 line II-II'. Figures 11 to 14 is a schematic cross-sectional view taken along Figure 8 line III-III'. Figure 15 is a schematic cross-sectional view taken along Figure 8 line IV-IV'.

[0224] Figure 12 The embodiment of Figure 11 relates to a modification of the embodiment of

[0225] Figure 13 and Figure 14 The embodiment of Figure 11Modifications to the embodiments related to both the steps of forming the first electrode PE1, the second electrode PE2, and the intermediate electrode CTE and the presence or absence of the sixth insulating layer INS6. For example, Figure 13 An embodiment is shown in which the intermediate electrode CTE is formed after forming the first electrode PE1, the second electrode PE2, and the sixth insulating layer INS6. Figure 14 An embodiment is shown in which the first electrode PE1 and the second electrode PE2 are formed after forming the intermediate electrode CTE and the sixth insulating layer INS6.

[0226] Although Figures 10 to 15 simply shows the stacked structure (or cross-sectional structure) of the first sub-pixel SPX1. For example, it shows that each electrode is formed of a single-layer electrode and each insulating layer is formed of a single insulating layer, but the present disclosure is not limited thereto.

[0227] The following description of the Figures 10 to 15 embodiments will focus on the differences from the above embodiments to avoid redundant description.

[0228] Referring to Figures 1 to 15 , according to an embodiment, the first sub-pixel SPX1 may be located in a first sub-pixel region SPXA1 provided in the substrate SUB or the display device DD. The first sub-pixel region SPXA1 may include a first region A1 and a second region A2.

[0229] Circuit elements (e.g., transistors T1, T2, and T3) of the pixel circuit PXC for forming the first sub-pixel SPX1 and signal lines electrically connected to the pixel circuit PXC may be provided in the first region A1.

[0230] The light-emitting element layer LDL forming the emission assembly EMU of the first sub-pixel SPX1 and the signal lines provided in the first region A1 may be provided in the second region A2. The second region A2 may include a first emission region EMA1 from which light may be emitted.

[0231] At least one or more insulating layers may be provided on the substrate SUB. For example, a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, a fourth insulating layer INS4, and a fifth insulating layer INS5 stacked in sequence in a third direction DR3 may be provided on the substrate SUB. In an embodiment, the sixth insulating layer INS6 may be selectively provided on the fifth insulating layer INS5.

[0232] At least one or more conductive layers may be provided on a substrate SUB. For example, the conductive layers may include a first conductive layer C1 provided on the substrate SUB, a second conductive layer C2 provided on a second insulating layer INS2, a third conductive layer C3 provided on a third insulating layer INS3, a fourth conductive layer C4 provided on a fourth insulating layer INS4, and a fifth conductive layer C5 provided on a fifth insulating layer INS5.

[0233] The first conductive layer C1 may include a first vertical power line PL1a, a second vertical power line PL2a, an initialization power line IPL, a first data line D1, a second data line D2, and a third data line D3, and a bottom metal pattern BML. The second conductive layer C2 may include a first gate electrode GE1, a second gate electrode GE2, and a third gate electrode GE3, and a first additional conductive pattern ACP1, a second additional conductive pattern ACP2, and a third additional conductive pattern ACP3. The third conductive layer C3 may include a first alignment electrode ALE1, a second alignment electrode ALE2, and a third alignment electrode ALE3, and a first floating pattern FTP1, a second floating pattern FTP2, and a third floating pattern FTP3. The fourth conductive layer C4 may include a first horizontal power line PL1b, a first dummy power line PL1c, a second horizontal power line PL2b, a second dummy power line PL2c, a first connection pattern CNP1, a second connection pattern CNP2, a third connection pattern CNP3, and a fourth connection pattern CNP4, an upper electrode UE, a dummy pattern DMP, and a scan line SC. The fifth conductive layer C5 may include a first electrode PE1, a second electrode PE2, an intermediate electrode CTE, a bridge wire BRL, and a protruding portion PRP.

[0234] The substrate SUB may include a transparent insulating material that allows light transmission. The substrate SUB may be a rigid substrate or a flexible substrate.

[0235] A first insulating layer INS1 (or buffer layer) may be provided on the entire surface of the substrate SUB. The first insulating layer INS1 may prevent impurities from diffusing into transistors T1, T2, and T3 included in the pixel circuit PXC. The first insulating layer INS1 may be an inorganic insulating layer including an inorganic material. The first insulating layer INS1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), or at least one of these, or such as aluminum oxide (AlO x) at least one of the metal oxides. Although the first insulating layer INS1 may have a single-layer structure, the first insulating layer INS1 may also have a multi-layer structure having at least two or more layers. In the case where the first insulating layer INS1 has a multi-layer structure, the corresponding layers may be formed of the same material or different materials. Depending on the material or process conditions of the substrate SUB, the first insulating layer INS1 may be omitted.

[0236] The second insulating layer INS2 (or gate insulating layer) may be partially disposed on the first insulating layer INS1. For example, the second insulating layer INS2 may be disposed only under the second conductive layer C2 and may have the same width as the second conductive layer C2. The second insulating layer INS2 may include the same material as the first insulating layer INS1, or may include a suitable (or selected) material among the materials listed as the constituent materials of the first insulating layer INS1. For example, the second insulating layer INS2 may be formed of an inorganic insulating layer including an inorganic material.

[0237] The third insulating layer INS3 (or interlayer insulating layer) may be disposed and / or formed on the entire surface of the first insulating layer INS1 and the second conductive layer C2. The third insulating layer INS3 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials among the materials listed as the constituent materials of the first insulating layer INS1. For example, the third insulating layer INS3 may be formed of an inorganic insulating layer including an inorganic material.

[0238] The fourth insulating layer INS4 (or passivation layer) may be disposed and / or formed on the entire surface of the third insulating layer INS3. The fourth insulating layer INS4 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials among the materials listed as the constituent materials of the first insulating layer INS1. For example, the fourth insulating layer INS4 may be formed of an inorganic insulating layer including an inorganic material.

[0239] The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst disposed on the first insulating layer INS1.

[0240] The first transistor T1 may include a first active pattern ACT1, a first source electrode SE1, and a first drain electrode DE1 disposed on the first insulating layer INS1, and a first gate electrode GE1 disposed on the second insulating layer INS2. The bottom metal pattern BML may be disposed under the first transistor T1. The bottom metal pattern BML may be formed of the first conductive layer C1 located between the substrate SUB and the first insulating layer INS1.

[0241] The second transistor T2 may include a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2 disposed on the first insulating layer INS1, and a second gate electrode GE2 disposed on the second insulating layer INS2.

[0242] The third transistor T3 may include a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3 disposed on the first insulating layer INS1, and a third gate electrode GE3 disposed on the second insulating layer INS2.

[0243] The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may be formed of a second conductive layer C2.

[0244] The storage capacitor Cst may include a lower electrode LE disposed on the first insulating layer INS1 and an upper electrode UE disposed on the fourth insulating layer INS4. The lower electrode LE may be integrally formed with the second source electrode SE2 and thus electrically connected to the second source electrode SE2 and may thus have conductivity. The upper electrode UE may be formed of a fourth conductive layer C4 and may be electrically connected to the bottom metal pattern BML through corresponding contact holes passing through the fourth insulating layer INS4, the third insulating layer INS3, and the first insulating layer INS1.

[0245] In an embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 of the pixel circuit PXC forming the first sub-pixel SPX1 and the storage capacitor Cst may include conductive patterns formed of a first conductive layer C1, a second conductive layer C2, and a fourth conductive layer C4.

[0246] A fifth insulating layer INS5 may be provided and / or formed on the pixel circuit PXC.

[0247] The fifth insulating layer INS5 (or via layer) may be provided and / or formed on the entire surface of the fourth insulating layer INS4. The fifth insulating layer INS5 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ). The organic insulating layer may include, for example, at least one of polypropylene resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin. In an embodiment, the fifth insulating layer INS5 may be formed of an organic insulating layer.

[0248] The emission module EMU may include a first alignment electrode ALE1, a second alignment electrode ALE2, and a third alignment electrode ALE3, a first floating pattern FTP1, a second floating pattern FTP2, and a third floating pattern FTP3, and a light-emitting element LD disposed on a third insulating layer INS3, and a first electrode PE1, a second electrode PE2, and / or an intermediate electrode CTE disposed on a fifth insulating layer INS5.

[0249] The first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 may be located in a first emission area EMA1 of a second area A2 and disposed on the third insulating layer INS3. The first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 may be formed of a third conductive layer C3.

[0250] The first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 may be disposed on the same plane and have the same thickness in a third direction DR3. The first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 may be formed simultaneously by the same process or may be formed sequentially.

[0251] The first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 may be formed of a material having a reflectivity to allow the light emitted from the light-emitting element LD to travel in the image display direction (or front direction) of the display device DD. For example, the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 may be formed of a conductive material (or substance). The conductive material may include an opaque metal suitable for reflecting the light emitted from the light-emitting element LD in the image display direction of the display device DD.

[0252] Each of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 may have a single-layer structure, but is not limited thereto. In an embodiment, each of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 may be disposed and / or formed as a multi-layer structure formed by stacking at least two or more materials among metals, alloys, conductive oxides, and conductive polymers.

[0253] In the case where the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 are formed of a conductive material having a reflectivity, the light emitted from the first end EP1 and the second end EP2 of each of the light-emitting elements LD may travel more reliably in the image display direction of the display device DD.

[0254] In an embodiment, in a first emission region EMA1 (or a second region A2) where a first alignment electrode ALE1, a second alignment electrode ALE2, and a third alignment electrode ALE3 are provided, another conductive layer may not be provided under the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3. For example, in addition to a first insulating layer INS1, a second insulating layer INS2, and a third insulating layer INS3 formed of an inorganic insulating layer, for example, a first conductive layer C1, a second conductive layer C2, and a conductive pattern of a semiconductive pattern having conductivity may not be provided under the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3. Accordingly, in the first emission region EMA1 (or the second region A2), each of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 may not be affected by a step difference (or height difference) that may be caused by components located thereunder, and thus has a flat surface.

[0255] In an embodiment, a first floating pattern FTP1, a second floating pattern FTP2, and a third floating pattern FTP3 formed of a third conductive layer C3 provided on a third insulating layer INS3 may be provided in the second region A2. The first floating pattern FTP1 may be provided to be spaced apart from the first alignment electrode ALE1, and an electrode separation region ESA may be interposed therebetween. The second floating pattern FTP2 may be provided to be spaced apart from the second alignment electrode ALE2, and the electrode separation region ESA may be interposed therebetween. The third floating pattern FTP3 may be provided to be spaced apart from the third alignment electrode ALE3, and the electrode separation region ESA may be interposed therebetween.

[0256] A fourth insulating layer INS4 may be provided and / or formed on the first alignment electrode ALE1, the second alignment electrode ALE2, the third alignment electrode ALE3, the first floating pattern FTP1, the second floating pattern FTP2, and the third floating pattern FTP3. For example, the first alignment electrode ALE1, the second alignment electrode ALE2, the third alignment electrode ALE3, the first floating pattern FTP1, the second floating pattern FTP2, and the third floating pattern FTP3 may be covered by the fourth insulating layer INS4.

[0257] In an embodiment, the first floating pattern FTP1 may be electrically connected to a second horizontal power line PL2b formed of a fourth conductive layer C4 provided on the fourth insulating layer INS4. For example, the first floating pattern FTP1 may be electrically connected to the second horizontal power line PL2b through a first contact hole CH1 penetrating the fourth insulating layer INS4.

[0258] The second floating pattern FTP2 can be electrically connected to a first horizontal power line PL1b formed by a fourth conductive layer C4 provided on a fourth insulating layer INS4. For example, the second floating pattern FTP2 can be electrically connected to the first horizontal power line PL1b through a second contact hole CH2 passing through the fourth insulating layer INS4.

[0259] The third floating pattern FTP3 can be electrically connected to a first horizontal power line PL1b formed by a fourth conductive layer C4 provided on a fourth insulating layer INS4. For example, the third floating pattern FTP3 can be electrically connected to the first horizontal power line PL1b through a third contact hole CH3 passing through the fourth insulating layer INS4.

[0260] A fifth insulating layer INS5 can be provided on the fourth insulating layer INS4.

[0261] A first bank BNK1 can be provided on the fifth insulating layer INS5 in a non-emitting area NEA of a second area A2.

[0262] The first bank BNK1 can be provided on the fifth insulating layer INS5 in at least the second area A2, but the present disclosure is not limited thereto. The first bank BNK1 can be formed between adjacent sub-pixels to surround a first emission area EMA1, such that a pixel defining layer for separating (or defining) the first emission area EMA1 can be formed. In a step of providing a light-emitting element LD to the first emission area EMA1, the first bank BNK1 can be a dam structure configured to prevent a solution (or ink) that is mixed with the light-emitting element LD from being introduced into a second emission area EMA2 or a third emission area EMA3 or to control the amount of the solution, such that a constant amount of the solution is provided to each of the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3.

[0263] In an embodiment, as Figure 12 shown, a bank pattern BNP can be provided in the first emission area EMA1.

[0264] The bank pattern BNP may be disposed on the fifth insulating layer INS5 and may protrude in a third direction DR3 on one surface of the fifth insulating layer INS5. The bank pattern BNP may include an inorganic insulating layer containing an inorganic material and / or an organic insulating layer containing an organic material. In an embodiment, the bank pattern BNP may include an organic insulating layer having a single-layer structure and / or an inorganic insulating layer having a single-layer structure, but the present disclosure is not limited thereto. In an embodiment, the bank pattern BNP may be provided in a multilayer structure formed by stacking at least one or more organic insulating layers and at least one or more inorganic insulating layers. However, the material of the bank pattern BNP is not limited to the foregoing embodiments. In an embodiment, the bank pattern BNP may include a conductive material (or substance). In this case, the bank pattern BNP may be used as a reflector. For example, the bank pattern BNP may be used as a reflector configured to guide the light emitted from the light-emitting element LD to the image display direction of the display device DD, thereby improving the light output efficiency of the first sub-pixel SPX1.

[0265] The bank pattern BNP may be located above each of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 in at least the first emission area EMA1 and overlap with the corresponding alignment electrode ALE. The first light-emitting element LD1 may be aligned on the fifth insulating layer INS5 between the bank pattern BNP on the first alignment electrode ALE1 and the bank pattern BNP on the second alignment electrode ALE2. The second light-emitting element LD2 may be aligned on the fifth insulating layer INS5 between the bank pattern BNP on the first alignment electrode ALE1 and the bank pattern BNP on the third alignment electrode ALE3. The bank pattern BNP may be a structure for precisely defining (or providing) the alignment position of the light-emitting element LD in the first emission area EMA1.

[0266] The first bank BNK1 and the bank pattern BNP may be formed by different processes and disposed in different layers, but the present disclosure is not limited thereto. In an embodiment, the first bank BNK1 and the bank pattern BNP may be formed by different processes and disposed in the same layer, or may be formed by the same process and disposed in the same layer.

[0267] In the second region A2, the light-emitting element LD may be aligned (or disposed) in a first emission region EMA1 in which a fifth insulating layer INS5 and a first bank BNK1 are formed. For example, the light-emitting element LD may be provided (or input) into the first emission region EMA1 by an inkjet printing scheme or the like. The light-emitting element LD may be aligned between a first alignment electrode ALE1, a second alignment electrode ALE2, and a third alignment electrode ALE3 by an electric field formed by signals (or alignment signals) applied to the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3, respectively. For example, the light-emitting element LD may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2 on the fifth insulating layer INS5, and may be aligned between the first alignment electrode ALE1 and the third alignment electrode ALE3 on the fifth insulating layer INS5.

[0268] The first light-emitting element LD1 may be disposed between a first side (or right side) of the first alignment electrode ALE1 and the second alignment electrode ALE2. The first light-emitting element LD1 may include a first end EP1 overlapping the first alignment electrode ALE1 and a second end EP2 overlapping the second alignment electrode ALE2.

[0269] The second light-emitting element LD2 may be disposed between a second side (or left side) of the first alignment electrode ALE1 and the third alignment electrode ALE3. The second light-emitting element LD2 may include a first end EP1 overlapping the first alignment electrode ALE1 and a second end EP2 overlapping the third alignment electrode ALE3.

[0270] An insulating pattern INSP may be disposed on the first light-emitting element LD1 and the second light-emitting element LD2. The insulating pattern INSP may be disposed on each of the first light-emitting element LD1 and the second light-emitting element LD2, and may partially cover an outer circumferential surface (or surface) of each of the first light-emitting element LD1 and the second light-emitting element LD2, such that the first end EP1 and the second end EP2 of each of the first light-emitting element LD1 and the second light-emitting element LD2 may be exposed to the outside.

[0271] The insulating pattern INSP may include an inorganic insulating layer and / or an organic insulating layer containing an inorganic material. For example, the insulating pattern INSP may include an inorganic insulating layer suitable for protecting an active layer 12 of each of the first light-emitting element LD1 and the second light-emitting element LD2 from external oxygen, water, etc. However, the present disclosure is not limited thereto. Depending on design conditions of a display device DD (or a display panel DP) to which the first light-emitting element LD1 and the second light-emitting element LD2 are applied, the insulating pattern INSP may be formed of an organic insulating layer including an organic material. The insulating pattern INSP may be formed of a single layer or multiple layers.

[0272] Since the insulating pattern INSP is formed on the light-emitting element LD that has been perfectly aligned in the first emission region EMA1, the light-emitting element LD can be prevented from being removed from the alignment position.

[0273] Different electrodes among the first electrode PE1, the second electrode PE2, and the intermediate electrode CTE can be formed on the first end EP1 and the second end EP2 of the light-emitting element LD that are not covered by the insulating pattern INSP. For example, the first electrode PE1 can be formed on the first end EP1 of the first light-emitting element LD1. The intermediate electrode CTE can be formed on the second end EP2 of the first light-emitting element LD1. The intermediate electrode CTE can be formed on the first end EP1 of the second light-emitting element LD2. The second electrode PE2 can be formed on the second end EP2 of the second light-emitting element LD2.

[0274] In an embodiment, the first electrode PE1, the intermediate electrode CTE, and the second electrode PE2 can be formed in the same layer or different layers. For example, the relative positions and / or the formation order of the first electrode PE1, the intermediate electrode CTE, and the second electrode PE2 can be changed in various ways according to the embodiment.

[0275] In Figure 11 and Figure 12 In the embodiment shown, the first electrode PE1, the second electrode PE2, and the intermediate electrode CTE can be formed simultaneously, and the corresponding insulating pattern INSP is interposed therebetween. For example, the first electrode PE1 can be positioned adjacent to the first side surface (e.g., the left side surface) of the insulating pattern INSP on the first light-emitting element LD1. The intermediate electrode CTE can be positioned adjacent to the second side surface (e.g., the right side surface) of the insulating pattern INSP. The second electrode PE2 can be positioned adjacent to the first side surface (e.g., the left side surface) of the insulating pattern INSP on the second light-emitting element LD2. The intermediate electrode CTE can be positioned adjacent to the second side surface (e.g., the right side surface) of the insulating pattern INSP. The first electrode PE1 can directly contact the first end EP1 of the first light-emitting element LD1 and be electrically connected to the first light-emitting element LD1. The intermediate electrode CTE can directly contact the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2 and thus be electrically connected to each of the first light-emitting element LD1 and the second light-emitting element LD2. The second electrode PE2 can directly contact the second end EP2 of the second light-emitting element LD2 and be electrically connected to the second light-emitting element LD2. In Figure 11 and Figure 12 In the embodiment of, when the first electrode PE1, the second electrode PE2, and the intermediate electrode CTE are provided in the same layer and formed simultaneously, the process of manufacturing the first pixel SPX1 (or the display device DD) can be simplified, and its manufacturing efficiency can be improved.

[0276] In Figure 13 the embodiment, the first electrode PE1 and the second electrode PE2 may be first formed on the insulating pattern INSP. The first electrode PE1 may directly contact the first end EP1 of the first light-emitting element LD1 and be electrically connected to the first light-emitting element LD1. The second electrode PE2 may directly contact the second end EP2 of the second light-emitting element LD2 and be electrically connected to the second light-emitting element LD2. The sixth insulating layer INS6 may be formed to cover the first electrode PE1 and the second electrode PE2. The sixth insulating layer INS6 may be located on the first electrode PE1 and the second electrode PE2 and cover the first electrode PE1 and the second electrode PE2 (or prevent the first electrode PE1 and the second electrode PE2 from being exposed), thereby protecting the first electrode PE1 and the second electrode PE2.

[0277] The sixth insulating layer INS6 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The sixth insulating layer INS6 may be formed of a single layer or multiple layers.

[0278] The intermediate electrode CTE may be formed on the sixth insulating layer INS6. The intermediate electrode CTE may directly contact the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2, and thus be electrically connected between the first light-emitting element LD1 and the second light-emitting element LD2.

[0279] In Figure 14 the embodiment, the intermediate electrode CTE may be first formed on the insulating pattern INSP. Thereafter, the sixth insulating layer INS6 may be formed to cover the intermediate electrode CTE. The first electrode PE1 and the second electrode PE2 may be formed in the first emission region EMA1 in which the sixth insulating layer INS6 has been formed.

[0280] As Figure 13 and Figure 14 shown in the embodiments of, in the case where the electrodes provided on the first end EP1 and the second end EP2 of each of the light-emitting elements LD are provided in different layers, the electrodes can be reliably electrically separated from each other, thereby ensuring electrical stability between the first end EP1 and the second end EP2 of the light-emitting element LD.

[0281] Each of the first electrode PE1, the second electrode PE2, and the intermediate electrode CTE can be formed of various transparent conductive materials. For example, each of the first electrode PE1, the second electrode PE2, and the intermediate electrode CTE can include at least one of transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc oxide tin, or gallium tin oxide, and can be substantially transparent or translucent to provide a satisfactory transmittance. Accordingly, light emitted from the first end EP1 and the second end EP2 of the light-emitting element LD can pass through the electrodes PE and the intermediate electrode CTE, and then be emitted to the outside of the display device DD (or the display panel DP).

[0282] At least one outer coating can also be provided over the electrodes PE and the intermediate electrode CTE.

[0283] In an embodiment, the optical layer LCL can be selectively provided on the first electrode PE1, the second electrode PE2, and the intermediate electrode CTE. For example, the optical layer LCL can include a color conversion layer and a color filter layer that can convert light emitted from the light-emitting element LD into light having excellent color reproducibility and emit the converted light. A detailed description of the optical layer LCL will be given below with reference to Figure 25 and Figure 26 for a detailed description of the optical layer LCL.

[0284] As described above, the first sub-pixel region SPXA1 in which the first sub-pixel SPX1 is provided, the second sub-pixel region SPXA2 in which the second sub-pixel SPX2 is provided, and the third sub-pixel region SPXA3 in which the third sub-pixel SPX3 is provided can be separated into a first region A1 in which the pixel circuit PXC is provided and a second region A2 in which the emission component EMU is provided. In the foregoing embodiment, each of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 forming the emission component EMU can be formed of a third conductive layer C3 provided on the third insulating layer INS3. In each of at least the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3, in addition to the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 including inorganic insulating layers, additional conductive patterns may not be provided under the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3. For example, the additional conductive patterns may include electrode patterns and signal lines formed of the first conductive layer C1, electrode patterns formed of the second conductive layer C2, and semiconductor patterns having conductivity. In each of at least the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3, since no conductive patterns are provided therein, the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 can have a uniform profile and thus can have a flat surface. Since the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 are provided on the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 each having a flat surface, the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 can be prevented from being affected by the step difference formed by the components provided thereunder, and thus the step coverage of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 can be improved.

[0285] Since the step coverage of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 is improved, the alignment accuracy of the light-emitting elements LD aligned on the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 can be increased. In this case, the number of light-emitting elements LD that can be used as effective light sources in each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be increased, and thus the light output efficiency of each of the first sub-pixel ALE1, the second sub-pixel ALE2, and the third sub-pixel ALE3 can be improved.

[0286] Since the step coverage of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 is improved, the reliability of components (e.g., the light-emitting element LD, the first electrode PE1, the second electrode PE2, and the intermediate electrode CTE) provided on the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 can be enhanced.

[0287] According to the foregoing embodiment, the light-emitting elements LD are densely aligned in a desired region (e.g., the second region A2 in each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3) such that the alignment distribution of the light-emitting elements LD in each sub-pixel and the alignment distribution of the light-emitting elements LD in adjacent sub-pixels can be uniform. In this case, the display device DD can have a uniform light output distribution over its entire region, thereby enhancing its reliability.

[0288] Figure 16 is a schematic cross-sectional view taken along Figure 3 the line I-I'.

[0289] The following reference Figure 16 will focus on the differences from the description of the foregoing embodiment to avoid redundant explanations.

[0290] Reference Figure 3 and Figure 16 , each of the pads PD provided in the pad region PDA of the non-display region NDA may include a first pad electrode PDE1 and a second pad electrode PDE2.

[0291] The first pad electrode PDE1 may be formed of a fourth conductive layer C4 provided on the fourth insulating layer INS4. The first pad electrode PDE1 may be provided in the same layer as the connection patterns CNP1, CNP2, CNP3, and CNP4, the upper electrode UE, the dummy pattern DMP, etc. described with reference to Figures 6 to 15 , and may have the same material as the connection patterns CNP1, CNP2, CNP3, and CNP4, the upper electrode UE, the dummy pattern DMP, etc.

[0292] The fifth insulating layer INS5 may be provided on the first pad electrode PDE1.

[0293] The fifth insulating layer INS5 may be partially opened in the pad region PDA to expose a region of the first pad electrode PDE1. For example, the fifth insulating layer INS5 may be partially opened to include a pad electrode contact hole PD_CH, and a region of the first pad electrode PDE1 is exposed through the pad electrode contact hole PD_CH in at least the pad region PDA.

[0294] The second pad electrode PDE2 may be formed of a fifth conductive layer C5 disposed on a fifth insulating layer INS5. The second pad electrode PDE2 may be disposed in the same layer as the first electrode PE1, the second electrode PE2, and the intermediate electrode CTE described with reference to Figures 6 to 15 and may include the same materials as the first electrode PE1, the second electrode PE2, and the intermediate electrode CTE. The second pad electrode PDE2 may be in direct contact with the first pad electrode PDE1 exposed through a pad contact hole PD_CH and be electrically connected to the first pad electrode PDE1. The second pad electrode PDE2 may be exposed to the outside and may be electrically connected to a driver through a conductive adhesive or the like.

[0295] Figures 17 to 24 FIG. is a diagram for describing a method of manufacturing a first sub-pixel SPX1 according to an embodiment and is a schematic cross-sectional view corresponding to Figure 8 line II-II′.

[0296] Hereinafter, a method of manufacturing the first sub-pixel SPX1 (or display device) according to an embodiment will be described with reference to Figures 17 to 24 in sequence.

[0297] In the embodiment, a case where steps of manufacturing the first sub-pixel (or display device) are sequentially performed according to a cross-sectional view is shown. However, without changing the technical scope of the present disclosure, some steps shown as being continuously performed may be performed simultaneously, the order of the steps may be changed, some steps may be skipped, or additional steps may be included between the steps.

[0298] With reference to Figures 17 to 24 the description will focus on differences from the above-described embodiment to avoid redundant description.

[0299] With reference to Figures 1 to 17 , a first conductive layer C1 is formed on a substrate SUB. The first conductive layer C1 may include a first vertical power line PL1a, a second vertical power line PL2a, an initialization power line IPL, a first data line D1, a second data line D2, a third data line D3, and a bottom metal pattern BML. The first conductive layer C1 may be located in a first region A1 and a second region A2.

[0300] A first insulating layer INS1 is formed on the entire surfaces of the first conductive layer C1 and the substrate SUB. The first insulating layer INS1 may be disposed on the first conductive layer C1 and the substrate SUB in the first region A1 and the second region A2. In the embodiment, the first insulating layer INS1 may include an inorganic insulating layer containing an inorganic material. For example, the first insulating layer INS1 may include a first layer formed of silicon nitride (SiN x ) and a second layer formed of silicon oxide (SiO x)The formed second inorganic insulating layer.

[0301] A semiconductor pattern is formed on the first insulating layer INS1. The semiconductor pattern may include a first active pattern ACT1, a second active pattern ACT2, and a third active pattern ACT3, a first source electrode SE1, a second source electrode SE2, and a third source electrode SE3, a first drain electrode DE1, a second drain electrode DE2, and a third drain electrode DE3, and a lower electrode LE. The first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3, the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3, and the first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3 may be located only in the first region A1. The lower electrode LE may be located in the first region A1 and the second region A2.

[0302] A second insulating layer INS2 and a second conductive layer C2 provided on the second insulating layer INS2 are formed on the semiconductor pattern and the first insulating layer INS1. The second insulating layer INS2 may include an inorganic insulating layer containing an inorganic material. The second conductive layer C2 may be provided in a bilayer structure stacked in the order of titanium (Ti) / copper (Cu), but the present disclosure is not limited thereto.

[0303] The second conductive layer C2 may include a first gate electrode GE1, a second gate electrode GE2, and a third gate electrode GE3, and a first additional conductive pattern ACP1, a second additional conductive pattern ACP2, and a third additional conductive pattern ACP3. The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may be located only in the first region A1. The first additional conductive pattern ACP1, the second additional conductive pattern ACP2, and the third additional conductive pattern ACP3 may be located in the first region A1 and the second region A2.

[0304] A third insulating layer INS3 is formed on the entire surface of the second conductive layer C2 and the first insulating layer INS1. The third insulating layer INS3 may be provided on the second conductive layer C2 and the first insulating layer INS1 in the first region A1 and the second region A2. In an embodiment, the third insulating layer INS3 may include an inorganic insulating layer containing an inorganic material. For example, the third insulating layer INS3 may include an inorganic insulating layer containing silicon oxynitride (SiO x N y ). However, the embodiment is not limited thereto.

[0305] A third conductive layer C3 is formed on a third insulating layer INS3 in a second region A2. The third conductive layer C3 may include a first alignment line ALL1, a second alignment line ALL2, and a third alignment line ALL3. The first alignment line ALL1 may be divided into a first alignment electrode ALE1 and a first floating pattern FTP1 by removing a part thereof in an electrode separation region ESA after the light-emitting element LD is aligned. The second alignment line ALL2 may be divided into a second alignment electrode ALE2 and a second floating pattern FTP2 by removing a part thereof in the electrode separation region ESA after the light-emitting element LD is aligned. The third alignment line ALL3 may be divided into a third alignment electrode ALE3 and a third floating pattern FTP3 by removing a part thereof in the electrode separation region ESA after the light-emitting element LD is aligned.

[0306] Reference Figures 1 to 18 , a fourth insulating layer INS4 is formed on the entire surfaces of the first alignment line ALL1, the second alignment line ALL2, the third alignment line ALL3, and the third insulating layer INS3. The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 in a first region A1, and may be disposed on the third insulating layer INS3 and the third conductive layer C3 in a second region A2. In an embodiment, the fourth insulating layer INS4 may include an inorganic insulating layer containing an inorganic material. For example, the fourth insulating layer INS4 may include an inorganic insulating layer containing silicon nitride (SiN x ). However, the embodiment is not limited thereto.

[0307] The fourth insulating layer INS4 may be partially opened to include a plurality of contact holes. In an embodiment, the fourth insulating layer INS4 may be partially opened to include a first contact hole CH1, a second contact hole CH2, and a third contact hole CH3 in a second region A2, a region of the first alignment line ALL1 is exposed through the first contact hole CH1, a region of the second alignment line ALL2 is exposed through the second contact hole CH2, and a region of the third alignment line ALL3 is exposed through the third contact hole CH3.

[0308] Reference Figures 1 to 19 , a fourth conductive layer C4 is disposed on the fourth insulating layer INS4. The fourth conductive layer C4 may be located in the first region A1 and the second region A2. The fourth conductive layer C4 may be disposed as a multilayer structure stacked in the order of titanium, copper, and indium tin oxide, but the present disclosure is not limited thereto.

[0309] The fourth conductive layer C4 may include a first horizontal power line PL1b, a first dummy power line PL1c, a second horizontal power line PL2b, a second dummy power line PL2c, a first connection pattern CNP1, a second connection pattern CNP2, a third connection pattern CNP3, and a fourth connection pattern CNP4, an upper electrode UE, a dummy pattern DMP, and a scan line SC. The second horizontal power line PL2b may be electrically connected to a first alignment line ALL1 exposed through a first contact hole CH1 in the second region A2. The first horizontal power line PL1b in the second region A2 may be electrically connected to both a second alignment line ALL2 exposed through a second contact hole CH2 and a third alignment line ALL3 exposed through a third contact hole CH3.

[0310] Reference Figures 1 to 20 , a fifth insulating layer INS5 is formed on the entire surfaces of the fourth conductive layer C4 and the fourth insulating layer INS4. The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 and the fourth conductive layer C4 in the first region A1, and may be disposed on the fourth insulating layer INS4 in the second region A2.

[0311] The fifth insulating layer INS5 may be partially opened to include a first contact portion CNT1 and a second contact portion CNT2. In an embodiment, the fifth insulating layer INS5 may be partially opened to include the first contact portion CNT1 and the second contact portion CNT2 in the first region A1, and a region of the third connection pattern CNP3 is exposed through the first contact portion CNT1, and a region of the third additional conductive pattern ACP3 is exposed through the second contact portion CNT2.

[0312] Reference Figures 1 to 21 , a first bank BNK1 is formed on the fifth insulating layer INS5 in the second region A2. The first bank BNK1 may define a first emission region EMA1 of the first sub-pixel SPX1. In addition, the first bank BNK1 may also define a second emission region EMA2 of a second sub-pixel SPX2 adjacent to the first sub-pixel SPX1 and a third emission region EMA3 of a third sub-pixel SPX3 adjacent to the second sub-pixel SPX2.

[0313] Reference Figures 1 to 22 , the first alignment line ALL1 electrically connected to the second horizontal power line PL2b and the second alignment line ALL2 and the third alignment line ALL3 electrically connected to the first horizontal power line PL1b may be provided with respective corresponding alignment signals such that an electric field may be formed between the first alignment line ALL1, the second alignment line ALL2, and the third alignment line ALL3.

[0314] The ink including the light-emitting element LD is input into the second region A2 by an inkjet printing scheme or the like. For example, at least one inkjet head may be disposed on the fifth insulating layer INS5 in the second region A2, and the ink mixed with the light-emitting element LD may be input into the second region A2 through the inkjet head. Self-alignment of the first light-emitting element LD1 on the fifth insulating layer INS5 between the first alignment line ALL1 and the second alignment line ALL2 may be induced. Self-alignment of the second light-emitting element LD2 on the fifth insulating layer INS5 between the first alignment line ALL1 and the third alignment line ALL3 may be induced.

[0315] After the first light-emitting element LD1 and the second light-emitting element LD2 are self-aligned, the solvent included in the ink may be removed by a volatilization scheme or other schemes.

[0316] Reference Figures 1 to 23 , an insulating pattern INSP is formed on each of the first light-emitting element LD1 and the second light-emitting element LD2. The first end EP1 and the second end EP2 of each of the first light-emitting element LD1 and the second light-emitting element LD2 may be exposed from the insulating pattern INSP.

[0317] Reference Figures 1 to 24 , a fifth conductive layer C5 is formed on the insulating pattern INSP and the fifth insulating layer INS5. The fifth conductive layer C5 may be located in the first region A1 and the second region A2. The fifth conductive layer C5 may include a first electrode PE1, a second electrode PE2, an intermediate electrode CTE, a bridge wiring BRL, and a protruding portion PRP. In an embodiment, the first electrode PE1 may be formed throughout the second region A2 and the first region A1, and may be electrically connected to the third connection pattern CNP3 through the first contact portion CNT1. The second electrode PE2 may branch off from the bridge wiring BRL and be located in the second region A2. The bridge wiring BRL may include a protruding portion PRP extending into the first region A1. The protruding portion PRP may be electrically connected to the third additional conductive pattern ACP3 through the second contact portion CNT2.

[0318] After the fifth conductive layer C5 is formed, an electrode separation process of forming a first alignment electrode ALE1, a second alignment electrode ALE2, and a third alignment electrode ALE3 may be performed by removing corresponding portions of the first alignment line ALL1, the second alignment line ALL2, and the third alignment line ALL3 in the electrode separation region ESA of the second region A2.

[0319] In the first sub-pixel SPX1 (or display device DD) formed by the above manufacturing method, in the second region A2 where the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 are located, except for the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 formed of an inorganic insulating layer, no other conductive patterns are provided under the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3. Therefore, the step coverage of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 can be improved.

[0320] Figure 25 and Figure 26 shows a first sub-pixel SPX1 according to an embodiment, and is a schematic cross-sectional view corresponding to Figure 8 line III-III’ of.

[0321] Figure 25 and Figure 26 Embodiments of relate to different modifications regarding the position of the color conversion layer CCL. For example, Figure 25 shows an embodiment in which the color conversion layer CCL and the color filter layer CFL are provided above the electrodes PE1 and PE2 and the intermediate electrode CTE through a continuous process. Figure 26 shows an embodiment in which the upper substrate U_SUB including the color conversion layer CCL and the color filter layer CFL is provided on the electrodes PE1 and PE2 and the intermediate electrode CTE by using an adhesion process with an intermediate layer CTL.

[0322] Figure 25 and Figure 26 The description of the embodiments of will focus on the differences from the above embodiments in order to avoid redundant description.

[0323] Referring to Figures 1 to 8 and Figure 25 , the first sub-pixel SPX1 may include an optical layer LCL and a packaging layer ENC provided on the electrodes PE1 and PE2 and the intermediate electrode CTE.

[0324] The optical layer LCL may include a color conversion layer CCL provided on the electrodes PE1 and PE2 and the intermediate electrode CTE to correspond to a light-emitting element LD in at least a first emission region EMA1 of the second region A2, and a color filter layer CFL provided on the color conversion layer CCL. In addition, the optical layer LCL may further include a second bank BNK2 in at least a non-emission region NEA of the second region A2, the second bank BNK2 surrounding the color conversion layer CCL and provided on the first bank BNK1.

[0325] The second bank BNK2 can be disposed on the first bank BNK1 in the non-emission area NEA of the first sub-pixel SPX1. The second bank BNK2 can be a dam structure that surrounds the first emission area EMA1 of the first sub-pixel SPX1 and defines a position where the color conversion layer CCL is to be provided, thereby ultimately defining the first emission area EMA1.

[0326] The second bank BNK2 can include a light-shielding material. For example, the second bank BNK2 can be a black matrix, but the present disclosure is not limited thereto. In an embodiment, the second bank BNK2 can include at least one light-shielding material and / or a reflective material, and allow the light emitted from the color conversion layer CCL to travel more reliably in the image display direction of the display device DD, thereby improving the light output efficiency of the color conversion layer CCL.

[0327] The color conversion layer CCL can include color conversion particles QD corresponding to a specific color. For example, the color conversion layer CCL can include color conversion particles QD that convert light of a first color emitted from the light-emitting element LD into light of a second color (light of a specific color, or light having excellent color reproducibility).

[0328] In the case where the first sub-pixel SPX1 is a red sub-pixel, the color conversion layer CCL of the first sub-pixel SPX1 can include color conversion particles QD formed of red quantum dots, and the red quantum dots convert light of a first color emitted from the light-emitting element LD into light of a second color (e.g., red light).

[0329] In the case where the first sub-pixel SPX1 is a green sub-pixel, the color conversion layer CCL of the first sub-pixel SPX1 can include color conversion particles QD formed of green quantum dots, and the green quantum dots convert light of a first color emitted from the light-emitting element LD into light of a second color (e.g., green light).

[0330] In the case where the first sub-pixel SPX1 is a blue sub-pixel, the color conversion layer CCL of the first sub-pixel SPX1 can include color conversion particles QD formed of blue quantum dots, and the blue quantum dots convert light of a first color emitted from the light-emitting element LD into light of a second color (e.g., blue light). In the case where the first sub-pixel SPX1 is a blue sub-pixel, according to an embodiment, a light-scattering layer including light-scattering particles SCT can be provided instead of the color conversion layer CCL including color conversion particles QD. For example, in the case where the light-emitting element LD emits blue-based light, the first sub-pixel SPX1 can include a light-scattering layer including light-scattering particles SCT. According to an embodiment, the light-scattering layer can be omitted. In the case where the first sub-pixel SPX1 is a blue sub-pixel, according to an embodiment, a transparent polymer can be provided instead of the color conversion layer CCL.

[0331] The first cover layer CPL1 may be disposed on the color conversion layer CCL and the second bank BNK2.

[0332] The first cover layer CPL1 may be disposed to cover the second bank BNK2 and the color conversion layer CCL over the entire surface of the first sub-pixel region SPXA1 (or display area DA) in which the first sub-pixel SPX1 is disposed.

[0333] The first cover layer CPL1 may be an inorganic insulating layer including an inorganic material. The first cover layer CPL1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), or at least one of such materials. The first cover layer CPL1 may cover the entire second bank BNK2 and the color conversion layer CCL, and thus prevent external moisture, oxygen, etc. from being introduced into the color conversion layer CCL.

[0334] In an embodiment, the first cover layer CPL1 may reduce the step difference formed by the components disposed thereunder and have a flat surface. For example, the first cover layer CPL1 may include an organic insulating layer including an organic material, but the present disclosure is not limited thereto. The first cover layer CPL1 may be a common layer commonly disposed in the display area DA.

[0335] The color filter layer CFL may be disposed on the first cover layer CPL1.

[0336] The color filter layer CFL may include a color filter CF corresponding to the first emission area EMA1. For example, the color filter layer CFL may include a first color filter CF1 disposed on the color conversion layer CCL of the first sub-pixel SPX1, a second color filter CF2 disposed on the color conversion layer CCL of the second sub-pixel SPX2, and a third color filter CF3 disposed on the color conversion layer CCL of the third sub-pixel SPX3.

[0337] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed in the non-emission area NEA and overlap each other, thereby serving as a light shielding component for preventing optical interference from occurring between adjacent sub-pixels. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a filter material that allows light of a second color converted by the corresponding color conversion layer CCL to selectively pass therethrough. For example, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter, but the present disclosure is not limited thereto.

[0338] The encapsulation layer ENC can be disposed on the color filter layer CFL.

[0339] The encapsulation layer ENC can include a second capping layer CPL2. The second capping layer CPL2 can be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The second capping layer CPL2 can cover the entirety of the components disposed thereunder and prevent external moisture, humidity, etc. from being introduced into the optical layer LCL. In an embodiment, the second capping layer CPL2 can serve as a planarization layer for reducing the step difference caused by the components of the optical layer LCL located under the second capping layer CPL2.

[0340] The second capping layer CPL2 can have a multilayer structure. For example, the second capping layer CPL2 can be formed of at least two inorganic insulating layers and at least one organic insulating layer interposed between the at least two inorganic insulating layers. Here, the constituent materials and / or structures of the second capping layer CPL2 can be changed in various ways. In some embodiments, at least one outer coating, at least one filling layer, and / or at least another substrate can also be disposed above the second capping layer CPL2.

[0341] In the first sub-pixel SPX1 according to the foregoing embodiments, the color conversion layer CCL and the color filter layer CFL can be disposed on the light-emitting element LD through a continuous process, such that light with excellent color reproducibility can be emitted through the color conversion layer CCL and the color filter layer CFL, thereby improving the light output efficiency.

[0342] In an embodiment, as Figure 26 shown, the color conversion layer CCL and the color filter layer CFL can be formed on one surface of the base layer BSL through a continuous process, thereby forming a separate substrate, such as the upper substrate U_SUB. The upper substrate U_SUB can be coupled to the substrate SUB on which the electrodes PE1 and PE2, the intermediate electrode CTE, etc. are disposed through the intermediate layer CTL. Here, the seventh insulating layer INS7 can be selectively disposed on the electrodes PE1 and PE2 and the intermediate electrode CTE. The seventh insulating layer INS7 can prevent the electrodes PE1 and PE2 and the intermediate electrode CTE from being exposed to the outside during the process of coupling the substrate SUB and the upper substrate U_SUB. The seventh insulating layer INS7 can be an inorganic insulating layer including an inorganic material, but the present disclosure is not limited thereto.

[0343] The intermediate layer CTL may be a transparent adhesive layer (or a transparent bonding layer), such as an optically transparent adhesive layer, for enhancing the adhesion between the substrate SUB and the upper substrate U_SUB, but the present disclosure is not limited thereto. In an embodiment, the intermediate layer CTL may be a refractive index conversion layer configured to change the refractive index of light emitted from the light-emitting element LD toward the upper substrate U_SUB and to increase the emission brightness of the first sub-pixel SPX1. In an embodiment, the intermediate layer CTL may include a filler formed of an insulating material having insulating properties and adhesive properties.

[0344] The upper substrate U_SUB may include a base layer BSL, a color filter layer CFL, an eighth insulating layer INS8, a color conversion layer CCL, and a ninth insulating layer INS9 stacked in a direction opposite to the third direction DR3. The upper substrate U_SUB may include a second bank BNK2 configured to surround the color conversion layer CCL.

[0345] The base layer BSL may be a rigid substrate or a flexible substrate, and there is no particular limitation on its material or properties. The base layer BSL may be formed of the same material as the substrate SUB or may be formed of a material different from the material of the substrate SUB.

[0346] The color filter layer CFL may be disposed on one surface of the base layer BSL to face the electrodes PE1 and PE2 and the intermediate electrode CTE. The first color filter CF1 of the color filter layer CFL may be disposed on one surface of the base layer BSL to correspond to the light-emitting element LD in the first emission region EMA1. The first color filter CF1, the second color filter CF2, and the third color filter CF3 of the color filter layer CFL may be disposed in the non-emission region NEA and overlap each other, thereby serving as a light-blocking component.

[0347] The eighth insulating layer INS8 may be disposed on the color filter layer CFL. The eighth insulating layer INS8 may be disposed on the color filter layer CFL and cover the color filter layer CFL to protect the color filter layer CFL. The eighth insulating layer INS8 may be an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material.

[0348] The second bank BNK2 and the color conversion layer CCL may be disposed on one surface of the eighth insulating layer INS8.

[0349] The ninth insulating layer INS9 may be disposed on the entire surface of the second bank BNK2 and the color conversion layer CCL.

[0350] The ninth insulating layer INS9 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The ninth insulating layer INS9 may be disposed on the color conversion layer CCL and protect the color conversion layer CCL from external moisture or humidity, so that the reliability of the color conversion layer CCL can be further improved.

[0351] The upper substrate U_SUB may be coupled to the substrate SUB through the intermediate layer CTL.

[0352] Although various exemplary embodiments have been described above, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope of the present disclosure.

[0353] Therefore, the embodiments disclosed in this specification are for illustrative purposes only and do not limit the technical scope of the present disclosure. The scope of the present disclosure must be defined by the appended claims.

Claims

1. Display device, comprising: a substrate including a pixel region, each of the pixel regions including a first region and a second region; and pixels disposed in each of the pixel regions, wherein the pixels include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer, stacked in sequence on the substrate; a power line disposed on the substrate; a pixel circuit component disposed in the first region and including a transistor disposed on the substrate and electrically connected to the power line; and a light emitting component disposed in the second region and including a first alignment electrode, a second alignment electrode, and a third alignment electrode disposed on the substrate at spaced positions from each other, and a light emitting element disposed between the first alignment electrode, the second alignment electrode, and the third alignment electrode, wherein at least one of the first insulating layer to the fifth insulating layer is disposed under the first alignment electrode, the second alignment electrode, and the third alignment electrode, and wherein at least one of the first insulating layer to the fifth insulating layer includes an inorganic insulating layer.

2. The display device according to claim 1, wherein, the first alignment electrode, the second alignment electrode, and the third alignment electrode are formed of a third conductive layer disposed on the third insulating layer, and wherein each of the first insulating layer, the second insulating layer, and the third insulating layer includes the inorganic insulating layer.

3. The display device according to claim 2, wherein, the power line includes a first power line and a second power line, the first power line is configured to be supplied with a voltage of a first driving power source, the second power line is configured to be supplied with a voltage of a second driving power source, and the voltage of the second driving power source is different from the voltage of the first driving power source, the first power line includes a first vertical power line, a first horizontal power line, and a first dummy power line, the first vertical power line is formed of a first conductive layer disposed on the substrate, the first horizontal power line is formed of a fourth conductive layer disposed on the fourth insulating layer, the first dummy power line is integrally formed with the first horizontal power line and extends in a direction different from that of the first horizontal power line, and the second power line includes a second vertical power line, a second horizontal power line, and a second dummy power line, the second vertical power line is formed of the first conductive layer, the second horizontal power line is formed of the fourth conductive layer, the second dummy power line is integrally formed with the second horizontal power line and extends in a direction different from that of the second horizontal power line.

4. The display device according to claim 3, wherein, the light emitting component further includes a first floating pattern spaced apart from the first alignment electrode, a second floating pattern spaced apart from the second alignment electrode, and a third floating pattern spaced apart from the third alignment electrode, and the first floating pattern is electrically connected to the first horizontal power line, and the second floating pattern and the third floating pattern are electrically connected to the second horizontal power line.

5. The display device according to claim 3, wherein, the transistor includes an active pattern disposed on the first insulating layer, a gate electrode disposed on the active pattern, a source electrode electrically connected to a first end of the active pattern, and a drain electrode electrically connected to a second end of the active pattern, and the second insulating layer is interposed between the active pattern and the gate electrode, and the gate electrode is formed of a second conductive layer disposed on the second insulating layer.

6. The display device according to claim 5, wherein, the pixel further includes: an emission region and a non-emission region, in which light is emitted from the light-emitting element in the emission region, and the non-emission region surrounds the emission region; and a first bank, disposed in the non-emission region and including an opening corresponding to the emission region, and wherein, the emission region is located in the second region.

7. The display device according to claim 6, wherein, in at least the emission region, the first conductive layer and the second conductive layer are not disposed below the first alignment electrode, the second alignment electrode, and the third alignment electrode.

8. The display device according to claim 7, wherein, in at least the emission region, the third alignment electrode, the first alignment electrode, and the second alignment electrode are arranged in a listed order in a first direction, the light-emitting element includes: a first light-emitting element, disposed between the first alignment electrode and the second alignment electrode and including a first end and a second end facing each other; and a second light-emitting element, disposed between the first alignment electrode and the third alignment electrode and including a first end and a second end facing each other.

9. The display device according to claim 8, wherein, the emission assembly further includes a first electrode, a second electrode, and an intermediate electrode, the first electrode, the second electrode, and the intermediate electrode are formed of a fifth conductive layer disposed on the fifth insulating layer and are disposed spaced apart from each other, the first electrode is disposed on a first side of the first alignment electrode and is electrically connected to the first end of the first light-emitting element, the second electrode is disposed on the third alignment electrode and is electrically connected to the second end of the second light-emitting element, and the intermediate electrode is disposed on the second alignment electrode and is electrically connected to the second end of the first light-emitting element, and is disposed on a second side of the first alignment electrode and is electrically connected to the first end of the second light-emitting element.

10. The display device according to claim 9, wherein, the pixel circuit assembly further includes a storage capacitor electrically connected to the transistor, and a connection pattern electrically connected to one electrode of the storage capacitor and formed of the fourth conductive layer, the connection pattern is located in the first region, and the first electrode extends to the first region and is electrically connected to the connection pattern through a first contact portion passing through the fifth insulating layer.

11. The display device according to claim 9, wherein, The emission assembly further includes a bridge wire, the bridge wire is disposed in the non-emission area and integrally formed with the second electrode and electrically connected to the second electrode, and the bridge wire includes a protruding portion, the protruding portion protrudes in a second direction different from the first direction, and is electrically connected to the second power line through a second contact portion passing through the fifth insulating layer.

12. The display device according to claim 9, wherein, the display device further includes a pad area, and pads electrically connected to the pixels are disposed in the pad area, the pads include a first pad electrode formed of the fourth conductive layer and a second pad electrode formed of the fifth conductive layer, and the first pad electrode and the second pad electrode are electrically connected to each other through a pad contact hole passing through the fifth insulating layer.

13. The display device according to claim 8, wherein, the pixel further includes: a second bank, disposed above the first bank in the second region; a color conversion layer, surrounded by the second bank and disposed above the light-emitting element; and a color filter, disposed on the color conversion layer.

14. The display device according to claim 3, wherein, the first vertical power line, the first horizontal power line and the first dummy power line are electrically connected to each other, and the second vertical power line, the second horizontal power line and the second dummy power line are electrically connected to each other.

15. The display device according to claim 14, wherein, the first dummy power line overlaps with the first vertical power line in a plan view, the first horizontal power line extends from the first dummy power line in a first direction, the second dummy power line overlaps with the second vertical power line in a plan view, and the second horizontal power line extends from the second dummy power line in the first direction.

16. A display device, comprising: a first sub-pixel, a second sub-pixel and a third sub-pixel, disposed adjacent to each other and each including a first region and a second region, wherein each of the first sub-pixel, the second sub-pixel and the third sub-pixel includes: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer, sequentially stacked on a substrate; power lines, disposed on the substrate, and including a first power line configured to be supplied with a voltage of a first driving power source and a second power line spaced apart from the first power line and configured to be supplied with a voltage of a second driving power source; a pixel circuit assembly, disposed in the first region, and including a transistor and a storage capacitor, the transistor is disposed on the substrate and electrically connected to the power lines, and the storage capacitor is electrically connected to the transistor; and an emission assembly, disposed in the second region, and including a first alignment electrode, a second alignment electrode and a third alignment electrode disposed on the substrate at spaced positions from each other, and a light-emitting element disposed between the first alignment electrode, the second alignment electrode and the third alignment electrode, Among them, at least one of the first insulating layer to the fifth insulating layer is disposed under the first alignment electrode, the second alignment electrode, and the third alignment electrode, and Among them, at least one of the first insulating layer to the fifth insulating layer includes an inorganic insulating layer.

17. The display device according to claim 16, Among them, The second region includes an emission region in which light is emitted from the light-emitting element, and In at least the emission region, the conductive layer is not disposed under the first alignment electrode, the second alignment electrode, and the third alignment electrode.

18. The display device according to claim 16, Among them, The light-emitting element includes: A first light-emitting element disposed between the first alignment electrode and the second alignment electrode and including a first end and a second end facing each other; and A second light-emitting element disposed between the first alignment electrode and the third alignment electrode and including a first end and a second end facing each other, and Among them, the emission assembly further includes a first electrode, a second electrode, and an intermediate electrode disposed on the fifth insulating layer and spaced apart from each other.

19. The display device according to claim 18, Among them, The emission assembly further includes a bridge wire located in the second region and electrically connected to the second electrode of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, and The bridge wire includes a protruding portion that extends from the second region to the first region and is electrically connected to the second power line.

20. A method of manufacturing a display device, including: Forming pixels on a substrate in each of the pixel regions, each of the pixel regions including a first region and a second region, Among them, forming the pixels includes: Forming a first insulating layer, a second insulating layer, and a third insulating layer on the substrate; Forming a first alignment line, a second alignment line, and a third alignment line spaced apart from each other on the third insulating layer in the second region; Forming a fourth insulating layer on the first alignment line, the second alignment line, and the third alignment line, the fourth insulating layer including contact holes, and one region of each of the first alignment line, the second alignment line, and the third alignment line being exposed through the contact holes; Forming a first horizontal power line and a second horizontal power line on the fourth insulating layer in the second region, the first horizontal power line being electrically connected to the first alignment line, and the second horizontal power line being electrically connected to the second alignment line and the third alignment line; Forming a fifth insulating layer on the first horizontal power line and the second horizontal power line; Aligning a first light-emitting element on the fifth insulating layer between the first alignment electrode and the second alignment electrode, and aligning a second light-emitting element on the fifth insulating layer between the first alignment electrode and the third alignment electrode; A first electrode is formed on a first end of the first light-emitting element, an intermediate electrode is formed on a second end of the first light-emitting element and a first end of the second light-emitting element, and a second electrode is formed on a second end of the second light-emitting element; and By removing a part of each of the first alignment line, the second alignment line, and the third alignment line in the second region, an alignment electrode and a floating pattern are formed to be spaced apart from each other, and Wherein each of the first insulating layer, the second insulating layer, and the third insulating layer located under the first alignment line, the second alignment line, and the third alignment line includes an inorganic insulating layer.

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