Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device is provided with a transistor section and a diode section, and is provided with: a plurality of trench sections provided on the front surface of a semiconductor substrate; a drift region of a first conductivity type provided on the semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a first contact region of a second conductivity type provided on a mesa portion of the transistor portion and having a doping concentration higher than that of the base region; an anode region of a second conductivity type provided above the drift region in the diode portion; and a second contact region of a second conductivity type provided on the mesa portion of the diode portion and having a higher doping concentration than the anode region. The amount per unit volume of the dopant of the second conductivity type in the mesa portion of the diode portion is equal to or greater than the amount per unit volume of the dopant of the second conductivity type in the mesa portion of the transistor portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] In Patent Document 1, a semiconductor device is described in which "holes injected from the collector layer 11 can be easily extracted from the contact layer 5".

[0003] Prior Art Documents Patent Documents Patent Document 1: Japanese Unexamined Patent Application Publication No. 2022-67972 Summary of the Invention

[0004] In a first aspect of the present invention, a semiconductor device is provided, which includes a transistor portion and a diode portion. The semiconductor device includes: a plurality of trench portions provided on the front surface of a semiconductor substrate; a drift region of a first conductivity type provided in the semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a first contact region of the second conductivity type provided on a mesa portion of the transistor portion and having a doping concentration higher than that of the base region; an anode region of the second conductivity type provided above the drift region in the diode portion; and a second contact region of the second conductivity type provided on a mesa portion of the diode portion and having a doping concentration higher than that of the anode region. The amount per unit volume of the dopant of the second conductivity type in the mesa portion of the diode portion may be equal to or more than the amount per unit volume of the dopant of the second conductivity type in the mesa portion of the transistor portion.

[0005] In the above semiconductor device, trench contact portions may be provided in the transistor portion and the diode portion.

[0006] In any of the above semiconductor devices, in the depth direction of the semiconductor substrate, the depth of the lower end of the trench contact portion may be deeper than the depth of the lower end of the emitter region.

[0007] In any of the above semiconductor devices, the first contact region may be provided at the lower end of the trench contact portion.

[0008] In any of the above semiconductor devices, the second contact region may be provided at the lower end of the trench contact portion.

[0009] In any of the above semiconductor devices, in the arrangement direction of the plurality of trench portions, the width of the trench contact portion in the diode portion may be the same as the width of the trench contact portion in the transistor portion.

[0010] In any of the above semiconductor devices, in the arrangement direction of the plurality of trench portions, the width of the trench contact portion in the diode portion may be larger than the width of the trench contact portion in the transistor portion.

[0011] In any of the above semiconductor devices, the plurality of trench portions may include a gate trench portion to which a gate potential is applied and a dummy trench portion to which a potential different from the gate potential is applied. The trench contact portion may be disposed on the mesa portion provided between the gate trench portion and the dummy trench portion so as to be closer to the dummy trench portion than the gate trench portion.

[0012] In any of the above semiconductor devices, the doping concentration of the first contact region in the transistor portion may be 1E19 cm -3 or more and 1E21 cm -3 or less.

[0013] In any of the above semiconductor devices, in the transistor portion, the first contact region may be disposed so as to extend along the extending direction of the plurality of trench portions.

[0014] In any of the above semiconductor devices, in the transistor portion, the first contact region may be disposed so as to be separated from the emitter region.

[0015] In any of the above semiconductor devices, the plurality of trench portions may include a gate trench portion to which a gate potential is applied and a dummy trench portion to which a potential different from the gate potential is applied. In the transistor portion, the first contact region may be disposed so as to be separated from the gate trench portion.

[0016] In any of the above semiconductor devices, the doping concentration of the second contact region in the diode portion may be 1E19 cm -3 or more and 1E21 cm -3 or less.

[0017] In any of the above semiconductor devices, in the diode portion, the second contact region may be disposed so as to extend along the extending direction of the plurality of trench portions.

[0018] In any of the above semiconductor devices, the plurality of trench portions may include a gate trench portion to which a gate potential is applied and a dummy trench portion to which a potential different from the gate potential is applied. In the mesa portion of the diode portion sandwiched between two of the dummy trench portions, the second contact region may be disposed to extend from the side wall of one dummy trench portion to the side wall of the other dummy trench portion.

[0019] In any of the above semiconductor devices, on the front surface of the semiconductor substrate, the emitter region and the base region may be alternately arranged in the extending direction of the plurality of trench portions.

[0020] In any of the above semiconductor devices, on the front surface of the semiconductor substrate, the emitter region may be arranged to extend in the extending direction of the plurality of trench portions.

[0021] In any of the above semiconductor devices, the doping concentration of the base region may be the same as the doping concentration of the anode region.

[0022] In any of the above semiconductor devices, a cathode region of a first conductivity type may be provided, and the cathode region of the first conductivity type is provided on the back surface of the semiconductor substrate and has a doping concentration higher than that of the drift region. The doping concentration of the cathode region may be 1E18 cm -3 or more and 1E21 cm -3 or less.

[0023] In any of the above semiconductor devices, in the transistor portion, a storage region of a first conductivity type having a doping concentration higher than that of the drift region may be provided.

[0024] In any of the above semiconductor devices, the semiconductor substrate may not have a lifetime control region.

[0025] In any of the above semiconductor devices, the transistor portion may have a main region that operates as a transistor. The main region of the transistor portion may be provided adjacent to the diode portion.

[0026] In any of the above semiconductor devices, the amount per unit volume of the dopant of the second conductivity type in the mesa portion of the diode portion may be equal to or more than the amount per unit volume of the dopant of the second conductivity type in the mesa portion of the main region.

[0027] In the second aspect of the present invention, a semiconductor device is provided, which has a transistor portion, and the semiconductor device includes: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; a first contact region of the second conductivity type provided in the mesa portion of the transistor portion and having a doping concentration higher than that of the base region; and a trench contact portion provided on the front surface of the semiconductor substrate. The first contact region may not be provided on the front surface of the semiconductor substrate.

[0028] In a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, which is a method for manufacturing a semiconductor device including a transistor portion and a diode portion. The method for manufacturing the semiconductor device includes: a step of forming a plurality of trench portions on a front surface of a semiconductor substrate; a step of forming a drift region of a first conductivity type on the semiconductor substrate; a step of forming a base region of a second conductivity type above the drift region; a step of forming an emitter region of a first conductivity type having a doping concentration higher than that of the drift region above the base region; in the diode portion, a step of forming an anode region of a second conductivity type above the drift region; a first ion implantation step of forming a first contact region of a second conductivity type having a doping concentration higher than that of the base region on a mesa portion of the transistor portion; and a second ion implantation step of forming a second contact region of a second conductivity type having a doping concentration higher than that of the anode region above the drift region in the diode portion. The amount per unit volume of the dopant of the second conductivity type in the mesa portion of the diode portion may be equal to or more than the amount per unit volume of the dopant of the second conductivity type in the mesa portion of the transistor portion.

[0029] In the above method for manufacturing a semiconductor device, the first ion implantation step and the second ion implantation step may be the same ion implantation step.

[0030] In any of the above methods for manufacturing a semiconductor device, the dose of the ions implanted in the first ion implantation step may be different from the dose of the ions implanted in the second ion implantation step.

[0031] It should be noted that the above description of the invention does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also form inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1A FIG. is an example showing an upper surface of the semiconductor device 100.

[0033] Figure 1B FIG. is an example showing an a-a' cross section of the semiconductor device 100.

[0034] Figure 1C FIG. is an example showing a b-b' cross section of the semiconductor device 100.

[0035] Figure 1D FIG. is an example showing a c-c' cross section of the semiconductor device 100.

[0036] Figure 2 FIG. is a diagram showing a modified example of the upper surface of the semiconductor device 100.

[0037] Figure 3AIt is a diagram showing a modified example of the upper surface of the semiconductor device 100.

[0038] Figure 3B It is a diagram showing an example of the d-d' cross section of the semiconductor device 100.

[0039] Figure 4 It is a diagram showing a modified example of the upper surface of the semiconductor device 100.

[0040] Figure 5A It is a diagram showing the relationship between the doping concentration of the cathode region 82 and the forward voltage Vf of the diode section 80.

[0041] Figure 5B It is a diagram showing the relationship between the forward voltage Vf of the diode section 80 and the reverse recovery loss Err.

[0042] Figure 6 It is a flowchart showing an example of the manufacturing method of the semiconductor device 100.

[0043] Symbol Explanation 10... Semiconductor substrate, 12... Emitter region, 14... Base region, 16... Accumulation region, 17... Well region, 18... Drift region, 19... Anode region, 20... Buffer region, 21... Front surface, 22... Collector region, 23... Back surface, 24... Collector electrode, 25... Connection portion, 30...Dummy trench portion, 31... Extension portion, 32... Dummy insulating film, 33... Connection portion, 34... Dummy conductive portion, 38... Interlayer insulating film, 40... Gate trench portion, 41... Extension portion, 42... Gate insulating film, 43... Connection portion, 44... Gate conductive portion, 50... Gate metal layer, 52... Emitter electrode, 54... Contact hole, 55... Contact hole, 56... Contact hole, 60... Trench contact portion, 70... Transistor portion, 71... Terrace portion, 73... First contact region, 75... Main region, 80... Diode portion, 81... Terrace portion, 82... Cathode region, 83... Second contact region, 181... First cathode portion, 182... Second cathode portion, 100... Semiconductor device Detailed Embodiments

[0044] Hereinafter, the present invention will be described by way of embodiments of the invention. However, the following embodiments do not limit the invention described in the claims. In addition, all combinations of the features described in the embodiments are not necessarily essential for the technical solution of the invention.

[0045] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other is referred to as the lower surface. The directions of "upper", "lower", "front", and "back" are not limited to the direction of gravity or the mounting direction toward the substrate when mounting the semiconductor device.

[0046] In this specification, orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis are sometimes used to explain technical matters. The orthogonal coordinate axes only determine the relative positions of the components and do not limit a specific direction. For example, the Z-axis is not limited to representing the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the Z-axis direction is described without indicating positive or negative, it refers to the direction parallel to the +Z-axis and the -Z-axis.

[0047] In this specification, the plane parallel to the upper surface of the semiconductor substrate is set as the XY plane, and the orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are set as the X-axis and the Y-axis. In addition, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is set as the Z-axis. Sometimes the depth direction of the semiconductor substrate is referred to as the Z-axis. It should be noted that in this specification, observing the semiconductor substrate along the Z-axis direction is referred to as a top view. In addition, in this specification, sometimes the direction including the X-axis and the Y-axis and parallel to the upper surface and the lower surface of the semiconductor substrate is referred to as the horizontal direction.

[0048] In each embodiment, an example is shown in which the first conductivity type is N-type and the second conductivity type is P-type. However, the first conductivity type can also be P-type and the second conductivity type can be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment become opposite polarities.

[0049] In this specification, when described as "the same" or "equal", it may also include cases with errors caused by manufacturing deviations, etc. Such an error is, for example, within 10%.

[0050] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, impurities sometimes particularly refer to either an N-type donor or a P-type acceptor, and are sometimes referred to as dopants. In this specification, doping means introducing a donor or an acceptor into the semiconductor substrate to form a semiconductor with an N-type conductivity type or a semiconductor with a P-type conductivity type.

[0051] In this specification, the doping concentration refers to the concentration of donors or acceptors in the thermal equilibrium state.

[0052] When denoted as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of P type or N type. When denoted as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. In addition, when denoted as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0053] Figure 1A An example of the upper surface of the semiconductor device 100 is shown. The semiconductor device 100 in this example is a semiconductor chip including a transistor portion 70 and a diode portion 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT: ReverseConducting IGBT). The transistor portion 70 may include a boundary region in a portion adjacent to the diode portion 80. The transistor portion 70 in this example does not include a boundary region.

[0054] On the front surface 21 of the semiconductor substrate 10, a plurality of trench portions extending along a predetermined direction (in this example, the Y-axis direction) and arranged in a predetermined direction (in this example, the X-axis direction) are provided. The front surface 21 will be described later. The plurality of trench portions include gate trench portions 40 to which a gate potential is applied and dummy trench portions 30 to which a potential different from the gate potential is applied.

[0055] The transistor portion 70 is a region obtained by projecting a collector region 22 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 has a second conductivity type. As an example, the collector region 22 in this example is P+ type. The transistor portion 70 includes transistors such as IGBTs. The transistor portion 70 in this example includes a main region 75.

[0056] The main region 75 is a region that forms a channel region during the operation of the semiconductor device 100 and operates as a transistor. The main region 75 may be a region in the transistor portion 70 other than the boundary region. Since the transistor portion 70 in this example does not have a boundary region, the transistor portion 70 coincides with the main region 75. That is, the main region 75 of the transistor portion 70 is provided adjacent to the diode portion 80.

[0057] The diode portion 80 is a region obtained by projecting a cathode region 82 provided on the back surface of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. As an example, the cathode region 82 in this example is N+ type. The diode portion 80 includes diodes such as a free wheel diode (FWD) provided adjacent to the transistor portion 70 on the upper surface of the semiconductor substrate 10.

[0058] In the transistor section 70, an anode region 19 can be formed on the front surface. In the diode section 80, an emitter region 12 and a base region 14 can be formed on the front surface. In the trench arrangement direction of the plurality of trench sections (the X-axis direction in this example), the distance between the boundary of the region where the emitter region 12 or the base region 14 is provided and the region where the anode region 19 is provided, and the boundary between the collector region 22 and the cathode region 82 can be 0 μm or more and 10 μm or less. In this example, this distance is 0 μm.

[0059] In Figure 1A shows the region around the chip end portion on the edge side of the semiconductor device 100, and other regions are omitted. For example, an edge termination structure portion can be provided in the region on the negative side of the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure portion alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion has, for example, a guard ring, a field plate, a structure for reducing the surface electric field, and a structure formed by combining these. It should be noted that, for convenience, the edge on the negative side of the Y-axis direction is described in this example, and the same applies to other edges of the semiconductor device 100. The edge termination structure portion can be provided to surround the active region including the transistor section 70 and the diode section 80.

[0060] The semiconductor substrate 10 can be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate.

[0061] The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, an emitter region 12, a base region 14, a well region 17, and an anode region 19 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example includes a first contact region 73 provided on the mesa surface 71 of the transistor section 70 and a second contact region 83 provided on the mesa surface 81 of the diode section 80. In addition, the semiconductor device 100 in this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0062] The emitter electrode 52 is provided above the gate trench section 40, the dummy trench section 30, the emitter region 12, the base region 14, the well region 17, and the anode region 19. In addition, the gate metal layer 50 is provided above the gate trench section 40 and the well region 17.

[0063] The emission electrode 52 and the gate metal layer 50 are formed of a metal-containing material. At least a part of the region of the emission electrode 52 can be formed of a metal such as aluminum (Al), or a metal alloy containing aluminum such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu), etc. At least a part of the region of the gate metal layer 50 can be formed of a metal such as aluminum (Al), or a metal alloy containing aluminum such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu), etc. The emission electrode 52 and the gate metal layer 50 can have a barrier metal formed of titanium, titanium compounds, etc. in the lower layer of the region formed of aluminum or an aluminum-containing alloy, etc. The emission electrode 52 and the gate metal layer 50 are provided in a separated manner from each other.

[0064] The emission electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 therebetween. In Figure 1A the interlayer insulating film 38 is omitted. The contact hole 54, the contact hole 55, and the contact hole 56 are provided to penetrate through the interlayer insulating film 38.

[0065] The contact hole 54 is provided to extend along the depth direction of the semiconductor substrate 10 from the upper surface of the interlayer insulating film 38. The contact hole 54 has a bottom and side portions. The contact hole 54 electrically connects the emission electrode 52 to the semiconductor substrate 10. The contact hole 54 is provided to extend along the trench extending direction. The contact hole 54 in this example is arranged in a striped pattern along the gate trench portion 40 and the dummy trench portion 30.

[0066] The contact hole 54 is provided in both the transistor portion 70 and the diode portion 80. In the transistor portion 70, the contact hole 54 is formed on the upper surfaces of the regions of the emitter region 12 and the base region 14. In the diode portion 80, the contact hole 54 is provided above the anode region 19. The contact hole 54 is not provided above the well regions 17 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 can be provided to extend along the extending direction. A trench contact portion 60 can be provided in the contact hole 54. That is, the trench contact portion 60 can be provided in both the transistor portion 70 and the diode portion 80. The trench contact portion 60 will be described later.

[0067] The contact hole 55 connects the gate metal layer 50 to the gate conductive portion within the transistor portion 70. A plug formed of tungsten or the like can be formed inside the contact hole 55 with a barrier metal therebetween.

[0068] The contact hole 56 connects the emission electrode 52 to the dummy conductive portion within the dummy trench portion 30. A plug formed of tungsten or the like can be formed inside the contact hole 56 with a barrier metal therebetween.

[0069] The connection portion 25 electrically connects the front side electrode such as the emitter electrode 52 or the gate metal layer 50 to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with impurities. The connection portion 25 of this example is polysilicon doped with N-type impurities (N+). The connection portion 25 is provided above the front side 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0070] The gate groove portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate groove portions 40 of this example may include two extension portions 41 extending parallel to the front surface 21 of the semiconductor substrate 10 and along an extension direction perpendicular to the arrangement direction (in this example, the Y-axis direction), and a connection portion 43 connecting the two extension portions 41.

[0071] At least a portion of the connection portion 43 may be formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, the electric field concentration at the ends of the extension portions 41 can be alleviated. In the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0072] The dummy groove portion 30 is a groove portion electrically connected to the emitter electrode 52. The dummy groove portion 30 is arranged at a predetermined interval along a predetermined arrangement direction (in this example, the X-axis direction) similarly to the gate groove portion 40. The dummy groove portion 30 of this example may have a U-shape on the front surface 21 of the semiconductor substrate 10 similarly to the gate groove portion 40. That is, the dummy groove portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.

[0073] The main region 75 in the transistor section 70 of this example has a structure in which one gate trench section 40 and one dummy trench section 30 are repeatedly arranged. That is, the transistor section 70 of this example has the gate trench section 40 and the dummy trench section 30 at a ratio of 1:1. For example, the transistor section 70 has one extension section 31 between two extension sections 41. In addition, the transistor section 70 has one extension section 41 between two extension sections 31.

[0074] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 2:3 or 2:4. In addition, the transistor portion 70 may have all trench portions as gate trench portions 40 without having dummy trench portions 30.

[0075] The mesa portion 71 is a mesa portion provided adjacent to the trench portion within a plane of the semiconductor substrate 10 parallel to the front surface 21. The mesa portion refers to a portion of the semiconductor substrate 10 clamped by two adjacent trench portions, and may be a portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. The extended portions of each trench portion can be set as one trench portion. That is, the region clamped by the two extended portions can be set as the mesa portion.

[0076] In the transistor portion 70, the mesa portion 71 is provided adjacent to at least one of the dummy trench portion 30 and the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, and a base region 14 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, on the front surface 21 of the semiconductor substrate 10, the emitter region 12 and the base region 14 are alternately provided in the extending direction of the trench portion (in the Y-axis direction in this example).

[0077] The base region 14 is a region of the second conductivity type provided above the drift region 18 described later. As an example, the base region 14 is P-type. On the front surface 21 of the semiconductor substrate 10, the base region 14 can be provided at both end portions in the Y-axis direction of the mesa portion 71. In Figure 1A only one end portion in the Y-axis direction of the base region 14 is shown.

[0078] The emitter region 12 is a region of the first conductivity type provided above the base region 14 and having a doping concentration higher than that of the drift region 18. As an example, the emitter region 12 in this example is N+-type. An example of the dopant of the emitter region 12 is arsenic (As). On the front surface 21 of the mesa portion 71, the emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 can be provided to extend from one trench portion clamping the mesa portion 71 to the other trench portion in the X-axis direction.

[0079] In addition, the emitter region 12 can be in contact with the dummy trench portion 30 or can be not in contact with the dummy trench portion 30. The emitter region 12 in this example is in contact with the dummy trench portion 30.

[0080] In the diode portion 80, the mesa portion 81 is provided in the region clamped by the adjacent dummy trench portions 30. On the front surface 21 of the semiconductor substrate 10, the mesa portion 81 has an anode region 19. The mesa portion 81 in this example has the anode region 19, the base region 14, and the well region 17 on the negative side in the Y-axis direction.

[0081] The anode region 19 is a region of the second conductivity type provided above the drift region 18. The doping concentration of the anode region 19 can be the same as that of the base region 14 or can be larger than the doping concentration of the base region 14. The doping concentration of the anode region 19 in this example is the same as that of the base region 14. As an example, the anode region 19 in this example is P-type.

[0082] In this example, the anode region 19 is provided on the front surface 21 of the stage surface portion 81. The anode region 19 can be provided from one of the two dummy groove portions 30 that sandwich the stage surface portion 81 to the other dummy groove portion in the X-axis direction. The anode region 19 can be in contact with the dummy groove portion 30 or not in contact with the dummy groove portion 30. In this example, the anode region 19 is in contact with the dummy groove portion 30.

[0083] The doping concentration of the anode region 19 in this example can be 1E16 cm -3 or more, and can also be 1E18 cm -3 or less. It should be noted that E refers to the power of 10. For example, 1E18 cm -3 refers to 1×10 18 cm -3 . The anode region 19 can have a peak in the doping concentration in the depth direction of the semiconductor substrate 10. In addition, in the depth direction of the semiconductor substrate 10, the depth of the lower end of the anode region 19 can be the same as the depth of the lower end of the base region 14, or the lower end of the anode region 19 can be located at a position deeper than the lower end of the base region 14.

[0084] The first contact region 73 is a region of the second conductivity type with a doping concentration higher than that of the base region 14. As an example, the first contact region 73 in this example is of the P++ type. The doping concentration of the first contact region 73 in the transistor portion 70 can be 1E19 cm -3 or more, and can also be 1E21 cm -3 or less.

[0085] In the transistor portion 70, the first contact region 73 can be arranged to extend in the extending direction of the plurality of groove portions. In this example, the first contact region 73 is arranged to extend along the emitter region 12 and the base region 14 alternately provided on the front surface 21 of the semiconductor substrate 10.

[0086] The second contact region 83 is a region of the second conductivity type with a doping concentration higher than that of the anode region 19. As an example, the second contact region 83 in this example is of the P++ type. The doping concentration of the second contact region 83 can be the same as or different from that of the first contact region. The doping concentration of the second contact region 83 can be higher than that of the first contact region 73. The doping concentration of the second contact region 83 in the diode portion 80 can be 1E19 cm -3 or more, and can also be 1E21 cm -3 or less.

[0087] In the diode portion 80, the second contact region 83 can be arranged to extend in the extending direction of the plurality of groove portions. In this example, the second contact region 83 is arranged corresponding to the extending direction of the first contact region 73.

[0088] Figure 1B is Figure 1A an example of the a-a' cross-section. The a-a' cross-section is the XZ plane passing through the emitter region 12 in the transistor portion 70. The semiconductor device 100 of this example has a semiconductor substrate 10 provided with an emitter region 12, a base region 14, a storage region 16, a drift region 18, a buffer region 20, a first contact region 73, and a second contact region 83 in the a-a' cross-section, as well as an interlayer insulating film 38, a trench contact portion 60, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0089] The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. As an example, the drift region 18 of this example is an N-type. The drift region 18 may be a region remaining without forming other doped regions in the semiconductor substrate 10. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0090] A buffer region 20 of the first conductivity type may be provided below the drift region 18. The buffer region 20 of this example is an N-type. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may be a field stop layer that prevents the depletion layer diffusing from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0091] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal.

[0092] The base region 14 is a region of the second conductivity type provided above the drift region 18. The doping concentration of the base region 14 may be the same as or different from the doping concentration of the anode region 19. The doping concentration of the base region 14 may be 1E16 cm -3 or more and 1E18 cm -3 or less. The base region 14 may be provided below the emitter region 12. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0093] The storage region 16 is a region of the first conductivity type provided at a position deeper than the base region 14 in the depth direction of the semiconductor substrate 10 and having a doping concentration higher than that of the drift region 18. As an example, the storage region 16 of this example is an N+-type. The storage region 16 is provided in the main region 75 of the transistor portion 70 and is not provided in the diode portion 80. By providing the first storage region 16, the carrier injection enhancement effect (IE effect) can be improved, and the on-voltage of the transistor portion 70 can be reduced.

[0094] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In a region where at least any one of the emitter region 12, the base region 14, the accumulation region 16, and the anode region 19 is provided, each trench portion also penetrates these regions and reaches the drift region 18. The case where the trench portion penetrates the doped region is not limited to the manufacturing order of forming the trench portion after forming the doped region. A method of forming a doped region between the trench portions after forming the trench portions is also included in the method of the trench portion penetrating the doped region.

[0095] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed so as to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position closer to the inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered with an interlayer insulating film 38 on the front surface 21.

[0096] The gate conductive portion 44 includes a region facing the base region 14 adjacent to the mesa portion 71 side across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. If a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed on the surface layer of the interface in contact with the gate trench in the base region 14.

[0097] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench formed on the front surface 21 side, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed so as to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and at a position closer to the inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered with an interlayer insulating film 38 on the front surface 21.

[0098] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more trench contact portions 60 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10 are provided in the interlayer insulating film 38. The contact holes 55 and 56 may also be provided to penetrate the interlayer insulating film 38 in the same manner as the trench contact portions 60.

[0099] The trench contact portion 60 penetrates through the interlayer insulating film 38 and the emitter region 12 to reach the base region 14 or the anode region 19. The trench contact portion 60 electrically connects the emitter electrode 52 to the semiconductor substrate 10. In this example, the depth of the lower end of the trench contact portion 60 is deeper than the depth of the lower end of the emitter region 12 in the depth direction of the semiconductor substrate 10. Thereby, the latch-up tolerance of the semiconductor device 100 can be improved.

[0100] The first contact region 73 is provided at the lower end of the trench contact portion 60. The first contact region 73 may be provided to cover the bottom and a part of the side wall of the trench contact portion 60. In the transistor portion 70, the first contact region 73 is provided so as to be separated from the emitter region 12. In the transistor portion 70, the first contact region 73 is provided so as to be separated from the gate trench portion 40.

[0101] In one example, the first contact region 73 is formed by implanting dopants via the trench contact portion 60. The trench contact portion 60 may also be provided after the first contact region 73 is formed first. By providing the first contact region 73, the resistance of the bottom of the trench contact portion 60 in the transistor portion 70 can be reduced, and latch-up breakdown can be suppressed.

[0102] The second contact region 83 is provided at the lower end of the trench contact portion 60. The second contact region 83 may be provided to cover the bottom and a part of the side wall of the trench contact portion 60. In one example, the second contact region 83 is formed by implanting dopants via the trench contact portion 60. The trench contact portion 60 may also be provided after the second contact region 83 is formed first.

[0103] The doping concentration of the second contact region 83 may be the same as or different from the doping concentration of the first contact region 73. In this example, the doping concentration of the second contact region 83 is greater than the doping concentration of the first contact region 73.

[0104] The amount of the dopant of the second conductivity type per unit volume in the mesa portion 81 of the diode portion 80 may be the same as or different from the amount of the dopant of the second conductivity type per unit volume in the mesa portion 71 of the transistor portion 70. In the present specification, the amount of the dopant of the second conductivity type per unit volume in the mesa portion 71 of the transistor portion 70 may be the amount obtained by dividing the total amount of the dopants contained in the base region 14 and the first contact region 73 by the volume of the mesa portion 71. In the present specification, the amount of the dopant of the second conductivity type per unit volume in the mesa portion 81 of the diode portion 80 may be the amount obtained by dividing the total amount of the dopants contained in the anode region 19 and the second contact region 83 by the volume of the mesa portion 81. In this example, the amount of the dopant of the second conductivity type per unit volume in the mesa portion 81 of the diode portion 80 is greater than the amount of the dopant of the second conductivity type per unit volume in the mesa portion 71 of the transistor portion 70. Thereby, injection of holes from the transistor portion 70 into the diode portion 80 can be suppressed, and the reverse recovery loss Err can be reduced.

[0105] The amount of the dopant of the second conductivity type per unit volume in the mesa portion 81 of the diode portion 80 may be the same as or different from the amount of the dopant of the second conductivity type per unit volume in the mesa portion 71 of the main region 75. In this example, the amount of the dopant of the second conductivity type per unit volume in the mesa portion 81 of the diode portion 80 is greater than the amount of the dopant of the second conductivity type per unit volume in the mesa portion 71 of the main region 75.

[0106] In the transistor portion 70, the collector region 22 is provided on the back surface 23 of the semiconductor substrate 10. The collector region 22 is a region of the second conductivity type having a doping concentration higher than that of the base region 14.

[0107] In the diode portion 80, the cathode region 82 is provided on the back surface 23 of the semiconductor substrate 10. The cathode region 82 is a region of the first conductivity type having a doping concentration higher than that of the drift region 18. The doping concentration of the cathode region may be 1E18 cm -3 or more, and may also be 1E21 cm -3 or less.

[0108] The doping concentration of the cathode region 82 can be changed corresponding to the amount of the dopant of the second conductivity type per unit volume in the mesa portion 71 of the transistor portion 70 and the amount of the dopant of the second conductivity type per unit volume in the mesa portion 81 of the diode portion 80. Thereby, the trade-off between the forward voltage Vf and the reverse recovery loss Err in the diode portion 80 can be improved. Details will be described later.

[0109] The semiconductor device 100 of this example does not have a lifetime control region inside the semiconductor substrate 10. Thereby, it is not necessary to additionally inject ions or the like for forming the lifetime control region, and the cost can be reduced.

[0110] Figure 1C is Figure 1A An example of the b-b' cross-section. The b-b' cross-section is the YZ plane along the trench contact portion 60 in the transistor portion 70.

[0111] The first contact region 73 is arranged to extend in the extending direction of the trench contact portion 60. The first contact region 73 can cover the bottom and a part of the side wall of the trench contact portion 60. The first contact region 73 can cover the side wall of the trench contact portion 60 at the end in the trench extending direction (the Y-axis direction in this example).

[0112] The well region 17 is a region of the second conductivity type provided closer to the front surface 21 side of the semiconductor substrate 10 than the drift region 18. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. As an example, the well region 17 is of P+ type.

[0113] The well region 17 is formed within a predetermined range starting from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 can be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. A part of the regions of the gate trench portion 40 and the dummy trench portion 30 closer to the gate metal layer 50 side are formed within the well region 17. The bottom of the end in the extending direction of the gate trench portion 40 and the dummy trench portion 30 can be covered by the well region 17.

[0114] Figure 1D is Figure 1A An example of the c-c' cross-section. The c-c' cross-section is the YZ plane along the trench contact portion 60 in the diode portion 80.

[0115] The second contact region 83 is arranged to extend in the extending direction of the trench contact portion 60. The second contact region 83 can cover the bottom and a part of the side wall of the trench contact portion 60. The second contact region 83 can also be arranged discretely in the extending direction of the trench contact portion 60. The second contact region 83 can cover the side wall of the trench contact portion 60 at the end in the trench extending direction (the Y-axis direction in this example).

[0116] The first cathode portion 181 is a region of the first conductivity type with a doping concentration higher than that of the drift region 18. In one example, the first cathode portion 181 is of N type. The width of the first cathode portion 181 in the trench extending direction (the Y-axis direction) can be greater than the width of the second cathode portion 182 in the trench extending direction.

[0117] The second cathode portion 182 is a region of the second conductivity type provided adjacent to the first cathode portion 181 on the back surface 23 of the semiconductor substrate 10. That is, the second cathode portion 182 can be in direct contact with the first cathode portion 181. In one example, the second cathode portion 182 is of P type.

[0118] After P-type dopant is ion-implanted through the ion implantation process for forming the second cathode portion 182, the first cathode portion 181 can be formed by ion-implanting N-type dopant. Conversely, after N-type dopant is ion-implanted through the ion implantation process for forming the first cathode portion 181, the second cathode portion 182 can be formed by ion-implanting P-type dopant.

[0119] The first cathode portion 181 and the second cathode portion 182 are arranged in such a way as to form a boundary in contact with each other. The first cathode portion 181 and the second cathode portion 182 can be alternately arranged in any direction. The first cathode portion 181 and the second cathode portion 182 in this example can be alternately arranged in the trench extension direction (for example, the Y-axis direction) or alternately arranged in the trench arrangement direction (for example, the X-axis direction). The first cathode portion 181 and the second cathode portion 182 can be arranged in a striped pattern when viewed from above. One of the first cathode portion 181 and the second cathode portion 182 can also be formed in a dot shape.

[0120] In the cathode region 82 of the diode portion 80 in this example, the second cathode portion 182 can be provided. In the cathode region 82 of the diode portion 80 in this example, the first cathode portion 181 and the second cathode portion 182 can be alternately provided. In the cathode region 82 of the diode portion 80 in this example, it can be set such that the first cathode portion 181 is in contact with the second cathode portion 182. Thereby, the concentration of the dopant of the first conductivity type in the cathode region 82 can be reduced, and the forward voltage Vf of the diode portion 80 can be increased.

[0121] Figure 2 It is a diagram showing a modified example of the upper surface of the semiconductor device 100. Use Figure 2 To illustrate points different from Figure 1A the above.

[0122] In Figure 2 the modified example shown, on the front surface 21 of the semiconductor substrate 10, the emission region 12 is provided to extend in the extension direction of a plurality of trench portions. The emission region 12 can be provided to extend in the Y-axis direction from one base region 14 adjacent to the well region 17 to another base region 14. Thereby, the amount per unit volume of the dopant of the second conductivity type in the transistor portion 70 can be reduced, the amount of hole injection from the transistor portion 70 to the diode portion 80 can be reduced, and the forward voltage Vf of the diode portion 80 can be reduced.

[0123] In Figure 2In the illustrated modified example, the doping concentration of the anode region 19 is higher than that of the base region 14. In the modified example, the anode region 19 is of P type. As a result, the amount of hole injection from the front surface 21 toward the back surface 23 in the diode section 80 becomes larger than the amount of hole injection from the transistor section 70 into the diode section 80, and the forward voltage Vf of the diode section 80 can be reduced.

[0124] Figure 3A FIG. is a diagram showing a modified example of the upper surface of the semiconductor device 100. Use Figure 3A to illustrate the points Figure 1A different from

[0125] The width in the trench arrangement direction of the contact hole 54a in the transistor section 70 and the width in the trench arrangement direction of the contact hole 54b in the diode section 80 may be the same or different. The width in the trench arrangement direction of the trench contact portion 60a in the transistor section 70 and the width in the trench arrangement direction of the trench contact portion 60b in the diode section 80 may be the same or different. In one example, in the arrangement direction of the trench portion, the width of the trench contact portion 60b in the diode section 80 is the same as the width of the trench contact portion 60a in the transistor section 70. In Figure 3A the example of

[0126] The trench contact portion 60 may be provided on the mesa portion provided between the gate trench portion 40 and the dummy trench portion 30 so as to be closer to the dummy trench portion 30 than the gate trench portion 40. In this example, the trench contact portion 60a in the transistor section 70 is provided so as to be closer to the dummy trench portion 30 than the gate trench portion 40.

[0127] In the transistor section 70, an emitter region 12 may not be provided between the trench contact portion 60a and the dummy trench portion 30. In this example, a base region 14 is provided between the trench contact portion 60a and the dummy trench portion 30.

[0128] Figure 3B is Figure 3A an example of the d-d' cross section in Figure 3B Use Figure 1B to illustrate the points

[0129] In the arrangement direction of the trench portions, the width of the trench contact portion 60 in the diode portion 80 may be greater than the width of the trench contact portion 60a in the transistor portion 70. The width of the trench contact portion 60 may be the opening width at the upper end of the interlayer insulating film 38, may be the width of the bottom of the trench contact portion 60, or may be the width at the same depth as the front surface 21 of the semiconductor substrate 10. In this example, the width W60b of the trench contact portion 60b in the diode portion 80 is greater than the width W60a of the trench contact portion 60a in the transistor portion 70. Thus, when forming the first contact region 73 and the second contact region 83, since more dopants are injected through the trench contact portion 60b with a wider width than through the trench contact portion 60a with a narrower width, the doping concentration of the second contact region 83 can be made greater than the doping concentration of the first contact region 73.

[0130] In the mesa portion provided between the gate trench portion 40 and the dummy trench portion 30, the trench contact portion 60a in the transistor portion 70 may be arranged closer to the dummy trench portion 30 than the gate trench portion 40. In this example, in the mesa portion 71, the distance D1 between the center of the trench contact portion 60a and the gate trench portion 40 is greater than the distance D2 between the center of the trench contact portion 60a and the dummy trench portion 30. Thus, the first contact region 73 can be arranged so as to be separated from the gate trench portion 40, and the deviation of the threshold value generated by the contact between the low-concentration portion of the first contact region 73 formed by the diffusion of the first contact region 73 in the trench arrangement direction (X-axis direction) and the side wall of the gate trench portion 40 can be reduced.

[0131] In the diode portion 80, the second contact region 83 may be arranged to contact the dummy trench portion 30. In this example, in the mesa portion 81 of the diode portion 80 sandwiched by two dummy trench portions 30, the second contact region 83 is arranged to extend from the side wall of one dummy trench portion 30 to the side wall of the other dummy trench portion 30. Thus, the amount per unit volume of the dopants of the second conductivity type in the diode portion 80 can be made greater than the amount per unit volume of the dopants of the second conductivity type in the transistor portion 70.

[0132] Figure 4 FIG. is a diagram showing a modification of the upper surface of the semiconductor device 100. The semiconductor device 100 has a transistor portion. The semiconductor device 100 includes a drift region 18, a base region 14, an emitter region 12, a first contact region 73, and a trench contact portion 60. Since the structures of these respective regions are the same as those of the semiconductor device 100 described above, they are omitted.

[0133] In Figure 4In the semiconductor device 100 shown, a first contact region 73 is not provided on the front surface 21. On the front surface 21 of the semiconductor device 100, an emitter region 12 and a base region 14 are alternately provided in the trench extending direction.

[0134] Figure 5A It is a graph showing the relationship between the doping concentration of the cathode region 82 and the forward voltage Vf of the diode portion 80. The horizontal axis is the doping concentration of the cathode region 82, and the vertical axis is the forward voltage Vf of the diode portion 80. It is plotted by changing the amount per unit volume of the dopant of the second conductivity type in the mesa portion 81 of the diode portion 80. Each value is normalized.

[0135] In Examples 1 to 3, the amount per unit volume of the dopant of the second conductivity type in the mesa portion 81 of the diode portion 80 is different. The doping concentration Qp1 of the dopant of the second conductivity type in Example 1 represented by a quadrilateral is less than the doping concentration Qp2 of Example 2 represented by a circle. The doping concentration Qp2 of Example 2 is less than the doping concentration Qp3 of Example 3 represented by a triangle. If the amount per unit volume of the dopant of the second conductivity type in the mesa portion 81 of the diode portion 80 increases, the forward voltage Vf of the diode portion 80 decreases.

[0136] If the doping concentration of the cathode region 82 is decreased, the forward voltage Vf of the diode portion 80 increases. As an example, by providing a second cathode portion 182 in the cathode region 82, the forward voltage Vf of the diode portion 80 can be increased. Thus, by adjusting the amount per unit volume of the dopant of the second conductivity type in the mesa portion 81 of the diode portion 80 and the doping concentration of the cathode region 82, the value of the forward voltage Vf of the diode portion 80 can be adjusted.

[0137] Figure 5B It is a graph showing the relationship between the forward voltage Vf of the diode portion 80 and the reverse recovery loss Err. The horizontal axis is the forward voltage Vf of the diode portion 80, and the vertical axis is the reverse recovery loss Err. It is plotted by changing the amount per unit volume of the dopant of the second conductivity type in the mesa portion 81 of the diode portion 80. Each value is normalized.

[0138] For each of Examples 1, 2, and 3, the relationship of the amount per unit volume of the dopant of the second conductivity type in the mesa portion 81 of the diode portion 80 is as described above. If the amount per unit volume of the dopant of the second conductivity type in the mesa portion 81 of the diode portion 80 increases, the forward voltage Vf of the diode portion 80 decreases and the reverse recovery loss Err increases. Thus, by adjusting the amount per unit volume of the dopant of the second conductivity type in the mesa portion 81 of the diode portion 80 and the doping concentration of the cathode region 82, the relationship between the forward voltage Vf and the reverse recovery loss Err can be adjusted.

[0139] Figure 6 It is a flowchart showing an example of a manufacturing method of the semiconductor device 100. The manufacturing method of the semiconductor device 100 in this example has: a step S100 of forming a plurality of trench portions in the semiconductor substrate 10; a step S110 of forming a drift region 18 in the semiconductor substrate 10; a step S120 of forming a base region 14, an emitter region 12, and an anode region 19; a first ion implantation step S130 of forming a first contact region 73; and a second ion implantation step S140 of forming a second contact region 83. Among them, since the step S100 of forming a plurality of trench portions in the semiconductor substrate 10, the step S110 of forming a drift region 18 in the semiconductor substrate 10, and the step S120 of forming a base region 14, an emitter region 12, and an anode region 19 are contents that can be understood by those having ordinary knowledge, the description thereof is omitted.

[0140] The dose of ions implanted in the first ion implantation step S130 can be different from the dose of ions implanted in the second ion implantation step S140. The first ion implantation step S130 and the second ion implantation step S140 can be performed at different times using different masks. In this example, the dose of the dopant of the second conductivity type implanted in the second ion implantation step S140 is larger than the dose of the dopant of the second conductivity type implanted in the first ion implantation step S130. Thereby, the amount per unit volume of the dopant of the second conductivity type in the diode portion 80 can be made larger than the amount per unit volume of the dopant of the second conductivity type in the transistor portion 70.

[0141] The first ion implantation step S130 and the second ion implantation step S140 can be the same ion implantation step. The first ion implantation step S130 and the second ion implantation step S140 can be performed simultaneously using the same mask. The first contact region 73 and the second contact region 83 can be formed simultaneously using the same mask, or can be formed at different times using the same mask.

[0142] As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious that various changes or improvements can be made to the above embodiments by those skilled in the art. It can be clearly understood from the description of the claims that the embodiments with such changes or improvements can also be included in the technical scope of the present invention.

[0143] It should be noted that, as long as there is no specific indication such as "before...", "prior to...", etc., and as long as the output of the previous process is not used in the subsequent process, the execution order of each process such as the actions, sequences, steps, stages, etc. in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order. Regarding the action flow in the claims, specification, and drawings, even if descriptions such as "first," "next," etc. are used for convenience, it does not mean that it must be implemented in that order.

Claims

1. A semiconductor device, characterized in that: A semiconductor device including a transistor portion and a diode portion includes: A plurality of groove portions are provided on the front surface of the semiconductor substrate; A drift region of a first conductivity type, which is disposed on the semiconductor substrate; A base region of a second conductivity type, which is arranged above the drift region; An emitter region of a first conductivity type, which is disposed above the base region and has a doping concentration higher than that of the drift region; A first contact region of a second conductivity type, which is disposed in a mesa portion of the transistor portion and has a doping concentration higher than that of the base region; an anode region of a second conductivity type, which is disposed above the drift region in the diode portion; as well as a second contact region of a second conductivity type, which is provided in the mesa portion of the diode portion and has a doping concentration higher than that of the anode region; An amount per unit volume of the second conductivity type dopant in the mesa portion of the diode portion is greater than or equal to an amount per unit volume of the second conductivity type dopant in the mesa portion of the transistor portion.

2. The semiconductor device according to claim 1, wherein: The transistor portion and the diode portion include trench contacts.

3. The semiconductor device according to claim 2, wherein: In a depth direction of the semiconductor substrate, a depth of a lower end of the trench contact portion is deeper than a depth of a lower end of the emitter region.

4. The semiconductor device according to claim 2, wherein: The first contact region is disposed at a lower end of the trench contact portion.

5. The semiconductor device according to claim 2, wherein: The second contact region is disposed at a lower end of the trench contact portion.

6. The semiconductor device according to claim 2, wherein: In the arrangement direction of the plurality of trench portions, a width of the trench contact portion in the diode portion is the same as a width of the trench contact portion in the transistor portion.

7. The semiconductor device according to claim 2, wherein: In the arrangement direction of the plurality of trench portions, a width of the trench contact portion in the diode portion is greater than a width of the trench contact portion in the transistor portion.

8. The semiconductor device according to claim 2, wherein: The plurality of trench portions include a gate trench portion to which a gate potential is applied, and a dummy trench portion to which a potential different from the gate potential is applied, The trench contact portion is provided in a mesa portion provided between the gate trench portion and the dummy trench portion so as to be closer to the dummy trench portion than to the gate trench portion.

9. The semiconductor device according to claim 1, wherein: The doping concentration of the first contact region in the transistor portion is 1E19 cm -3 Above and 1E21cm -3 the following.

10. The semiconductor device according to claim 1, wherein: In the transistor portion, the first contact region is provided so as to extend along an extending direction of the plurality of trench portions.

11. The semiconductor device according to claim 1, wherein: In the transistor portion, the first contact region is provided in a manner separated from the emitter region.

12. The semiconductor device according to claim 1, wherein: The plurality of trench portions include a gate trench portion to which a gate potential is applied, and a dummy trench portion to which a potential different from the gate potential is applied, In the transistor portion, the first contact region is provided in a manner separated from the gate trench portion.

13. The semiconductor device according to claim 1, wherein: The doping concentration of the second contact region in the diode portion is 1E19 cm -3 Above and 1E21cm -3 the following.

14. The semiconductor device according to claim 1, wherein: In the diode portion, the second contact region is provided so as to extend along an extending direction of the plurality of trench portions.

15. The semiconductor device according to claim 1, wherein: The plurality of trench portions include a gate trench portion to which a gate potential is applied, and a dummy trench portion to which a potential different from the gate potential is applied, In the mesa portion of the diode portion sandwiched between the two dummy trench portions, the second contact region is provided so as to extend from a side wall of one of the dummy trench portions to a side wall of the other dummy trench portion.

16. The semiconductor device according to claim 1, wherein: On the front surface of the semiconductor substrate, the emitter regions and the base regions are alternately arranged in an extending direction of the plurality of trench portions.

17. The semiconductor device according to claim 1, wherein: The emitter region is provided on the front surface of the semiconductor substrate to extend in the extending direction of the plurality of groove portions.

18. The semiconductor device according to claim 1, wherein: The doping concentration of the base region is the same as the doping concentration of the anode region.

19. The semiconductor device according to claim 1, wherein: A cathode region of a first conductivity type is provided, wherein the cathode region of the first conductivity type is provided on the back surface of the semiconductor substrate and has a doping concentration higher than that of the drift region, The doping concentration of the cathode region is 1E18 cm -3 Above and 1E21cm -3 the following.

20. The semiconductor device according to claim 1, wherein The transistor portion includes an accumulation region of the first conductivity type having a doping concentration higher than that of the drift region.

21. The semiconductor device according to any one of claims 1 to 20, characterized in that The semiconductor substrate does not have a lifetime controlled region.

22. The semiconductor device according to any one of claims 1 to 20, characterized in that The transistor portion has a main region that operates as a transistor, The main region of the transistor portion is provided adjacent to the diode portion.

23. The semiconductor device according to claim 22, wherein: An amount per unit volume of the second conductivity type dopant in the mesa portion of the diode portion is greater than or equal to an amount per unit volume of the second conductivity type dopant in the mesa portion of the main region.

24. A semiconductor device, characterized in that: The semiconductor device has a transistor portion, and includes: A drift region of the first conductivity type, which is disposed on a semiconductor substrate; A base region of a second conductivity type, which is arranged above the drift region; A first contact region of a second conductivity type, which is disposed in a mesa portion of the transistor portion and has a doping concentration higher than that of the base region; as well as A trench contact portion is provided on the front surface of the semiconductor substrate, The first contact region is not disposed on the front surface of the semiconductor substrate.

25. A method for manufacturing a semiconductor device, characterized in that: A method for manufacturing a semiconductor device including a transistor portion and a diode portion, the method comprising: The step of providing a plurality of groove portions on the front surface of the semiconductor substrate; A step of providing a drift region of a first conductivity type on the semiconductor substrate; A step of providing a base region of a second conductivity type above the drift region; A step of providing an emitter region of a first conductivity type having a doping concentration higher than that of the drift region above the base region; In the diode portion, a step of providing an anode region of a second conductivity type above the drift region; a first ion implantation step of providing a first contact region of a second conductivity type having a doping concentration higher than that of the base region in the mesa portion of the transistor portion; as well as In the diode portion, a second ion implantation step is performed to provide a second contact region of a second conductivity type having a doping concentration higher than that of the anode region above the drift region, An amount per unit volume of the second conductivity type dopant in the mesa portion of the diode portion is greater than or equal to an amount per unit volume of the second conductivity type dopant in the mesa portion of the transistor portion.

26. The method for manufacturing a semiconductor device according to claim 25, wherein: The first ion implantation step and the second ion implantation step are the same ion implantation step.

27. The method for manufacturing a semiconductor device according to claim 25, wherein: The dose of ions implanted in the first ion implantation step is different from the dose of ions implanted in the second ion implantation step.

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