Display substrate, manufacturing method thereof and display device

Abstract

The invention discloses a display substrate, a manufacturing method thereof and a display device, the display substrate comprises a sub-pixel, the sub-pixel comprises a pixel circuit, the pixel circuit comprises a light-emitting device and a driving transistor, and the driving transistor is configured to control the size of a driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a data transistor configured to write a data signal to a first pole of the driving transistor in response to a data driving signal; the material of the active layer of the driving transistor is a metal oxide semiconductor material, and the material of the active layer of the data transistor is a silicon semiconductor material.

Description

Display substrate, manufacturing method thereof, and display device Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device. Background Art

[0002] LTPO display substrates integrate oxide transistors (Oxide TFTs) and low-temperature polycrystalline silicon transistors (LTPS TFTs), and have the advantage of low-frequency driving, which can reduce the power consumption of display products. They have been increasingly used in organic light-emitting diode (OLED) display substrates, such as flexible active organic light-emitting diode (AMOLED) display substrates in mobile display products.

[0003] In existing LTPO display substrates, the driving transistors of the pixel circuits in the display area are LTPS TFTs, while some of the switching transistors in the pixel circuits are LTPS TFTs and some are oxide TFTs. Compared to oxide TFTs, LTPS TFTs have higher hysteresis and off-state current (Ioff), which can affect the display quality of the OLED display substrate. Oxide TFTs, on the other hand, have lower hysteresis and off-state current (Ioff). However, the mobility of oxide TFTs is lower than that of LTPS TFTs, resulting in a lower on-state current (Ion). When oxide TFTs are used as switching transistors in the pixel circuits in the display area, their lower Ion affects their driving capability, resulting in reduced accuracy of the signals transmitted through the switching transistors.

[0004] Summary of the Invention

[0005] At least one embodiment of the present disclosure provides a display substrate, which includes a sub-pixel, each sub-pixel including a pixel circuit, each pixel circuit including a light-emitting device and a driving transistor, each driving transistor configured to control the magnitude of a driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a data transistor, each configured to write the data signal into a first electrode of the driving transistor in response to a data driving signal; the material of the active layer of the driving transistor is a metal oxide semiconductor material, and the material of the active layer of the data transistor is a silicon semiconductor material.

[0006] At least one embodiment of the present disclosure also provides a display substrate, which includes a sub-pixel, the sub-pixel includes a pixel circuit, the pixel circuit includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the display substrate also includes a base substrate, and the pixel circuit is arranged on the main surface of the base substrate; the pixel circuit also includes a storage capacitor, the first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and the second electrode of the storage capacitor is electrically connected to the first power supply voltage terminal to receive the first power supply voltage; the gate of the driving transistor includes a bottom gate, and in a direction perpendicular to the main surface of the base substrate, the bottom gate of the driving transistor is located on the side of the active layer of the driving transistor close to the base substrate; the first electrode of the storage capacitor, the second electrode of the storage capacitor and the bottom gate of the driving transistor are all arranged in different layers, and the first electrode of the storage capacitor and the second electrode of the storage capacitor are both located on the side of the active layer of the driving transistor close to the base substrate.

[0007] At least one embodiment of the present disclosure also provides a display substrate, which includes a sub-pixel, each sub-pixel includes a pixel circuit, each pixel circuit includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the display substrate also includes a base substrate, and the pixel circuit is arranged on the main surface of the base substrate; the pixel circuit also includes a storage capacitor, a first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and a second electrode of the storage capacitor is electrically connected to a first power supply voltage terminal to receive the first power supply voltage; the orthographic projection of the storage capacitor on the main surface of the base substrate at least partially overlaps with the orthographic projection of the driving transistor on the main surface of the base substrate.

[0008] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the display substrate also includes a base substrate, and the pixel circuit is arranged on the main surface of the base substrate; the pixel circuit also includes a storage capacitor, the first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and the second electrode of the storage capacitor is electrically connected to the first power supply voltage terminal to receive the first power supply voltage; the gate of the driving transistor includes a bottom gate, and in a direction perpendicular to the main surface of the base substrate, the bottom gate of the driving transistor is located on the side of the active layer of the driving transistor close to the base substrate; the first electrode of the storage capacitor, the second electrode of the storage capacitor and the bottom gate of the driving transistor are all arranged in different layers, and the first electrode of the storage capacitor and the second electrode of the storage capacitor are both located on the side of the active layer of the driving transistor close to the base substrate.

[0009] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit also includes a control transistor, the first electrode of the control transistor is electrically connected to the gate of the driving transistor, and the material of the active layer of the control transistor is the metal oxide semiconductor material; the pixel circuit includes a first reset transistor, and the first reset transistor is configured to write a first reset signal to the gate of the driving transistor under the control of a first reset control signal; the pixel circuit also includes a compensation transistor, and the compensation transistor is configured to compensate for the signal applied to the gate of the driving transistor in response to a compensation scan signal and the data signal; the control transistor includes at least one of the first reset transistor and the compensation transistor, and the material of the active layer of at least one of the first reset transistor and the compensation transistor is the metal oxide semiconductor material.

[0010] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the gate of the driving transistor also includes a top gate, and the top gate is located on the side of the active layer of the driving transistor away from the substrate in a direction perpendicular to the main surface of the substrate; the first electrode of the storage capacitor is electrically connected to the top gate of the driving transistor, and the second electrode of the storage capacitor is electrically connected to the first power supply voltage terminal.

[0011] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the orthographic projection of the storage capacitor on the main surface of the base substrate at least partially overlaps with the orthographic projection of the driving transistor on the main surface of the base substrate.

[0012] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the first electrode of the storage capacitor is located on a side of the second electrode of the storage capacitor close to the base substrate, the orthographic projection of the first electrode of the storage capacitor on the main surface of the base substrate is located within the orthographic projection range of the second electrode of the storage capacitor on the main surface of the base substrate, and the orthographic projection of the bottom gate of the driving transistor on the main surface of the base substrate is located within the orthographic projection range of the first electrode of the storage capacitor on the main surface of the base substrate.

[0013] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the gate of the driving transistor also includes a top gate, and the top gate of the driving transistor is located on a side of the active layer of the driving transistor away from the substrate in a direction perpendicular to the main surface of the base substrate; the orthographic projection of the top gate of the driving transistor on the main surface of the base substrate is located within the range of the orthographic projection of the bottom gate of the driving transistor on the main surface of the base substrate.

[0014] For example, at least one embodiment of the present disclosure provides a display substrate, in which the active layer of the control transistor is arranged on the same layer as the active layer of the driving transistor; the control transistor includes a bottom gate, and the bottom gate of the control transistor is arranged on the same layer as the second electrode of the storage capacitor, or the bottom gate of the control transistor is arranged on the same layer as the bottom gate of the driving transistor.

[0015] For example, at least one embodiment of the present disclosure provides a display substrate in which the orthographic projection of the storage capacitor on the main surface of the base substrate does not overlap with the orthographic projection of the driving transistor on the main surface of the base substrate and the orthographic projection of the control transistor on the main surface of the base substrate.

[0016] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the orthographic projection of the storage capacitor on the main surface of the base substrate at least partially overlaps with the orthographic projection of the control transistor on the main surface of the base substrate.

[0017] For example, at least one embodiment of the present disclosure provides a display substrate, in which the active layer of the control transistor is arranged in the same layer as the active layer of the driving transistor; the control transistor includes a bottom gate, and the bottom gate of the control transistor is arranged in the same layer as the bottom gate of the driving transistor; the orthographic projection of the first electrode of the storage capacitor on the main surface of the base substrate is located within the orthographic projection range of the second electrode of the storage capacitor on the main surface of the base substrate, and the orthographic projection of the bottom gate of the control transistor on the main surface of the base substrate is located within the orthographic projection range of the first electrode of the storage capacitor on the main surface of the base substrate.

[0018] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the gate of the control transistor also includes a top gate, and in a direction perpendicular to the main surface of the base substrate, the top gate of the control transistor is located on the side of the active layer of the control transistor away from the base substrate; the orthographic projection of the top gate of the control transistor on the main surface of the base substrate is located within the range of the orthographic projection of the bottom gate of the control transistor on the main surface of the base substrate.

[0019] For example, at least one embodiment of the present disclosure provides a display substrate in which the orthographic projection of the storage capacitor on the main surface of the base substrate at least partially overlaps with the orthographic projection of the driving transistor on the main surface of the base substrate and the orthographic projection of at least one of the control transistors on the main surface of the base substrate.

[0020] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the active layer of the control transistor is arranged in the same layer as the active layer of the driving transistor; the control transistor includes a bottom gate, and the bottom gate of the control transistor is arranged in the same layer as the bottom gate of the driving transistor; the orthographic projection of the first electrode of the storage capacitor on the main surface of the base substrate is located within the orthographic projection range of the second electrode of the storage capacitor on the main surface of the base substrate, and the orthographic projection of the bottom gate of the driving transistor on the main surface of the base substrate and the orthographic projection of the bottom gate of the control transistor on the main surface of the base substrate are both located within the orthographic projection range of the first electrode of the storage capacitor on the main surface of the base substrate.

[0021] For example, at least one embodiment of the present disclosure provides a display substrate in which the orthographic projection of the interval between the driving transistor and the control transistor on the main surface of the base substrate is within the orthographic projection range of the storage capacitor on the main surface of the base substrate.

[0022] For example, at least one embodiment of the present disclosure provides a display substrate in which the orthographic projection of the storage capacitor on the main surface of the base substrate does not overlap with the orthographic projection of the driving transistor on the main surface of the base substrate, and at least partially overlaps with the orthographic projections of the plurality of control transistors on the main surface of the base substrate.

[0023] For example, at least one embodiment of the present disclosure provides a display substrate, in which the active layers of the multiple control transistors are arranged in the same layer as the active layer of the driving transistor; each of the control transistors includes a bottom gate, and the bottom gates of the multiple control transistors are arranged in the same layer as the bottom gates of the driving transistor; the orthographic projection of the first electrode of the storage capacitor on the main surface of the base substrate is located within the orthographic projection range of the second electrode of the storage capacitor on the main surface of the base substrate, and the orthographic projections of the bottom gates of the multiple control transistors on the main surface of the base substrate are all located within the orthographic projection range of the first electrode of the storage capacitor on the main surface of the base substrate.

[0024] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the second electrode of the storage capacitor is located between the first electrode of the storage capacitor and the bottom gate of the driving transistor.

[0025] For example, at least one embodiment of the present disclosure provides a display substrate in which the bottom gate of the driving transistor and the second electrode of the storage capacitor are arranged in the same layer and are located between the bottom gates of multiple control transistors and the first electrode of the storage capacitor.

[0026] For example, at least one embodiment of the present disclosure provides a display substrate in which the bottom gate of the driving transistor is arranged in the same layer as the second electrode of the storage capacitor, and the control transistor does not have a gate located between the layer where the second electrode of the storage capacitor is located and the active layer of the control transistor.

[0027] For example, at least one embodiment of the present disclosure provides a display substrate, in which the first electrode of the driving transistor is located on a side of the active layer of the driving transistor away from the base substrate, and the first electrode of the driving transistor is electrically connected to the active layer of the driving transistor through a first via hole, and is electrically connected to the bottom gate of the driving transistor through a second via hole.

[0028] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit also includes a switching transistor, and the material of the active layer of the switching transistor of the pixel circuit is the silicon semiconductor material; in the direction perpendicular to the main surface of the substrate, the active layer of the switching transistor of the pixel circuit is located on the side of the storage capacitor close to the substrate; or, the material of the active layers of all transistors of the pixel circuit is a metal oxide semiconductor material.

[0029] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the base substrate includes a display area and a non-display area at least partially surrounding the display area, the display substrate also includes a scanning drive circuit located in the non-display area, the scanning drive circuit includes a switching transistor, and the scanning drive circuit is configured to provide a driving scanning signal to the pixel circuit of the display area; in a direction perpendicular to the main surface of the base substrate, the active layer of the switching transistor of the scanning drive circuit is located on the side of the storage capacitor close to the base substrate; the material of the active layer of the switching transistor of the scanning drive circuit is the silicon semiconductor material; the first electrode and the second electrode of the switching transistor of the scanning drive circuit are electrically connected to the active layer of the switching transistor of the scanning drive circuit through a third via and a fourth via, respectively.

[0030] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the base substrate includes a display area and a non-display area at least partially surrounding the display area, the display substrate also includes a non-display area, the display substrate has a bending portion located in the non-display area, the bending portion includes a driving circuit board and a connecting trace, the connecting trace is electrically connected to the driving circuit board and electrically connected to a signal line extending to the display area, the signal line is electrically connected to the pixel circuit to provide a display signal to the pixel circuit; the display substrate is a flexible display substrate, including a flexible organic layer and an inorganic insulating layer, the inorganic insulating layer and the flexible organic layer are stacked on the main surface of the base substrate and are located on the side of the flexible organic layer away from the base substrate, the inorganic insulating layer includes a first sub-inorganic layer located between the first electrode and the second electrode of the storage capacitor, and a second sub-inorganic layer located between the second electrode of the storage capacitor and the bottom gate of the driving transistor; the display substrate includes a fifth via hole at least passing through the inorganic insulating layer, and the connecting trace is at least partially located in the fifth via hole.

[0031] At least one embodiment of the present disclosure further provides a display device, which includes any one of the display substrates provided in the embodiments of the present disclosure.

[0032] At least one embodiment of the present disclosure also includes a method for manufacturing a display substrate, which includes: forming sub-pixels, including forming a pixel circuit for the sub-pixels, wherein the pixel circuit includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device according to a data signal; and forming the pixel circuit also includes a data transistor, wherein the data transistor is configured to write the data signal into a first electrode of the driving transistor in response to a data driving signal; the material of the active layer of the driving transistor is a metal oxide semiconductor material, and the material of the active layer of the data transistor is a silicon semiconductor material.

[0033] At least one embodiment of the present disclosure also includes a method for manufacturing a display substrate, which includes: providing a base substrate, and forming sub-pixels on the main surface of the base substrate, including a pixel circuit for forming the sub-pixels, wherein the pixel circuit includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a storage capacitor, a first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and a second electrode of the storage capacitor is electrically connected to a first power supply voltage terminal to receive the first power supply voltage; the gate of the driving transistor includes a bottom gate, and in a direction perpendicular to the main surface of the base substrate, the bottom gate of the driving transistor is located on a side of the active layer of the driving transistor close to the base substrate; the first electrode of the storage capacitor, the second electrode of the storage capacitor and the bottom gate of the driving transistor are all arranged in different layers, and the first electrode of the storage capacitor and the second electrode of the storage capacitor are both located on a side of the active layer of the driving transistor close to the base substrate.

[0034] At least one embodiment of the present disclosure also includes a method for manufacturing a display substrate, which includes: providing a base substrate, and forming sub-pixels on the main surface of the base substrate, including a pixel circuit for forming the sub-pixels, wherein the pixel circuit includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a storage capacitor, a first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and a second electrode of the storage capacitor is electrically connected to a first power supply voltage terminal to receive the first power supply voltage; the orthographic projection of the storage capacitor on the main surface of the base substrate at least partially overlaps with the orthographic projection of the driving transistor on the main surface of the base substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0036] FIG1A is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure;

[0037] FIG1B is a schematic plan view of a portion of pixels in the display area in FIG1A ;

[0038] FIG2 is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure;

[0039] FIG3 is a partial cross-sectional schematic diagram of a pixel circuit of a display substrate provided by at least one embodiment of the present disclosure;

[0040] FIG4 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0041] FIG5 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0042] FIG6 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0043] FIG7 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0044] FIG8 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0045] FIG9 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0046] FIG10 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0047] FIG11 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure;

[0048] FIG12 is a schematic diagram of a display device provided by an embodiment of the present disclosure;

[0049] 13A-13C are schematic diagrams of a method for manufacturing a display substrate provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. The embodiments described below are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0051] Unless otherwise defined, the technical or scientific terms used herein should have the usual meanings understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0052] The terms in this disclosure are explained as follows:

[0053] (1) The term "integrated structure" refers to a structure A and a structure B that are seamless and uniform, for example, formed by a single patterning process. The letters A and B are used to refer to the corresponding structures described in the text.

[0054] (2) The meaning of "same-layer arrangement" refers to the relationship between multiple structures formed by the same material after the same patterning process. "Same-layer arrangement" here does not always mean that the multiple structures have the same thickness or the same height in the cross-sectional view.

[0055] (3) The meaning of a patterning process: a film layer is patterned by using a mask and a single exposure process.

[0056] The drawings in this disclosure are not drawn strictly to scale, and the number of sub-pixels in the display substrate is not limited to the number shown in the drawings. The specific size and number of each structure can be determined according to actual needs. The drawings described in this disclosure are only schematic diagrams of the structures.

[0057] At least one embodiment of the present disclosure provides a display substrate, which includes a sub-pixel, each sub-pixel including a pixel circuit, each pixel circuit including a light-emitting device and a driving transistor, each driving transistor configured to control the magnitude of a driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a data transistor, each configured to write the data signal into a first electrode of the driving transistor in response to a data driving signal; the material of the active layer of the driving transistor is a metal oxide semiconductor material, and the material of the active layer of the data transistor is a silicon semiconductor material.

[0058] At least one embodiment of the present disclosure also provides a display substrate, which includes a sub-pixel, the sub-pixel includes a pixel circuit, the pixel circuit includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the display substrate also includes a base substrate, and the pixel circuit is arranged on the main surface of the base substrate; the pixel circuit also includes a storage capacitor, the first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and the second electrode of the storage capacitor is electrically connected to the first power supply voltage terminal to receive the first power supply voltage; the gate of the driving transistor includes a bottom gate, and in a direction perpendicular to the main surface of the base substrate, the bottom gate of the driving transistor is located on the side of the active layer of the driving transistor close to the base substrate; the first electrode of the storage capacitor, the second electrode of the storage capacitor and the bottom gate of the driving transistor are all arranged in different layers, and the first electrode of the storage capacitor and the second electrode of the storage capacitor are both located on the side of the active layer of the driving transistor close to the base substrate.

[0059] At least one embodiment of the present disclosure also provides a display substrate, which includes a sub-pixel, each sub-pixel includes a pixel circuit, each pixel circuit includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the display substrate also includes a base substrate, and the pixel circuit is arranged on the main surface of the base substrate; the pixel circuit also includes a storage capacitor, a first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and a second electrode of the storage capacitor is electrically connected to a first power supply voltage terminal to receive the first power supply voltage; the orthographic projection of the storage capacitor on the main surface of the base substrate at least partially overlaps with the orthographic projection of the driving transistor on the main surface of the base substrate.

[0060] At least one embodiment of the present disclosure further provides a display device, which includes any one of the display substrates provided in the embodiments of the present disclosure.

[0061] At least one embodiment of the present disclosure also includes a method for manufacturing a display substrate, which includes: forming sub-pixels, including forming a pixel circuit for the sub-pixels, wherein the pixel circuit includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device according to a data signal; and forming the pixel circuit also includes a data transistor, wherein the data transistor is configured to write the data signal into a first electrode of the driving transistor in response to a data driving signal; the material of the active layer of the driving transistor is a metal oxide semiconductor material, and the material of the active layer of the data transistor is a silicon semiconductor material.

[0062] At least one embodiment of the present disclosure also includes a method for manufacturing a display substrate, which includes: providing a base substrate, and forming sub-pixels on the main surface of the base substrate, including a pixel circuit for forming the sub-pixels, wherein the pixel circuit includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a storage capacitor, a first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and a second electrode of the storage capacitor is electrically connected to a first power supply voltage terminal to receive the first power supply voltage; the gate of the driving transistor includes a bottom gate, and in a direction perpendicular to the main surface of the base substrate, the bottom gate of the driving transistor is located on a side of the active layer of the driving transistor close to the base substrate; the first electrode of the storage capacitor, the second electrode of the storage capacitor and the bottom gate of the driving transistor are all arranged in different layers, and the first electrode of the storage capacitor and the second electrode of the storage capacitor are both located on a side of the active layer of the driving transistor close to the base substrate.

[0063] At least one embodiment of the present disclosure also includes a method for manufacturing a display substrate, which includes: providing a base substrate, and forming sub-pixels on the main surface of the base substrate, including a pixel circuit for forming the sub-pixels, wherein the pixel circuit includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a storage capacitor, a first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and a second electrode of the storage capacitor is electrically connected to a first power supply voltage terminal to receive the first power supply voltage; the orthographic projection of the storage capacitor on the main surface of the base substrate at least partially overlaps with the orthographic projection of the driving transistor on the main surface of the base substrate.

[0064] 1A is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure. As shown in FIG1A , the base substrate 1 includes a display area AA and a non-display area BA at least partially surrounding the display area.

[0065] FIG1B is a planar schematic diagram of some pixels in the display area in FIG1A . As shown in FIG1B , for example, the display substrate 10 includes a plurality of pixels 100 arranged in an array, at least some of the plurality of pixels 100 include a plurality of sub-pixels, and at least some of the plurality of sub-pixels include a light-emitting device and a pixel circuit that drives the light-emitting device to emit light. For example, the pixel circuit may include a 2T1C (i.e., two transistors and one capacitor) pixel circuit, a 4T2C, 5T1C, 7T1C, or an nTmC (n, m are positive integers) pixel circuit. For example, in different embodiments, the pixel circuit may further include a compensation subcircuit, and the compensation subcircuit includes an internal compensation subcircuit or an external compensation subcircuit, and the compensation subcircuit may include a transistor, a capacitor, and the like. For example, as needed, the pixel circuit may further include a reset circuit, a light-emitting control subcircuit, a detection circuit, and the like.

[0066] For example, as shown in FIG1B , a plurality of pixels 100 are located in a display area. For example, in the display substrate 10 provided in some embodiments, some of the plurality of pixels 100 are dummy pixels 101. The dummy pixels 101 do not participate in display operations. Each dummy pixel 101 includes a plurality of dummy sub-pixels, but does not include sub-pixels that perform a display driving function. Of course, the display area may not include dummy pixels.

[0067] For example, the display substrate 10 is an organic light-emitting diode (OLED) display substrate, and the light-emitting device is an OLED. The display substrate 10 may further include a plurality of scan lines and a plurality of data lines for providing scan signals (e.g., gate lines, control signals, see FIG. 5 ) and data signals to the plurality of sub-pixels, thereby driving the plurality of sub-pixels. As needed, the display substrate 10 may further include power lines, detection lines, etc.

[0068] It should be noted that the phrase “the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor” here means that the electrode where the active layer of the control transistor is located is in direct contact with the gate of the driving transistor and the first electrode of the control transistor, thereby electrically connecting the gate of the driving transistor and the first electrode of the control transistor, rather than indirectly electrically connecting the first electrode of the active layer of the control transistor to the gate of the driving transistor through other conductive structures (for example, conductive structures located on other layers).

[0069] For example, FIG2 is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure. Here, the structure of the sub-pixel of the display substrate is introduced by taking the 7T1C pixel circuit shown in FIG2 as an example.

[0070] As shown in FIG2 , the pixel circuit includes first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 and a storage capacitor Cst. For example, the driving transistor T3 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.

[0071] For example, as shown in FIG2 , the pixel circuit of the display substrate 10 provided by the embodiment of the present disclosure includes a light-emitting device EL, a driving transistor T3, and a data transistor T4. The gate of the driving transistor T3 is electrically connected to the first node N1; the first electrode of the driving transistor T3 is electrically connected to the second node N2; and the second electrode of the driving transistor T3 is electrically connected to the third node N3. The gate of the data transistor T4 is electrically connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, the first electrode of the data transistor T4 is connected to the data line (data signal terminal Vd) to receive the data signal, and the second electrode of the data transistor T4 is electrically connected to the second node N2. The driving transistor T3 is configured to control the magnitude of the driving current flowing through the light-emitting device EL according to the data signal.

[0072] For example, as shown in FIG2 , the gate of the compensation transistor T2 is electrically connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal. The compensation transistor T2 is configured to compensate for the signal applied to the gate of the driving transistor T3 in response to the compensation scan signal and the data signal. The first electrode T3s of the compensation transistor T2 is electrically connected to the second electrode (the third node N3) of the driving transistor T3, and the second electrode of the compensation transistor T2 is electrically connected to the gate (the first node N1) of the driving transistor T3.

[0073] For example, as shown in FIG2 , the pixel circuit further includes a storage capacitor Cst, which includes a first electrode C1 and a second electrode C2. The first electrode C1 of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the first electrode C1 is electrically connected to the gate of the driving transistor T3 (the first node N1). The second electrode C2 of the storage capacitor Cst is electrically connected to the first power supply voltage terminal vdd to receive the first power supply voltage VDD.

[0074] For example, as shown in Figure 2, the gate of the first light-emitting control transistor T5 is electrically connected to the first light-emitting control line (first light-emitting control terminal EM1) to receive the first light-emitting control signal, the first electrode of the first light-emitting control transistor T5 is electrically connected to the first voltage terminal vdd to receive the first power supply voltage VDD, and the second electrode of the first light-emitting control transistor T5 is electrically connected to the second node N2.

[0075] For example, the light-emitting device EL is specifically implemented as a light-emitting diode (LED), such as an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or an inorganic light-emitting diode, such as a micro light-emitting diode (Micro LED) or a micro OLED. For example, the light-emitting device EL can have a top-emitting structure, a bottom-emitting structure, or a double-sided emission structure. The light-emitting device EL can emit red light, green light, blue light, or white light, etc. The embodiments of the present disclosure do not limit the specific structure of the light-emitting device.

[0076] For example, a first electrode (e.g., an anode) of the light-emitting device EL is connected to the fourth node N4 and is configured to be connected to the second electrode (third node N3) of the driving transistor T3 via the second light-emission control transistor T6. A second electrode (e.g., a cathode) of the light-emitting device EL is electrically connected to the common power supply voltage terminal vss to receive the common power supply voltage VSS. The current flowing from the second electrode of the driving transistor T3 into the light-emitting device EL determines the brightness of the light-emitting device. For example, the common power supply voltage terminal vss can be grounded, that is, the common power supply voltage VSS can be 0V. For example, the common power supply voltage VSS can also be a negative voltage.

[0077] For example, the gate of the second light-emitting control transistor T6 is electrically connected to the second light-emitting control line (the second light-emitting control terminal EM2) to receive the second light-emitting control signal, the first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T3 (the third node N3), and the second electrode of the second light-emitting control transistor T6 is electrically connected to the first electrode (the fourth node N4) of the light-emitting device EL.

[0078] 2 , for example, the pixel circuit further includes a first reset transistor T1, which is configured to write a first reset signal Vinit1 to the gate of the driving transistor T3 under the control of a first reset control signal Rst1. For example, the gate of the first reset transistor T1 is configured to be connected to the first reset control terminal Rst1 to receive the first reset control signal Rst1, a first electrode of the first reset transistor T1 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1, and a second electrode of the first reset transistor T1 is configured to be connected to the first node N1. For example, the pixel circuit further includes a second reset transistor T7, a gate of the second reset transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset control signal Rst2, a first electrode of the second reset transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2, and a second electrode of the second reset transistor T7 is configured to be connected to the fourth node N4.

[0079] For example, the first reset signal Vinit1 and the second reset signal Vinit2 are the same signal and come from the same reset signal line connected to the same reset signal terminal, thus saving one reset signal line. Of course, the first reset signal Vinit1 and the second reset signal Vinit2 can also be two independent signals.

[0080] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples. The source and drain of the transistors used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0081] In addition, transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages). For example, as shown in Figure 2, the first to seventh transistors T1-T7 are all P-type transistors as an example. However, the embodiment of the present disclosure does not limit the type of transistor. When the type of transistor changes, the connection relationship in the circuit can be adjusted accordingly.

[0082] FIG3 is a partial cross-sectional schematic diagram of a pixel circuit of a display substrate provided in at least one embodiment of the present disclosure. Referring to FIG3 , the display substrate 10 further includes a base substrate 1 , and the pixel circuit is disposed on a major surface of the base substrate 1 . FIG3 shows a driving transistor T3 (DTFT) T3 of the pixel circuit. For example, in at least one embodiment of the present application, the material of the active layer T3a of the driving transistor T3 is a metal oxide semiconductor material, and the material of the active layer of the data transistor T4 is a silicon semiconductor material, that is, the driving transistor T3 is an oxide transistor (Oxide TFT), and the data transistor T4 is a low-temperature polysilicon transistor (LTPS TFT). This takes advantage of the characteristics of the Oxide TFT, which has low hysteresis and low off-state current Ioff, so that the driving transistor T3 has better driving performance. At the same time, since the mobility of the Oxide TFT is lower than that of the LTPS TFT, the on-state current Ion of the Oxide TFT is also lower. When the Oxide TFT is used as the switching transistor of the pixel circuit in the display area, its low Ion will affect its driving capability, thereby reducing the accuracy of the signal transmitted through the switching transistor. However, the data transistor T4, as one of the switching transistors of the pixel circuit, adopts an LTPS TFT, which can avoid the problem that the data transistor T4 is an Oxide TFT. TFT causes the problem of reduced accuracy of transmitted data signals. Since the data signal is used to control the grayscale of the display, the signal transmission ability of the data transistor T4 has a more obvious impact on the display image than other switching transistors in the pixel circuit except the driving transistor T3. Therefore, when the driving transistor T1 is an oxide TFT and the data transistor T4 is an LTPS TFT, the advantages of these two types of transistors can be fully utilized to achieve better display quality.

[0083] For example, the metal oxide semiconductor material may include indium gallium zinc oxide (IGZO); or, the metal oxide semiconductor material may include indium gallium tin oxide (IGTO), where the zinc in IGZO is replaced with tin (Sn); or, the metal oxide semiconductor material may include indium gallium zinc tin oxide (IGZTO), where tin is added to IGZO. Of course, the metal oxide semiconductor material is not limited to the types listed above, and the embodiments of the present disclosure do not limit the specific types of metal oxide semiconductor materials.

[0084] In a display substrate provided by the present disclosure, referring to FIG3 , the display substrate includes the above-mentioned sub-pixel 100, the sub-pixel 100 includes a pixel circuit, the pixel circuit includes a light-emitting device EL and a driving transistor T3, the driving transistor T3 is configured to control the magnitude of the driving current flowing through the light-emitting device EL according to a data signal; the display substrate 10 also includes a base substrate 1, the pixel circuit is arranged on the main surface of the base substrate 1, the pixel circuit also includes a storage capacitor Cst, a first electrode C1 of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and a second electrode C2 of the storage capacitor Cst is electrically connected to the first power supply voltage terminal vdd to receive the first power supply voltage VDD; for example, the gate of the driving transistor T3 includes a bottom gate T3g1 and a top gate T3g2. In a direction perpendicular to the main surface of the substrate 1, the bottom gate T3g1 of the driving transistor T3 is located on the side of the active layer T3a of the driving transistor T3 close to the substrate 1, and the top gate T3g2 of the driving transistor T3 is located on the side of the active layer T3a of the driving transistor T3 away from the substrate 1; the first electrode C1 of the storage capacitor Cst, the second electrode C2 of the storage capacitor Cst and the bottom gate T3g1 of the driving transistor T3 are all arranged in different layers. In this way, in the film layer where the first electrode C1 of the storage capacitor Cst and the second electrode C2 of the storage capacitor Cst are located, there is more sufficient space to expand the area of ​​the first electrode C1 and the second electrode C2, and the freedom of the position of the first electrode C1 and the second electrode C2 is expanded.

[0085] For example, referring to FIG3 , the first electrode C1 of the storage capacitor Cst and the second electrode C2 of the storage capacitor Cst are both located on a side of the active layer T3a of the driving transistor T3 that is close to the substrate 1. For example, when the driving transistor T3 has a bottom gate T3g1, the first electrode C1 of the storage capacitor Cst and the second electrode C2 of the storage capacitor Cst are both located on a side of the bottom gate T3g1 of the driving transistor T3 that is close to the substrate 1. In some embodiments, the driving transistor T3 does not have a bottom gate T3g1 but only has a top gate T3g2. That is, the first electrode C1 of the storage capacitor Cst and the second electrode C2 of the storage capacitor Cst are located on a side of the driving transistor T3 that is close to the substrate 1. Typically, the source, drain, and connection lines of each transistor are disposed on a side of the driving transistor T3 away from the base substrate 1, for example, on the first conductive layer SD1 to be described below. Thus, in the embodiment of the present disclosure, the first electrode C1 of the storage capacitor Cst and the second electrode C2 of the storage capacitor Cst are both located on a side of the bottom gate T3g1 of the driving transistor T3 close to the base substrate 1. The first electrode C1 of the storage capacitor Cst and the second electrode C2 of the storage capacitor Cst can be disposed in the space between the insulating layers on the side of the driving transistor T3 close to the base substrate 1, and the first electrode C1 of the storage capacitor Cst is conveniently electrically connected to the top gate T3g2 of the driving transistor T3. In this way, the structure of the pixel circuit can be realized using a limited space, and the areas of the first electrode C1 and the second electrode C2 of the storage capacitor Cst can be increased to increase the capacitance value of the storage capacitor Cst, thereby meeting pixel circuit designs that have higher requirements on the capacitance value of the storage capacitor Cst.

[0086] For example, the pixel circuit includes a control transistor, a first electrode of which is electrically connected to the gate of the driving transistor T3, and an active layer of the control transistor is made of a metal oxide semiconductor material. The control transistor includes at least one of a first reset transistor T1 and a compensation transistor T2; the active layer of at least one of the first reset transistor and the compensation transistor is made of a metal oxide semiconductor material, so that the leakage current of the first reset transistor T1 and / or the compensation transistor T2 is reduced, thereby reducing the fluctuation of the signal provided by the gate of the driving transistor T3 and enhancing the reliability of the signal provided to the gate of the driving transistor T3. At the same time, the display substrate 10 is an LTPO display substrate that integrates oxide transistors (Oxide TFTs) and low-temperature polycrystalline silicon transistors (LTPS TFTs), which has the advantage of low-frequency drive and can reduce the power consumption of the display product.

[0087] In FIG3 , the compensation transistor T2 is used as an example of a control transistor. The control transistor may also be the first reset transistor T1. Of course, the control transistor is not limited to the compensation transistor T2 and the first reset transistor T1. In other embodiments, all transistors in the pixel circuit except the driving transistor may be control transistors, that is, the material of their active layers may be silicon semiconductor materials, and the pixel circuit is not limited to the 7T1C pixel circuit shown in FIG2 .

[0088] For example, referring to FIG3 , the first electrode C1 of the storage capacitor Cst is electrically connected to the top gate T3g2 of the driving transistor T3, and the second electrode C2 of the storage capacitor Cst is electrically connected to the first power supply voltage terminal vdd. Of course, in other embodiments, the first electrode C1 of the storage capacitor Cst may also be electrically connected to the top gate T3g2 of the driving transistor T3.

[0089] For example, at least one embodiment of the present disclosure also provides a display substrate, which includes the above-mentioned sub-pixel 100, the sub-pixel 100 includes a pixel circuit, the pixel circuit includes a light-emitting device EL and a driving transistor T3, and the driving transistor T3 is configured to control the magnitude of the driving current flowing through the light-emitting device EL according to the data signal; the display substrate 10 also includes a base substrate 1, the pixel circuit is arranged on the main surface of the base substrate 1, the pixel circuit also includes a storage capacitor Cst, the first electrode C1 of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second electrode C2 of the storage capacitor Cst is electrically connected to the first power supply voltage terminal vdd to receive the first power supply voltage VDD; the orthographic projection of the storage capacitor Cst on the main surface of the base substrate 1 at least partially overlaps with the orthographic projection of the driving transistor T3 on the main surface of the base substrate 1. Referring to Figure 3, the orthographic projection of the storage capacitor Cst on the main surface of the base substrate 1 at least partially overlaps with the orthographic projection of the driving transistor T3 on the main surface of the base substrate 1. In this way, not only can the first electrode C1 and the second electrode C2 of the storage capacitor Cst be set using the space under the driving transistor T3, but the storage capacitor Cst is close to the driving transistor T3, which facilitates the electrical connection between the first electrode C1 of the storage capacitor Cst and the gate of the driving transistor T3, avoiding design difficulties caused by the winding of the connecting wire used to electrically connect the first electrode C1 of the storage capacitor Cst and the gate of the driving transistor T3.

[0090] For example, referring to FIG3 , the first electrode C1 of the storage capacitor Cst is located on a side of the second electrode C2 of the storage capacitor Cst that is closer to the base substrate 1. That is, the second electrode C2 of the storage capacitor Cst is located between the first electrode C1 of the storage capacitor Cst and the bottom gate T3g1 of the drive transistor T3. The orthographic projection of the first electrode C1 of the storage capacitor Cst on the main surface of the base substrate 1 is located within the orthographic projection of the second electrode C2 of the storage capacitor Cst on the main surface of the base substrate 1. The second electrode C2 covers the first electrode C1 to ensure uniformity in the size of the storage capacitor Cst. Typically, the first electrode C1 is fabricated first, and then the second electrode C2 is fabricated above the first electrode C1 (on the side away from the base substrate 1). If the orthographic projection of the second electrode C2 on the main surface of the base substrate 1 is within the orthographic projection of the first electrode C1 of the storage capacitor Cst on the main surface of the base substrate 1, that is, the first electrode C1 located below covers the second electrode C2 above it, the influence of the uniformity of the critical dimension (CD, hereinafter referred to as this abbreviation) during the etching process of the second electrode C2 also needs to be considered. Therefore, when the first electrode C1 covers the second electrode C2 above it, the etching uniformity of the storage capacitor Cst is not as good as when the second electrode C2 located above covers the first electrode C1 below it.

[0091] For example, the orthographic projection of the bottom gate T3g1 of the driving transistor T3 on the main surface of the substrate 1 is located within the orthographic projection range of the first electrode C1 of the storage capacitor Cst on the main surface of the substrate 1, that is, the first electrode C1 located below the bottom gate T3g1 of the driving transistor T3 covers the bottom gate T3g1 of the driving transistor T3, so as to ensure the etching uniformity of the bottom gate T3g1 of the driving transistor T3. This is because the stability and uniformity of the equipment and process need to be considered. If the first electrode C1 cannot completely cover the bottom gate T3g1 of the driving transistor T3, then the bottom gate T3g1 of the driving transistor T3 may be misaligned with the first electrode C1 (the two may partially overlap in a direction perpendicular to the main surface of the base substrate 1), or the bottom gate T3g1 of the driving transistor T3 may be aligned with an edge of the first electrode C1. In these cases, the CD uniformity of the bottom gate T3g1 of the driving transistor T3 is not as good as the CD uniformity of the bottom gate T3g1 of the driving transistor T3 when the first electrode C1 completely covers the bottom gate T3g1 of the driving transistor T3. In addition, if the bottom gate T3g1 of the driving transistor T3 wraps around the first electrode C1, since the bottom gate T3g1 is located below the active layer of the driving transistor T3 (close to the side of the base substrate 1), if the size of the bottom gate T3g1 of the driving transistor T3 increases, the size of the driving transistor T3 will also increase, which is not conducive to improving the resolution (PPI) of the display substrate 10.

[0092] For example, further, the orthographic projection of the top gate T3g2 of the driving transistor T3 on the main surface of the substrate 1 is located within the orthographic projection range of the bottom gate T3g1 of the driving transistor T3 on the main surface of the substrate 1, that is, the bottom gate T3g1 of the driving transistor T3 covers the top gate T3g2 of the driving transistor T3. As above, this is conducive to improving the CD uniformity of the top gate T3g2 of the driving transistor T3. In addition, making the bottom gate T3g1 of the driving transistor T3 cover the top gate T3g2 of the driving transistor T3 can also avoid the situation where one end of the bottom gate T3g1 of the driving transistor T3 and one end of the top gate T3g2 of the driving transistor T3 are completely aligned under the influence of factors such as the exposure machine alignment deviation and the uniformity of the photolithography process. The end where the bottom gate T3g1 of the driving transistor T3 is aligned with the top gate T3g2 of the driving transistor T3 and the end where the two are not aligned will be directly affected by the thickness and taper angle of the photoresist. 2 and the Taper angle of the top gate T3g2 of the driving transistor T3 after etching, thereby affecting the CD uniformity of the bottom gate T3g1 of the driving transistor T3. In addition, after the Taper angle of the top gate T3g2 of the driving transistor T3 at one end where the two are aligned becomes larger, the second interlayer insulating layer ILD2 subsequently formed above the top gate T3g2 of the driving transistor T3 becomes less flat and less effective in fully covering the conductive layer thereunder, which is likely to cause cracks, thereby causing a short circuit between the top gate T3g2 of the driving transistor T3 and the wiring located on the first conductive layer SD1.

[0093] Figure 3 illustrates a compensation transistor T2 as a control transistor. For example, referring to Figure 3 , the active layer T2a of the compensation transistor T2 is co-located with the active layer T3a of the drive transistor T3. That is, the active layer T2a of the control transistor and the active layer T3a of the drive transistor T3 are co-located. These two layers are made of the same material and can be formed simultaneously through the same patterning process. The compensation transistor T2 includes a bottom gate T2g1. For example, referring to Figure 3 , the bottom gate T2g1 of the compensation transistor T2 is co-located with the second electrode C2 of the storage capacitor Cst, allowing for simultaneous formation through the same patterning process.

[0094] Alternatively, as shown in FIG4 , the embodiment shown in FIG4 differs from that shown in FIG3 in that the bottom gate T2g1 of the compensation transistor T2 is disposed in the same layer as the bottom gate T3g1 of the driving transistor T3, that is, the bottom gate of the control transistor is disposed in the same layer as the bottom gate T3g1 of the driving transistor T3. Because the thickness of the insulating layer between the bottom gate T3g1 of the driving transistor T3 and the active layer T3a of the driving transistor T3 is less than the thickness of the insulating layer between the second electrode C2 of the storage capacitor Cst and the active layer T3a of the driving transistor T3, when the bottom gate T2g of the compensation transistor T2 (representing any control transistor defined in this application) is disposed in the same layer as the bottom gate T3g1 of the driving transistor T3, the on-state current Ion of the compensation transistor T2 is larger, which can enhance the driving capability of the compensation transistor T2 and improve the accuracy of the signal transmitted by the compensation transistor T2. Other features and technical effects of the embodiment shown in FIG4 are the same as those in FIG3 , and reference may be made to the description of FIG3 for details.

[0095] Continuing with FIG. 3 , compensation transistor T2 further includes a top gate T2g2 electrically connected to bottom gate T2g1 of compensation transistor T2. This improves the current saturation of compensation transistor T2, resulting in a smaller and more stable current change rate ΔI% of driving transistor T3, thereby enhancing the current stability of driving transistor T3. Because OLEDs are current-driven devices, a more stable current in driving transistor T3 leads to more stable light emission and better image quality. For example, an electrode for top gate T2g2 of compensation transistor T2 and an electrode for bottom gate T2g1 of compensation transistor T2 extend from display area AA into non-display area BD to connect to each other in non-display area BD, thereby electrically connecting top gate T2g2 of compensation transistor T2 to bottom gate T2g1 of compensation transistor T2.

[0096] For example, the pixel circuit further includes a switching transistor. Among the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 of the pixel circuit, all transistors except the driving transistor T3 and the control transistor (T1 and / or T2) are switching transistors. For example, the material of the active layer of the switching transistor of the pixel circuit is a silicon semiconductor material. In a direction perpendicular to the main surface of the substrate 1, the active layer of the switching transistor of the pixel circuit is located on a side of the storage capacitor Cst close to the substrate 1. Alternatively, in other embodiments, the material of the active layers of all transistors in the pixel circuit is a metal oxide semiconductor material.

[0097] For example, referring to Figure 1A, the first electrode T3s of the driving transistor T3 is located on the side of the active layer T3a of the driving transistor T3 away from the base substrate 1, and the first electrode T3s of the driving transistor T3 is electrically connected to the active layer T3a of the driving transistor T3 through the first via V1, and is electrically connected to the bottom gate T3g1 of the driving transistor T3 through the second via V2; the second electrode T3d of the driving transistor T3 is electrically connected to the active layer T3a of the driving transistor T3 through the sixth via V6; the first electrode T2s and the second electrode T2d of the compensation transistor T2 are electrically connected to the active layer T2a of the compensation transistor T2 through the seventh via V7 and the eighth via V8, respectively.

[0098] For example, referring to FIG1A , the display substrate 10 further includes a scan driver circuit 01 located in the non-display area BD. The scan driver circuit 01 is, for example, a GOA (Gate Driven on Array) circuit. In FIG1A , the scan driver circuit 01 is provided only in the non-display area BD on one side of the display area AA. In other embodiments, the scan driver circuit 01 may be provided in the non-display areas BD on both sides of the display area AA. The scan driver circuit 01 includes a switching transistor and is configured to provide drive scan signals to the pixel circuits in the display area. These drive scan signals include, for example, a first scan signal, a second scan signal, a first light-emitting control signal, a second light-emitting control signal, a first reset control signal Rst1, and a second reset control signal Rst2 required by the aforementioned pixel circuits. For example, in a direction perpendicular to the main surface of the base substrate 1, the active layer STa of the switching transistor ST of the scan driver circuit 01 is located on the side of the storage capacitor Cst that is closer to the base substrate 1. For example, the material of the active layer STa of the switching transistor ST of the scan driving circuit 01 is silicon semiconductor material; the first electrode STs and the second electrode STd of the switching transistor ST of the scan driving circuit 01 are electrically connected to the active layer STa of the switching transistor ST of the scan driving circuit 01 through the third via V3 and the fourth via V4 respectively.

[0099] For example, the display substrate 10 has a bent portion BP located in the non-display area BD. For example, the display substrate 10 has a flexible substrate. The bent portion BP can be bent toward the back of the display surface for displaying images to reduce the bezel of the display substrate. For example, the bent portion BP includes a driver circuit board IC and a first connection electrode E1. The first connection electrode E1 is electrically connected to the driver circuit board IC and to a signal line extending to the display area. The signal line is electrically connected to the pixel circuit to provide display signals to the pixel circuit. For example, the display signals include a first power supply voltage VDD, a common power supply voltage VSS, and a data signal. For example, the display substrate 10 is a flexible display substrate 10, comprising a flexible organic layer and an inorganic insulating layer. The inorganic insulating layer and the flexible organic layer are stacked on the main surface of the base substrate 1 and located on the side of the flexible organic layer away from the base substrate 1. The inorganic insulating layer includes a first sub-inorganic layer located between the first electrode C1 and the second electrode C2 of the storage capacitor Cst, and a second sub-inorganic layer located between the second electrode C2 of the storage capacitor Cst and the bottom gate T3g1 of the driving transistor T3. The display substrate 10 includes a fifth via V5 that at least penetrates the inorganic insulating layer, and the first connection electrode E1 is at least partially located in the fifth via V5. Because the inorganic insulating layer above the flexible organic layer is prone to cracking when bent, resulting in poor reliability, the inorganic insulating layer above the flexible organic layer at the bend portion BP is removed by opening the fifth via V5.

[0100] For example, referring to FIG3 , the display substrate 10 further includes a first flexible layer PI1, a second flexible layer PI2, a first barrier layer Barrier1, a second barrier layer Barrier1, a third barrier layer Barrier2, a first buffer layer Buffer1, a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a second buffer layer Buffer2, a third gate insulating layer GI3, and a second interlayer insulating layer ILD2, disposed on a base substrate BS. Each insulating layer directly insulates each conductive layer, and each buffer layer can isolate impurities from a film layer subsequently formed on the corresponding buffer layer. The first flexible layer PI1 and the second flexible layer PI2 are made of, for example, polyimide (PI), making the display substrate a flexible substrate. The polyimide (PI) substrate contains movable fixed charges. When the gate voltage of the driving transistor T3 changes, the movable charges move up and down as the electric field formed by the gate voltage of the driving transistor T3 changes, forming a built-in electric field that changes with the gate voltage of the driving transistor T3, thereby affecting the characteristics of the driving transistor T3 and the image quality of the display substrate.

[0101] For example, the flexible organic layer includes a first flexible layer PI1 and a second flexible layer PI2; the insulating layers penetrated by the fifth via V5 include a second barrier layer Barrier1, a third barrier layer Barrier2, a first buffer layer Buffer1, a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a second buffer layer Buffer2, a third gate insulating layer GI3, and a second interlayer insulating layer ILD2. Some or all of these layers are inorganic insulating layers. For example, the first sub-inorganic layer is the second gate insulating layer GI2, and the second sub-inorganic layer is the first interlayer insulating layer ILD1.

[0102] Referring to Figure 3, the first electrode T3s and the second electrode T3d of the driving transistor T3, the first electrode T2s and the second electrode T2d of the compensation transistor T2, the first electrode STs and the second electrode STd of the switching transistor ST of the scan driving circuit 01, and the first connection electrode E1 are arranged in the same layer, for example, all are located in the first conductive layer SD1. The first conductive layer SD1 is located on the side of the active layer T3a of the driving transistor T3 away from the base substrate 1, for example, on the side of the top gate T3g2 of the driving transistor T3 away from the base substrate 1.

[0103] FIG5 is a partial cross-sectional schematic diagram of another pixel circuit of a display substrate provided in at least one embodiment of the present disclosure. FIG5 still uses the compensation transistor T2 as an example of the control transistor. The control transistor may also be the first reset transistor T1. Of course, the control transistor is not limited to the compensation transistor T2 and the first reset transistor T1. In other embodiments, all transistors in the pixel circuit except the driving transistor T3 may be control transistors, that is, the material of their active layers may all be silicon semiconductor materials.

[0104] Referring to Figure 5 , the embodiment shown in Figure 5 differs from that shown in Figure 3 in that the orthographic projection of the storage capacitor Cst on the main surface of the substrate 1 does not overlap with the orthographic projection of the drive transistor T3 on the main surface of the substrate 1 and the orthographic projection of the control transistor on the main surface of the substrate 1. This reduces the complexity of the film stack beneath the drive transistor T3 (Oxide TFT), thereby improving the CD uniformity of the top gate T3g2 of the drive transistor T3, and thereby improving the uniformity of the device characteristics of the drive transistor T3, allowing the drive transistor T3 to achieve a better driving effect. The other features and technical effects of the embodiment shown in Figure 5 are the same as those in Figure 3 , and reference may be made to the description of Figure 3 .

[0105] FIG6 is a partial cross-sectional schematic diagram of another pixel circuit of a display substrate provided in at least one embodiment of the present disclosure. FIG6 still uses the compensation transistor T2 as an example of the control transistor. The control transistor can also be the first reset transistor T1. Of course, the control transistor is not limited to the compensation transistor T2 and the first reset transistor T1. In other embodiments, all transistors in the pixel circuit except the driving transistor T3 can be control transistors, that is, the material of their active layers can all be silicon semiconductor materials.

[0106] The embodiment shown in FIG6 differs from the embodiment shown in FIG4 in the following ways. Referring to FIG6 , the orthographic projection of the storage capacitor Cst on the main surface of the substrate 1 at least partially overlaps with the orthographic projection of the control transistor (e.g., the compensation transistor T2) on the main surface of the substrate 1. Of course, the control transistor here can also be the first reset transistor T1, i.e., the orthographic projection of the storage capacitor Cst on the main surface of the substrate 1 at least partially overlaps with the orthographic projection of the first reset transistor T1 on the main surface of the substrate 1. Compared to being arranged below the driving transistor T3 (Oxide TFT), the solution shown in FIG6 can reduce the complexity of the film layer stack below the driving transistor T3 (Oxide TFT), thereby improving the CD uniformity of the top gate T3g2 of the driving transistor T3, thereby improving the uniformity of the device characteristics of the driving transistor T3, and enabling the driving transistor T3 to achieve a better driving effect. Since the performance of the driving transistor T3 has an extremely important effect on the driving current and the display effect, it is crucial to ensure that the performance of the driving transistor T3 is not affected by the complex film layer below. In addition, in the display substrate, the connection lines near the driving transistor T3 are more dense and complex. Arranging the first electrode and the second electrode of the storage capacitor Cst below the control transistor (i.e., the orthographic projections of the two overlap) is more conducive to pixel design, and can utilize limited space to rationally arrange various electrodes and wirings, thereby improving the PPI of the display substrate 10.

[0107] 6 , for example, the active layer T2a of the compensation transistor T2 is disposed on the same layer as the active layer T3a of the driving transistor T3; the compensation transistor T2 includes a bottom gate T2g1, which is disposed on the same layer as the bottom gate T3g1 of the driving transistor T3, so that the existing film layer below the compensation transistor T2 is rationally utilized to dispose the bottom gate T2g1 of the compensation transistor T2 and the first electrode C1 and the second electrode C2 of the storage capacitor Cst, thereby simplifying the structure and the manufacturing process of the display substrate 10.

[0108] 6 , for example, the orthographic projection of the first electrode C1 of the storage capacitor Cst on the main surface of the base substrate 1 is located within the orthographic projection of the second electrode C2 of the storage capacitor Cst on the main surface of the base substrate 1, and the orthographic projection of the bottom gate T2g1 of the compensation transistor T2 on the main surface of the base substrate 1 is located within the orthographic projection of the first electrode C1 of the storage capacitor Cst on the main surface of the base substrate 1. As described above, this helps ensure uniform etching or CD uniformity of the first and second electrodes C1 and C2 of the storage capacitor Cst and the bottom gate T2g1 of the compensation transistor T2.

[0109] For example, the gate of the compensation transistor T2 further includes a top gate T2g2. In a direction perpendicular to the main surface of the base substrate 1, the top gate T2g2 of the compensation transistor T2 is located on a side of the active layer T2a of the compensation transistor T2 that is away from the base substrate 1. The orthographic projection of the top gate T2g2 of the compensation transistor T2 on the main surface of the base substrate 1 is located within the orthographic projection of the bottom gate T2g1 of the compensation transistor T2 on the main surface of the base substrate 1. Similarly, this helps ensure the uniform etching or CD uniformity of the top gate T2g2 of the compensation transistor T2, as well as the taper angle of the top gate T2g2, thereby improving the coverage reliability of the second interlayer insulating layer ILD2 and ensuring its insulation effect.

[0110] Other features and technical effects of the embodiment shown in FIG6 are the same as those in FIG4 , and reference may be made to the description of FIG4 .

[0111] FIG7 is a partial cross-sectional schematic diagram of another pixel circuit of a display substrate provided in at least one embodiment of the present disclosure. FIG7 still uses the compensation transistor T2 as an example of the control transistor. The control transistor can also be the first reset transistor T1. Of course, the control transistor is not limited to the compensation transistor T2 and the first reset transistor T1. In other embodiments, all transistors in the pixel circuit except the drive transistor T3 can be control transistors, that is, the material of their active layers can all be silicon semiconductor materials.

[0112] The embodiment shown in FIG7 differs from the embodiment shown in FIG6 in the following ways. Referring to FIG7 , the orthographic projection of the storage capacitor Cst on the main surface of the substrate 1 at least partially overlaps with the orthographic projection of the drive transistor T3 on the main surface of the substrate 1 and the orthographic projection of at least one control transistor on the main surface of the substrate 1. For example, the orthographic projection of the storage capacitor Cst on the main surface of the substrate 1 at least partially overlaps with the orthographic projection of the drive transistor T3 on the main surface of the substrate 1 and the orthographic projection of the compensation transistor T2 on the main surface of the substrate 1; or, the orthographic projection of the storage capacitor Cst on the main surface of the substrate 1 at least partially overlaps with the orthographic projection of the drive transistor T3 on the main surface of the substrate 1 and the orthographic projection of the first reset transistor T1 on the main surface of the substrate 1; or, the orthographic projection of the storage capacitor Cst on the main surface of the substrate 1 at least partially overlaps with the orthographic projection of the drive transistor T3 on the main surface of the substrate 1, the orthographic projection of the first reset transistor T1 on the main surface of the substrate 1, and the orthographic projection of the compensation transistor T2 on the main surface of the substrate 1. In this way, the size of the pixel capacitor can be increased by increasing the area of ​​the pixel capacitor without affecting the pixel design space and the PPI of the display substrate 10, thereby improving the compensation capability of the pixel capacitor for the pixel.

[0113] 7 , for example, the active layer T2a of the compensation transistor T2 is disposed on the same layer as the active layer T3a of the driving transistor T3; the bottom gate T2g1 of the compensation transistor T2 is disposed on the same layer as the bottom gate T3g1 of the driving transistor T3, so as to rationally utilize the existing film layers below the driving transistor T3 and the compensation transistor T2 to form the bottom gates of the two transistors, thereby simplifying the structure and manufacturing process of the display substrate 10.

[0114] 7 , for example, the orthographic projection of the first electrode C1 of the storage capacitor Cst on the main surface of the substrate 1 is within the orthographic projection of the second electrode C2 of the storage capacitor Cst on the main surface of the substrate 1. The orthographic projections of the bottom gate T3g1 of the drive transistor T3 and the bottom gate T3g1 of the control transistor on the main surface of the substrate 1 are both within the orthographic projection of the first electrode C1 of the storage capacitor Cst on the main surface of the substrate 1. Similarly, this ensures etching uniformity, or CD uniformity, of the storage capacitor Cst and the bottom gate T3g1 of the drive transistor T3.

[0115] Referring to Figure 7, for example, the orthographic projection of the gap between the driving transistor T3 and the compensation transistor T2 on the main surface of the substrate substrate 1 is also located within the orthographic projection range of the storage capacitor Cst on the main surface of the substrate substrate 1, that is, within the orthographic projection range of the first electrode C1 of the storage capacitor Cst on the main surface of the substrate substrate 1 and within the orthographic projection range of the second electrode C2 of the storage capacitor Cst on the main surface of the substrate substrate 1.

[0116] Other features and technical effects of the embodiment shown in FIG. 7 are the same as those in FIG. 6 , and reference may be made to the description of FIG. 6 .

[0117] FIG8 is a partial cross-sectional schematic diagram of another pixel circuit of a display substrate provided in at least one embodiment of the present disclosure. FIG8 illustrates a compensation transistor T2 and a first reset transistor T1 as examples of control transistors. However, the control transistors are not limited to the compensation transistor T2 and the first reset transistor T1. In other embodiments, all transistors in the pixel circuit other than the drive transistor T3 may be control transistors, i.e., their active layers may be made of silicon semiconductor material.

[0118] The embodiment shown in FIG8 differs from the embodiment shown in FIG7 in the following ways. Referring to FIG8 , for example, the orthographic projection of the storage capacitor Cst on the main surface of the substrate 1 does not overlap with the orthographic projection of the drive transistor T3 on the main surface of the substrate 1, and at least partially overlaps with the orthographic projections of the multiple control transistors on the main surface of the substrate 1. For example, the orthographic projections of the compensation transistor T2 on the main surface of the substrate 1 and the orthographic projections of the first reset transistor T1 on the main surface of the substrate 1 both at least partially overlap. This, on the one hand, allows the area of ​​the storage capacitor to be further increased to increase the storage capacitance value without affecting the pixel design space and the PPI of the display substrate 10, thereby improving the compensation capability of the pixel capacitor for the pixel. On the other hand, it reduces the complexity of the film stack below the drive transistor T3 (Oxide TFT). In a display substrate, the connection lines near the drive transistor T3 are more dense and complex. Disposing the first and second electrodes of the storage capacitor Cst below the multiple control transistors is more conducive to pixel design, allowing the limited space to be used to rationally layout the various electrodes and lines, thereby improving the PPI of the display substrate 10.

[0119] Referring to Figure 8 , for example, the active layer T2a of the compensation transistor T2 and the active layer T1a of the first reset transistor T1 are both disposed on the same layer as the active layer T3a of the drive transistor T3, and are made of the same material, and can be formed through the same patterning process. The bottom gate T2g1 of the compensation transistor T2 and the bottom gate T1g1 of the first reset transistor T1 are both disposed on the same layer as the bottom gate T3g1 of the drive transistor T3. In other words, the active layers of the control transistors are all disposed on the same layer as the active layer T3a of the drive transistor T3. Each control transistor includes a bottom gate, and the bottom gates of the multiple control transistors are all disposed on the same layer as the bottom gate T3g1 of the drive transistor T3.

[0120] Referring to FIG8 , for example, the orthographic projection of the first electrode C1 of the storage capacitor Cst on the main surface of the substrate 1 is within the orthographic projection of the second electrode C2 of the storage capacitor Cst on the main surface of the substrate 1. The orthographic projections of the bottom gates of the multiple control transistors (e.g., the bottom gate T2g1 of the compensation transistor T2 and the bottom gate T1g1 of the first reset transistor T1) on the main surface of the substrate 1 are all within the orthographic projection of the first electrode C1 of the storage capacitor Cst on the main surface of the substrate 1. For example, the orthographic projections of the spacing between the multiple control transistors on the main surface of the substrate 1 are also within the orthographic projection of the storage capacitor Cst on the main surface of the substrate 1. For example, in FIG8 , the orthographic projection of the spacing between the compensation transistor T2 and the first reset transistor T1 on the main surface of the substrate 1 is within the orthographic projection of the storage capacitor Cst on the main surface of the substrate 1. Similarly, this ensures etching uniformity or CD uniformity of the storage capacitor Cst and the bottom gates of the multiple control transistors. Further, for example, the orthographic projection of the top gate of each control transistor (for example, the top gate T2g2 of the compensation transistor T2 and the top gate T1g2 of the first reset transistor T1) on the main surface of the substrate 1 is located within the range of the orthographic projection of the bottom gate of the control transistor (for example, the gate T2g1 of the compensation transistor T2 and the bottom gate T1g1 of the first reset transistor T1) on the main surface of the substrate 1.

[0121] Referring to Figure 8, for example, the bottom gate T3g1 of the driving transistor T3 is arranged in the same layer as the second electrode C2 of the storage capacitor Cst, and is located between the bottom gates of multiple control transistors and the first electrode C1 of the storage capacitor Cst. In this way, the relatively ample space in the conductive layer where the second electrode C2 of the storage capacitor Cst is located is utilized to set the bottom gate T3g1 of the driving transistor T3, reduce the electrode density of the conductive layer where the gate T2g1 of the compensation transistor T2 and the bottom gate T1g1 of the first reset transistor T1 are located, prevent short circuits and signal interference between electrodes that are too close, and rationally layout the structure of the pixel circuit.

[0122] Other features and technical effects of the embodiment shown in FIG8 are the same as those in FIG7 , and reference may be made to the description of FIG7 .

[0123] Figure 9 is a partial cross-sectional schematic diagram of another pixel circuit of a display substrate provided in at least one embodiment of the present disclosure. In Figure 9 , the compensation transistor T2 and the first reset transistor T1 are used as examples of control transistors. Of course, the control transistors are not limited to the compensation transistor T2 and the first reset transistor T1. In other embodiments, all transistors in the pixel circuit other than the drive transistor T3 may be control transistors, i.e., their active layers may be made of silicon semiconductor material.

[0124] The embodiment shown in FIG9 differs from the embodiment shown in FIG8 in the following ways. Referring to FIG9 , for example, the bottom gate T3g1 of the driving transistor T3 is arranged in the same layer as the second electrode C2 of the storage capacitor Cst, and the control transistor does not have a gate located between the layer where the second electrode C2 of the storage capacitor Cst is located and the active layer of the control transistor. Furthermore, for the driving transistor T3, in order to enhance its driving performance, the dual-gate structure is retained, and the bottom gate T3g1 of the driving transistor T3 is arranged in the same layer as the second electrode C2 of the storage capacitor Cst. In this way, the conductive layer where the bottom gate under the control transistor is located can be omitted, that is, the control transistor is a single-gate transistor. On the one hand, the process of the conductive layer where the bottom gate is located can be reduced, thereby reducing the production cost of the display substrate 10; on the other hand, by omitting the bottom gate under the control transistor, the metal wiring in the pixel area can be reduced, thereby improving the PPI of the display substrate 10.

[0125] Other features and technical effects of the embodiment shown in FIG9 are the same as those in FIG8 , and reference may be made to the description of FIG8 .

[0126] Figure 10 is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure. The embodiment shown in Figure 10 differs from the embodiment shown in Figure 3 in the following ways. Referring to Figure 10 , for example, the display substrate 10 further includes a second conductive layer SD2, which is located on a side of the first conductive layer SD1 away from the base substrate 1. The first connection electrode E1 can be located on the second conductive layer SD2. For example, the subpixel further includes a second connection electrode E2 electrically connected to the second electrode STd of the switching transistor of the scan drive circuit 01 and a third connection electrode E3 electrically connected to the second electrode T3d of the drive transistor T3. Both the second connection electrode E2 and the third connection electrode E3 are located on the second conductive layer SD2.

[0127] Other features and technical effects of the embodiment shown in FIG10 are the same as those in FIG3 , and reference may be made to the description of FIG3 .

[0128] FIG11 is a partial cross-sectional diagram of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure. The embodiment shown in FIG11 differs from the embodiment shown in FIG10 in the following ways. In Figure 11, the second via hole V2 penetrates the active layer T3a of the driving transistor T3 along a direction perpendicular to the main surface of the substrate substrate 1, and the sixth via hole V6 penetrates the active layer T3a of the driving transistor T3 along a direction perpendicular to the main surface of the substrate substrate 1. The first electrode T3s of the driving transistor T3 includes a first intra-hole portion PIV1 located in the second via hole V2, and the second electrode T3d of the driving transistor T3 includes a second intra-hole portion PIV2 located in the sixth via hole V6; the side surface of the first intra-hole portion PIV1 contacts the active layer T3a of the driving transistor T3 to be electrically connected to the active layer T3a of the driving transistor T3, and the side surface of the second intra-hole portion PIV2 contacts the active layer T3a of the driving transistor T3 to be electrically connected to the active layer T3a of the driving transistor T3; the surface where the side surface of the first intra-hole portion PIV1 is located intersects with the surface where the main surface of the substrate substrate 1 is located, and the surface where the side surface of the second intra-hole portion PIV2 is located intersects with the surface where the main surface of the substrate substrate 1 is located. FIG11 uses a side-strap method to electrically connect the first electrode T3s and the second electrode T3d of the driving transistor T3 to the active layer T3a of the driving transistor T3, respectively. In contrast, FIG10 uses a bottom-strap method to electrically connect the first electrode T3s and the second electrode T3d of the driving transistor T3 to the active layer T3a of the driving transistor T3, respectively.

[0129] FIG12 is a schematic diagram of a display device provided in accordance with an embodiment of the present disclosure. Referring to FIG12 , at least one embodiment of the present disclosure further provides a display device 100, comprising any one of the display substrates 10 provided in accordance with the present disclosure. The display device may be, for example, a display panel, or any product or component with a display function, such as a monitor, an OLED panel, an OLED TV, electronic paper, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, or a navigation system. Of course, the display devices provided in accordance with the present disclosure are not limited to the types listed above.

[0130] Accordingly, the display panel and display device provided by the embodiments of the present disclosure both have the technical effects of the pixel circuit and display substrate provided by the embodiments of the present disclosure.

[0131] At least one embodiment of the present disclosure also provides a method for manufacturing a display substrate, which includes: forming sub-pixels, including forming a pixel circuit of the sub-pixel, wherein the pixel circuit includes a light-emitting device and a driving transistor T3, and the driving transistor T3 is configured to control the magnitude of the driving current flowing through the light-emitting device according to a data signal; and forming the pixel circuit also includes a data transistor T4, wherein the data transistor T4 is configured to write a data signal into a first electrode of the driving transistor T3 in response to the data driving signal; the material of the active layer T3a of the driving transistor T3 is a metal oxide semiconductor material, and the material of the active layer of the data transistor T4 is a silicon semiconductor material.

[0132] For example, a method for manufacturing the display substrate 10 includes providing a base substrate 1, and forming various structures of the above-mentioned pixel circuit on a main surface of the base substrate 1. The method for manufacturing the display substrate includes forming a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, and a fifth via hole V5 through a single patterning process.

[0133] 13A to 13C are schematic diagrams of a method for manufacturing a display substrate according to an embodiment of the present disclosure, and the method is described using the manufacturing method of the display substrate 10 shown in FIG.

[0134] 13A , a base substrate BS is provided, and a first flexible layer PI1, a first barrier layer Barrier1, a second flexible layer PI2, a second barrier layer Barrier2, a first buffer layer Buffer1, an active layer T3a of a driving transistor T3, an active layer T2a of a compensation transistor T2, a first gate insulating layer GI1, a first electrode C1 of a storage capacitor Cst, a second gate insulating layer GI2, a first electrode C2 of the storage capacitor Cst, a bottom gate T2g1 of the compensation transistor T2, a first interlayer insulating layer ILD1, and a second buffer layer Buffer2, a bottom gate T3g1 of the driving transistor T3, a top gate T3g2 of the driving transistor T3, and a top gate T2g2 of the compensation transistor T2 are formed on the base substrate BS.

[0135] Then, referring to FIG. 13B , the first via hole V1 , the second via hole V2 , the third via hole V3 , the fourth via hole V4 , the fifth via hole V5 , the sixth via hole V6 , the seventh via hole V7 and the eighth via hole V8 are formed through a patterning process.

[0136] For example, the manufacturing method further includes, after forming the above-mentioned via holes, etching the surface of the active layer T3a of the driving transistor T3 exposed by the second via hole V2 and the sixth via hole V6 to remove the oxide layer on the surface of the active layer T3a of the driving transistor T3 exposed by the second via hole V2 and the sixth via hole V6, thereby reducing the contact resistance of the exposed surface.

[0137] Then, referring to Figure 13C, the above-mentioned electrodes located in the second conductive layer SD2 are formed through a composition process, and the electrodes include the first electrode T3s and the second electrode T3d of the driving transistor T3, the first electrode T2s and the second electrode T2d of the compensation transistor T2, the first electrode STs and the second electrode STd of the switching transistor ST of the scan driving circuit 01, and the first connecting electrode E1. The first electrode T3s of the driving transistor T3 is electrically connected to the active layer T3a of the driving transistor T3 through the first via V1, and is electrically connected to the bottom gate T3g1 of the driving transistor T3 through the second via V2. The second electrode T3d of the driving transistor T3 is electrically connected to the active layer T3a of the driving transistor T3 through the sixth via V6; the first electrode T2s and the second electrode T2d of the compensation transistor T2 are electrically connected to the active layer T2a of the compensation transistor T2 through the seventh via V7 and the eighth via V8, respectively; the first electrode STs and the second electrode STd of the switching transistor ST of the scan driving circuit O1 are electrically connected to the active layer STa of the switching transistor ST of the scan driving circuit O1 through the third via V3 and the fourth via V4, respectively; the first connection electrode E1 is electrically connected to the driving circuit board IC and to the signal line extending to the display area, and the first connection electrode E1 is at least partially located in the fifth via V5.

[0138] The display substrates provided in other embodiments can also be manufactured by similar methods.

[0139] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the scope defined in the claims.

Claims

1. A display substrate, comprising sub-pixels, wherein: The sub-pixel includes a pixel circuit, the pixel circuit includes a light-emitting device and a driving transistor, the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device according to a data signal; The pixel circuit further includes a data transistor configured to write the data signal into a first electrode of the drive transistor in response to a data drive signal; The material of the active layer of the driving transistor is a metal oxide semiconductor material, and the material of the active layer of the data transistor is a silicon semiconductor material.

2. The display substrate according to claim 1, wherein: The display substrate further comprises a base substrate, and the pixel circuit is arranged on a main surface of the base substrate; The pixel circuit further comprises a storage capacitor, a first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and a second electrode of the storage capacitor is electrically connected to the first power supply voltage terminal to receive the first power supply voltage; The gate of the driving transistor comprises a bottom gate, and in a direction perpendicular to the main surface of the substrate, the bottom gate of the driving transistor is located on a side of the active layer of the driving transistor close to the substrate; The first electrode of the storage capacitor, the second electrode of the storage capacitor and the bottom gate of the driving transistor are all arranged in different layers, and the first electrode of the storage capacitor and the second electrode of the storage capacitor are both located on a side of the active layer of the driving transistor close to the substrate.

3. The display substrate according to claim 2, wherein: The pixel circuit further comprises a control transistor, a first electrode of the control transistor is electrically connected to a gate of the driving transistor, and a material of an active layer of the control transistor is the metal oxide semiconductor material; The pixel circuit comprises a first reset transistor, wherein the first reset transistor is configured to write a first reset signal to a gate of the driving transistor under the control of a first reset control signal; The pixel circuit further includes a compensation transistor configured to compensate a signal applied to a gate of the driving transistor in response to a compensation scan signal and the data signal; The control transistor includes at least one of the first reset transistor and the compensation transistor, and the active layer of at least one of the first reset transistor and the compensation transistor is a material is the metal oxide semiconductor material.

4. The display substrate according to claim 3, wherein: The gate of the driving transistor further comprises a top gate, wherein the top gate is located on a side of the active layer of the driving transistor away from the substrate in a direction perpendicular to the main surface of the substrate; A first electrode of the storage capacitor is electrically connected to a top gate of the driving transistor, and a second electrode of the storage capacitor is electrically connected to the first power supply voltage terminal.

5. The display substrate according to any one of claims 3 to 4, wherein: An orthographic projection of the storage capacitor on the main surface of the base substrate at least partially overlaps with an orthographic projection of the driving transistor on the main surface of the base substrate.

6. The display substrate according to claim 5, wherein: The first electrode of the storage capacitor is located on a side of the second electrode of the storage capacitor close to the substrate, the orthographic projection of the first electrode of the storage capacitor on the main surface of the substrate is located within the orthographic projection range of the second electrode of the storage capacitor on the main surface of the substrate, and the orthographic projection of the bottom gate of the driving transistor on the main surface of the substrate is located within the orthographic projection range of the first electrode of the storage capacitor on the main surface of the substrate.

7. The display substrate according to claim 6, wherein: The gate of the driving transistor further comprises a top gate, and the top gate of the driving transistor is in a direction perpendicular to the main surface of the substrate, and the top gate of the driving transistor is located on a side of the active layer of the driving transistor away from the substrate; The orthographic projection of the top gate of the driving transistor on the main surface of the base substrate is located within the orthographic projection range of the bottom gate of the driving transistor on the main surface of the base substrate.

8. The display substrate according to any one of claims 3 to 7, wherein: The active layer of the control transistor is arranged in the same layer as the active layer of the drive transistor; The control transistor includes a bottom gate, and the bottom gate of the control transistor is arranged in the same layer as the second electrode of the storage capacitor, or, The bottom gate of the control transistor is arranged in the same layer as the bottom gate of the drive transistor.

9. The display substrate according to any one of claims 3 to 5, wherein: The orthographic projection of the storage capacitor on the main surface of the base substrate does not overlap with the orthographic projection of the driving transistor on the main surface of the base substrate and the orthographic projection of the control transistor on the main surface of the base substrate.

10. The display substrate according to any one of claims 3 to 5, wherein: An orthographic projection of the storage capacitor on the main surface of the substrate at least partially overlaps with an orthographic projection of the control transistor on the main surface of the substrate.

11. The display substrate according to claim 10, wherein: The active layer of the control transistor is arranged in the same layer as the active layer of the drive transistor; The control transistor comprises a bottom gate, and the bottom gate of the control transistor is arranged in the same layer as the bottom gate of the driving transistor; The orthographic projection of the first electrode of the storage capacitor on the main surface of the substrate is located within the range of the orthographic projection of the second electrode of the storage capacitor on the main surface of the substrate, and the orthographic projection of the bottom gate of the control transistor on the main surface of the substrate is located within the range of the orthographic projection of the first electrode of the storage capacitor on the main surface of the substrate.

12. The display substrate according to claim 11, wherein: The gate of the control transistor further comprises a top gate, and in a direction perpendicular to the main surface of the substrate, the top gate of the control transistor is located on a side of the active layer of the control transistor away from the substrate; The orthographic projection of the top gate of the control transistor on the main surface of the substrate is located within the orthographic projection range of the bottom gate of the control transistor on the main surface of the substrate.

13. The display substrate according to any one of claims 3 to 5, wherein: The orthographic projection of the storage capacitor on the main surface of the substrate at least partially overlaps with the orthographic projection of the drive transistor on the main surface of the substrate and the orthographic projection of at least one of the control transistors on the main surface of the substrate.

14. The display substrate according to claim 13, wherein: The active layer of the control transistor is arranged in the same layer as the active layer of the drive transistor; The control transistor comprises a bottom gate, and the bottom gate of the control transistor is arranged in the same layer as the bottom gate of the driving transistor; The orthographic projection of the first electrode of the storage capacitor on the main surface of the substrate is located within the orthographic projection range of the second electrode of the storage capacitor on the main surface of the substrate, and the orthographic projection of the bottom gate of the driving transistor on the main surface of the substrate and the orthographic projection of the bottom gate of the control transistor on the main surface of the substrate are both located within the orthographic projection range of the first electrode of the storage capacitor on the main surface of the substrate.

15. The display substrate according to claim 13 or 14, wherein: The orthographic projection of the interval between the driving transistor and the control transistor on the main surface of the base substrate is located within the orthographic projection range of the storage capacitor on the main surface of the base substrate.

16. The display substrate according to any one of claims 3 to 5, wherein: The orthographic projection of the storage capacitor on the main surface of the base substrate does not overlap with the orthographic projection of the driving transistor on the main surface of the base substrate, and at least partially overlaps with the orthographic projections of the plurality of control transistors on the main surface of the base substrate.

17. The display substrate according to claim 16, wherein: The active layers of the plurality of control transistors are arranged in the same layer as the active layer of the driving transistor; Each of the control transistors comprises a bottom gate, and the bottom gates of the control transistors and the bottom gates of the driving transistor are arranged in the same layer; The orthographic projection of the first electrode of the storage capacitor on the main surface of the substrate is located within the range of the orthographic projection of the second electrode of the storage capacitor on the main surface of the substrate, and the orthographic projections of the bottom gates of the plurality of control transistors on the main surface of the substrate are all located within the range of the orthographic projection of the first electrode of the storage capacitor on the main surface of the substrate.

18. The display substrate according to any one of claims 2 to 17, wherein: The second electrode of the storage capacitor is located between the first electrode of the storage capacitor and the bottom gate of the driving transistor.

19. The display substrate according to claim 10 or 16, wherein: The bottom gate of the driving transistor is arranged in the same layer as the second electrode of the storage capacitor, and is located between the bottom gates of the plurality of control transistors and the first electrode of the storage capacitor.

20. The display substrate according to claim 10 or 16, wherein: The bottom gate of the driving transistor is arranged in the same layer as the second electrode of the storage capacitor, and the control transistor does not have a gate located between the layer where the second electrode of the storage capacitor is located and the active layer of the control transistor.

21. The display substrate according to any one of claims 2 to 20, wherein: The first electrode of the driving transistor is located on a side of the active layer of the driving transistor away from the substrate, and the first electrode of the driving transistor is electrically connected to the active layer of the driving transistor through a first via hole, and is electrically connected to the bottom gate of the driving transistor through a second via hole.

22. The display substrate according to any one of claims 2 to 21, wherein: The pixel circuit further includes a switch transistor, and the material of the active layer of the switch transistor of the pixel circuit is the silicon semiconductor material; in a direction perpendicular to the main surface of the substrate, the active layer of the switch transistor of the pixel circuit is located on a side of the storage capacitor close to the substrate; or, The active layers of all transistors in the pixel circuit are made of metal oxide semiconductor material.

23. The display substrate according to any one of claims 2 to 22, wherein: The base substrate comprises a display area and a non-display area at least partially surrounding the display area, the display substrate further comprises a scan drive circuit located in the non-display area, the scan drive circuit comprises a switch transistor, and the scan drive circuit is configured to provide a drive scan signal to a pixel circuit in the display area; in a direction perpendicular to the main surface of the base substrate, an active layer of the switch transistor of the scan drive circuit is located on a side of the storage capacitor close to the base substrate; The material of the active layer of the switch transistor of the scan driving circuit is the silicon semiconductor material; The first electrode and the second electrode of the switch transistor of the scan driving circuit are electrically connected to the active layer of the switch transistor of the scan driving circuit through the third via hole and the fourth via hole, respectively.

24. The display substrate according to any one of claims 2 to 23, wherein: The base substrate includes a display area and a non-display area at least partially surrounding the display area, the display substrate also includes a portion located in the non-display area, the display substrate has a bending portion located in the non-display area, the bending portion includes a driving circuit board and a connecting wire, the connecting wire is electrically connected to the driving circuit board and is electrically connected to a signal line extending to the display area, the signal line is electrically connected to the pixel circuit to provide a display signal to the pixel circuit; The display substrate is a flexible display substrate, including a flexible organic layer and an inorganic insulating layer, the inorganic insulating layer and the flexible organic layer are stacked on the main surface of the base substrate, and are located on the side of the flexible organic layer away from the base substrate, the inorganic insulating layer includes a first sub-inorganic layer located between the first electrode and the second electrode of the storage capacitor, and a second sub-inorganic layer located between the second electrode of the storage capacitor and the bottom gate of the driving transistor; the display substrate includes at least a fifth via hole penetrating the inorganic insulating layer, and the connecting wiring is at least partially located in the fifth via hole.

25. A display device comprising the display substrate according to any one of claims 1-24.

26. A method for manufacturing a display substrate, comprising: The method comprises forming a sub-pixel, wherein the sub-pixel circuit comprises a light emitting device and a driving transistor, wherein the driving transistor is configured to control the light flowing through the sub-pixel according to a data signal. The magnitude of the driving current of the light emitting device; and The pixel circuit further includes a data transistor, wherein the data transistor is configured to write the data signal into the first electrode of the drive transistor in response to a data drive signal; The material of the active layer of the driving transistor is a metal oxide semiconductor material, and the material of the active layer of the data transistor is a silicon semiconductor material.

27. The method for manufacturing a display substrate according to claim 26, comprising: Providing a base substrate, and forming the pixel circuit on the main surface of the base substrate, wherein forming the pixel circuit further comprises forming a storage capacitor; a first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and a second electrode of the storage capacitor is electrically connected to a first power supply voltage terminal to receive the first power supply voltage; the gate of the driving transistor comprises a bottom gate, and in a direction perpendicular to the main surface of the base substrate, the bottom gate of the driving transistor is located on a side of the active layer of the driving transistor close to the base substrate; The first electrode of the storage capacitor, the second electrode of the storage capacitor and the bottom gate of the driving transistor are all arranged in different layers, and the first electrode of the storage capacitor and the second electrode of the storage capacitor are both located on a side of the active layer of the driving transistor close to the base substrate; The first electrode of the driving transistor is located on a side of the active layer of the driving transistor away from the substrate, the first electrode of the driving transistor is electrically connected to the active layer of the driving transistor through a first via hole, and is electrically connected to the bottom gate of the driving transistor through a second via hole; The base substrate comprises a display area and a non-display area at least partially surrounding the display area, the display substrate further comprises a scan drive circuit located in the non-display area, the scan drive circuit comprises a switch transistor, and the scan drive circuit is configured to provide a drive scan signal to a pixel circuit in the display area; in a direction perpendicular to the main surface of the base substrate, an active layer of the switch transistor of the scan drive circuit is located on a side of the storage capacitor close to the base substrate; a first electrode and a second electrode of the switch transistor of the scan drive circuit are electrically connected to the active layer of the switch transistor of the scan drive circuit through a third via hole and a fourth via hole, respectively; The display substrate has a bending portion located in the non-display area, the bending portion includes a driving circuit board and a connecting wire, the connecting wire is electrically connected to the driving circuit board and is electrically connected to a signal line extending to the display area, and the signal line is electrically connected to the pixel circuit to provide a display signal to the pixel circuit; The display substrate is a flexible display substrate, comprising a flexible organic layer and an inorganic insulating layer, wherein the inorganic insulating layer and the flexible organic layer are stacked on the main surface of the base substrate and are located on a side of the flexible organic layer away from the base substrate, and the inorganic insulating layer comprises a first sub-inorganic layer located between the first electrode and the second electrode of the storage capacitor, and a second sub-inorganic layer located between the second electrode of the storage capacitor and the bottom gate of the driving transistor; the display substrate comprises a fifth via hole at least penetrating the inorganic insulating layer, and the connecting wire is at least partially located in the fifth via hole; The production method comprises: The first via hole, the second via hole, the third via hole, the fourth via hole and the fifth via hole are formed by one patterning process.

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