System and method for enhancing stability of HBM and DDR memories

Abstract

The invention discloses a system and method for enhancing HBM and DDR memory stability, and the method comprises the steps: enabling a DDR memory module to be connected with a super capacitor module, and obtaining a memory voltage value, a capacitor voltage value and capacitance in real time; the super-capacitor is powered and charged by the system when the system works normally, and when a power supply abnormal event is detected, the power supply of the main power supply to the DDR memory is switched into the power supply of the super-capacitor to provide enough power for the memory, so that the normal work of the memory is ensured. The invention aims to solve the problems of data loss caused by charge leakage of a DRAM, high cost of a battery backup scheme, complex maintenance, slow response speed, incapability of accurately supplying power to DDR memories with different frequencies and rates and the like.

Description

Technical Field

[0001] This application relates to the technical field of memories, and more particularly, to a technology for power supply and data stability of a high bandwidth memory (HBM) and a double data rate (DDR) memory device memory module. Background Art

[0002] With the rapid development of computer technology, the performance requirements for memories are getting higher and higher, especially in the fields of high-performance computing, artificial intelligence, and big data processing. High bandwidth memories (HBMs) and double data rate (DDR) memories are widely used in these fields due to their high bandwidth and low latency characteristics. However, the stability problem of memories in the case of power failure remains an urgent challenge to be solved.

[0003] Existing technical solutions have many deficiencies in dealing with power anomalies, such as data loss caused by DRAM leakage charge, high cost and complex maintenance of battery backup solutions, slow response speed, and inability to accurately supply power to DDR memories with different frequencies and rates.

[0004] Therefore, it is of great practical significance to develop a memory stability enhancement solution that can effectively solve these problems. Summary of the Invention

[0005] The purpose of this application is to provide a system and method for enhancing the stability of HBM and DDR memories to improve problems such as data loss caused by DRAM leakage charge, high cost and complex maintenance of battery backup solutions, slow response speed, and inability to accurately supply power to DDR memories with different frequencies and rates.

[0006] To solve the above technical problems, this application adopts the following technical solutions: A system for enhancing the stability of HBM and DDR memories, characterized by comprising: A DDR inner layer module, including a plurality of DDR memory main chips, and the DDR inner layer module is connected to the main power supply to obtain power supply in the normal working state; A supercapacitor module, including a supercapacitor with a capacitance of ≥1000 farads, connected to the DDR inner layer module through a voltage pin, setting a P-channel MOSFET as the charging switch of the supercapacitor, and configuring another N-channel MOSFET as the discharging switch between the positive pole of the supercapacitor and the system power input; Monitoring device, comprising: a first type of voltage sensor, which is arranged on each DDR memory main chip in one-to-one correspondence to form a plurality of parallel connections for obtaining the memory voltage value in real time; a second type of voltage sensor, which is connected to the super capacitor in a plurality of parallel ways for obtaining the capacitance value and voltage of the super capacitor in real time; a capacitance meter, which is connected to the super capacitor in a plurality of parallel ways for obtaining the capacitance; a voltage detection comparator, which is connected to the gate of the P-channel MOSFET for monitoring the main power supply voltage and controlling the discharge switch to turn on and keep the charging switch off when the main power supply loses power, so as to realize the fast switching from the main power supply to the super capacitor for power supply to the DDR inner layer module; Power management module, which is connected to the main power supply through the system power supply and supplies power to each module.

[0007] In the above technical solution, a filter voltage stabilization circuit is also arranged in the super capacitor module, including an LC filter circuit and a linear voltage regulator or a switching voltage regulator connected after the main power supply.

[0008] In the above technical solution, a sliding rheostat is connected between the main power supply and the filter voltage stabilization circuit.

[0009] In the above technical solution, in the super capacitor module, a charging resistor is connected in series with the super capacitor between the P-channel MOSFET and the super capacitor.

[0010] In the above technical solution, in the super capacitor module, a linear voltage regulator is arranged on the circuit connecting the rear of the discharge switch and the DDR inner layer module to stabilize the output voltage.

[0011] In the above technical solution, a lithium battery is used instead of the super capacitor.

[0012] A method for enhancing the stability of HBM and DDR memory, characterized in that: Connect the DDR memory module to the super capacitor module, and obtain the memory voltage value, the capacitor voltage value and the capacitance in real time; The super capacitor is charged when the system is working normally. When a power supply abnormal event is detected, the power supply to the DDR memory is switched from the main power supply to the super capacitor discharging to provide sufficient power for the memory to ensure that the memory can work normally. In the above technical solution, when the memory voltage value is lower than 85% or 95% of the nominal value, it is regarded as detecting a power supply abnormal event.

[0013] In the above technical solution, the frequencies of the voltage values of the first type of voltage sensor and the second type of voltage sensor are obtained in sequence, then the obtained memory voltage value V DDR = (V1×M1 + V2×M2 + V3×M3 +... + Vn×Mn) / n; the capacitor voltage value V F= (U1×P1 + U2×P2 + U3×P3 + … + Un×Pn) / n; Capacitance F = (F1×P1 + F2×P2 + F3×P3 + … + Fn×Pn) / n; where, the frequencies of the values V1, V2, V3…Vn of N first-class voltage sensors are M1, M2, M3…Mn times in sequence; the frequencies of the values U1, U2, U3…Un of N second-class voltage sensors are P1, P2, P3…Pn times; F1, F2…Fn are the measured values of each capacitance meter respectively.

[0014] In the above technical solution, when the capacitance < 85% of the nominal value of the supercapacitor or it cannot be charged, switch to the backup capacitor in time to keep the supercapacitor in the best capacitance state all the time; when 85% of the nominal value < the current capacitance < 95% of the nominal value, charge the supercapacitor in time to keep the supercapacitor in the best capacitance state all the time; stop charging when the supercapacitor is full.

[0015] In summary, the technical solution of the present invention realizes the improvement of the stability of the memory under power-off conditions through the collaborative work of the supercapacitor module, the power management module, the monitoring module and the control unit. The supercapacitor module provides instantaneous power support when the power supply is abnormal, and the monitoring module and the control unit are responsible for real-time monitoring.

[0016] The key improvement points of the present invention include using a supercapacitor to provide short-time power support, real-time monitoring and dynamic adjustment, and identifying different frequencies of DDR to perform precise power supply of specified voltage values.

[0017] Compared with the existing technologies, the beneficial effects of the present invention are as follows: 1. Improve data security: Especially in the scenario where the DDR inner layer is used as the cache of the SSD, a supercapacitor is used as the power supply device after the DDR power-off to provide more power and time support to flush the data (mapping table + user data) in the DRAM to the SSD. 2. Reduce costs: Compared with the traditional battery backup solution, the present invention uses a supercapacitor, which has lower costs and simpler maintenance. 3. Quick response: Through the supercapacitor module circuit composed of a charging switch and a discharging switch, it can quickly respond when the power supply is abnormal, supply power to the memory in time, and make the DDR work stably. 4. Since multiple first-class voltage sensors can be set, different frequencies of DDR can be accurately identified, and precise power supply with specified voltage values can be performed for different DDRs.

[0018] 5. The power supply of the supercapacitor can be dynamically adjusted through the second-class voltage sensor, improving the effectiveness of the stability of DDR data. 6. A lithium battery can be adaptively used instead of the supercapacitor: Although the cost is higher, it can provide longer power support. Description of the Drawings

[0019] To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0020] Figure 1 It is a connection block diagram of the DDR memory module and the supercapacitor module for the embodiments of the present application.; Figure 2 It is a circuit diagram for the embodiments of the present application.

[0021] Figure 3 It is a general system structure block diagram of the present application. Detailed Embodiments

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. The components of the embodiments of the present application usually described and shown in the drawings here can be arranged and designed in various different configurations.

[0023] The features and performance of the present application will be further described in detail below in conjunction with the embodiments.

[0024]

Embodiment 1

[0025] (1) The structure of the supercapacitor module 2 is as Figures 1-3 shown:[[]] Installing the supercapacitor 26 near the DDR memory module 1 can quickly charge and discharge, providing short-term power support. The supercapacitor 26 charges when the system is working normally. When a power anomaly event is detected, it can immediately provide sufficient power for the DDR memory module 1 to ensure that the memory can work properly. The specific structure description is as follows:[[]] Main power supply 21: The main power supply 21 circuit inputs from the AC power supply (voltage range 110V - 220V) of the power management module 5.

[0026] Filtering and Voltage Regulation: After the main power supply 21, an LC filter circuit 22 and a linear voltage regulator or a switching voltage regulator 23 are connected to ensure a clean and stable voltage is provided for the subsequent circuits.

[0027] Charge Control: A P-channel MOSFET 25 is used as the charging switch for the supercapacitor 26. The gate is controlled by a charge controller or a simple comparator circuit that monitors the supercapacitor voltage and turns off the MOSFET when the set threshold is reached to prevent overcharging. A large resistor is added as the charging resistor 28 in series with the supercapacitor 26 to achieve initial current-limiting soft start, and then the charge controller precisely controls the charging rate.

[0028] Supercapacitor 26: A supercapacitor with a high farad value is selected, such as a supercapacitor with a capacitance of ≥1000 farads, to store sufficient energy for use during power outages.

[0029] The positive and negative terminals of the supercapacitor 26 are respectively connected to the source of the above-mentioned MOSFET 25 and the ground wire.

[0030] Discharge Path: Another N-channel MOSFET is configured as the discharge switch between the positive terminal of the supercapacitor 26 and the system power input. It is usually controlled by a voltage monitoring comparator and quickly turns on when the main power failure is detected, allowing the supercapacitor 26 to supply power to the subsequent circuits. A linear voltage regulator 23 can be connected in the discharge path to ensure that the output voltage meets the requirements of the subsequent circuits.

[0031] Power Monitoring and Switching Logic: The voltage monitoring comparator continuously checks the status of the main power supply 21. Once the voltage is detected to be lower than the preset threshold (such as 95% or 85% of the nominal value, or a certain range thereof), the N-channel discharge MOSFET is immediately controlled to turn on through the logic circuit, and the P-channel charging MOSFET is kept off, realizing a fast switch from the main power supply to the power supply of the supercapacitor 26.

[0032] (2) The structure of the power management module 5 is as Figure 1 and Figure 3 shown, and it is used to supply power to all modules of the system.

[0033] The main power supply 21 is connected with 220V AC power supply, and a sliding rheostat 27 with a resistance range of 1Ω~10MΩ is connected in the middle to protect the circuit and ensure that the monitoring module 4 and the FPGA control unit 3 are always powered during the operation of the entire system.

[0034] (3) Two types of sensors are set in the monitoring module 4, as Figure 1 shown: The first type of sensor: In the DDR memory module 1, multiple DDR main chips 11 are connected in parallel. On each DDR main chip 11, 1 voltage sensor 12 is installed in series respectively, with a total of N voltage sensors 12, where N represents natural numbers 1, 2, 3....n, to monitor the memory voltage in real time and detect the voltage value V DDR The calculation of

[0035] is represented by the weighted average. That is, if the frequencies of the values V1, V2, V3…Vn of the N voltage sensors appear as M1, M2, M3…Mn times in sequence, then the detected voltage value V DDR = (V1×M1 + V2×M2 + V3×M3 + … + Vn×Mn) / n.

[0036] Data acquisition: The analog signal of the voltage sensor 12 is converted into a digital signal through an ADC (analog-to-digital converter) and transmitted to the FPGA control unit 3.

[0037] The second type of sensor: N measurement sensors are installed in parallel on the supercapacitor 26, where N represents natural numbers 1, 2, 3....n. In each measurement sensor, N measuring gauges for measuring capacitance and voltage sensors are connected in series to monitor the capacitance value and voltage of the supercapacitor 26 in real time. The voltage value V F of the capacitance is represented by the weighted average: if the frequencies of the values U1, U2, U3…Un of the second type of voltage sensors appear as P1, P2, P3…Pn times, the voltage value V F = (U1×P1 + U2×P2 + U3×P3 + … + Un×Pn) / n. The capacitance value F = (F1×P1 + F2×P2 + F3×P3 + … + Fn×Pn) / n.

[0038] (IV) Control unit A microcontroller or FPGA is used as the control unit, which is responsible for monitoring the working state of the DDR memory module 1. When it is found that the farad value of the supercapacitor 26 is lower than the first threshold (such as 85% of the nominal value), or the capacitor cannot be charged, a red light alarm is given and it is switched to the backup capacitor to ensure that the capacitor is always in the best power supply state. When it is found that the first threshold < the farad value of the supercapacitor < the second threshold (such as 95% or 85% of the nominal value, or the end range thereof), the capacitor is immediately charged to ensure that the capacitor is always in the best power supply state. When it is found that the farad value of the supercapacitor reaches the third threshold (such as 100% of the nominal value), the charging of the capacitor is immediately stopped to ensure that the capacitor is always in the best power supply state.

[0039]

Embodiment 2

[0040] Combine the capacitance value and voltage value of the capacitor to charge and cut off the power of the capacitor. When it is found that the farad value of the supercapacitor is lower than the first threshold (such as 85% of the nominal value), or the capacitor cannot be charged, a red light alarm is issued and switched to the backup capacitor to ensure that the capacitor is always in the best power supply state.

[0041] When it is found that the first threshold < the farad value of the supercapacitor < the second threshold (such as 95% of the nominal value), immediately charge the capacitor to ensure that the capacitor is always in the best power supply state.

[0042] When it is found that the farad value of the supercapacitor reaches the third threshold (such as 100% of the nominal value), immediately stop charging the capacitor to ensure that the capacitor is always in the best power supply state. (5) Process to enhance DDR stability Under normal working conditions, the control unit regularly monitors the memory status. If a power supply anomaly is detected, immediately enable the supercapacitor to supply power to the memory.

Example 3

[0043] 3. Monitoring module (1)Sensor selection: Install a voltage sensor (which can be done in the manner of Embodiment 1) to monitor the working status of the memory in real time. Ensure that the sensor can respond quickly and transmit data to the control unit. (2)Data acquisition: Convert the analog signal of the sensor into a digital signal through an ADC (Analog-to-Digital Converter) and transmit it to the control unit for processing. 4. Control unit (1)Hardware selection: Adopt a high-performance microcontroller or FPGA as the control unit, which is responsible for monitoring the memory status and the supercapacitor module. 5. Process to protect DDR stability (1)Normal working state: The control unit continuously monitors the status and voltage of the memory. The control unit continuously monitors the status of the supercapacitor, including the capacitance value and voltage, to keep it in the best state at all times (sufficient capacitance value and normal voltage). (2)Power anomaly detection: The control unit monitors the power supply status in real time. When it detects a drop in the power supply voltage or a power outage, it immediately activates the supercapacitor to provide power support for the memory. When it is found that the farad value of the supercapacitor is lower than the first threshold (such as 85% of the nominal value), or the capacitor cannot be charged, a red light alarm is given and it switches to the backup capacitor to ensure that the capacitor is always in the best power supply state.

[0044] When it is found that the first threshold < the farad value of the supercapacitor < the second threshold (such as 95% of the nominal value), immediately charge the capacitor to ensure that the capacitor is always in the best power supply state.

[0045] When it is found that the farad value of the supercapacitor reaches the third threshold (such as 100% of the nominal value), immediately stop charging the capacitor to ensure that the capacitor is always in the best power supply state. The embodiments described above are some, but not all, of the embodiments of the present application. The detailed description of the embodiments of the present application is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

Claims

1. A system for enhancing the stability of HBM and DDR memory, characterized in that include: DDR inner module, including several DDR memory master chips, the DDR inner module is connected to the main power supply to obtain power supply in normal working state; The supercapacitor module includes a supercapacitor with a capacity of ≥1000 farads, connected to the DDR inner module through a voltage pin, a P-channel MOSFET is set as a charging switch of the supercapacitor, and another N-channel MOSFET is configured between the positive electrode of the supercapacitor and the system power input as a discharge switch; The monitoring device includes: a first type of voltage sensor, which is arranged on each DDR memory main chip in a one-to-one correspondence to form a plurality of parallel structures, and is used to obtain the memory voltage value in real time; a second type of voltage sensor, which is connected to a super capacitor in a plurality of parallel ways, and is used to obtain the voltage of the super capacitor in real time; a capacitance meter, which is connected to the super capacitor in a plurality of parallel ways to obtain the capacitance; a voltage detection comparator, which is connected to the gate of a P-channel MOSFET and is used to monitor the main power supply voltage and control the discharge switch to be turned on and the charging switch to be turned off when the main power supply is powered off, so as to realize the rapid switching from the main power supply to the DDR inner module to the super capacitor power supply; The power management module is connected to the main power supply through the system power supply and supplies power to each module.

2. The system for enhancing HBM and DDR memory stability according to claim 1, characterized in that A filtering and voltage stabilizing circuit is also provided in the supercapacitor module, including an LC filtering circuit and a linear voltage regulator or a switching voltage regulator connected after the main power supply.

3. The system for enhancing HBM and DDR memory stability according to claim 1, characterized in that A sliding rheostat is connected between the main power supply and the filtering and voltage stabilizing circuit.

4. The system for enhancing HBM and DDR memory stability according to claim 1, characterized in that In the supercapacitor module, a charging resistor is arranged between the P-channel MOSFET and the supercapacitor and is connected in series with the supercapacitor.

5. The system for enhancing HBM and DDR memory stability according to claim 1, characterized in that In the supercapacitor module, a linear regulator is provided on the circuit connecting the DDR inner module behind the discharge switch to stabilize the output voltage.

6. The system for enhancing HBM and DDR memory stability according to claim 1, characterized in that Use lithium batteries instead of supercapacitors.

7. A method for enhancing the stability of HBM and DDR memory, characterized in that: Connect the DDR memory module to the supercapacitor module to obtain the memory voltage value, capacitor voltage value and capacitance in real time; The supercapacitor is charged by the system power supply when the system is working normally. When a power abnormality event is detected, the main power supply to the DDR memory is switched to the supercapacitor to discharge to provide sufficient power for the memory, ensuring that the memory can work normally.

8. The method for enhancing the stability of HBM and DDR memory according to claim 7, characterized in that: When the memory voltage value is lower than 85% or 95% of the nominal value, it is considered that a power abnormality event is detected.

9. The method for enhancing the stability of HBM and DDR memory according to claim 7, characterized in that: The frequency of occurrence of each voltage value of the first type voltage sensor and the second type voltage sensor is obtained in sequence, and the memory voltage value V is obtained. DDR = (V1×M1+V2×M2+V3×M3+…+Vn×Mn) / n; capacitor voltage value V F = (U1×P1+U2×P2+U3×P3+…+Un×Pn) / n; capacitance F= (F1×P1+F2×P2+F3×P3+…+Fn×Pn) / n; among them, the values ​​V1, V2, V3…Vn of the N first-type voltage sensors appear M1, M2, M3…Mn times respectively; the values ​​U1, U2, U3…Un of the N second-type voltage sensors appear P1, P2, P3…Pn times; F1, F2…Fn are the measured values ​​of each capacitance meter respectively.

10. The method for enhancing the stability of HBM and DDR memory according to claim 7, characterized in that: When the capacity is less than 85% of the nominal value of the supercapacitor or cannot be charged, switch to the backup capacitor in time to keep the supercapacitor in the best capacity state; when 85% of the nominal value is less than the current capacity and less than 95% of the nominal value, charge the supercapacitor in time to keep the supercapacitor in the best capacity state; stop charging when the supercapacitor is full.

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