Data processing method, device and system

Abstract

The invention provides a data processing method, device and system, and relates to the technical field of computers. According to the data processing method, an access logic address of a user in the storage system is converted into a first physical address and a second physical address, an error correction code is read or written according to the first physical address and the second physical address, and the first physical address and the second physical address correspond to different address spaces of different storage particles in a memory. Under the condition that the storage medium fault area has aggregation characteristics and the fault areas of different storage particles are the same or similar, code words of error correction codes are written or read in different address spaces, namely different bit fault rate areas, in different storage particles, so that the code words of the error correction codes are dispersed in the address spaces of the different bit fault rate areas; the maximum error bit number of the code word of the error correction code can be reduced, the error bit number difference of accessing different address spaces is reduced, the waste of error correction code resources is reduced, and the reliability of a memory is improved while the utilization rate of the error correction code resources is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to a data processing method, apparatus, and system. Background Art

[0002] As an effective solution for checking and correcting data errors, error correction code (ECC) is widely used in storage fields such as dynamic random access memory (DRAM) and NAND-flash memory. The core principle of error correction code is to detect and correct errors within a codeword by adding a certain amount of redundant information (check information). Among them, the added check information requires a certain amount of encoding and storage overhead. Generally speaking, the higher the bit error ratio (BER) of the storage medium, the stronger the error correction ability of the error correction code needs to be correspondingly, that is, the same amount of data needs to carry more redundant information to ensure the reliability of the storage system.

[0003] In the actual application process, storage medium failures often have the characteristics of uneven distribution within particles and regional concentrated distribution. At present, common technologies such as error correction codes for improving storage reliability do not fully consider the failure distribution characteristics of storage medium particles. In the case where there is an aggregation characteristic in the failure area of the storage medium, the bit error ratios of different address spaces of the storage medium vary greatly. In order to meet the system reliability, it is necessary to improve the error correction ability of the error correction code to ensure access to the address space area with a high bit error ratio in the storage medium, while exceeding the demand for error correction ability in the address space area with a low bit error ratio in the storage medium. Therefore, the storage medium needs to consume more storage resources and input / output (I / O) resources to implement the ability to detect and correct errors within the codeword of the error correction code, resulting in a problem of low resource utilization rate of the error correction code. Summary of the Invention

[0004] This application provides a data processing method, apparatus, and system to solve the problem of low resource utilization rate of error correction codes.

[0005] In a first aspect, a data processing method is provided. The data processing method is applied to a storage system, which includes a storage controller and a memory, and the data processing method can be executed by the memory. The data processing method includes: First, the memory obtains a first physical address and a second physical address. The first physical address is obtained by performing address conversion on the user's access logical address according to a first address mapping relationship, and the second physical address is obtained by performing address conversion on the access logical address according to a second address mapping relationship. Since the first address mapping relationship is different from the second address mapping relationship, the first physical address and the second physical address correspond to different address spaces of different storage granules in the memory. Then, the memory reads or writes an error correction code according to the first physical address and the second physical address.

[0006] When the distribution of faulty areas within a storage granule is uneven and concentrated, and the fault distribution characteristics among different granules of the same memory are roughly the same, the bit error rates of different address spaces vary greatly. In the traditional error correction code storage method, the memory allocates error correction codes to the same address spaces of different storage granules in the memory according to the same address mapping relationship. If the bit error rate of this address space is high, resulting in a high bit error rate for the same address space of different storage granules, it greatly increases the error correction ability requirements for the error correction codes stored in the same address space of different storage granules. The error correction code needs to carry more parity information to ensure the access reliability of the address space area with a high bit error rate. However, due to the large difference in bit error rates among different address spaces, the parity information of this error correction code exceeds the error correction ability requirements for the address space with a lower bit error rate in the storage granule, resulting in a large waste of error correction code resources and a low utilization rate of error correction code resources.

[0007] Based on the above data processing method, the memory converts the access logical address into two different physical addresses, and the two different physical addresses correspond to different address spaces of different storage granules in the memory, avoiding the storage of the codewords of the error correction code in the address spaces with the same bit error rate. The codewords of the error correction code are as scattered as possible in the areas with different bit error rates in the memory, reducing the possibility that the error correction codes stored in the address space with a high bit error rate have multiple data all in the area with a high bit error rate. In this way, the maximum number of error bits of the codewords of the error correction code can be reduced, the difference in the number of error bits for accessing different address spaces of the memory can be reduced, the waste of error correction code resources can be reduced, and while improving the utilization rate of error correction code resources, the reliability of the memory is improved.

[0008] As a possible implementation, the failure area distribution characteristics of different memory cells are the same, and the failure area distribution characteristics are used to indicate the correspondence between the address space and the bit error rate in the memory cells. In this application, the same failure area distribution characteristics do not limit that the bit error rates of any address space of different memory cells are the same. The correspondence between the address space and the bit error rate in different memory cells is similar, for example, the similarity is higher than a threshold (such as 80%, 90%, 95%, etc.), which can also be said that the failure area distribution characteristics of different memory cells are the same.

[0009] As a possible implementation, the first address mapping relationship or the second address mapping relationship is obtained according to the failure area distribution characteristics of different memory cells. Any one of the different memory cells includes a high bit error rate area and a low bit error rate area. The function of the first address mapping relationship or the second address mapping relationship is to convert the access logical address into a combination of an address space with a first bit error rate and an address space with a second bit error rate, where the first bit error rate is greater than the second bit error rate, that is, the access logical address of the same user is mapped to address spaces with different bit error rates in different memory cells. In this way, the memory can map the same logical address to address spaces with different bit error rates in the memory cells through the first address mapping relationship and the second address mapping relationship, realizing adjustable distribution of the number of error bits of the codeword of the error correction code and meeting the reliability requirements of different users.

[0010] Optionally, when the number of addresses in the high and low bit error rate areas of the memory cells of the memory is close, the high and low bit error rate addresses can be combined one by one.

[0011] Optionally, when the number of addresses in the high bit error rate area of the memory cells of the memory is less than the number of addresses in the low bit error rate area, the lowest bit error rate address is preferentially selected to be paired with the high bit error rate, that is, the second bit error rate is preferentially the lowest bit error rate.

[0012] Optionally, when the number of addresses in the high bit error rate area of the memory cells of the memory is greater than the number of addresses in the low bit error rate area, the address with the highest bit error rate is preferentially selected to be paired with the low bit error rate address, that is, the first bit error rate is preferentially the highest bit error rate.

[0013] In this application, the first address mapping relationship or the second address mapping relationship can be dynamically and flexibly adjusted specifically according to the time and space distribution characteristics of the storage medium failure, combined with the memory reliability requirements. The above content does not limit the first address mapping relationship or the second address mapping relationship.

[0014] As a possible implementation, the present application does not limit the types of the first address mapping relationship and the second address mapping relationship. For example, the first address mapping relationship and the second address mapping relationship can both be arithmetic mapping relationships, or both be table mapping relationships, or one can be an arithmetic mapping relationship and the other can be a table mapping relationship.

[0015] As a possible implementation, the address mapping of the data processing method can be implemented in the storage controller or in the memory, i.e., the storage module.

[0016] Optionally, when the address mapping of the data processing method is implemented in the memory, the memory receives the access logical address sent by the storage controller, and then performs address conversion on the access logical address according to the first address mapping relationship to obtain the first physical address, and performs address conversion on the access logical address according to the second address mapping relationship to obtain the second physical address.

[0017] Optionally, when the address mapping of the data processing method is implemented in the storage controller, the storage controller performs address conversion on the access logical address according to the first address mapping relationship to obtain the first physical address, and performs address conversion on the access logical address according to the second address mapping relationship to obtain the second physical address, and then sends the first physical address and the second physical address to the memory. The memory receives the first physical address and the second physical address sent by the storage controller.

[0018] In a second aspect, a data processing method is provided. The data processing method is applied to a storage system. The storage system includes a storage controller and a memory. The data processing method can be executed by the memory. The data processing method includes: the storage controller receives the user's access logical address, and respectively performs conversion on the access logical address according to the first address mapping relationship and the second address mapping relationship to obtain the first physical address and the second physical address, and then sends the first physical address and the second physical address to the memory, so that the memory reads or writes an error correction code according to the first physical address and the second physical address.

[0019] For various possible implementation manners of the above second aspect, please refer to the first aspect, and details are not described herein again.

[0020] In a third aspect, a data processing device is provided. The data processing device includes a transceiver module and a processing module. The transceiver module is used to obtain the first physical address and the second physical address. The first physical address is obtained by performing address conversion on the user's access logical address according to the first address mapping relationship, and the second physical address is obtained by performing address conversion on the access logical address according to the second address mapping relationship. The first physical address and the second physical address correspond to different address spaces of different storage grains in the memory. The processing module is used to read or write an error correction code according to the first physical address and the second physical address.

[0021] As a possible implementation, the data processing device may further include other modules that perform the operation steps of the data processing method described in the first aspect.

[0022] In a fourth aspect, a data processing device is provided. The data processing device includes a transceiver module and a processing module. The transceiver module is configured to receive the access logical address of the user. The processing module is configured to perform address conversion on the access logical address according to a first address mapping relationship to obtain a first physical address, and perform address conversion on the access logical address according to a second address mapping relationship to obtain a second physical address. The first physical address and the second physical address correspond to different address spaces of different memory grains in the memory. The transceiver module is further configured to send the first physical address and the second physical address to the memory, so that the memory reads or writes an error correction code according to the first physical address and the second physical address.

[0023] As a possible implementation, the data processing device may further include other modules that perform the operation steps of the data processing method described in the second aspect.

[0024] In a fifth aspect, a memory is provided. The memory is configured to perform the operation steps of the data processing method described in any one of the possible implementations in the first aspect.

[0025] In a sixth aspect, a storage controller is provided. The storage controller is configured to perform the data processing method described in any one of the possible implementations in the second aspect.

[0026] In a seventh aspect, a storage system is provided. The storage system includes the memory described in the fifth aspect above and the storage controller described in the sixth aspect above, and the memory and the storage controller are connected.

[0027] Regarding the technical principles and beneficial effects of the second aspect to the seventh aspect, reference may be made to the relevant descriptions of the first aspect above, and details are not described herein again.

[0028] In an eighth aspect, a computer program product is provided. The computer program product includes a computer program or instruction. When the computer program or instruction runs on a computer, the computer is caused to execute the data processing method described in any one of the possible implementations in the first aspect or the second aspect.

[0029] In a ninth aspect, a computer-readable storage medium is provided. The readable storage medium includes: a computer program or instruction; when the computer program or instruction runs on a computer, the computer is caused to execute the data processing method described in any one of the possible implementations in the first aspect or the second aspect. Description of the Drawings

[0030] Figure 1Schematic diagram of a failure area of a storage medium provided by this application;

[0031] Figure 2 Schematic diagram of a codeword of an error correction code;

[0032] Figure 3 Schematic diagram of the storage of an error correction code in the same address space of different storage grains Figure 1 ;

[0033] Figure 4 Schematic diagram of an architecture of a storage system provided by this application;

[0034] Figure 5 Schematic diagram of a process of a data processing method provided by this application Figure 1 ;

[0035] Figure 6 Schematic diagram of an arithmetic mapping provided by this application;

[0036] Figure 7 Schematic diagram of the storage of an error correction code in different address spaces of different storage grains Figure 1 ;

[0037] Figure 8 Schematic diagram of a process of a data processing method provided by this application Figure 2 ;

[0038] Figure 9 Schematic diagram of a preset address mapping relationship provided by this application;

[0039] Figure 10 Schematic diagram of a first address mapping relationship of a table mapping relationship type provided by this application;

[0040] Figure 11 Schematic diagram of a second address mapping relationship of a table mapping relationship type provided by this application;

[0041] Figure 12 Schematic diagram of the storage of an error correction code in the same address space of different storage grains Figure 2 ;

[0042] Figure 13 Schematic diagram of the storage of an error correction code in different address spaces of different storage grains Figure 2 ;

[0043] Figure 14 Schematic diagram of a structure of a data processing device provided by this application Figure 1 ;

[0044] Figure 15 Schematic diagram of a structure of a data processing device provided by this applicationFigure 2 ;

[0045] Figure 16 A structural schematic diagram of a computing device provided for this application. Detailed implementation manners

[0046] In the big data era, with the growth of the amount of data to be processed, new storage and computing devices have shown an explosive growth, posing demands for lower cost, higher speed, and larger capacity on storage media, and new types of storage media have emerged continuously. With the continuous evolution of technology, the continuous improvement of the hardware operation speed, and the superposition of factors such as immature technology, the probability of errors occurring in storage media is also relatively high, and the reliability problem of storage media (modules) has become more prominent. In actual storage scenarios, the faulty areas of storage media often have uneven distribution within particles and show characteristics of regional concentrated distribution. As Figure 1 shown, Figure 1 The left diagram shows that the space of the low failure rate area in the storage medium particle failure distribution is larger than that of the high failure rate area. Figure 1 The middle diagram shows that the space of the low failure rate area in the storage medium particle failure distribution is close to (or equal to) that of the high failure rate area. Figure 1 The right diagram shows that the space of the low failure rate area in the storage medium particle failure distribution is smaller than that of the high failure rate area.

[0047] As an effective solution for checking and correcting data errors, error correction codes can be used to detect and correct in-word errors in various types of storage media. As Figure 2 shown, the codeword of the error correction code includes an information bit and a check bit. The information bit is used to store user data and metadata, and the check bit is used to store the data of the ECC check bit (also called check information or redundant data). Among them, the additional check information requires a certain encoding and storage overhead. Generally speaking, the higher the medium bit error rate, the stronger the ECC error correction ability needs to be correspondingly to ensure system reliability. The user side only perceives the data of the information bit in the codeword of the error correction code (such as Figure 2 the bit positions 0-63 in Figure 2 ), and the data of the check bit is added to the information bit after ECC encoding (such as Figure 2 the bit positions 68-71 in

[0048] For example, taking the BCH (Bose-Chaudhuri-Hocquenghem code) error correction algorithm commonly used in NAND as an example, if the information bit is 560 bits and the parity bit is 130 bits, the maximum number of errors that can be corrected is 13 bits. However, if 14 bits of errors need to be corrected, the parity bit needs to be increased to 140 bits. Generally speaking, with the improvement of the ECC error correction ability, the required coding overhead also increases, the complexity of the storage system increases, and the resource and latency overheads also increase. At the same time, existing ECC algorithms mainly target errors occurring at random addresses in the storage medium, and there is a large bucket effect. As Figure 3 shown, the error correction code is usually stored in the same address space of different memory grains, and the same address space of different memory grains ( Figure 3 only memory grain 0 and memory grain N-1 are shown in the figure, but it is not limited to memory grain 0 and memory grain N-1) has the same or similar bit error rate. Figure 3 In the figure, low-fault (bit error rate) regions, medium-fault regions, and high-fault regions are represented by different filling patterns respectively. When the same error correction code is stored in the storage spaces with relatively large bit error rates of different memory grains (for example, the physical address corresponding to row address 4 and column address 4 of logical address 36), due to the superposition of the bit error rates in the high-bit error rate region, the possible number of error bits is relatively large, and parity bits capable of covering the maximum bit error rate of the storage medium or memory grain are required. In the case where there is an aggregation characteristic in the storage medium fault region, it will cause a relatively large difference in the bit error rates of accessing different address spaces. In order to meet the reliability requirements of the storage system, it is necessary to further improve the ECC error correction ability to ensure the access to the address space region with a high bit error rate. For the address space region with a low bit error rate, there is an over-design and resource waste situation in the ECC of the storage system.

[0049] The present application provides a data processing method. When the memory reads or writes the codeword of the error correction code, it obtains a first physical address and a second physical address. The first physical address is obtained by performing address conversion on the user's access logical address according to a first address mapping relationship, and the second physical address is obtained by performing address conversion on the access logical address according to a second address mapping relationship, and the first physical address and the second physical address correspond to different address spaces of different memory grains in the memory. Then, the memory reads or writes the error correction code according to the first physical address and the second physical address.

[0050] Thus, considering the actual characteristic that the faulty areas of storage media such as memories show a concentrated distribution, by applying multiple address mapping relationships, the codewords of the error correction code are stored dispersedly in different address spaces corresponding to the first physical address and the second physical address of different storage grains, so as to avoid storing the codewords of an error correction code in the same address space with the same bit error rate of different storage grains, which can reduce the maximum number of error bits of the error correction code, reduce the difference in the number of error bits when the user accesses different address spaces of the memory, and effectively improve the reliability of the memory while improving the resource utilization rate of the error correction code.

[0051] The data processing method provided by this application can be applied to a storage system. A storage system is the general term for the devices and technologies used by a computer to store data and programs, including various storage media and storage devices used by the computer. Distributed storage and centralized storage are two different architectures of the storage system. This application does not limit the type of the storage system, and the above data processing method can be applied to a distributed storage system, a centralized storage system or any other type of storage system. Next, in combination with the attached Figure 4 figures, taking a centralized storage system as an example, the storage system that executes the data processing method will be described exemplarily.

[0052] Figure 4 It is a schematic diagram of the architecture of a storage system provided by this application.

[0053] In Figure 4 the application scenario shown, the user accesses and stores data through an application program. The computer that runs these application programs is called an "application server". The application server 401 can be a physical machine or a virtual machine. Physical application servers include but are not limited to desktop computers, servers, laptop computers, and mobile devices. The application server accesses the storage system 420 through the fiber optic switch 410 to access and store data. However, the switch 410 is just an optional device, and the application server 401 can also directly communicate with the storage system 420 through the network. Or, the fiber optic switch 410 can also be replaced with an Ethernet switch, an InfiniBand switch, a RoCE (RDMA over converged ethernet) switch, etc.

[0054] Figure 4 The storage system 420 shown is a centralized storage system. The characteristic of a centralized storage system is that there is a unified entry, and all data from external devices has to pass through this entry, and this entry is the computing node 421 of the centralized storage system. The computing node 421 is the most core component in the centralized storage system, and many functions of the storage system are implemented therein.

[0055] As Figure 4As shown, there is one or more controllers in the computing node 421. Figure 4 Taking the case where the computing node contains one controller as an example for illustration. There is a mirror channel between controller 0 and controller 1. Then, when controller 0 writes a piece of data into its memory 423, it can send a copy of the data to controller 1 through the mirror channel, and controller 1 stores the copy in its local memory 423. Thus, controller 0 and controller 1 are backup to each other. When controller 0 fails, controller 1 can take over the business of controller 0. When controller 1 fails, controller 0 can take over the business of controller 1, thereby avoiding the unavailability of the entire storage system 420 caused by hardware failures.

[0056] In some possible embodiments, the computing node 421 may also be referred to as an engine.

[0057] The computing node 421 also includes a front-end interface 424 and a back-end interface 425. The front-end interface 424 is used to communicate with the application server 401 to provide storage services for the application server 401. The back-end interface 425 is used to communicate with the memory 433 to expand the capacity of the storage system. Through the back-end interface 425, the computing node 421 can connect more memories 433 to form a very large storage resource pool.

[0058] In terms of hardware, as Figure 4 shown, controller 0 at least includes a processor 422 and a memory 423. The processor 422 is a central processing unit (CPU), which is used to process data access requests from outside the storage system (servers or other storage systems), and is also used to process requests generated inside the storage system. When the processor 422 receives a write data request sent by the application server 401 through the front-end port 424, it will temporarily save the data in these write data requests in the memory 423. When the total amount of data in the memory 423 reaches a certain threshold, the processor 422 sends the data stored in the memory 423 to the memory 433 through the back-end port 425 for persistent storage.

[0059] For example, after the processor 422 receives an access request sent by the application server 401 through the front-end port 424, it converts the access logical address carried by the access request into a first physical address according to the first address mapping relationship, converts the access logical address into a second physical address according to the second address mapping relationship, and then sends the first physical address and the second physical address to the storage node 430 through the back-end interface 425, so that the storage node 430 writes or reads an error correction code according to the first physical address and the second physical address. Among them, the first physical address and the second physical address correspond to different address spaces of different storage grains in the memory.

[0060] The memory 423 refers to the internal memory that directly exchanges data with the processor. It can read and write data at any time and is very fast. It serves as the temporary data storage for the operating system or other running programs. The memory includes at least two types of memories. For example, the memory can be either a random access memory or a read-only memory (ROM). For instance, the random access memory can be a dynamic random access memory (DRAM) or a storage class memory (SCM). DRAM is a semiconductor memory, and like most random access memories (RAM), it belongs to a volatile memory device. SCM is a composite storage technology that combines the characteristics of traditional storage devices and memories. The storage class memory can provide faster read and write speeds than hard disks, but its access speed is slower than that of DRAM, and its cost is also cheaper than DRAM. However, DRAM and SCM are only exemplary in this embodiment, and the memory can also include other random access memories, such as static random access memory (SRAM), etc. For the read-only memory, for example, it can be a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), etc. In addition, the memory 423 can also be a dual in-line memory module or a dual-line memory module (DIMM), that is, a module composed of dynamic random access memories (DRAM), or it can be a solid state disk (SSD). In practical applications, multiple memories 423 and different types of memories 423 can be configured in the controller 0. The number and type of the memory 413 are not limited in this embodiment. In addition, the memory 423 can be configured to have a power retention function. The power retention function means that when the system experiences a power failure and then powers on again, the data stored in the memory 423 will not be lost. The memory with the power retention function is called a non-volatile memory.

[0061] The software program is stored in the memory 423, and the processor 422 running the software program in the memory 423 can realize the management of the hard disk. For example, the hard disk is abstracted as a storage resource pool and then divided into logical unit numbers (LUNs) for the server to use. Here, the LUN is actually the hard disk seen on the server. Of course, some centralized storage systems are also file servers themselves and can provide shared file services for the server.

[0062] The hardware components and software structure of the controller 1 (and other controllers not shown in the figure) are similar to those of the controller 0, which will not be elaborated here. Figure 4

[0063] Figure 4 Shown is a centralized storage system with disk control separation. In this system, the computing node 421 may not have a storage device slot, the memory 433 needs to be placed in the storage node 430, and the backend interface 425 communicates with the storage node 430. The backend interface 425 exists in the computing node 421 in the form of an adapter card. Two or more backend interfaces 425 can be used simultaneously on one computing node 421 to connect multiple storage nodes. Alternatively, the adapter card can also be integrated on the motherboard. In this case, the adapter card can communicate with the processor 422 through the peripheral component interconnect express (PCIE) bus.

[0064] Figure 4 It should be noted that only one computing node 421 is shown in the figure. However, in actual applications, the storage system may include two or more computing nodes 421, and redundancy or load balancing is performed among multiple computing nodes 421.

[0065] The storage node 430 includes a control unit 431 and several memories 433.

[0066] Figure 4 The control unit 431 can have various forms. In one case, the storage node 430 belongs to an intelligent disk enclosure in the hard disk enclosure. As shown in the figure, the control unit 431 includes a CPU and a memory. The CPU is used to perform operations such as address conversion and data reading and writing. The memory is used to temporarily store the data to be written into the memory 433 or the data read from the memory 433 and to be sent to the controller.

[0067] ​​In another case, the control unit 431 is a programmable electronic component, such as a data processing unit (DPU). The DPU has the versatility and programmability of a CPU, but is more specialized and can operate efficiently on network data packets, storage requests, or analysis requests. The DPU is distinguished from the CPU by a greater degree of parallelism (required to handle a large number of requests). Optionally, the DPU here can also be replaced with a processing chip such as a graphics processing unit (GPU), a neural-network processing unit (NPU), etc.

[0068] Generally, the number of control units 431 can be one, or two or more. When the storage node 430 includes at least two control units 431, there may be an ownership relationship between the memory 433 and the control unit 431. If there is an ownership relationship between the memory 433 and the control unit 431, then each control unit can only access the hard disk that belongs to it, which often involves forwarding read / write data requests between the control units 431, resulting in a longer data access path. Additionally, if the storage space is insufficient, when adding a new memory 433 in the storage node 430, it is necessary to re-bind the ownership relationship between the memory 433 and the control unit 431, and the operation is complex, resulting in poor scalability of the storage space. Therefore, in another implementation, the function of the control unit 431 can be offloaded to the network card 432. In other words, in this implementation, the storage node 430 does not have a control unit 431 internally, but the network card 432 is used to complete data reading and writing, address conversion, and other computing functions. At this time, the network card 432 is a smart network card. It can include a CPU and memory. The network card 432 can also be a programmable electronic component, such as a data processing unit (DPU). The DPU has the versatility and programmability of a CPU, but is more specialized and can operate efficiently on network data packets, storage requests, or analysis requests. The DPU is distinguished from the CPU by a greater degree of parallelism (required to handle a large number of requests). Optionally, the DPU here can also be replaced with a processing chip such as a graphics processing unit (GPU), a neural-network processing unit (NPU), etc. There is no ownership relationship between the network card 432 and the memory 433 in the storage node 430, and the network card 432 can access any memory 433 in the storage node 430. Therefore, it is more convenient to expand the hard disk when the storage space is insufficient.

[0069] In a possible embodiment of the present application, after the control unit 431 or the network card 432 receives an access request sent by the computing node 421, it writes or reads data in the memory 433 and returns a processing result to the computing node 421. For example, the controller 0 converts the access logical address carried in the user's access request into an intermediate address and sends it to the control unit 431 or the network card 432 through the back-end interface 425. The control unit 431 or the network card 432 converts the intermediate address into a first physical address according to the first address mapping relationship, converts the intermediate address into a second physical address according to the second address mapping relationship, and then writes or reads an error correction code according to the first physical address and the second physical address. Among them, the first physical address and the second physical address correspond to different address spaces of different storage granules in the memory.

[0070] In the above embodiment, the intermediate address may be a physical address obtained by converting the access logical address. When using the address mapping relationship of the storage system itself as the first address mapping relationship, the intermediate address is the same as the first physical address, and the control unit 431 or the network card 432 does not need to perform address conversion according to the first address mapping relationship.

[0071] According to the type of communication protocol between the computing node 421 and the storage node 430, the storage node 430 may be a SAS (Serial Attached SCSI) storage node, or an NVMe storage node, an IP storage node, or other types of storage nodes. The SAS storage node uses the SAS3.0 protocol, and each enclosure supports 25 SAS hard disks. The computing node 421 is connected to the storage node 430 through an on-board SAS interface or a SAS interface module. The NVMe storage node is more like a complete computer system, and the NVMe hard disk is inserted into the NVMe storage node. The NVMe storage node is then connected to the computing node 421 through an RDMA port.

[0072] Figure 4 It is only a schematic diagram of a storage system architecture provided by the embodiments of the present application. Figure 4 The positional relationships between the devices, components, modules, etc. shown do not constitute any limitation. For example, Figure 4 Taking the disk control separation architecture as an example to illustrate the computer system. In other embodiments, the computer system may also be a disk control integrated architecture or a distributed storage architecture, which will not be elaborated here.

[0073] Next, the data processing method provided by the present application will be specifically described with reference to the accompanying drawings.

[0074] In the scenario of a storage system applying an error correction code, as described above Figure 4In the storage system, the computing node 421 and the storage node 430 can be the execution entities of the data processing method. Next, taking the storage node 430 in the storage system as an example to execute the conversion of the user's access logical address to the first physical address and the second physical address, the data processing method will be elaborated in detail. As Figure 5 shown, the controller shares 1 group of command / address lines with all the particles in the memory 433 in the storage node 430, uses solid lines to represent the command path, and uses dashed lines to represent the data path. The controller includes a command module and a data module. The command module is used to convert the user's logical access address into an intermediate address and send it to the storage node 430 through the command line. The data module is used to cooperate with the command line to write / read data in the storage node 430 through ECC encoding or ECC decoding. Among them, the ECC-encoded data (error correction code) will be evenly distributed on all the storage particles used, that is, each storage particle stores data with a bit width of (number of ECC-encoded data bits / number of particles).

[0075] Please refer to Figure 5 , Figure 5 which is a schematic flow of a data processing method provided by this application Figure 1 , and this data processing method may include the following steps 501-step 507.

[0076] Step 501, the application server 401 receives a user access request.

[0077] When the application server 401 receives a user access request, it sends a data access request to the computing node 421.

[0078] Step 502, the application server 401 sends a data access request to the computing node 421.

[0079] In response to the user's operation of triggering the user access request, the application server 401 sends a data access request to the computing node 421. The data access request includes the user's access logical address.

[0080] As a possible implementation, the data access request can be a data write (write) request or a data read (read) request. When the data access request is a data write request, the data access request further includes the user's write data.

[0081] Step 503, the computing node 421 converts the access logical address into an intermediate address.

[0082] The computing node 421 converts the access logical address into an intermediate address according to the preset address mapping relationship.

[0083] Step 504, the computing node 421 sends the intermediate address to the storage node 430.

[0084] Step 505: The storage node 430 performs address conversion on the access logical address according to the first address mapping relationship to obtain a first physical address.

[0085] Step 506: The storage node 430 performs address conversion on the access logical address according to the second address mapping relationship to obtain a second physical address.

[0086] As a possible implementation manner, the preset address mapping relationship, the first address mapping relationship, and the second address mapping relationship may be arithmetic mapping relationships.

[0087] Optionally, the first address mapping relationship may be an existing address mapping relationship of the storage system, and the second address mapping relationship is obtained by transforming the first address mapping relationship. The first address mapping relationship is the above-mentioned preset address mapping relationship, and the second address mapping relationship is obtained by inverting all rows / columns in the first address mapping relationship. In this way, continuing to use the preset address mapping relationship of the storage system itself can speed up data processing and ensure the concurrency of the storage system.

[0088] For example, taking arithmetic mapping as an example, the first address mapping relationship is: PHA[i]=LHA[i]; wherein i is an integer between 0 and m, and m is the value of the address bit width of the storage particle minus 1. The second mapping relationship is: PHA[u+:p]=~LHA[u+:p]; wherein u is the bit corresponding to the starting row address of the storage particle, p is the row address bit width of the storage particle, ~ indicates negation, and +: indicates addition; PHA[v+:q]=~LHA[v+:q], v is the bit corresponding to the starting column address of the storage particle, q is the column address bit width of the storage particle, PHA[w+:s]=LHA[w+:s], w is the bit corresponding to the starting bank address of the storage particle, and s is the bank address bit width of the storage particle. Exemplarily, as Figure 6 Taking the address bit width of the storage particle shown as 8 bits as an example, the logical address bits 0-2 correspond to the row address of the storage particle, the logical address bits 3-5 correspond to the column address of the storage particle, and the logical address bits 6-7 correspond to the bank address of the storage particle, that is, m=7, u=0, v=3, w=6, p=3, q=3, s=2.

[0089] This application does not limit the first address mapping relationship and the second address mapping relationship. The first address mapping relationship and the second address mapping relationship can be address mapping relationships constructed according to the bit error rate region distribution characteristics of the memory granules of the memory 233. The applicable arithmetic mapping methods are not limited to the rules described in this embodiment. It is only necessary to ensure a one-to-one mapping between the logical space and the media space (the address space of the memory granules). Specifically, it can be flexibly adjusted according to the media fault distribution characteristics. For any logical address accessed by a user, the corresponding ECC encoding and decoding are the same as those of the traditional scheme, and the codewords of the error correction code are evenly distributed to the corresponding granules. However, the difference is that through different address mapping methods, complementary combinations of different address mapping relationships are achieved, so that the address space for each memory granule to store the data corresponding to the codeword is different, and it is a combination of physical addresses with different bit error rates. While reducing the maximum number of error bits of the error correction code of the memory 433, it also makes the distribution of the number of error bits more uniform, thereby reducing the demand for the ECC error correction ability and resource waste, ensuring storage reliability under the condition of reducing ECC resource consumption, or improving storage reliability under the condition of the same ECC resource consumption.

[0090] Among them, the first address mapping relationship and the second address mapping relationship are used to convert the accessed logical address into a combination of the address space with the first bit error rate and the address space with the second bit error rate, where the first bit error rate is greater than the second bit error rate. For example, for the same accessed logical address, the first address mapping relationship converts it into a first physical address, and the first physical address is in the address space with the first bit error rate, and the second address mapping relationship converts it into a second physical address, and the second physical address is in the address space with the second bit error rate. The principle of the complementary combination of the first address mapping relationship and the second address mapping relationship can be as follows: when the number of address spaces in the high and low bit error rate regions is close, the first address mapping relationship and the second address mapping relationship are used to combine the high and low bit error rate address spaces one by one; when the number of address spaces in the high bit error rate region is less than that in the low bit error rate region, the first address mapping relationship and the second address mapping relationship are used to preferentially select the lowest bit error rate address space to match with the high bit error rate; when the number of addresses in the high bit error rate region is greater than that in the low bit error rate region, the first address mapping relationship and the second address mapping relationship are used to preferentially select the address with the highest bit error rate to match with the low bit error rate address. For different user requirements for memory reliability, through a variety of combinations of address mapping relationships, the address spaces of memory granules with different bit error rates can be combined and matched to achieve adjustable distribution of the number of error bits of the ECC codewords and meet the reliability indicators of different users.

[0091] In a possible embodiment of the present application, the preset address mapping relationship, the first address mapping relationship, and the second address mapping relationship may also be any type of address mapping relationship other than the arithmetic mapping relationship, such as a table mapping relationship, etc. For the method of the table mapping relationship, please refer to Figures 9 - 11 , which will not be elaborated here.

[0092] Step 507: The storage node 430 reads or writes an error correction code according to the first physical address and the second physical address.

[0093] The storage node 430 sequentially reads or writes the data of each bit of the error correction code in different memory grains of the memory 433 according to the first physical address and the second physical address. Among them, the first physical address and the second physical address correspond to different address spaces of different memory grains in the memory.

[0094] As a possible implementation manner, the failure area distribution characteristics of different memory grains are the same. The failure area distribution characteristics are used to indicate the correspondence between the address space and the bit error rate in the memory grain. For example Figure 7 As shown, the failure area distribution characteristics of each of the memory grains from memory grain_0 to memory grain_N-1 are the same, including a low failure rate area, a medium failure rate area, and a high failure rate area. Therefore, when the first physical address and the second physical address correspond to different address spaces of different memory grains in the memory, the bit error rate of the address space corresponding to the first physical address is different from the bit error rate of the address space corresponding to the second physical address.

[0095] Continuing with the arithmetic mapping in step 506 as an example, when the second address mapping relationship is the row / column inversion of the first address mapping relationship, the address spaces of the first physical address and the second physical address in different memory grains are arranged in a central symmetry. For example Figure 7 , the user's access logical address is 36. The storage node 430 writes or reads the data of the nth bit of the error correction code in the address space of the 4th row and the 4th column of the memory grain_0 of the memory 433 according to the first physical address, and writes or reads the data of the (n + 1)th bit of the error correction code in the address space of the 3rd row and the 3rd column of the memory grain N-1 of the memory 433 according to the second physical address. Among them, the address space corresponding to the first physical address is in the high failure rate area of the memory grain_0, and the address space of the second physical address is in the medium failure rate area of the memory grain N-1.

[0096] When the data access request is a data write request, the storage node 430 receives the data while receiving the intermediate address, and writes the data in different memory grains of the memory 433 according to the first physical address and the second physical address. Among them, the above data is the codeword of the error correction code obtained by the data module in the controller after performing ECC encoding on the write data sent by the user.

[0097] When the data access request is a data read request, while receiving the intermediate address, the storage node 430 reads data from different memory dies of the memory 433 in sequence according to the first physical address and the second physical address, and sends the read data to the controller. The data module in the controller performs ECC decoding on the read data to obtain the user's read data, and sends the user's read data to the application server 401.

[0098] As described above in connection with Figures 5 - 7 the conversion of the user's access logical address to the first physical address and the second physical address by the storage node 430 as an example, the data processing method has been described in detail. However, the present application does not limit the execution entity for performing the address conversion. For example, the conversion of the user's access logical address to the first physical address and the second physical address can also be performed by the controller of the computing node 421. Next, in connection with Figure 8 , taking the computing node 421 in the storage system performing the conversion of the user's access logical address to the first physical address and the second physical address as an example, the data processing method will be described in detail. As Figure 8 shown, in the case of multiple channels (such as channel 0 to channel K), there are multiple groups of command buses between the controller and the storage node 430, where the command buses of different channels are independent of each other, and the dies within a channel share 1 group of command / address lines. Therefore, in the controller, at the granularity of channels, the user data is scattered and stored in the address spaces with different bit error rates in the memory 433. Among them, the ECC encoded data (error correction code) will be evenly distributed on all the used memory dies, that is, each memory die stores data with a width of (number of bits of ECC encoded data / number of dies) bits.

[0099] Please refer to Figure 8 , Figure 8 which is a flowchart illustration of a data processing method provided by the present application Figure 2 , and the data processing method may include the following steps 801 - step 807.

[0100] Step 801, the application server 401 receives a user access request.

[0101] Step 802, the application server 401 sends a data access request to the computing node 421.

[0102] Step 803, the computing node 421 converts the access logical address into an intermediate address.

[0103] For the specific processing manners of the above steps 801 - step 803, please refer to Figure 5 steps 501 - step 503 therein, which will not be elaborated here.

[0104] Step 804: The computing node 421 performs address conversion on the access logical address according to the first address mapping relationship to obtain a first physical address.

[0105] Step 805: The computing node 421 performs address conversion on the access logical address according to the second address mapping relationship to obtain a second physical address.

[0106] As a possible implementation manner, the preset address mapping relationship, the first address mapping relationship, and the second address mapping relationship may be table mapping relationships.

[0107] Optionally, the first address mapping relationship may be an existing address mapping relationship of the storage system, and the second address mapping relationship is obtained by transforming the first address mapping relationship. The first address mapping relationship is the above-mentioned preset address mapping relationship, and the second address mapping relationship is obtained by bit-shifting part of the row addresses in the first address mapping relationship. In this way, continuing to use the preset address mapping relationship of the storage system itself can speed up data processing and ensure the concurrency of the storage system.

[0108] For example, taking table mapping as an example, the preset address mapping relationship is as follows Figure 9 As shown in FIG, the user's access logical address is mapped to the physical address according to the existing address mapping relationship. Figure 10 As shown, the first address mapping relationship is the same as the existing address mapping relationship. Figure 11 As shown, the second address mapping relationship moves the highest bit in the row address in the first address mapping relationship to between the bank address and the column address.

[0109] In the present application, the first physical address and the second physical address correspond to different address spaces of different storage particles in the memory, and the fault area distribution characteristics of different storage particles are the same. Therefore, when the first physical address and the second physical address correspond to different address spaces of different storage particles in the memory, the bit error rate of the address space corresponding to the first physical address is different from the bit error rate of the address space corresponding to the second physical address. Figure 12 As shown, when the user's access logical address is 35, the data of each bit of the error correction code codeword is written or read according to the traditional unified address mapping relationship. When storage particle 0 and storage particle N-1 include the same low failure rate area, medium failure rate area and high failure rate area, the data of each bit of the error correction code codeword is in the high failure rate area. Figure 13As shown in the figure, this application uses different table mapping relationships as the first address mapping relationship and the second address mapping relationship. The logical address accessed by the user is 35. The first physical address is in the address space of row 3 and column 4 of memory cell 0 of memory 433, and the second physical address is in the address space of row 7 and column 0 of memory cell N - 1 of memory 433. Among them, the address space corresponding to the first physical address is in the high failure rate area of memory cell 0, and the address space of the second physical address is in the low failure rate area of memory cell N - 1.

[0110] Step 806: Compute node 421 sends the first physical address and the second physical address to storage node 430.

[0111] Step 807: Storage node 430 reads or writes an error correction code according to the first physical address and the second physical address.

[0112] For the specific processing method of the above step 807, please refer to Figure 5 step 507 therein, which will not be elaborated here.

[0113] In this way, the address mapping of this application can be implemented at the storage controller level or inside the memory, and can be flexibly adjusted according to the existing architecture of the storage system, reducing the architecture changes to the existing storage system.

[0114] As mentioned above in combination with Figures 5 - 13 , taking arithmetic mapping and table mapping with two memory cells as examples, the process of the data processing method has been described in detail. However, this application does not limit the number of memory cells and address mapping relationships. For a memory composed of N memory cells, the address mapping relationships of M memory cells are configured as address mapping relationship 1, and the address mapping relationships of L memory cells are configured as address mapping relationship 2. Among them, N > 1, M ≥ 1, L ≥ 1, all three are integers, and N = M + L. Optionally, the correspondence between the address mapping relationship and the memory cell can be flexibly adjusted, and the number of paired address mapping relationships can also be flexibly adjusted. The memory cell numbers with the same address mapping relationship can be consecutive or non - consecutive. For any logical address accessed by a user, the corresponding ECC encoding and decoding are the same as the traditional scheme, and the codewords of the error correction code are evenly distributed to the corresponding memory cells. However, the difference is that since different memory cells in the memory use different address mapping relationships, the physical addresses for each memory cell to store the data corresponding to the codeword are different. Through the combination of physical address spaces with high - low bit error rates in the memory, while reducing the maximum number of error bits of the error correction code in the memory, it also makes the distribution of error bits more uniform, thereby reducing the demand for ECC error correction ability and resource waste, ensuring storage reliability while reducing ECC resource consumption, or improving storage reliability under the same ECC resource consumption.

[0115] In an embodiment of the present application, it is assumed that the module consists of two memory particles, and the maximum number of error bits corresponding to the low, medium, and high failure (bit error) rate regions of each memory particle is 1, 2, and 3 respectively. That is, N = 2, M = 1, L = 1. The first address mapping relationship of the first memory particle is the first address mapping relationship in the above arithmetic mapping example, and the second address mapping relationship of the second memory particle is the second address mapping relationship in the above arithmetic mapping example. For the traditional scheme, the range of the number of error bits of the error correction code of ECC encoding and decoding is 2 - 6. The extreme value of the number of error bits is large and the distribution difference is large, resulting in problems such as low ECC resource utilization and reduced storage reliability. However, when using the data processing method of the present application, the range of the number of error bits of the error correction code of ECC encoding and decoding is 3 - 5. The maximum value of the number of error bits is reduced and the distribution is more uniform. The requirement for the ECC error correction ability is reduced, and the ECC resource utilization is more balanced. Under the condition of the same ECC error correction resources, the storage reliability is significantly improved.

[0116] Figure 14 FIG. is a schematic structural diagram of a possible data processing device provided for this embodiment. This data processing device can be used to implement the functions of the storage node 430 in the above method embodiment, and thus also has the beneficial effects possessed by the above method embodiment. In this embodiment, this data processing device can be a node composed of the storage node 430 and / or other servers as shown in Figure 4 and can also be a module (such as a chip) applied to a server.

[0117] As Figure 14 shown, the data processing device 1400 includes an address module 1410 and a processing module 1420.

[0118] The data processing device 1400 can be used to implement the functions of the storage node 430 in the above Figure 5 shown method embodiment, and each module included in the data processing device 1400 is specifically used to implement the following functions.

[0119] The address module 1410 is used to obtain a first physical address and a second physical address. The first physical address is obtained by performing address conversion on the user's access logical address according to the first address mapping relationship, and the second physical address is obtained by performing address conversion on the access logical address according to the second address mapping relationship. The first physical address and the second physical address correspond to different address spaces of different memory particles in the memory. For example, the address module 1410 is used to execute Figure 5 the steps 505 - step 506 shown in

[0120] The processing module 1420 is used to read or write an error correction code according to the first physical address and the second physical address. For example, the processing module 1420 is used to execute Figure 5Step 507 shown in

[0121] As a possible implementation, the failure area distribution characteristics of different memory particles are the same, and the failure area distribution characteristics are used to indicate the correspondence between the address space and the bit error rate in the memory particles.

[0122] As a possible implementation, the bit error rate of the address space corresponding to the first physical address is different from the bit error rate of the address space corresponding to the second physical address.

[0123] As a possible implementation, the first address mapping relationship or the second address mapping relationship is obtained according to the failure area distribution characteristics of different memory particles. Any one of the different memory particles includes a high bit error rate area and a low bit error rate area. The first address mapping relationship and the second address mapping relationship are used to convert the access logical address into a combination of an address space with a first bit error rate and an address space with a second bit error rate, where the first bit error rate is greater than the second bit error rate. When the number of addresses in the high bit error rate area is less than the number of addresses in the low bit error rate area, the second bit error rate is preferentially the lowest bit error rate. When the number of addresses in the high bit error rate area is greater than the number of addresses in the low bit error rate area, the first bit error rate is preferentially the highest bit error rate.

[0124] As a possible implementation, the first address mapping relationship or the second address mapping relationship is an arithmetic mapping relationship.

[0125] As a possible implementation, the first address mapping relationship or the second address mapping relationship is a table mapping relationship.

[0126] As a possible implementation, the address module 1410 is specifically configured to: receive the access logical address sent by the storage controller; perform address conversion on the access logical address according to the first address mapping relationship to obtain the first physical address; perform address conversion on the access logical address according to the second address mapping relationship to obtain the second physical address.

[0127] As a possible implementation, the address module 1410 is specifically configured to: receive the first physical address and the second physical address sent by the storage controller; the first physical address is obtained by the storage controller performing address conversion on the access logical address according to the first address mapping relationship, and the second physical address is obtained by the storage controller performing address conversion on the access logical address according to the second address mapping relationship. Among them, after the access logical address is converted into an intermediate address, it is then respectively converted into the first physical address and the second physical address, which can also be said to be obtained by performing address conversion on the access logical address.

[0128] It should be understood that the data processing device 1400 in the embodiments of the present invention and the present application can be implemented by a CPU, or by an ASIC, or by a programmable logic device (PLD). The above PLD can be a complex programmable logical device (CPLD), an FPGA, a generic array logic (GAL), or any combination thereof. When the data processing device 1400 is implemented by software Figure 5 in the data processing method shown, the data processing device 1400 and its various modules can also be software modules.

[0129] It should be understood that nodes such as storage nodes in the embodiments of the present application can correspond to the data processing device 1400 in the embodiments of the application, and can correspond to the corresponding main bodies in the methods executed according to the embodiments of the present application. The above and other operations and / or functions of the various modules in the data processing device 1400 are respectively for implementing Figure 5 the corresponding processes of the methods in, and for the sake of brevity, they will not be elaborated here.

[0130] Figure 15 FIG. is a schematic structural diagram of another possible data processing device provided in this embodiment. This data processing device can be used to implement the functions of the computing node 421 in the above method embodiments, and thus also has the beneficial effects possessed by the above method embodiments. In this embodiment, this data processing device can be a node composed of the computing node 421 and / or other servers as shown in Figure 4 and / or a module (such as a chip) applied to a server.

[0131] As Figure 15 shown, the data processing device 1500 includes a transceiver module 1510 and a processing module 1520.

[0132] The data processing device 1500 can be used to implement the functions of the computing node 421 in the method embodiments shown in the above Figure 8 , and the various modules included in the data processing device 1500 are specifically used to implement the following functions.

[0133] The transceiver module 1510 is used to receive the access logical address of the user. For example, the transceiver module 1510 is used to receive the data access request in step 802 as shown in Figure 8 , and the data access request includes the access logical address of the user.

[0134] The processing module 1520 is configured to perform address conversion on an access logical address according to a first address mapping relationship to obtain a first physical address, and perform address conversion on the access logical address according to a second address mapping relationship to obtain a second physical address. The first physical address and the second physical address correspond to different address spaces of different memory dies in the memory. For example, the processing module 1520 is configured to execute Figure 8 the steps 804 - 805 shown in

[0135] The transceiver module 1510 is further configured to send the first physical address and the second physical address to the memory, so that the memory reads or writes an error correction code according to the first physical address and the second physical address. For example, the transceiver module 1510 is configured to execute Figure 8 the step 806 shown in

[0136] For other possible implementation manners of each module in the data processing apparatus 1500, reference may be made to the data processing apparatus 1400, which will not be elaborated herein.

[0137] It should be understood that the data processing apparatus 1500 in the embodiments of the present invention and the present application may be implemented by a CPU, or may be implemented by an ASIC, or a PLD. The above PLD may be a complex programmable logic device CPLD, FPGA, GAL, or any combination thereof. When the data processing apparatus 1500 is implemented by software Figure 8 for the data processing method shown in

[0138] It should be understood that nodes such as computing nodes in the embodiments of the present application may correspond to the data processing apparatus 1500 in the embodiments of the application, and may correspond to the corresponding main bodies executing the methods in the embodiments of the present application. And the above and other operations and / or functions of each module in the data processing apparatus 1500 are respectively for implementing Figure 8 the corresponding processes of the methods in

[0139] The present application further provides a computing device composition system as shown in Figure 16 The composed system may be Figure 4 the storage system shown in Figure 4 The system includes a plurality of computing devices 1600. Each computing device 1600 includes a memory 1601, a processor 1602, a communication interface 1603, and a bus 1604. Among them, the memory 1601, the processor 1602, and the communication interface 1603 are communicatively connected to each other through the bus 1604. The computing device 1600 may be Figure 4 the computing node or storage node in

[0140] The memory 1601 can be a read-only memory, a static storage device, a dynamic storage device, or a random access memory. The memory 1601 can store computer instructions and a set of data required for executing the computer instructions. When the computer instructions stored in the memory 1601 are executed by the processor 1602, the processor 1602 and the communication interface 1603 are used to execute the data processing method.

[0141] The processor 1602 can be a general-purpose central processing unit (CPU), an application specific integrated circuit (ASIC), a graphics processing unit (GPU), or any combination thereof. The processor 1602 can include one or more chips. The processor 1602 can include an AI accelerator, for example, a neural processing unit (NPU). In addition, Figure 16 In this example, each computing device 1600 includes one processor 1602. Specifically, in implementation, the number and type of the processors 1602 in each computing device 1600 can be set according to service requirements. For the same computing device 1600, it can include one or more processors. When the same computing device 1600 includes multiple processors, the type of the processor is not limited in this application.

[0142] The communication interface 1603 uses a transceiver module such as, but not limited to, a transceiver to implement the communication between the computing device 1600 and other devices or a communication network. For example, requests can be received or sent through the communication interface 1603.

[0143] The bus 1604 can include a path for transmitting information between various components of the computing device 1600 (for example, the memory 1601, the processor 1602, and the communication interface 1603).

[0144] A communication path is established between each of the above computing devices 1600 through a communication network. Any one of the computing devices 1600 can be a computer (for example, a server) in a distributed storage system, or a computer in an edge data center, or a terminal computing device.

[0145] The functions of nodes such as computing nodes and / or storage nodes can be deployed on each computing device 1600. For example, execute Figure 5 or Figure 8 any step in the data processing method shown, or execute the functions of each module in the data processing device 1400 and the data processing device 1500.

[0146] The method steps in this embodiment can be implemented in a hardware manner or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in a random access memory (RAM), flash memory, read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), registers, hard disk, removable hard disk, CD-ROM, or any other form of storage medium well-known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. Additionally, the ASIC can be located in a terminal device. Of course, the processor and the storage medium can also exist as discrete components in a network device or a terminal device.

[0147] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are executed in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or other programmable devices. The computer program or instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program or instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired or wireless manner. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); it can also be a semiconductor medium, such as a solid state drive (SSD). As described above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A data processing method, characterized in that, Comprising: Obtaining a first physical address and a second physical address; The first physical address is obtained by performing address conversion on the access logical address of the user according to a first address mapping relationship, and the second physical address is obtained by performing address conversion on the access logical address according to a second address mapping relationship. The first physical address and the second physical address correspond to different address spaces of different memory grains in the memory; Reading or writing an error correction code according to the first physical address and the second physical address.

2. The method according to claim 1, characterized in that, The failure area distribution characteristics of the different memory grains are the same, and the failure area distribution characteristics are used to indicate the correspondence between the address space and the bit error rate in the memory grain.

3. The method according to claim 1 or 2, characterized in that, The bit error rate of the address space corresponding to the first physical address is different from the bit error rate of the address space corresponding to the second physical address.

4. The method according to any one of claims 1-3, characterized in that, The first address mapping relationship or the second address mapping relationship is obtained according to the failure area distribution characteristics of the different memory grains. Any one of the different memory grains includes a high bit error rate area and a low bit error rate area; The first address mapping relationship and the second address mapping relationship are used to convert the access logical address into a combination of an address space with a first bit error rate and an address space with a second bit error rate, where the first bit error rate is greater than the second bit error rate; When the number of addresses in the high bit error rate area is less than the number of addresses in the low bit error rate area, the second bit error rate is preferentially the lowest bit error rate; When the number of addresses in the high bit error rate area is greater than the number of addresses in the low bit error rate area, the first bit error rate is preferentially the highest bit error rate.

5. The method according to any one of claims 1-4, characterized in that, The first address mapping relationship or the second address mapping relationship is an arithmetic mapping relationship.

6. The method according to any one of claims 1-4, characterized in that, The first address mapping relationship or the second address mapping relationship is a table mapping relationship.

7. The method according to any one of claims 1-6, characterized in that, The obtaining of the first physical address and the second physical address includes: Receiving the access logical address sent by the storage controller; Performing address conversion on the access logical address according to the first address mapping relationship to obtain the first physical address; Performing address conversion on the access logical address according to the second address mapping relationship to obtain the second physical address.

8. The method according to any one of claims 1-6, characterized in that, The obtaining of the first physical address and the second physical address includes: Receiving the first physical address and the second physical address sent by the storage controller; the first physical address is obtained by the storage controller performing address conversion on the access logical address according to the first address mapping relationship, and the second physical address is obtained by the storage controller performing address conversion on the access logical address according to the second address mapping relationship.

9. A data processing method, characterized in that, Comprising: Receiving the access logical address of the user; Performing address conversion on the access logical address according to the first address mapping relationship to obtain a first physical address; Performing address conversion on the access logical address according to the second address mapping relationship to obtain a second physical address; the first physical address and the second physical address correspond to different address spaces of different memory grains in the memory; Send the first physical address and the second physical address to a memory, so that the memory reads or writes an error correction code according to the first physical address and the second physical address.

10. The method according to claim 9, characterized in that, The failure area distribution characteristics of the different memory cells are the same, and the failure area distribution characteristics are used to indicate the correspondence between the address space and the bit error rate in the memory cells.

11. The method according to claim 9 or 10, characterized in that, The bit error rate of the address space corresponding to the first physical address is different from the bit error rate of the address space corresponding to the second physical address.

12. The method according to any one of claims 9-11, characterized in that, The first address mapping relationship or the second address mapping relationship is obtained according to the failure area distribution characteristics of the different memory cells, and any one of the different memory cells includes a high bit error rate area and a low bit error rate area; The first address mapping relationship and the second address mapping relationship are used to convert the access logical address into a combination of an address space with a first bit error rate and an address space with a second bit error rate, and the first bit error rate is greater than the second bit error rate; When the number of addresses in the high bit error rate area is less than the number of addresses in the low bit error rate area, the second bit error rate is preferentially the lowest bit error rate; When the number of addresses in the high bit error rate area is greater than the number of addresses in the low bit error rate area, the first bit error rate is preferentially the highest bit error rate.

13. The method according to any one of claims 9 - 12, characterized in that, The first address mapping relationship or the second address mapping relationship is an arithmetic mapping relationship.

14. The method according to any one of claims 9 - 12, characterized in that, The first address mapping relationship or the second address mapping relationship is a table mapping relationship.

15. A data processing device, characterized in that, The apparatus includes a module for performing the operation steps of the method according to any one of claims 1-8 above.

16. A data processing device, characterized in that, The apparatus includes a module for performing the operation steps of the method according to any one of claims 9-14 above.

17. A memory, characterized in that, The memory is used to perform the operation steps of the method according to any one of claims 1-8 above.

18. A storage controller, characterized in that, The storage controller is used to perform the operation steps of the method according to any one of claims 9-14 above.

19. A storage system, characterized in that, The storage system includes the memory according to claim 17 and the storage controller according to claim 18.

20. A readable storage medium, characterized in that, The readable storage medium includes a computer program or instruction, and when the computer program or instruction runs on a computer, the computer is caused to perform the operation steps of the method according to any one of claims 1-8 above, or perform the operation steps of the method according to any one of claims 9-14 above.

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