Data transmission system for LVDS (Low Voltage Differential Signaling) interface

Abstract

The invention discloses a data transmission system for an LVDS (Low Voltage Differential Signaling) interface. Comprising a sending end and a receiving end, the sending end comprises a first splicing module, a first FIFO memory, a mapping module and a first conversion module, and the first splicing module is used for receiving video data, splicing each row of pixel data and then writing the spliced video data into the first FIFO memory; the mapping module is used for reading the spliced video data, receiving packet data and the number of data lines sent from the outside, and then sequentially mapping the spliced video data and the packet data to the corresponding data lines according to the number of the data lines and a mapping principle; and the first conversion module is used for converting each group of data with the bit width of 1 byte mapped to the data line into serial bit stream data with the bit width of 1 bit, and then sending the serial bit stream data to a receiving end. According to the invention, the problem of Lane quantity stiffness in the XN mode is avoided, and the bandwidth utilization rate of the LVDS interface is improved to the maximum extent.

Description

Technical Field

[0001] The present invention relates to the technical field of video data transmission, and particularly to a data transmission system for an LVDS interface. Background Art

[0002] The current mainstream LVDS transmission system has a low transmission rate and cannot flexibly adjust the number of data lines (Data Lane) under the premise of meeting the bandwidth. The general video signal interface includes Pixel_clk (pixel clock), Vsync (vertical sync), Hsync (horizontal sync), DataEnable (data valid), and Data (video data). The bandwidth required for video transmission is calculated as follows: (unit: Mbps) Bandwidth = Pixel_Clk × bpp. Where Pixel_Clk refers to the pixel clock frequency, and bpp (bits per pixel) refers to the effective number of bits occupied by one pixel.

[0003] The existing common parallel transmission interfaces are TTL and LVDS. TTL generally transmits at the original Pixel_Clk frequency, that is, Data Rate = Pixel_Clk × 1. The common transmission mode of LVDS is VESA (OpenLDI) / JEIDA (SPWG), and its Data Rate = Pixel_Clk × 7. These two modes can be collectively referred to as the "XN mode". This fixed XN mode has many application limitations. The X1 (TTL) mode requires too many PINs and has a maximum speed of 300 Mbps. The number of data lines (Lane_num) required by the XN mode can be obtained by dividing bpp by N. Therefore, when bpp and N are determined, Lane_num is fixed; no matter how low the input maximum clock frequency Pixel_Clk is, the corresponding Lane must be fully utilized. And the input maximum clock frequency Pixel_Clk can be calculated by the maximum bandwidth per Lane and N.

[0004] Disadvantages of the prior art: 1. The adjustment of the Data Lane number and bandwidth utilization is not flexible enough, and it is impossible to achieve the highest bandwidth of the Lane to minimize the Lane num; 2. Under the premise of meeting the bandwidth, due to the Lane number limitation, no XN mode supports all Timings of 4K60 and below, that is, different video formats need to switch modes, which is inconvenient to use; 3. The VESA - format dual - pixel mode cannot send Timing with a pixel clock of 594MHz for 4K60. If the quad - pixel mode is used, too many PINs are occupied. Summary of the Invention

[0005] An object of the present invention is to provide a data transmission system for an LVDS interface in view of the deficiencies of the existing technology.

[0006] To achieve the above object, the present invention provides a data transmission system for an LVDS interface, including a transmitting end and a receiving end. The transmitting end includes: A first splicing module, configured to receive video data, splice each row of pixel data in the video data, and then write the spliced video data into a first FIFO memory. The first FIFO memory is configured to temporarily store the spliced video data written by the first splicing module. A mapping module, configured to read the spliced video data from the first FIFO memory, receive the number of data lines sent externally, and then map the spliced video data to the corresponding data lines in sequence according to the number of data lines and the mapping principle, and generate a row - data valid signal during mapping. Each time, 1 byte is mapped as a group for mapping. A first conversion module, configured to convert each group of data with a bit width of 1 byte mapped to the data line into a serial bit - stream data with a bit width of 1 bit, and send the converted serial bit - stream data with a bit width of 1 bit and the row - data valid signal to the receiving end. The receiving end includes: A second conversion module, configured to receive the data sent by the first conversion module from the data line, obtain the boundary of the serial bit - stream according to the row - data valid signal for boundary alignment, and then convert the serial bit - stream data with a bit width of 1 bit into data with a bit width of 1 byte for each group. An unpacking module, configured to perform validity judgment on each group of data with a bit width of 1 byte converted by the second conversion module, and generate a CRC stable signal after the validity judgment passes. A second splicing module, configured to splice each group of data with a bit width of 1 byte converted by the second conversion module, and write the spliced video data into a second FIFO memory. The second FIFO memory is configured to receive the video data spliced by the second splicing module, and temporarily store the received spliced video data in sequence when receiving the CRC stable signal. A video timing generation module, configured to read the spliced video data from the second FIFO memory and restore it to standard data conforming to the video transmission protocol.

[0007] Further, the first splicing module splices the valid data of each pixel in the video data according to the number of valid bits occupied by one pixel.

[0008] Further, when the mapping module sequentially maps the spliced video data to the corresponding data lines, the video data read from the first FIFO memory for the first time is mapped starting from the first data line Lane1, and is mapped in sequence from bottom to top according to the data line numbers. If there is still remaining video data after all the data lines in the current cycle are mapped, continue to map cyclically starting from the first data line Lane1 until all the video data read this time is mapped. In subsequent FIFO read operations, the mapping start position will inherit the data line position where the previous mapping was completed. Further, after the last line of video data in each frame, a configuration information packet is sent on the first data line lane1, and the configuration information packet contains the information required for the receiving end to receive and process the data on the data line.

[0009] Further, the information includes the effective time of the data valid signal and the amount of valid data occupied by the last cycle of the data valid signal. The specific calculation method is as follows: Calculate the number of cycles N of the effective time of the data valid signal occupying the first FIFO memory as: N = (Hactive bpp) / (Lane_num 8) where Hactive is the number of valid pixels, bpp is the number of valid bits occupied by one pixel, and Lane_num is the number of data lines; Calculate the number of bits occupied by the data on the data line in the last cycle according to the number of valid pixels, and then determine the amount of valid data occupied by the last cycle of the data valid signal.

[0010] Further, the sending end further includes a packet arbitration module, and the packet arbitration module is used to receive other types of data packets, such as audio packets. During the short blank period after the transmission of the valid pixel data is completed, the mapping module is also used to sequentially map the data in other types of data packets to the corresponding data lines, and convert the data in other types of data packets mapped to the data lines into serial bit stream data through the first conversion module, and then send it to the receiving end; The unpacking module is also used to parse and process the data in other types of data packets converted by the second conversion module.

[0011] ​Further, the first conversion module supports sending data at a fixed rate, so that the receiving end can perform one clock calibration and then adapt to and stably receive video data of multiple different resolutions.

[0012] Beneficial effects: 1. Avoid the problem of rigid number of Lanes in the XN mode, and maximize the utilization rate of the LVDS interface for bandwidth; 2. Whether it is Progressive Video, Interlaced Video, VRR Video, or FreeSync Video, according to the Vsync position and valid timing parameters, the Pixel clock can be accurately restored, and infinite cascading can be achieved thereby; 3. Avoid sending Video's Hsync / Vsync signals, saving the overhead of Lanes; 4. Flexibly transmit other types of data packet modes. Except for the packet header (Header) and the immediately following packet length (Length), the rest of each type of data packet can be customized; 5. The sending end can transmit configuration information to the receiving end, and the downstream can automatically configure relevant modes; 6. Support the fixed Data Rate mode, greatly simplifying the calibration process of the receiving end. Description of the Drawings

[0013] Figure 1 is the principle block diagram of the sending end of the embodiment of the present invention; Figure 2 is the principle block diagram of the receiving end of the embodiment of the present invention; Figure 3 is the schematic diagram of mapping data to the data line; Figure 4 is the schematic diagram of mapping the data in the configuration information packet to the data line; Figure 5 is the schematic diagram of mapping the data in other types of data packets to the data line. Detailed Embodiments

[0014] The following combines the drawings and specific embodiments to further clarify the present invention. These embodiments are implemented on the premise of the technical solution of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention.

[0015] As Figure 1 and Figure 2 shown, the embodiment of the present invention provides a data transmission system for an LVDS interface, including a sending end and a receiving end. Among them, the sending end includes a first splicing module 11, a first FIFO memory 12, a mapping module 13, and a first conversion module 14.

[0016] The first splicing module 11 is used to receive video data, splice each row of pixel data in the video data, and then write the spliced video data into the first FIFO memory 12. Refer to Figure 1 , in addition to the above video data, the first splicing module 11 generally also receives signals such as pixel clock (Pixel_clk), vertical synchronization (Vsync), horizontal synchronization (Hsync), data valid (DataEnable), etc. These are all prior arts and their uses will not be specifically described. The specific splicing method is to splice the valid data of each pixel in the video data according to the number of valid bits bpp (bits per pixel) occupied by one pixel.

[0017] The first FIFO memory 12 is used to temporarily store the spliced video data written by the first splicing module 11.

[0018] The mapping module 13 is used to read the spliced video data from the first FIFO memory 12, receive the number of data lines lane_num sent externally, and then map the spliced video data to the corresponding data lines in sequence according to the number of data lines lane_num and the mapping principle, and generate a line data valid signal DataDE during the mapping. Each time, 1 byte is mapped as a group. When the mapping module 13 maps the spliced video data to the corresponding data lines in sequence, the video data read from the first FIFO memory for the first time starts to be mapped from the first data line Lane1, and is mapped in sequence from bottom to top according to the data line number. If there is still remaining data after all the data lines in the current cycle are mapped, continue to map from the first data line Lane1 in a loop until all the video data read this time is mapped. After the mapping of the video data read this time is completed, continue to read data from the first FIFO memory 12, and the mapping start position will inherit the data line position where the previous mapping was completed. The maximum number of supported data lines lane_num can be obtained by the following method: Lane_num = ⌈Total Data Rate / Per Lane Max Data Rate⌉ Where, Total Data Rate represents the total bandwidth of the video data to be transmitted, Per Lane Max DataRate is the maximum bandwidth of each Lane, and ⌈.⌉ is the ceiling symbol. The value of Lane_num can be calculated according to actual requirements and can be selected between 1 and 50.

[0019] The first conversion module 14 is used to convert each group of data with a bit width of 1 byte mapped to the data line into serial bit-stream data with a bit width of 1 bit, thereby forming a bit stream, and sending the converted serial bit-stream data with a bit width of 1 bit and the line data valid signal to the receiving end.

[0020] The receiving end of the embodiment of the present invention includes a second conversion module 21, a unpacking module 22, a second splicing module 23, a second FIFO memory 24, and a video timing generation module 25.

[0021] The second conversion module 21 is used to receive the data sent by the first conversion module from the data line, obtain the boundary of the serial bit stream according to the line data valid signal, and perform boundary alignment. Then, the serial bit-stream data with a bit width of 1 bit is converted into data with a bit width of 1 byte for each group.

[0022] The unpacking module 22 is used to perform validity judgment on each group of data with a size of 1 byte converted by the second conversion module 21, including frame header identification, Lane length parsing, valid data extraction, CRC check and judgment, etc., and generate a CRC stable signal after the validity judgment passes.

[0023] The second splicing module 23 is used to splice each group of video data with a bit width of 1 byte converted by the second conversion module 21, and write the spliced video data into the second FIFO memory 24.

[0024] The second FIFO memory 24 is used to receive the spliced video data of the second splicing module 23, and temporarily store the received spliced video data in sequence when receiving the CRC stable signal.

[0025] The video timing generation module 25 is used to read the spliced video data from the second FIFO memory 24 and restore it to standard data conforming to the video transmission protocol. Specifically, when a certain depth is written into the second FIFO memory 24, the video timing generation module 25 is started, and signals such as data valid, HSync, and VSync are generated by the video timing generation module 25; then, the video data in the second FIFO memory 24 is taken out in sequence, and the video data after reading the second FIFO memory 24 is restored to standard data conforming to the video transmission protocol using the data valid signal.

[0026] After the last line of video data in each frame, a configuration information packet is sent on the lane1 data line. The configuration information packet contains information required for the receiving end to receive and process the data on the data line, including bpp, lane_num, and video timing parameters, etc. In addition, it also includes the valid time of the data valid signal and the amount of valid data occupied by the last cycle of the data valid signal. The specific calculation method is as follows: The number of cycles N that the valid time of the calculated data valid signal occupies for reading the first FIFO memory is: N = (Hactive * bpp) / (Lane_num * 8) where Hactive is the number of valid pixels, bpp is the number of valid bits occupied by one pixel, and Lane_num is the number of data lines; Calculate the number of bits occupied by the data on the data line in the last cycle according to the number of valid pixels, and then determine the amount of valid data occupied by the last cycle of the data valid signal.

[0027] The sending end further includes a packet arbitration module 15. The packet arbitration module 15 is used to receive other types of data packets, such as Audio or other custom packets. During the short blank period (Video Blank) after the transmission of the valid pixel data is completed, the mapping module 13 is also used to sequentially map the data in other types of data packets to the corresponding data lines, and convert the data in other types of data packets mapped to the data lines into serial bit stream data through the first conversion module 14, and then send it to the receiving end. The unpacking module 22 is also used to parse the data in other types of data packets after being converted by the second conversion module 21, and then send the content of the parsed data packet to the subsequent corresponding processing modules, such as the Audio processing module, etc. When the above other types of data packets are sent to the packet arbitration module 15, a request message pkt_req is also sent. The packet arbitration module 15 arbitrates these requests, and only one data packet is sent at the same time.

[0028] For the convenience of the receiving end to receive, the first conversion module 14 of the embodiment of the present invention supports sending data at a fixed rate (Lane pixel clock), so that the receiving end can perform one clock calibration to adapt to and stably receive video data of multiple different resolutions. At this time, the data is discontinuous. The sending end needs to give a Data Valid signal to indicate when the data is valid during the valid period of this line of data.

[0029] The following is combined with Figures 3 to 5 for specific description: See Figure 3 , for video transmission based on the LVDS transmission standard of up to 1.5 Gbps per Lane, taking Htotal = 120, Hactive = 100, bpp = 30, Lane_num = 4, Pixel_clk = 150Mhz as an example. Hactive = 100 has a total of 100 valid pixel data. According to bpp, the pixel valid bits are spliced and cut into bytes, and each 8 bits is divided into a group for each Lane. Lane PHY clock = DataRate = Pixel_clk bpp / Lane_num = 150 30 / 4 = 1125 Gbps. If the maximum bandwidth per Lane does not exceed 1.5 Gbps, then the DataRate cannot be greater than 1.5 Gbps. The maximum input Pixel_clk supported under the condition of meeting the maximum bandwidth can be calculated through DataRate. Each byte is sent as a group to the analog side as an analog interface, and Phy_Clk = DataRate / 8. When mapping the data, a data valid signal DE_Lane needs to be given, and the valid 8-bit data boundary can be obtained through De_Lane.

[0030] See Figure 4 , which supports the transmission scheme proposed by the current LVDS interface data transceiver module. After the last line of video data in each frame, a configuration information packet is sent on the first data line lane1. The data of the configuration information packet includes information such as Lane_num and bpp required for the receiving module to receive data on the Lane. A complete frame data packet includes: frame header, packet length length, bpp, Lane_num, valid timing parameters such as H / V Total / Active / Front / Sync / Back / Polarity / Interlaced / Progressive, and CRC check. Taking 0xAA as an example for the frame header, the receiving end can uniquely identify the configuration information packet through De_Lane and 0xAA to obtain the valid information.

[0031] See Figure 5 , Audio and other data packets can be sent during the video Blank. Different packet headers represent different types. Except for the packet header and the immediately following packet length Length for each type, the rest can be customized. If a continuous packet request is received, the packet header of the second data packet can be immediately after the packet tail of the first data packet, so as to utilize the effective bandwidth. In addition, a Vsync packet needs to be sent to identify the moment when Vsync arrives. The Vsync packet includes a frame header (0xAB) and the number of cycles from Vsync to the packet header of the Vsync packet. Since Vsync may arrive when receiving Audio and other data packets, the packet header of the Vsync packet may have a delay of several cycles relative to Vsync. Therefore, when sending the Vsync packet to identify the position of Vsync, the number of cycles from Vsync to the packet header of the Vsync packet needs to be sent, so that the receiving module can accurately obtain the position of Vsync, which is beneficial to clock recovery and can accurately recover the Pixel timing.

[0032] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, the parts not specifically described belong to the prior art or common general knowledge. Without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A data transmission system for an LVDS interface, comprising a transmitting end and a receiving end, characterized in that: The transmitting end comprises: A first splicing module, used for receiving video data, splicing each row of pixel data in the video data, and then writing the spliced ​​video data into a first FIFO memory; A first FIFO memory, used for temporarily storing the spliced ​​video data written by the first splicing module; A mapping module, used for reading the spliced ​​video data from the first FIFO memory, and receiving the number of data lines sent externally, and then mapping the spliced ​​video data to the corresponding data lines in sequence according to the number of data lines and the mapping principle, and generating a row data valid signal during the mapping period, mapping 1 byte each time as a group; A first conversion module is used to convert each group of data with a bit width of 1 byte mapped to the data line into serial bit stream data with a bit width of 1 bit, and send the converted serial bit stream data with a bit width of 1 bit and a row data valid signal to the receiving end; The receiving end comprises: The second conversion module is used to receive the data sent by the first conversion module from the data line, obtain the boundary of the serial bit stream according to the row data valid signal, perform boundary alignment, and then convert the serial bit stream data with a bit width of 1 bit into data with a bit width of 1 byte per group; An unpacking module, used for performing validity judgment on each group of data with a bit width of 1 byte after the conversion by the second conversion module, and generating a CRC stable signal after the validity judgment is passed; A second splicing module is used to splice each group of video data with a bit width of 1 byte after being converted by the second conversion module, and write the spliced ​​video data into a second FIFO memory; A second FIFO memory is used to receive the video data spliced ​​by the second splicing module, and to temporarily store the received spliced ​​video data in sequence when a CRC stable signal is received; The video timing generation module is used to read the spliced ​​video data from the second FIFO memory and restore it to standard data that complies with the video transmission protocol.

2. A data transmission system for LVDS interface according to claim 1, characterized in that: The first splicing module splices the valid data of each pixel in the video data according to the number of valid bits occupied by one pixel.

3. A data transmission system for LVDS interface according to claim 1, characterized in that: When the mapping module maps the spliced ​​video data to the corresponding data lines in sequence, the video data read from the first FIFO memory for the first time is mapped starting from the first data line Lane 1, and is mapped sequentially from bottom to top according to the data line number. If there is still remaining video data after all video data lines in the current cycle are mapped, the mapping continues in a loop starting from the first data line Lane 1 until all the video data read this time are mapped. In subsequent FIFO reading operations, the mapping start position will inherit the data line position where the last mapping was completed.

4. A data transmission system for LVDS interface according to claim 1, characterized in that: After the last line of video data in each frame, a configuration information packet is sent on the first data line lane1, and the configuration information packet contains information required by the receiving end to receive and process the data on the data line.

5. A data transmission system for LVDS interface according to claim 4, characterized in that: The information includes the effective time of the data valid signal and the effective data volume occupied by the last cycle of the data valid signal, and the specific calculation method is as follows: The effective time of the data valid signal is calculated as the number N of cycles of reading the first FIFO memory: N=(Hactive bpp) / (Lane_num 8) Among them, Hactive is the number of effective pixels, bpp is the number of effective bits occupied by a pixel, and Lane_num is the number of data lines; The number of bits occupied on the data line in the last cycle is calculated according to the number of valid pixels, and then the amount of valid data occupied in the last cycle of the data valid signal is determined.

6. A data transmission system for LVDS interface according to claim 1, characterized in that: The transmitting end further includes a packet arbitration module, the packet arbitration module is used to receive other types of data packets, and during a blank period after the effective pixel data transmission is completed, the mapping module is also used to map the data in the other types of data packets to the corresponding data lines in sequence, and convert the data in the other types of data packets mapped to the data lines into serial bit stream data through the first conversion module, and then send them to the receiving end; The unpacking module is also used to parse and process the data in other types of data packets converted by the second conversion module.

7. A data transmission system for LVDS interface according to claim 1, characterized in that: The first conversion module supports sending data at a fixed rate, so that the receiving end can adapt to and stably receive video data of multiple different resolutions by performing a clock calibration once.

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