Flash memory controller and control method thereof

Abstract

The invention provides a flash memory controller and a control method of the flash memory controller, after the flash memory controller completes power-on reset, a host side controller issues configuration information and an instruction of a register to the flash memory controller, and the instruction is written into an instruction cache; reading the instruction from the instruction cache, and decoding an operation code, an instruction weight and a command index corresponding to the instruction according to an instruction format; the weighted arbiter arbitrates and outputs instruction indexes from the instruction queues of all the states according to the weights, and the instruction indexes are stored in a command index buffer in the flash memory controller; and reading the instruction index from the instruction index buffer, and completing the reading of the command word according to the instruction index in the instruction corresponding to the instruction index. By customizing the instruction format, the weighted scheduling of different operations of the flash memory controller can be realized, the response sequence of each instruction of the arbiter can be dynamically adjusted by changing the weight value in the instruction code, and the quick response and dynamic scheduling of high-priority instructions can be realized.

Description

Technical Field

[0001] The present invention relates to the field of flash memory controllers, and more particularly, to a flash memory controller and a control method thereof. Background Art

[0002] Flash-based solid-state memories have advantages such as large capacity, low power consumption, strong anti-vibration ability, and fast read and write speeds, and have been widely used in various storage systems or application processing systems.

[0003] The organizational structure of a flash memory chip is hierarchical, including flash memory particles (Package), chips (Chip), wafers (Die), groups (Plane), blocks (Block), and pages (Page) from top to bottom. The concurrency levels and read / write latencies of different levels are different, and the performance of its read / write depends on the flash memory controller architecture and the adopted scheduling strategy.

[0004] A flash memory controller usually includes a control register, a data read / write buffer, and a logic control module. The host-side controller issues commands or command words to the flash memory controller to complete operation issuing. However, the latencies and priorities of different operations executed by the flash memory particles are different. Conventional flash memory controllers cannot specify the response order of each instruction, making it difficult to achieve fast response and dynamic scheduling for high-priority instructions. Existing flash-based storage systems adopt a multi-channel design. As the number of channels increases, the task scheduling overhead of the main controller becomes larger, the transmission efficiency of a single channel decreases, and the latency increases, resulting in a decline in service quality. Different types of flash memory particles have different time overheads when performing different operations. It is difficult for the software running in the host-side controller to implement more complex wear leveling scheduling algorithms and multi-channel concurrency control, which requires the flash memory controller to provide the time overhead and operating status of the flash memory particles when performing different operations. During actual operation, the host-side controller continuously migrates and aggregates valid data, and initiates an erase command to release the idle Block in the flash memory particles to handle the continuous write requests from the host. Since flash memory erase and write commands are high-latency requests, much higher than read commands, once an erase operation is initiated at a certain moment, the corresponding Die cannot respond to low-latency read commands until the erase operation or write operation is completed, resulting in a large request latency for the host. Summary of the Invention

[0005] In view of the technical problems existing in the prior art, the present invention provides a flash memory controller and a control method thereof, which can overcome the problem that it is difficult to dynamically adjust the response order of different operations in the flash memory controller by implementing the scheduling of the flash memory controller through software.

[0006] According to a first aspect of the present invention, there is provided a flash memory controller, including an instruction cache, registers, an instruction fetching and decoding module, a weighted arbiter, a command request and transmission module, and a scheduler module; After the flash memory controller completes power-on reset, the host-side controller issues configuration information and instructions of the registers to the flash memory controller through the AXI-Lite interface, and writes the instructions into the instruction cache in the flash memory controller; The instruction fetching and decoding module of the flash memory controller reads instructions from the instruction cache, and decodes an operation code, an instruction weight, and a command index corresponding to the instruction from the instructions according to the instruction format; The weighted arbiter in the flash memory controller arbitrates and outputs an instruction index from the instruction queues in each state according to the weight, and stores the instruction index in a command index buffer inside the flash memory controller; The command request and transmission module reads the instruction index from the command index buffer, and completes the reading of the command word according to the command index in the instruction corresponding to the instruction index; The scheduler module in the flash memory controller completes the control of the write operation state machine, the read operation state machine, and the erase operation state machine, and realizes the scheduling control of the flash memory particles.

[0007] According to a second aspect of the present invention, there is provided a control method for a flash memory controller, the flash memory controller including an instruction cache, registers, an instruction fetching and decoding module, a weighted arbiter, a command request and transmission module, and a scheduler module, the control method including: After the flash memory controller completes power-on reset, the host-side controller issues configuration information and instructions of the registers to the flash memory controller through the AXI-Lite interface, and writes the instructions into the instruction cache in the flash memory controller; Read instructions from the instruction cache through the instruction fetching and decoding module, and decode an operation code, an instruction weight, and a command index corresponding to the instruction from the instructions according to the instruction format; Arbitrate and output an instruction index from the instruction queues in each state according to the instruction weight through the weighted arbiter, and store the instruction index in a command index buffer inside the flash memory controller; Read the instruction index from the command index buffer through the command request and transmission module, and complete the reading of the command word according to the command index in the instruction corresponding to the instruction index; Complete the control of the write operation state machine, the read operation state machine, and the erase operation state machine through the scheduler module, and realize the scheduling control of the flash memory particles.

[0008] A flash memory controller and a control method thereof provided by the present invention. After the flash memory controller completes power-on reset, the host-side controller sends the configuration information and instructions of the register to the flash memory controller, and writes the instructions into the instruction cache; reads the instructions from the instruction cache, decodes the operation code, instruction weight, and command index corresponding to the instruction according to the instruction format; the weighted arbiter arbitrates and outputs the instruction index from the instruction queues in each state according to the weight, and stores the instruction index in the command index buffer inside the flash memory controller; reads the instruction index from the command index buffer, and completes the reading of the command word according to the command index in the instruction corresponding to the instruction index. By customizing the instruction format, the present invention can achieve weighted scheduling of different operations of the flash memory controller, and can dynamically adjust the response order of each instruction of the arbiter by changing the weight value in the instruction code, so as to achieve fast response and dynamic scheduling of high-priority instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic diagram of the instruction format of the flash memory controller of the present invention; Figure 2 It is a schematic diagram of the structure of a flash memory controller provided by the present invention; Figure 3 It is a schematic diagram of the structure of the weighted arbiter; Figure 4 It is a flowchart of the working process of the weighted arbiter; Figure 5 It is a schematic diagram of the state transition of the read DMA request state machine of the command request and emission module; Figure 6 It is a flowchart of the working process of the scheduler module; Figure 7 It is a schematic diagram of the state transition of the write operation state machine; Figure 8 It is a schematic diagram of the state transition of the erase operation state machine; Figure 9 It is a schematic diagram of the state transition of the recovery operation state machine; Figure 10 It is a flowchart of the control method of a flash memory controller provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0010] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention. In addition, the technical features in each embodiment or individual embodiment provided by the present invention can be combined with each other arbitrarily to form a feasible technical solution. This combination is not restricted by the order of steps and / or the structural composition mode, but must be based on what can be achieved by those of ordinary skill in the art. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0011] Based on the deficiencies of the prior art, the present invention proposes a flash memory controller, designs a custom instruction format for the flash memory controller, and according to the weight information in the instruction, the scheduler and the weighted arbiter can dynamically adjust the emission and response order of different operations in the flash memory controller, thereby achieving a fast response to high-priority instructions. Implementing the priority scheduling of different operations within a single channel through hardware can effectively reduce the overhead when the software performs task scheduling, reduce the response time of task suspension and resume operations within a single channel, improve the transmission efficiency of a single channel, and reduce latency. The flash memory controller is built with a performance monitoring module and a status register, which can count and record the time overhead and operating status of the flash memory particles when performing different operations, helping the software to implement more complex wear leveling scheduling and multi-channel concurrent control; the scheduler provides erase suspension, write suspension, and suspension resume support. By setting up a task stack, task resume logic, and data cache, the software can achieve a fast resume after erase suspension and write suspension operations without having to resend commands and data.

[0012] Before introducing the flash memory controller provided by the present invention, the custom instruction format of the present invention will be described. Among them, referring to Figure 1 , it is an instruction format for a flash memory controller proposed by the present invention. The instructions can be divided into two categories: 16-bit standard instructions and 32-bit extended instructions. The high 16-bit formats of the standard instructions and the extended instructions are the same. The highest bit of the opcode is a flag bit indicating whether the instruction is an extended instruction. When the highest bit is 1, it means the current instruction is an extended instruction; when the highest bit is 0, it means the current instruction is a standard instruction.

[0013] According to different operation codes, the standard instructions for the flash memory controller can be further divided into read, erase, write, erase suspend, write suspend, write suspend resume, erase suspend resume, and channel status read. The extended instructions for the flash memory controller can be further divided into copy, copy programming, and copy erase. The "channel" in the instruction specifies the channel number targeted by the current operation and can be used for the multi-channel expansion of the flash memory controller. The "weight" in the instruction specifies the scheduling priority of the operation corresponding to the current instruction. Level 0 has the highest priority, level 1 has a priority only lower than level 0, level 2 has a priority only higher than level 3, and level 3 has the lowest priority. The "command index" in the instruction specifies the offset of the starting address of the command word corresponding to the current instruction in the DDR relative to the base address of the command buffer of this channel.

[0014] The flash memory controller architecture proposed by the present invention is as Figure 2 shown. The flash memory controller consists of an instruction cache, registers, an instruction fetching and decoding module, a scheduler module, a status write-back module, a command request and emission module, a read / write DMA module, read / write data channels, a data stream multiplexer, and a flash memory interface module. Figure 2 The host-side controller in can adopt a processor core based on the RISC-V architecture or the ARM architecture and perform read / write data transfer, instruction distribution, and register configuration on the flash memory controller through the AXI bus. The page mapping area of the DDR stores the page mapping table for flash memory page mapping management, the data area stores the data read from the flash memory die or the data to be written to the flash memory die, the control firmware area stores the wear-leveling control algorithm for improving the service life of the flash memory die, the storage protocol stack stores the storage protocol for the interaction between the host-side controller and the host CPU file system, and the command buffer stores the command words to be transmitted to the flash memory controller. The flash memory interface module is used to transmit the microcode issued by the erase operation state machine, read operation state machine, write operation state machine, and erase / write suspend resume operation state machine in the scheduler to the flash memory die and complete the data transfer between the data stream multiplexer and the flash memory die.

[0015] Figure 2 The working principle of the flash memory controller in is as follows: After the flash memory controller completes power-on reset, the host-side controller issues the configuration information of the control register, the initialization information of the status register, and the configuration information of the parameter register to the flash memory controller through the AXI-Lite interface with a 64-bit data width. The host-side controller issues instructions to the flash memory controller through the AXI-Lite interface with a 64-bit data width and writes them into the instruction cache in the flash memory controller. The instruction fetching and decoding module of the flash memory controller reads the instructions from the instruction cache and according to Figure 1The instruction format shown decodes the operation code, instruction weight, and command index corresponding to the instruction. The weighted arbiter in the flash memory controller arbitrates and outputs the instruction sequence number from the instruction queues in each state according to the instruction weight, and the instruction sequence number is stored in the command index buffer inside the flash memory controller. The command request and transmission module reads the command word according to the command word index and controls the write operation state machine, read operation state machine, and erase operation state machine through the scheduler module, thereby realizing the scheduling control of the flash memory particles. Among them, the write cache of the write channel includes write cache 0 and write cache 1. The write cache has two states, dirty and clean, which are used to indicate whether the data in write cache 0 or write cache 1 has been overwritten by other write operations since the last write operation. The write operation state machine and write suspend resume operation state machine are responsible for generating the selection signal of the write cache data selector.

[0016] The following details each hardware module in the flash memory controller.

[0017] A. Instruction Cache and Registers: The instruction cache of the flash memory controller proposed by the present invention is implemented based on a synchronous first-in-first-out (FIFO) queue. The data bit width of the instruction cache is 64 bits, the queue depth is 16, and the memory is implemented using dual-port RAM, with independent write and read ports, which can accommodate 64 standard instructions or 32 extended instructions simultaneously.

[0018] The registers of the flash memory controller proposed by the present invention include a control register, a status register, and a parameter register. The bit width of all registers is 64 bits, which is consistent with the bus data bit width.

[0019] The control register stores the configuration information of the flash memory controller, which is used to specify whether to enable the ECC check function and whether to enable the hardware scrambling function.

[0020] The status register stores the instruction status information of the flash memory controller and includes three 64-bit registers. The first register uses 64-bit one-hot encoding, corresponding to 64 standard instructions of a single channel of the flash memory controller, and is used to specify the ready status of the current instruction; the second register of the status register uses 64-bit one-hot encoding, corresponding to 64 standard instructions of a single channel of the flash memory controller, and is used to specify the ready type of the instruction; the third register of the status register uses 64-bit one-hot encoding, corresponding to the number of clock cycles consumed by the previous command executed by the flash memory controller, and is used to evaluate the time overhead of the last operation. The instruction status of the flash memory controller of the present invention includes three states, namely, the ready state (both bit fields of the first register and the second register are 1), the non-ready state (the first register is 0 and the second register is 0), the suspended state (the first register is 1 and the second register is 0), and the abnormal state (the first register is 0 and the second register is 1). When a given operation is completed, the state machine in the scheduler initiates an instruction ready state write-back operation and updates the status register; when a given operation (erase or program operation) is suspended, the state machine in the scheduler initiates an instruction suspended state write-back operation and updates the status register; when a given operation fails to resume or times out, the state machine in the scheduler initiates an instruction abnormal state write-back operation and updates the status register; when a given operation is successfully transmitted from the flash memory command request and transmission module, the corresponding operation state machine in the scheduler resets the instruction status to the non-ready state during the initialization operation of the state machine.

[0021] The parameter register is used to specify the read and write timing parameters of the flash memory die, and is used to specify the number of clock cycles occupied by the address part of the erase operation command sent by the flash memory controller to the flash memory die, the number of clock cycles occupied by the address part of the read and write operation commands sent by the flash memory controller to the flash memory die, the number of clock cycles between the end address of the write operation and the first byte of the write data, and the input delay of the DQ and DQS signals of the flash memory interface module.

[0022] B. Instruction Decoding and Weighted Arbiter: The instruction fetch width of the instruction fetch and decoding module of the flash memory controller proposed by the present invention is 64 bits (8 bytes), corresponding to 4 standard instructions or 2 extended instructions. According to Figure 1 the flash memory controller instruction format shown, the decoding circuit extracts the operation code and weight in the instruction, and writes the extracted instruction index into the Figure 3 instruction queue in the weighted arbiter according to the different instruction weights. The instruction queue in the weighted arbiter consists of a level 0 queue, a level 1 queue, and a level 2 queue, all implemented by a synchronous FIFO circuit. Among them, the level 0 queue has the highest priority, the level 1 queue has the second highest priority, and the level 2 queue has the lowest priority.

[0023] As Figure 3As shown in the figure, the weighted arbiter of the flash memory controller proposed by the present invention is composed of a fixed priority arbiter and a round-robin priority arbiter. The request sources of the weighted arbiter come from three instruction queues with different weights inside the arbiter, and an arbitration request is initiated to the arbiter only when the instruction queue is not an empty queue. If the instruction queue with a weight of 0 is empty, the instruction queues with weights of 1 or 2 will reassign priorities according to the result of the previous arbitration and apply them to the next arbitration. The response signal generated by the arbiter will be used as the selection terminal signal of the secondary data selection path to select one of the three command word index queues and write it into the command index buffer queue. The advantage of this method is that for operations such as erase suspension, write suspension, and suspension recovery, the host-side controller can dynamically adjust the response order of each instruction of the arbiter by changing the weight value in the instruction code, so as to achieve fast response and dynamic scheduling of high-priority instructions.

[0024] The working process of the weighted arbiter for the flash memory controller proposed by the present invention is as Figure 4 shown, and mainly includes the following steps: Step S101: According to the instruction weight decoded by the instruction decoding circuit, write the instruction index into the instruction queue corresponding to the weight; if the decoded weight is 0, write the instruction index into the 0-level queue; if the decoded weight is 1, write the instruction index into the 1-level queue; if the decoded weight is 2, write the instruction index into the 2-level queue.

[0025] Step S102: Judge the states of the 0-level instruction queue, 1-level instruction queue, and 2-level instruction queue, and use the status signals of the instruction queues with different weights as the source-end requests of the arbiter; whether each instruction queue in the arbiter is in an empty state reflects whether the instruction of the current priority has been issued. If the high-priority instruction has been issued, the 0-level instruction queue should be in a non-empty state, so the non-empty signal of the instruction queue can be used as the source-end request of the arbiter.

[0026] Step S103: If the 0-level instruction queue is in a non-empty state, initiate an arbitration request to the fixed priority arbiter with the non-empty signal of the 0-level instruction queue as the source-end request of the arbiter, and at the same time select and read the instruction index in the 0-level instruction queue and write the instruction index into the command index buffer.

[0027] Step S104: If the 0-level instruction queue is in an empty state and the 1-level instruction queue and 2-level instruction queue are in a non-empty state, initiate an arbitration request to the round-robin priority arbiter with the non-empty signals of the 1-level instruction queue and 2-level instruction queue as the source-end requests of the arbiter; according to the response result of the round-robin priority arbiter, select the command word index to be written into the command index buffer from the output data of the 1-level queue and 2-level queue.

[0028] C. Command Request and Transmission Module: The command request and transmission module of the flash memory controller proposed by the present invention uses the instruction index read from the command index buffer as the command word offset address CMDW_OFFSET_ADDR of the DMA controller, and reads the command word base address CMDW_BASE_ADDR of the DMA controller in the control register inside the flash memory controller. The command word base address and the command word offset address are concatenated to generate a 32-bit command word read address CMDW_RD_ADDR, which is composed of three parts concatenated, that is, CMDW_RD_ADDR = {CMDW_BASE_ADDR[31:10], CMDW_OFFSET_ADDR, 4'b0000}. Among them, CMDW_BASE_ADDR [31:12] is the high 22 bits of the command word base address configured in the control register, CMDW_OFFSET_ADDR is a 6-bit command word index, and 4'b0000 is 4 zero bits, which are used to achieve 16Bytes command word alignment.

[0029] After obtaining the command word read address CMDW_RD_ADDR, the command request and transmission module will initiate a read command word arbitration request to the read-write DMA controller inside the flash memory controller. Since both the command word reading and the data reading process of the write operation need to occupy the read channel of the read-write DMA, the read command word request from the command request and transmission module and the read data request initiated by the write operation state machine need to be further arbitrated. The read-write DMA module of the flash memory controller architecture proposed by the present invention considers the instruction weight when arbitrating the read command word request and the read data request. The read-write arbiter on the read-write DMA side will give priority to requesting the command word corresponding to the instruction with a priority level of 0. The command word reading requests corresponding to the instructions with priority levels of 1 and 2 and the data request for reading the DDR initiated by the write operation state machine will be arbitrated through the polling state machine.

[0030] The command request and transmission module includes a command word cache with a depth of 4 and a data bit width of 128 bits, which is used to cache the command words obtained by the read-write DMA from the DDR, and a command word index cache with a depth of 4 and a data bit width of 8 bits, which is used to cache the command word indexes for which the DMA read requests have been initiated. The command word cache and the command word index cache in the command request and transmission module are implemented using a synchronous FIFO circuit.

[0031] The read DMA request state machine of the command request and transmission module is as Figure 5As shown in the figure, cmdw_req in the state machine is the read DMA request signal, indicating that the command index buffer queue is in a non-empty state. rdma_cmd_ack is the read DMA arbitration response signal, and rdma_req_ack is the read DMA request response signal. The corresponding state transition process is as follows: After initialization, the state is in the IDLE state, indicating that the current command request and transmission module have not received any command word requests. When the command index buffer queue is not an empty queue, the read DMA request signal cmdw_req is 1, and the state of the state machine transfers from the IDLE state to the ARB state, indicating that the current command request and transmission module have received a command word request and start to initiate a read DMA application to the read-write arbiter. When the read-write arbiter responds to the read command word request initiated by the command request and transmission module, the read DMA arbitration response signal rdma_cmd_ack is 1, and the state machine transfers from the ARB state to the REQ state, ready to receive the command word transmitted by the DMA controller to the flash controller. The command word adopted by the flash controller proposed in the present invention is 8 bytes, and the data bit width of the AXI4 bus is 128 bits. Therefore, the AXI4 transmission length of the read DMA request of the command request and transmission module is set to 1. When the read channel of the read-write DMA receives a command from the DDR, the read DMA request response signal rdma_req_ack is 1, and the state machine transfers from the REQ state to the IDLE state.

[0032] The command request and transmission module adopts the method of sequentially transmitting command words. When the command word index cache in the command request and transmission module is not an empty queue, the queue non-empty signal will be used as the command activation signal cmd_active for the erase operation state machine, read operation state machine, write operation state machine, and erase / write suspend operation state machine in the scheduler.

[0033] D. Scheduler module: In addition to the erase operation state machine, read operation state machine, write operation state machine, and erase / write suspend operation state machine that complete the basic flash read, write, and erase operations, the scheduler module of the flash controller proposed in the present invention also includes a task stack for recording current suspended task information, a task recovery logic, and a performance monitoring module.

[0034] The working process of the scheduler module of the flash controller proposed in the present invention is as Figure 6 shown: Step S201: When the command request and transmission module initiates an operation request for an erase operation, read operation, or write operation, the erase operation state machine, read operation state machine, or write operation state machine will exit the idle state and complete the corresponding operation according to the following state machine working process; Step S202: When an erase suspend or write suspend operation occurs during a write operation or an erase operation, the scheduler module writes the value of the write data counter, the command word index corresponding to the current operation, and the command word into the task stack; Step S203: When the state machine of any operation undergoes a state transition, the scheduler module synchronizes the state of the current operation to the bit field of the status register corresponding to the command word index in the flash controller; Step S204: When the state machine of any operation returns to the idle state, the scheduler module synchronizes the current operation time overhead counted by the performance monitoring module to the status register in the flash controller.

[0035] Specifically, the scheduler module proposed by the present invention supports both write operation suspension and erase operation suspension. The write operation state machine is as Figure 7 shown. The cmd_active of the write operation state machine is the command activation signal, indicating that the queue of the command word index cache of the command request and transmission module is non-empty. The use_cmd0, use_cmd1, use_cmd2, use_cmd3, and use_cmd4 of the write operation state machine are ONFI standard commands in different stages of the write operation. The phy_ack signal of the write operation state machine is the reply signal from the flash interface module for completing a single command or single data transmission to the flash die. The phy_ack_final signal of the write operation state machine is the reply signal from the flash interface module for completing the write operation address transmission to the flash die. The cnt_done signal of the write operation state machine is the flag signal indicating that the count value of the write operation data reaches the amount of data to be written. The do_suspend signal of the write operation state machine indicates that a write operation suspension command has been received. The done_suspend signal of the write operation state machine is the suspension response signal received by the flash interface module from the flash die, indicating that the suspension processing of the current write operation has been completed.

[0036] As Figure 7As shown, the state transition and working process of the write operation state machine are as follows: After initialization, the state is in the IDLE state, indicating that there is no current write operation request; when the command index buffer queue is not an empty queue and the command word corresponds to a write operation, cmd_active is 1. According to the different values of use_cmd0, use_cmd1, and use_cmd2, the state of the state machine transitions from the IDLE state to one of the CMD0, CMD1, or CMD2 states, indicating that there is a current write operation request and the write operation command word has been stored in the command word buffer by the DMA controller, and the parsing of the command word has been completed; when the ONFI standard command in the command word is transmitted to the flash memory die through the flash interface module, the write operation state machine waits for the phy_ack signal from the flash interface module. When phy_ack is 1, the write state machine transitions from the CMD2 state to the ADDR state, and transmits the write operation address in the command word to the flash memory die through the flash interface module; when phy_ack_final is 1, it indicates that the flash interface module has transmitted the address to the flash memory die through the ONFI interface. The write state machine transitions from the ADDR state to the WAIT state, and the data path control signal of the data flow multiplexer is enabled, and the write data corresponding to the write operation is transmitted from the DMA to the write cache according to the dirty state of the write cache; if both write caches are dirty, mark any one of the write caches as clean; if only one write cache is dirty, use the write cache in the clean state; if both write caches are clean, write to any one of the write caches; When there is no pending write operation request initiated and the write data is completely written from the write cache to the flash memory die through the flash interface module, the write data count signal cnt_done inside the write operation is 1, and the state machine transitions from the WAIT state to the DIN state; according to the different values of use_cmd3 and use_cmd4, the write operation state machine transitions from the DIN state to the CMD3 or CMD4 state, and sends the corresponding command word to the flash memory die through the flash interface module; when phy_ack is 1, the write state machine transitions from the CMD3 or CMD4 state to the WAIT_ACK state; when phy_ack is 1, the write state machine transitions from the WAIT_ACK state to the IDLE state, pauses the counting of the performance monitoring module, synchronizes the time overhead to the status register in the flash controller, and synchronizes the ready state of the write operation to the status register in the flash controller; When a write operation suspension request occurs and the write data has not been completely written from the write cache to the flash memory die via the flash interface module, the counter value, command word index, and command word of the write data counter inside the write operation are written into the task stack in the scheduler. The data path control signal of the data flow multiplexer is turned off, the current write cache is marked as dirty, and a command word and address information corresponding to the write operation suspension are sent to the flash interface module. The state machine transitions from the WAIT state to the SUSPEND state; when the do_suspend signal is 1, the state machine transitions from the SUSPEND state to the IDLE state, and synchronously synchronizes the suspension state of the write operation to the status register in the flash controller.

[0037] The erase operation state machine is as Figure 8 shown. The cmd_active signal of the state machine is the non-empty signal of the command word index cache queue of the command request and emission module. The use_cmd0, use_cmd1, use_cmd2, and use_cmd3 of the state machine are the ONFI standard commands in different stages of the erase operation. The phy_ack signal of the state machine is the reply signal from the flash interface module for completing a single command or single data transfer to the flash memory die. The phy_ack_final signal of the state machine is the reply signal from the flash interface module for completing the erase operation address transfer to the flash memory die. The do_suspend signal of the state machine indicates that an erase operation suspension command has been received. The done_suspend signal of the state machine is the suspension response signal received by the flash interface module from the flash memory die, indicating that the suspension processing of the current erase operation has been completed.

[0038] As Figure 8As shown in the figure, the state transition and working process of the erase operation state machine are as follows: After initialization, the state is in the IDLE state, indicating that there is no current erase operation request; when the command index buffer queue is not an empty queue and the command word corresponds to an erase operation, cmd_active is 1. According to the different values of use_cmd0, use_cmd1, and use_cmd2, the state of the state machine transitions from the IDLE state to one of the CMD0, CMD1, or CMD2 states, indicating that there is a current erase operation request and the erase operation command word has been stored in the command word cache by the DMA controller, and the parsing of the command word has been completed; when the ONFI standard command in the command word is transmitted to the flash memory chip through the flash memory interface module, the erase operation state machine waits for the phy_ack signal from the flash memory interface module. When phy_ack is 1, the erase state machine transitions from the CMD2 state to the ADDR state, and transmits the erase operation address in the command word to the flash memory chip through the flash memory interface module; when phy_ack_final is 1, it indicates that the flash memory interface module has transmitted the address to the flash memory chip through the ONFI interface. The erase state machine transitions from the ADDR state to the CMD3 state, and sends the corresponding command word to the flash memory chip through the flash memory interface module; when phy_ack is 1, the erase state machine transitions from the CMD3 state to the WAIT_ACK state and starts waiting for the completion of the erase operation; when there is no pending erase operation request initiated and phy_ack is 1, it indicates that the erase operation is completed normally. The erase state machine transitions from the WAIT_ACK state to the IDLE state, pauses the counting of the performance monitoring module, synchronizes the time overhead to the status register in the flash memory controller, and synchronizes the ready state of the erase operation to the status register in the flash memory controller; when a pending erase operation request occurs and phy_ack is 0, it starts sending the command word and address information corresponding to the pending erase operation to the flash memory interface module, and the state machine transitions from the WAIT state to the SUSPEND state; when the do_suspend signal is 1, the state machine transitions from the SUSPEND state to the IDLE state, and synchronizes the pending state of the erase operation to the status register in the flash memory controller.

[0039] The state machines for erase suspension and write suspension recovery operations are as Figure 9As shown, the cmd_active signal of the recovery state machine is the non-empty signal of the command word index buffer queue. The is_erase and is_prg of the state machine respectively indicate that the current operation is erase recovery or write recovery; the prg_idle and ers_idle signals of the state machine indicate whether the write state machine or the erase state machine is in the idle state; the is_dirty signal of the state machine indicates whether the dirty flag set when the write cache used in the previous write operation was pending has been cleared; the rdma_req_ack signal of the state machine indicates whether the data of the previous write operation has been received from the DMA; the cnt_ge signal of the state machine is whether the data position read by the current read data DMA is greater than the data position at the interruption of the previous write operation.

[0040] As Figure 9 shown, the state transition and working process of the recovery operation state machine are as follows: After initialization, the state is in the IDLE state, indicating that there is no current recovery operation request; when the command index buffer queue is not an empty queue and the command word corresponds to a recovery operation, cmd_active is 1. According to whether the instruction is for erase suspend recovery or write suspend recovery, the state of the state machine transfers from the IDLE state to one of the ESR or PRG states; the ERS state indicates that the current operation is erase suspend recovery, and the command word of the previous erase operation will be found from the task stack in the scheduler according to the command word index. When ers_idle is 1, the state machine will transfer from the ESR state to the SR state. When the command word index cannot be found from the task stack, the state machine will transfer from the ESR state to the SR state; in the SR state, the activation operation of the erase state machine will be initiated according to the found command word. When is_idle is 0, the state machine will transfer from the SR state to the IDLE state, and the non-ready state of the erase operation will be synchronized to the status register in the flash controller.

[0041] The PRG state indicates that the current operation is write suspend recovery, and the command word of the previous write operation will be found from the task stack in the scheduler according to the command word index. When prg_idle is 1, the state machine will transfer from the PRG state to the MEM state. When the command word index of the previous write operation cannot be found from the task stack, the state machine will transfer from the PRG state to the IDLE state.

[0042] In the MEM state, the write cache used in the last write operation will be checked according to the found command word. When is_dirty is 1, it means that the data in the write cache used in the last write operation has not been overwritten, and the state machine will transfer from the MEM state to the REQ state; when prg_idle is 1, the state machine will transfer from the REQ state to the SR state, initiate a write state machine activation operation according to the found command word, and reset the write data counter to the pause position of the last write operation read from the task stack; when is_idle is 0, the state machine will transfer from the SR state to the IDLE state, and synchronize the non-ready state of the write operation to the status register in the flash controller.

[0043] When is_dirty is 0, it means that the data in the write cache used in the last write operation has been overwritten, and the state machine will transfer from the MEM state to the ARB state to re-initiate a read request for the write operation data; when rdma_req_ack is 1 and the position of the read write operation data is greater than the data position at the last write operation interruption, the state machine will transfer from the ARB state to the REQ state; when prg_idle is 1, the state machine will transfer from the REQ state to the SR state, initiate a write state machine activation operation according to the found command word, and reset the write data counter to the pause position of the last write operation read from the task stack; and synchronize the non-ready state of the write operation to the status register in the flash controller; when is_idle is 0, the state machine will transfer from the SR state to the IDLE state, and synchronize the non-ready state of the write operation to the status register in the flash controller.

[0044] See Figure 10 , which provides a control method for a flash controller of the present invention. The control method includes: After the flash controller completes power-on reset, the host-side controller sends the configuration information and instructions of the register to the flash controller through the AXI-Lite interface, and writes the instructions into the instruction cache in the flash controller; Read the instructions from the instruction cache through the instruction fetch and decoding module, and decode the operation code, instruction weight, and command index corresponding to the instruction from the instructions according to the instruction format; Arbitrate and output the instruction index from the instruction queues of each state according to the instruction weight through the weighted arbiter, and store the instruction index in the command index buffer inside the flash controller; Read the instruction index from the command index buffer through the command request and emission module, and complete the reading of the command word according to the command index in the instruction corresponding to the instruction index; Complete the control of the write operation state machine, read operation state machine, and erase operation state machine through the scheduler module to achieve the scheduling control of the flash memory particles.

[0045] It is understood that the technical features of the control method of the flash memory controller provided by the present invention can refer to the relevant technical features of the flash memory controller provided in the foregoing embodiments. Therefore, the technical features of the control method of the flash memory controller will not be described repeatedly.

[0046] A flash memory controller and a control method thereof provided by the present invention have the following beneficial effects: (1) Automatically in an instruction format for the flash memory controller, it can achieve weighted scheduling of different operations of the flash memory controller. The response order of each instruction of the arbiter can be dynamically adjusted by changing the weight value in the instruction code, so as to achieve fast response and dynamic scheduling of high-priority instructions.

[0047] (2) The flash memory controller architecture uses the AXI bus to interact with the host-side controller for data and instructions, with strong compatibility. The host-side controller can be implemented using the ARM architecture or the RISC-V architecture.

[0048] (3) The flash memory controller architecture can dynamically adjust the read / write timing parameters of the flash memory particles by configuring parameter registers, which is convenient for prototype verification on the FPGA platform and adapts to different board-level layout schemes.

[0049] (4) The flash memory controller is built with a performance monitoring module and status registers. The host-side controller can read the status registers inside the flash memory controller through the AXI bus, and then obtain the time overhead of the flash memory controller when performing different operations, providing status information for software to implement more complex wear leveling scheduling algorithms and multi-channel concurrent control.

[0050] (5) The flash memory controller architecture implements the priority scheduling of different operations within a single channel through hardware, which can effectively reduce the task scheduling overhead of the host-side controller and reduce the response time of task suspension and task resumption within a single channel.

[0051] (6) The flash memory controller architecture is convenient for multi-channel expansion. The command word base address and read / write data base address of a single channel can be flexibly configured according to the storage space division method of the software. According to the different control capabilities of the host-side controller and the capacity and speed requirements of the storage system, the number of channels supported by the system can be changed by increasing or decreasing the number of flash memory controllers.

[0052] It should be noted that in the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0053] Those skilled in the art will understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) that contain computer-usable program code.

[0054] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices produce means for implementing the functions specified in Figure 1 one or more of the flows Figure 1 or blocks.

[0055] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including instruction means that implement the functions specified in Figure 1 one or more of the flows Figure 1 or blocks.

[0056] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one or more of the flows Figure 1 or blocks.

[0057] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications that fall within the scope of the present invention.

[0058] Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A flash memory controller, characterized in that: The flash memory controller includes an instruction cache, a register, an instruction fetch and decode module, a weighted arbiter, a command request and transmit module, and a scheduler module; After the flash memory controller completes power-on reset, the host-side controller sends register configuration information and instructions to the flash memory controller through the AXI-Lite interface, and writes the instructions into the instruction cache in the flash memory controller; The instruction fetching and decoding module of the flash memory controller reads instructions from the instruction cache, and decodes the operation code, weight and command index corresponding to the instruction from the instruction according to the instruction format; The weighted arbitrator in the flash memory controller arbitrates and outputs instruction indexes from instruction queues in each state according to the weights, and stores the instruction indexes in a command index buffer inside the flash memory controller; The command request and transmission module reads the instruction index from the command index buffer, and completes the reading of the command word according to the command index in the instruction corresponding to the instruction index; The scheduler module in the flash memory controller completes the control of the write operation state machine, the read operation state machine and the erase operation state machine, and realizes the scheduling control of the flash memory particles.

2. The flash memory controller according to claim 1, wherein: The instructions for the flash memory controller are divided into 16-bit standard instructions and 32-bit extended instructions, and the format of the upper 16 bits of the standard instructions and the extended instructions is the same; the upper 16 bits of the standard instructions and the extended instructions include an operation code, a channel, a weight, and a command index; The highest bit of the opcode is a flag indicating whether the instruction is an extended instruction. When the highest bit is 1, it indicates that the current instruction is an extended instruction; when the highest bit is 0, it indicates that the current instruction is a standard instruction. The "channel" in the instruction specifies the channel number for the operation corresponding to the current instruction, which is used for multi-channel expansion of the flash memory controller; the "weight" in the instruction specifies the scheduling priority of the operation corresponding to the current instruction, with level 0 being the highest priority and level 3 being the lowest priority; the "command index" in the instruction specifies the offset of the starting address of the command word in the DDR corresponding to the current instruction relative to the base address of the command buffer of this channel.

3. The flash memory controller according to claim 1, wherein: The registers in the flash memory controller include a control register, a status register and a parameter register, and the bit width of all registers is 64 bits, which is consistent with the bus data bit width; The control register stores the configuration information of the flash memory controller, which is used to specify whether to enable the ECC check function and whether to enable the hardware scrambling and descrambling function; The status register stores instruction status information of the flash memory controller, and the status register includes three 64-bit registers; wherein the first register adopts 64-bit one-hot encoding, corresponding to 64 standard instructions of a single channel of the flash memory controller, and is used to specify the ready state of the current instruction; the second register adopts 64-bit one-hot encoding, corresponding to 64 standard instructions of a single channel of the flash memory controller, and is used to specify the ready type of the current instruction; the third register adopts 64-bit one-hot encoding, corresponding to the number of clock cycles consumed by the last command executed by the flash memory controller, and is used to evaluate the time overhead of the last operation; the instruction status information of the flash memory controller is indicated according to the first register and the second register, and the instruction status information includes ready state, non-ready state, suspended state and abnormal state; The parameter register is used to specify the read and write timing parameters of the flash memory particles, and is used to specify the number of clock cycles occupied by the address part of the erase operation command sent by the flash memory controller to the flash memory particles, the number of clock cycles occupied by the address part of the read and write operation command sent by the flash memory controller to the flash memory particles, the number of clock cycles between the end address of the write operation and the first byte of the write data, and the input delay of the DQ and DQS signals of the flash memory interface module.

4. The flash memory controller according to claim 1, wherein: The instruction fetching and decoding module of the flash memory controller reads instructions from the instruction cache, and decodes an operation code, an instruction weight, and a command index corresponding to the instruction from the instruction according to the instruction format, including: The instruction fetch and decode module reads instructions from the instruction cache, extracts opcodes and weights from the instructions according to the instruction format, and writes instruction indexes into the instruction queues in the weighted arbitrator according to different weights. The instruction queues in the weighted arbitrator include level 0 queues, level 1 queues, and level 2 queues, wherein the level 0 queue has the highest priority, the level 1 queue has the second highest priority, and the level 2 queue has the lowest priority.

5. The flash memory controller according to claim 4, characterized in that: The weighted arbitrator includes a fixed priority arbitrator and a round-robin priority arbitrator. The weighted arbitrator in the flash memory controller arbitrates and outputs instruction indexes from instruction queues in each state according to the weights, and stores the instruction indexes in a command index buffer inside the flash memory controller, including: According to the weight decoded by the instruction fetch and decoding module, the instruction index is written into the instruction queue of the weighted arbiter corresponding to the weight, wherein if the weight obtained by decoding is 0, the instruction index is written into the level 0 queue; if the weight obtained by decoding is 1, the instruction index is written into the level 1 queue; if the weight obtained by decoding is 2, the instruction index is written into the level 2 queue; Determine the status of the level 0 instruction queue, the level 1 instruction queue, and the level 2 instruction queue, and use the status signals of the instruction queues with different weights as the source end request of the weighted arbitrator, and whether each instruction queue in the weighted arbitrator is empty reflects whether the instruction of the current priority is issued. If the instruction of the high priority is issued, the level 0 instruction queue is in a non-empty state; If the level 0 instruction queue is in a non-empty state, a non-empty signal of the level 0 instruction queue is used as a source request of the weighted arbitrator to initiate an arbitration request to the fixed priority arbitrator, and at the same time, the instruction index in the level 0 instruction queue is selected and read, and the instruction index is written into the command index buffer; If the level 0 instruction queue is in an empty state and the level 1 instruction queue and the level 2 instruction queue are in a non-empty state, the non-empty signals of the level 1 instruction queue and the level 2 instruction queue are used as the source request of the weighted arbitrator to initiate an arbitration request to the round-robin priority arbitrator; according to the response result of the round-robin priority arbitrator, the instruction index to be written into the command index buffer is selected from the output data of the level 1 instruction queue and the level 2 instruction queue.

6. The flash memory controller according to claim 1, wherein: The command request and transmission module reads the instruction index from the command index buffer, and completes the reading of the command word according to the command index in the instruction corresponding to the instruction index, including: After obtaining the command word read address, the command request and transmission module initiates a read command word request to the read-write DMA controller inside the flash memory controller; The read-write arbitrator on the read-write DMA side arbitrates the command request and the read command word request initiated by the transmission module and the read data request for reading DDR initiated by the write operation state machine in the scheduler module, wherein the read-write arbitrator preferentially requests the command word corresponding to the instruction with the priority level 0 according to the instruction weight, and arbitrates the command word read request corresponding to the instruction with the priority level 1 and 2 and the data request for reading DDR initiated by the write operation state machine through the polling state machine; The command word read from the DDR is cached in the command word cache, and the command word index corresponding to the read command word request initiated to the read-write DMA controller is cached in the command word index cache, wherein the command request and transmission module includes a command word cache and a command word index cache.

7. The flash memory controller according to claim 6, wherein: The obtaining of the command word read address comprises: The command request and transmission module uses the instruction index read from the command index buffer as the command word offset address CMDW_OFFSET_ADDR of the DMA controller, and reads the command word base address CMDW_BASE_ADDR of the DMA controller in the control register inside the flash memory controller; The command word base address and the command word offset address are concatenated to generate a 32-bit command word read address CMDW_RD_ADDR, which is composed of three parts, namely, CMDW_RD_ADDR = {CMDW_BASE_ADDR[31:10], CMDW_OFFSET_ADDR, 4'b0000}, where CMDW_BASE_ADDR [31:12] is the high 22 bits of the command word base address configured in the control register, CMDW_OFFSET_ADDR is a 6-bit command word index, and 4'b0000 is 4 zero bits for achieving 16Bytes command word alignment.

8. The flash memory controller according to claim 6, wherein: The scheduler module includes an erase operation state machine, a read operation state machine, a write operation state machine, an erase / write suspend operation state machine, a task stack for recording currently suspended task information, a task recovery logic, and a performance monitoring module; When the command request and transmission module initiates an operation request for an erase operation, a read operation, or a write operation, the erase operation state machine, the read operation state machine, or the write operation state machine exits an idle state; When an erase suspend or write suspend operation occurs during a write operation or an erase operation, the scheduler module writes the value of the write data counter, the command word index and the command word corresponding to the current operation into the task stack; When a state machine of any operation undergoes a state transition, the scheduler module synchronizes the state of the current operation to the bit field of the command word index corresponding to the state register in the flash memory controller; When the state machine of any operation returns to the idle state, the scheduler module synchronizes the current operation time overhead counted by the performance monitoring module to the status register in the flash memory controller.

9. The flash memory controller according to claim 8, characterized in that: When a write operation is performed, the corresponding write data is stored in a write cache through a write channel, wherein the write cache includes a write cache 0 and a write cache 1, and the write cache 0 and the write cache 1 have two states, dirty and clean, for identifying whether the data in the write cache 0 or the write cache 1 has been overwritten by other write operations since the last write operation; Among them, when writing the write data corresponding to the write operation into the write cache, if the write cache 0 and the write cache 1 are both in a dirty state, any one of the write caches 0 and the write cache 1 is marked as a clean state; if only one of the write caches 0 and the write cache 1 is in a dirty state, the write data is written to the write cache in the clean state; if the write cache 0 and the write cache 1 are both in a clean state, the write data is written to any one of the write caches 0 and the write cache 1.

10. A control method for a flash memory controller, characterized in that: The flash memory controller includes an instruction cache, a register, an instruction fetch and decode model, a weighted arbiter, a command request and transmission module and a scheduler module, and the control method includes: After the flash memory controller completes power-on reset, the host-side controller sends register configuration information and instructions to the flash memory controller through the AXI-Lite interface, and writes the instructions into the instruction cache in the flash memory controller; Reading instructions from the instruction cache through the instruction fetching and decoding module, and decoding an operation code, an instruction weight, and a command index corresponding to the instruction from the instruction according to the instruction format; Outputting instruction indexes from instruction queues of various states by arbitration through the weighted arbitrator according to the instruction weights, and storing the instruction indexes in a command index buffer inside the flash memory controller; Reading the instruction index from the command index buffer through the command request and transmission module, and completing the reading of the command word according to the command index in the instruction corresponding to the instruction index; The scheduler module is used to control the write operation state machine, the read operation state machine and the erase operation state machine, thereby realizing the scheduling control of the flash memory particles.

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