Test circuit and method for simulated neural memory in artificial neural network

Abstract

Disclosed herein are test circuits and methods for deep learning simulated neural memory in an artificial neural network. The simulated neural memory includes one or more arrays of non-volatile memory cells. The test circuit and method may be utilized to verify programming operations of one or more cells during a sorting test, a quality authentication test, and other tests.

Description

[0001] This divisional patent application is a divisional application of the invention patent application with the international application number PCT / US2019 / 068202, the international filing date of December 21, 2019, the application number in the Chinese national phase of 201980098532.4, and the title of "Testing Circuit and Method for Analog Neural Memory in Artificial Neural Network".

[0002] Priority Statement

[0003] This patent application claims priority from U.S. Provisional Patent Application 62 / 876,515 filed on July 19, 2019 and titled "Testing Circuitry and Methods for Analog Neural Memory in Artificial Neural Network" and U.S. Patent Application 16 / 569,647 filed on September 12, 2019 and titled "Testing Circuitry and Methods for Analog Neural Memory in Artificial Neural Network". Technical Field

[0004] Disclosed herein are testing circuits and methods for analog neural memories in deep learning artificial neural networks. The analog neural memory includes one or more arrays of non-volatile flash memory cells. Background Art

[0005] Artificial neural networks mimic biological neural networks (the central nervous system of animals, especially the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. Artificial neural networks typically include interconnected "neuron" layers that exchange messages with each other.

[0006] Figure 1 An artificial neural network is shown, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numerical weights that can be adjusted according to experience. This enables the neural network to adapt to the input and learn. Generally, a neural network includes a layer of multiple inputs. There is usually one or more intermediate layers of neurons, and an output layer of neurons that provides the output of the neural network. The neurons at each level make decisions separately or jointly based on the data received from the synapses.

[0007] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. In fact, actual neural networks rely on a large number of synapses to achieve high connectivity between neurons, that is, very high computational parallelism. In principle, such complexity can be achieved by digital supercomputers or clusters of dedicated graphics processing units. However, compared to biological networks, these methods are not only costly but also have mediocre energy efficiency, as biological networks consume less energy mainly due to their execution of low-precision analog computations. CMOS analog circuits have been used in artificial neural networks, but due to the need for a large number of neurons and synapses, most CMOS-implemented synapses are too large.

[0008] The applicant previously disclosed in U.S. Patent Application 15 / 594,439 (published as U.S. Patent Publication 2017 / 0337466), which is incorporated herein by reference, an artificial (analog) neural network that uses one or more non-volatile memory arrays as synapses. The non-volatile memory arrays operate as analog neural memories. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, where each memory cell among the memory cells includes: spaced-apart source and drain regions formed in a semiconductor substrate, where a channel region extends between the source and drain regions; a floating gate disposed above a first portion of the channel region and insulated from the first portion; and a non-floating gate disposed above a second portion of the channel region and insulated from the second portion. Each memory cell among the plurality of memory cells is configured to store a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. An array of memory cells used in this manner can be referred to as a vector matrix multiplication (VMM) array.

[0009] Each non-volatile memory cell used in an analog neural memory system must be erased and programmed to maintain a very specific and precise amount of electric charge (i.e., the number of electrons) in the floating gate. For example, each floating gate must maintain one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0010] Precision and accuracy are very important in operations involving a VMM array because each individual memory cell can store one of N different levels, where N can be greater than 2, as opposed to traditional memory cells where N is always 2. This makes testing a very important operation. For example, programming operations need to be verified to ensure that each individual cell or column of cells is accurately programmed to the desired value. Also, it is crucial to identify bad cells or groups of cells so that they can be removed from the set of cells used for storing data during the operation of the VMM array.

[0011] Improved test circuits and methods for VMM arrays are needed. Summary of the Invention

[0012] Test circuits and methods for an analog neural memory in a deep learning artificial neural network are disclosed herein. The analog neural memory includes one or more arrays of non-volatile flash memory cells. The test circuits and methods can be utilized during sort testing, cycling testing, high-temperature operating life (HTOL) testing, qualification testing, and other tests to verify the characteristics and operability of one or more cells.

[0013] One embodiment includes a method for verifying values programmed into a plurality of non-volatile memory cells in an analog neural non-volatile memory cell array, where the array is arranged in rows and columns, where each row is coupled to a word line and each column is coupled to a bit line, and where each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method including: asserting all word lines in the array by the row decoder; asserting the bit lines in the array by the column decoder; sensing a current received from the bit line by a sense amplifier; and comparing the current to a reference current to determine whether the non-volatile memory cell coupled to the bit line contains the expected value.

[0014] Another embodiment includes a method for measuring the current consumed by a plurality of non-volatile memory cells in an analog neural non-volatile memory cell array, where the array is arranged in rows and columns, where each row is coupled to a word line and each column is coupled to a bit line, and where each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method including: asserting all word lines in the array by the row decoder; asserting the bit lines in the array by the column decoder; and measuring the current received from the bit line.

[0015] Another method includes a method of testing a plurality of analog neural non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: asserting all word lines in the array by the row decoder; asserting all bit lines in the array by the column decoder; performing a deep programming operation on all non-volatile memory cells in the array; and measuring the total current received from the bit lines.

[0016] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, the method comprising: programming a plurality of cells coupled to the bit line; measuring the current consumed by the plurality of cells at K different times and storing the measurement for each of the K different times, wherein K is an integer; calculating an average value based on the K measurements; and identifying the bit line as a bad bit line if any one of the K measurements is less than the average value by more than a first threshold or greater than the average value by more than a second threshold.

[0017] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, the method comprising: programming a plurality of cells coupled to the bit line; measuring the voltage on a control gate line coupled to the control gate terminals of the plurality of cells at K different times and storing the measurement for each of the K different times, wherein K is an integer; calculating an average value based on the K measurements; and identifying the bit line as a bad bit line if any one of the K measurements is less than the average value by more than a first threshold or greater than the average value by more than a second threshold.

[0018] Another embodiment includes a method of testing an analog neural non-volatile memory cell for storing N different values, wherein N is an integer, the method comprising: programming the cell to a target value representing one of the N values; verifying whether the value stored in the cell is within an acceptable value window around the target value; repeating the programming step and the reading step for each of the N values; and identifying the cell as bad if any one of the verification steps in the verification step indicates that the value stored in the cell is outside the acceptable value window around the target value.

[0019] Another embodiment includes a method for compensating for leakage in an array of analog neural non-volatile memory cells, where the array is arranged in rows and columns, where each row is coupled to a word line and each column is coupled to a bit line, the method comprising: measuring the leakage of a column of non-volatile memory cells coupled to the bit line; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of non-volatile memory cells to compensate for the leakage.

[0020] Another embodiment includes a method for testing selected non-volatile memory cells in an array of analog neural non-volatile memory cells, the method comprising: determining a logarithmic slope factor of a selected non-volatile memory cell when the selected non-volatile memory cell is operating in the subthreshold region; storing the logarithmic slope factor; determining a linear slope factor of the selected non-volatile memory cell when the selected non-volatile memory cell is operating in the linear region; storing the linear slope factor; and utilizing one or more of the logarithmic slope factor and the linear slope factor when programming the selected cell to a target current.

[0021] Another embodiment includes a method for measuring the current consumed by a column of non-volatile memory cells in an array of analog neural non-volatile memory cells, where the array is arranged in rows and columns, where each row is coupled to a word line and each column is coupled to a bit line, and where each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: asserting all word lines in the array by the row decoder; asserting the bit lines in the array by the column decoder to select a column of non-volatile memory cells; and measuring the current received from the bit line.

[0022] Another embodiment includes a method for testing an array of analog neural non-volatile memory cells, the method comprising: erasing the non-volatile memory cells in the array by applying a series of voltages to the terminals of each non-volatile memory cell in the array, where the voltages in the series of voltages increase with time in a fixed step; and reading all non-volatile memory cells to determine the effectiveness of the erase step.

[0023] Another embodiment includes a method for testing an array of analog neural non-volatile memory cells, the method comprising: programming the non-volatile memory cells in the array by applying a series of voltages to the terminals of each non-volatile memory cell in the array, where the voltages in the series of voltages increase with time in a fixed step; and reading all non-volatile memory cells to determine the effectiveness of the programming step.

[0024] Another embodiment includes a method of testing a plurality of analog neural non-volatile memory cells in a non-volatile memory cell array, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: programming the plurality of non-volatile memory cells to store one of N different values, where N is the number of different levels that can be stored in any non-volatile memory cell; measuring the current consumed by the plurality of non-volatile memory cells; comparing the measured current to a target value; and if the difference between the measured value and the target value exceeds a threshold, identifying the plurality of non-volatile memory cells as bad.

[0025] Another embodiment includes a method of testing a plurality of analog neural non-volatile memory cells in a non-volatile memory cell array, wherein the memory array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: programming a first selected one of the plurality of non-volatile memory cells with the level among the N levels corresponding to the minimum cell current; programming a second selected one of the plurality of non-volatile memory cells with the level among the N levels corresponding to the maximum cell current, where each cell in the second selected cells is adjacent to one or more cells in the first selected cells; measuring the current consumed by the plurality of non-volatile memory cells; comparing the measured current to a target value; and if the difference between the measured value and the target value exceeds a threshold, identifying the plurality of non-volatile memory cells as bad. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram showing an artificial neural network of the prior art.

[0027] Figure 2 Showing a split-gate flash memory cell of the prior art.

[0028] Figure 3 Showing another split-gate flash memory cell of the prior art.

[0029] Figure 4 Showing another split-gate flash memory cell of the prior art.

[0030] Figure 5 Showing another split-gate flash memory cell of the prior art.

[0031] Figure 6 Showing another split-gate flash memory cell of the prior art.

[0032] Figure 7 Shows a stacked-gate flash memory cell of the prior art.

[0033] Figure 8 Is a schematic diagram showing different levels of an exemplary artificial neural network using one or more non-volatile memory arrays.

[0034] Figure 9 Is a block diagram showing a vector-matrix multiplication system.

[0035] Figure 10 Is a block diagram showing an exemplary artificial neural network using one or more vector-matrix multiplication systems.

[0036] Figure 11 Shows another embodiment of a vector-matrix multiplication system.

[0037] Figure 12 Shows another embodiment of a vector-matrix multiplication system.

[0038] Figure 13 Shows another embodiment of a vector-matrix multiplication system.

[0039] Figure 14 Shows another embodiment of a vector-matrix multiplication system.

[0040] Figure 15 Shows another embodiment of a vector-matrix multiplication system.

[0041] Figure 16 Shows another embodiment of a vector-matrix multiplication system.

[0042] Figure 17 Shows another embodiment of a vector-matrix multiplication system.

[0043] Figure 18 Shows another embodiment of a vector-matrix multiplication system.

[0044] Figure 19 Shows another embodiment of a vector-matrix multiplication system.

[0045] Figure 20 Shows another embodiment of a vector-matrix multiplication system.

[0046] Figure 21 Shows another embodiment of a vector-matrix multiplication system.

[0047] Figure 22 Shows another embodiment of a vector-matrix multiplication system.

[0048] Figure 23Shows another embodiment of a vector-matrix multiplication system.

[0049] Figure 24 Shows another embodiment of a vector-matrix multiplication system.

[0050] Figure 25 Shows one embodiment of a vector-matrix multiplication system including test control logic.

[0051] Figure 26 Shows a reference current source.

[0052] Figure 27 Shows in Figure 26 The reference sub-circuit used in the reference current source.

[0053] Figure 28 Shows a sense amplifier.

[0054] Figure 29A Shows a verification analog-to-digital converter.

[0055] Figure 29B Shows a verification analog-to-digital converter.

[0056] Figure 30 Shows a high-voltage generation circuit.

[0057] Figure 31 Shows an exemplary test algorithm implemented by test control logic in a vector-matrix multiplication system.

[0058] Figure 32 Shows one embodiment of a bitline neural read test.

[0059] Figure 33 Shows one embodiment of a bitline neural measurement test.

[0060] Figure 34 Shows one embodiment of an LSB screening test.

[0061] Figure 35 Shows one embodiment of a bitline sampling screening test.

[0062] Figure 36 Shows another embodiment of a bitline sampling screening test.

[0063] Figure 37 Shows one embodiment of a read window check test.

[0064] Figure 38 Shows one embodiment of a read calibration test.

[0065] Figure 39 Shows one embodiment of a read slope test.

[0066] Figure 40 Shows an embodiment of a read neuron quality identification test.

[0067] Figure 41 Shows an embodiment of a soft erase test.

[0068] Figure 42 Shows an embodiment of a soft program test.

[0069] Figure 43 Shows an embodiment of a verification test.

[0070] Figure 44 Shows an embodiment of a checkerboard verification test. Detailed Description

[0071] The artificial neural network of the present invention utilizes a combination of CMOS technology and a non-volatile memory array.

[0072] Non-volatile memory cell

[0073] Digital non-volatile memories are well known. For example, U.S. Patent 5,029,130 ("the '130 patent"), which is incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such memory cells 210 are shown in Figure 2 . Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed above and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed above a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed above and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion that extends upward and is located above the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line terminal 24 is coupled to the drain region 16.

[0074] The memory cell 210 is erased by placing a high positive voltage on the word line terminal 22 (where electrons are removed from the floating gate), which causes electrons on the floating gate 20 to tunnel through an intervening insulator from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim tunneling.

[0075] The memory cell 210 (where electrons are placed on the floating gate) is programmed by placing a positive voltage on the word line terminal 22 and a positive voltage on the source region 14. The electron current will flow from the source region 14 (source line terminal) to the drain region 16. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, the electrons will accelerate and heat up. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons will be injected onto the floating gate 20 through the gate oxide.

[0076] The memory cell 210 is read by placing a positive read voltage on the drain region 16 and the word line terminal 22 (which turns on the portion of the channel region 18 under the word line terminal). If the floating gate 20 is positively charged (i.e., the electrons are erased), then the portion of the channel region 18 under the floating gate 20 is also turned on, and current will flow through the channel region 18, which is sensed as the erased state or "1" state. If the floating gate 20 is negatively charged (i.e., programmed with electrons), then the portion of the channel region 18 under the floating gate 20 is mostly or completely turned off, and current will not (or very little current) flow through the channel region 18, which is sensed as the programmed state or "0" state.

[0077] Table 1 shows the typical voltage ranges that can be applied to the terminals of the memory cell 110 for performing read, erase, and program operations:

[0078] Table 1: Figure 2 Operation of the flash memory cell 210

[0079]

[0080]

[0081] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0082] Figure 3 The memory cell 310 is shown, which is similar to the Figure 2 memory cell 210, but with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, at a low voltage or negative voltage (e.g., 0V / -8V) during erase, and at a low voltage or medium voltage (e.g., 0V / 2.5V) during read. The other terminals are biased similar to Figure 2 that.

[0083] Figure 4FIG. 0 shows a four-gate memory cell 410, which includes a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (commonly coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating gates, which means they are electrically connected or can be electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasure is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0084] Table 2 shows the typical voltage ranges that can be applied to the terminals of the memory cell 410 to perform read, erase, and program operations:

[0085] Table 2: Figure 4 Operation of the flash memory cell 410

[0086] WL / SG BL CG EG SL Read 1 0.5-2V 0.1-2V 0-2.6V 0-2.6V 0V Read 2 0.5-2V 0-2V 0-2.6V 0-2.6V 2-0.1V Erase -0.5V / 0V 0V 0V / -8V 8-12V 0V Program 1V 1μA 8-11V 4.5-9V 4.5-5V

[0087] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0088] Figure 5 FIG. 16 shows a memory cell 510, which is similar to the memory cell 410 of FIG. 0 except that it does not include an erase gate EG terminal. Erasure is performed by biasing the substrate 18 to a high voltage and biasing the control gate CG terminal 28 to a low voltage or a negative voltage. Alternatively, erasure is performed by biasing the word line terminal 22 to a positive voltage and biasing the control gate terminal 28 to a negative voltage. Programming and reading are similar to those of FIG. 0. Figure 4 FIG. 0 Figure 4 FIG. 0

[0089] Figure 6 FIG. 24 shows a three-gate memory cell 610, which is another type of flash memory cell. The memory cell 610 is the same as the memory cell 410 of FIG. 0 except that the memory cell 610 does not have a separate control gate terminal. Except for not applying a control gate bias, the erase operation (erasing by using the erase gate terminal) and the read operation are similar to those of FIG. 0. In the absence of a control gate bias, the program operation is also completed, and as a result, a higher voltage must be applied to the source line terminal during the program operation to compensate for the lack of a control gate bias. Figure 4 FIG. 0 Figure 4 FIG. 0

[0090] Table 3 shows the typical voltage ranges that can be applied to the terminals of the memory cell 610 to perform read, erase, and program operations:

[0091] Table 3: Figure 6 Operation of the flash memory cell 610

[0092] WL / SG BL EG SL Read 1 0.5-2.2V 0.1-2V 0-2.6V 0V Read 2 0.5-2.2V 0-2V 0-2.6V 2-0.1V Erase -0.5V / 0V 0V 11.5V 0V Program 1V 2 - 3μA 4.5V 7-9V

[0093] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0094] Figure 7 A stacked-gate memory cell 710 is shown, which is another type of flash memory cell. The memory cell 710 is similar to Figure 2 the memory cell 210, except that the floating gate 20 extends over the entire channel region 18, and the control gate terminal 22 (which will be coupled to the word line here) extends over the floating gate 20, separated by an insulating layer (not shown). The erase, program, and read operations operate in a manner similar to that described previously for the memory cell 210.

[0095] Table 4 shows the typical voltage ranges that can be applied to the terminals of the memory cell 710 and the substrate 12 for performing read, erase, and program operations:

[0096] Table 4: Figure 7 Operation of the flash memory cell 710

[0097]

[0098]

[0099] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal. Optionally, in an array including rows and columns of memory cells 210, 310, 410, 510, 610, or 710, the source line can be coupled to one row of memory cells or two adjacent rows of memory cells. That is, the source line terminal can be shared by memory cells in adjacent rows.

[0100] To utilize a memory array including one of the above types of non-volatile memory cells in an artificial neural network, two modifications were made. First, the circuitry was configured such that each memory cell can be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as further explained below. Second, continuous (analog) programming of the memory cells was provided.

[0101] Specifically, the memory state of each memory cell in the array (i.e., the charge on the floating gate) can be continuously changed from a fully erased state to a fully programmed state independently and with minimal interference to other memory cells. In another embodiment, the memory state of each memory cell in the array (i.e., the charge on the floating gate) can be continuously changed from a fully programmed state to a fully erased state independently and with minimal interference to other memory cells, and vice versa. This means that the cell storage device is analog, or can at least store one discrete value out of many discrete values (such as 16 or 64 different values), which allows for very precise and individual tuning of all cells in the memory array, and which makes the memory array ideal for storing and fine-tuning the synaptic weights of a neural network.

[0102] The methods and devices described herein can be applied to other non-volatile memory technologies such as, but not limited to, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapped in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), OTP (one-time programmable bilayer or multilayer), and CeRAM (correlated electron ram), etc. The methods and devices described herein can be applied to volatile memory technologies for neural networks such as, but not limited to, SRAM, DRAM, and / or volatile synaptic units.

[0103] Neural network using an array of non-volatile memory cells

[0104] Figure 8 A non-limiting example of a neural network using a non-volatile memory array in this embodiment is conceptually shown. This example uses the non-volatile memory array neural network for a face recognition application, but any other suitable application can also be implemented using a neural network based on a non-volatile memory array.

[0105] For this example, S0 is the input layer, which is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, and each pixel is 5-bit precision). The synapse CB1 from the input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in other cases, and scans the input image with a 3x3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as indicated by the model). Specifically, the values of 9 pixels in a 3x3 portion of the image (i.e., what is called the filter or kernel) are provided to the synapse CB1, where these 9 input values are multiplied by appropriate weights, and after summing the output of this multiplication, a single output value is determined and provided by the first synapse of CB1 for a pixel in one of the layers C1 of the resulting feature map. Then the 3x3 filter is shifted one pixel to the right within the input layer S0 (i.e., the column of three pixels on the right is added and the column of three pixels on the left is released), whereby the 9 pixel values in this newly positioned filter are provided to the synapse CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process continues until the 3x3 filter has scanned all three colors and all bits (precision values) over the entire 32x32 pixel image of the input layer S0. Then this process is repeated with different sets of weights to generate different feature maps for C1 until all the feature maps for layer C1 have been computed.

[0106] At layer C1, in this example, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array, and thus in this example, layer C1 consists of 16 layers of two-dimensional arrays (remember that the layers and arrays referred to in this text are logical relationships and not necessarily physical relationships, i.e., the arrays do not have to be oriented as physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synaptic weights applied to the filter scans. The C1 feature maps can all relate to different aspects of the same image feature, such as edge recognition. For example, the first map (generated using the first set of weights, shared for all scans used to generate this first map) may identify circular edges, the second map (generated using a second set of weights different from the first set) may identify rectangular edges, or the aspect ratio of certain features, and so on.

[0107] Before transitioning from layer C1 to layer S1, an activation function P1 (pooling) is applied which pools the values from consecutive non-overlapping 2x2 regions in each feature map. The purpose of the pooling function is to take the mean (or alternatively the max function can be used) of neighboring locations to, for example, reduce the dependence on edge locations and reduce the data size before entering the next stage. At layer S1, there are 16 feature maps of 15x15 (i.e., sixteen different arrays of 15x15 pixels each). The synapse CB2 from layer S1 to layer C2 scans the maps in S1 using a 4x4 filter, where the filter is shifted by 1 pixel. At layer C2, there are 22 feature maps of 12x12. Before transitioning from layer C2 to layer S2, an activation function P2 (pooling) is applied which pools the values from consecutive non-overlapping 2x2 regions in each feature map. At layer S2, there are 22 feature maps of 6x6. The activation function (pooling) is applied to the synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected via the corresponding synapse of CB3 to each map in layer S2. At layer C3, there are 64 neurons. The synapse CB4 from layer C3 to the output layer S3 fully connects C3 to S3, i.e., each neuron in layer C3 is connected to each neuron in layer S3. The output at S3 includes 10 neurons, where the neuron with the highest output determines the class. For example, this output can indicate the recognition or classification of the content of the original image.

[0108] Each layer's synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0109] Figure 9 is a block diagram of a system that can be used for this purpose. The vector-matrix multiplication (VMM) system 32 includes non-volatile memory cells and serves as the synapse between one layer and the next layer (such as Figure 6 CB1, CB2, CB3, and CB4 in the example). Specifically, the VMM system 32 includes a VMM array 33 (including non-volatile memory cells arranged in rows and columns), an erase gate and word line decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the non-volatile memory cell array 33. The input to the VMM array 33 can come from the erase gate and word line decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0110] The VMM array 33 serves two purposes. First, it stores the weights to be used by the VMM system 32. Second, the VMM array 33 effectively multiplies the inputs with the weights stored in the VMM array 33 and each output line (source line or bit line) sums them to produce an output, which will be used as the input for the next layer or the input for the final layer. By performing the multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic circuits and is also highly efficient due to its in-situ memory computing.

[0111] The output of the VMM array 33 is provided to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the VMM array 33 to create a single value for this convolution. The differential summer 38 is arranged to perform the summation of both positive-weight inputs and negative-weight inputs to output a single value.

[0112] Then the output value of the differential summer 38 is provided to an activation function circuit 39 after summation, and this activation function circuit corrects the output. The activation function circuit 39 can provide sigmoid, tanh, ReLU functions or any other non-linear functions. The corrected output value of the activation function circuit 39 becomes an element of the feature map for the next layer (e.g., Figure 8 layer C1 in), and then is applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the VMM array 33 constitutes multiple synapses (which receive their inputs from an existing neuron layer or from an input layer such as an image database), and the summer 38 and the activation function circuit 39 constitute multiple neurons.

[0113] Figure 9 The inputs (WLx, EGx, CGx, and optionally BLx and SLx) to the VMM system 32 in can be analog levels, binary levels, digital pulses (in which case, a pulse-to-analog converter PAC may be required to convert the pulses to a suitable input analog level), or digital bits (in which case, a DAC is provided to convert the digital bits to a suitable input analog level); the output can be an analog level, binary level, digital pulse, or digital bits (in which case, an output ADC is provided to convert the output analog level into digital bits).

[0114] Figure 10 A block diagram showing the use of a multi-layer VMM system 32 (here labeled as VMM systems 32a, 32b, 32c, 32d, and 32e). As Figure 10As shown, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to an input VMM system 32a. The converted analog input can be a voltage or a current. The input D / A conversion of the first layer can be accomplished by using a function or a LUT (look-up table) that maps the input Inputx to an appropriate analog level of a matrix multiplier of the input VMM system 32a. The input conversion can also be done by an analog-to-analog (A / A) converter to convert an external analog input into a mapped analog input to the input VMM system 32a. The input conversion can also be done by a digital-to-digital pulse (D / P) converter to convert an external digital input into one or more mapped digital pulses to the input VMM system 32a.

[0115] The output generated by the input VMM system 32a is provided as an input to the next VMM system (hidden level 1) 32b, which in turn generates an output that is provided as an input to the next VMM system (hidden level 2) 32c, and so on. Each layer of the VMM system 32 serves as different layers of synapses and neurons of a convolutional neural network (CNN). Each of the VMM systems 32a, 32b, 32c, 32d, and 32e can be an independent physical system including a corresponding non-volatile memory array, or multiple VMM systems can utilize different parts of the same physical non-volatile memory array, or multiple VMM systems can utilize overlapping parts of the same physical non-volatile memory array. Each of the VMM systems 32a, 32b, 32c, 32d, and 32e can also be time-division multiplexed for different parts of its array or neurons. Figure 10 The example shown includes five layers (32a, 32b, 32c, 32d, 32e): an input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). A person of ordinary skill in the art will know that this is merely exemplary, and conversely, the system can include more than two hidden layers and more than two fully connected layers.

[0116] VMM array

[0117] Figure 11 A neuron VMM array 1100 is shown, which is particularly suitable for Figure 3 the memory cell 310 shown and serves as the synapses and components of neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (at the top of the array). Alternatively, another reference array can be placed at the bottom.

[0118] In the VMM array 1100, control gate lines (such as control gate line 1103) extend in the vertical direction (so the reference array 1102 is orthogonal to the control gate line 1103 in the row direction), and erase gate lines (such as erase gate line 1104) extend in the horizontal direction. Here, the inputs of the VMM array 1100 are set on the control gate lines (CG0, CG1, CG2, CG3), and the outputs of the VMM array 1100 appear on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current placed on each source line (SL0 and SL1 respectively) performs a summation function of all the currents from the memory cells connected to that particular source line.

[0119] As described herein for neural networks, the non-volatile memory cells of the VMM array 1100 (i.e., the flash memory of the VMM array 1100) are preferably configured to operate in the subthreshold region.

[0120] Bias the non-volatile reference memory cells and non-volatile memory cells described herein in weak inversion:

[0121] Ids = Io*e (Vg-Vth) / nVt = w*Io*e (Vg) / nVt ,

[0122] where w = e (-Vth) / nVt

[0123] where Ids is the drain-to-source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k*T / q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1+(Cdep / Cox), where Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is proportional to (Wt / L)*u*Cox*(n - 1)*Vt 2 where u is the carrier mobility, and Wt and L are the width and length of the memory cell respectively.

[0124] For an I-to-V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert an input current Ids to an input voltage Vg:

[0125] Vg = n*Vt*log[Ids / wp*Io]

[0126] Here, wp is the w of the reference memory cell or the peripheral memory cell.

[0127] For an I-to-V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert an input current Ids to an input voltage Vg:

[0128] Vg = n * Vt * log[Ids / wp * Io]

[0129] Here, wp is the w of the reference memory cell or the peripheral memory cell.

[0130] For a memory array used as a vector matrix multiplier VMM array, the output current is:

[0131] Iout = wa * Io * e (Vg) / nVt i.e.,

[0132] Iout = (wa / wp) * Iin = W * Iin

[0133] W = e (Vthp-Vtha) / nVt

[0134] Iin = wp * Io * e (Vg) / nVt

[0135] Here, wa = the w of each memory cell in the memory array.

[0136] The word line or the control gate can be used as the input of the memory cell for the input voltage.

[0137] Alternatively, the non-volatile memory cells of the VMM array described herein can be configured to operate in the linear region:

[0138] Ids = β * (Vgs - Vth) * Vds; β = u * Cox * Wt / L,

[0139] W α (Vgs - Vth),

[0140] means that the weight W in the linear region is proportional to (Vgs - Vth)

[0141] The word line or the control gate or the bit line or the source line can be used as the input of the memory cell operating in the linear region. The bit line or the source line can be used as the output of the memory cell.

[0142] For an I-to-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor or a resistor operating in the linear region can be used to linearly convert the input / output current to the input / output voltage.

[0143] Alternatively, the memory cells of the VMM array described herein can be configured to operate in the saturation region:

[0144] Ids = 1 / 2 * β * (Vgs - Vth)2 ; β = u * Cox * Wt / L

[0145] Wα(Vgs - Vth) 2 , meaning the weight W is proportional to (Vgs - Vth) 2 is proportional

[0146] A word line, control gate, or erase gate can be used as an input to a memory cell operating in the saturation region. A bit line or source line can be used as the output of an output neuron.

[0147] Alternatively, the memory cells of the VMM array described herein can be used in all regions or combinations thereof (subthreshold, linear, or saturation regions).

[0148] U.S. Patent Application 15 / 826,345 describes Figure 9 other embodiments of the VMM array 33, which is incorporated herein by reference. As described herein, a source line or bit line can be used as a neuron output (current summing output).

[0149] Figure 12 shows a neuron VMM array 1200, which is particularly suitable for Figure 2 the memory cell 210 shown, and serves as a synapse between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non - volatile memory cells, a reference array 1201 of first non - volatile reference memory cells, and a reference array 1202 of second non - volatile reference memory cells. The reference arrays 1201 and 1202 arranged along the column direction of the array are used to convert the current inputs flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In fact, the first non - volatile reference memory cells and the second non - volatile reference memory cells are diode - connected through a multiplexer 1214 (only partially shown), where the current inputs flow into them. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0150] The memory array 1203 serves two purposes. First, it stores the weights to be used by the VMM array 1200 on its respective memory cells. Second, the memory array 1203 effectively multiplies the inputs (i.e., the current inputs provided at terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert to input voltages to be provided to word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1203 and then sums all the results (memory cell currents) to produce an output on the respective bit lines (BL0 - BLN), which will be the input to the next layer or the input to the final layer. By performing the multiplication and addition functions, the memory array 1203 eliminates the need for separate multiplication and addition logic circuits and is also highly efficient. Here, the voltage inputs are provided on the word lines (WL0, WL1, WL2, and WL3), and the outputs appear on the respective bit lines (BL0 - BLN) during a read (inference) operation. The current placed on each of the bit lines in BL0 - BLN performs a summing function of the currents from all the non-volatile memory cells connected to that particular bit line.

[0151] Table 5 shows the operating voltages for the VMM array 1200. The columns in the table indicate the voltages placed on the word lines for selected cells, the word lines for unselected cells, the bit lines for selected cells, the bit lines for unselected cells, the source lines for selected cells, and the source lines for unselected cells, where FLT indicates floating, i.e., no voltage is applied. The rows indicate the read, erase, and program operations.

[0152] Table 5: Figure 12 Operation of the VMM array 1200

[0153] WL WL - unselected BL BL - unselected SL SL - unselected Read 0.5-3.5V -0.5V / 0V 0.1 - 2V (Ineuron) 0.6V - 2V / FLT 0V 0V Erase Approximately 5 - 13V 0V 0V 0V 0V 0V Program 1V - 2V -0.5V / 0V 0.1 - 3uA Vinh approximately 2.5V 4-10V 0 - 1V / FLT

[0154] Figure 13 A neuron VMM array 1300 is shown, which is particularly suitable for Figure 2The memory cell 210 shown is used as a synapse and component of a neuron between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of first non-volatile reference memory cells, and a reference array 1302 of second non-volatile reference memory cells. The reference arrays 1301 and 1302 extend in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that in the VMM array 1300, the word lines extend in the vertical direction. Here, the inputs are set on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the outputs appear on the source lines (SL0, SL1) during a read operation. The current placed on each source line performs a summation function of all the currents from the memory cells connected to that particular source line.

[0155] Table 6 shows the operating voltages for the VMM array 1300. The columns in the table indicate the voltages placed on the word lines for the selected cells, the word lines for the unselected cells, the bit lines for the selected cells, the bit lines for the unselected cells, the source lines for the selected cells, and the source lines for the unselected cells. The rows indicate the read, erase, and program operations.

[0156] Table 6: Figure 13 Operation of the VMM array 1300

[0157] WL WL - unselected BL BL - unselected SL SL - unselected Read 0.5-3.5V -0.5V / 0V 0.1-2V 0.1V - 2V / FLT Approximately 0.3 - 1V (Ineuron) 0V Erase Approximately 5 - 13V 0V 0V 0V 0V SL - inhibited (approximately 4 - 8V) Program 1V - 2V -0.5V / 0V 0.1 - 3uA Vinh approximately 2.5V 4-10V 0 - 1V / FLT

[0158] Figure 14 The neuron VMM array 1400 is shown, which is particularly suitable for Figure 3 the memory cell 310 shown and is used as a synapse and component of a neuron between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of first non-volatile reference memory cells, and a reference array 1402 of second non-volatile reference memory cells. The reference arrays 1401 and 1402 are used to convert the current inputs flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In fact, the first non-volatile reference memory cells and the second non-volatile reference memory cells are diode-connected through a multiplexer 1412 (only partially shown), where the current inputs flow into them through BLR0, BLR1, BLR2, and BLR3. Each multiplexer 1412 includes a corresponding multiplexer 1405 and a cascode transistor 1404 to ensure a constant voltage on the bit line (such as BLR0) of each of the first non-volatile reference memory cells and the second non-volatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0159] The memory array 1403 serves two purposes. First, it stores the weights to be used by the VMM array 1400. Second, the memory array 1403 effectively multiplies the inputs (the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1401 and 1402 convert into input voltages to be provided to control gates CG0, CG1, CG2, and CG3) by the weights stored in the memory array, and then sums all the results (cell currents) to produce an output that appears on BL0 - BLN and will be the input to the next layer or the input to the final layer. By performing the multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the outputs appear on the bit lines (BL0 - BLN) during a read operation. The current placed on each bit line performs the summation function of all the currents from the memory cells connected to that particular bit line.

[0160] The VMM array 1400 implements unidirectional tuning for the non - volatile memory cells in the memory array 1403. That is, each non - volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be performed, for example, using the precise programming techniques described below. If too much charge is placed on the floating gate (such that an incorrect value is stored in the cell), the cell must be erased, and the sequence of partial programming operations must be restarted. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (which is called a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

[0161] Table 7 shows the operating voltages for the VMM array 1400. The columns in the table indicate the voltages placed on the word line for the selected cell, the word line for the unselected cell, the bit line for the selected cell, the bit line for the unselected cell, the control gate for the selected cell, the control gate for the unselected cell in the same sector as the selected cell, the control gate for the unselected cell in a different sector from the selected cell, the erase gate for the selected cell, the erase gate for the unselected cell, the source line for the selected cell, and the source line for the unselected cell. The rows indicate the read, erase, and program operations.

[0162] Table 7: Figure 14 Operation of the VMM array 1400

[0163]

[0164] Figure 15 The neuron VMM array 1500 is shown, which is particularly applicable to Figure 3The memory cell 310 shown and serves as the synapse and component of the neuron between the input layer and the next layer. The VMM array 1500 includes a memory array 1503 of non-volatile memory cells, a reference array 1501 of first non-volatile reference memory cells, and a reference array 1502 of second non-volatile reference memory cells. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1500 is similar to the VMM array 1400, except that the VMM array 1500 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve the desired charge amount on the floating gate due to the use of separate EG lines. As shown, the reference arrays 1501 and 1502 convert the input current in the terminals BLR0, BLR1, BLR2, and BLR3 into the control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the row direction (through the action of the diode-connected reference cells via the multiplexer 1514). The current outputs (neurons) are in the bit lines BL0 - BLN, where each bit line sums all the currents from the non-volatile memory cells connected to that specific bit line.

[0165] Table 8 shows the operating voltages for the VMM array 1500. The columns in the table indicate the voltages placed on the word line for the selected cell, the word line for the unselected cell, the bit line for the selected cell, the bit line for the unselected cell, the control gate for the selected cell, the control gate for the unselected cell in the same sector as the selected cell, the control gate for the unselected cell in a different sector from the selected cell, the erase gate for the selected cell, the erase gate for the unselected cell, the source line for the selected cell, and the source line for the unselected cell. The rows indicate read, erase, and program operations.

[0166] Table 8: Figure 15 Operation of the VMM array 1500

[0167]

[0168] Figure 16 Shows the neuron VMM array 1600, which is particularly suitable for Figure 2 the memory cell 210 shown and serves as the synapse and component of the neuron between the input layer and the next layer. In the VMM array 1600, the inputs INPUT0,..., INPUT N are received on the bit lines BL0,... BL N respectively, and the outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on the source lines SL0, SL1, SL2, and SL3 respectively.

[0169] Figure 17 Shows the neuron VMM array 1700, which is particularly suitable for Figure 2 the memory cell 210 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, the inputs INPUT0, INPUT 1、 INPUT2, and INPUT3 are received on the source lines SL0, SL1, SL2, and SL3 respectively, and the outputs OUTPUT0, … OUTPUT N are generated on the bit lines BL0, …, BL N .

[0170] Figure 18 Shows the neuron VMM array 1800, which is particularly suitable for Figure 2 the memory cell 210 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, the inputs INPUT0, …, INPUT M are received on the word lines WL0, …, WL M respectively, and the outputs OUTPUT0, … OUTPUT N are generated on the bit lines BL0, …, BL N .

[0171] Figure 19 Shows the neuron VMM array 1900, which is particularly suitable for Figure 3 the memory cell 310 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, the inputs INPUT0, …, INPUT M are received on the word lines WL0, …, WL M respectively, and the outputs OUTPUT0, … OUTPUT N are generated on the bit lines BL0, …, BL N .

[0172] Figure 20 Shows the neuron VMM array 2000, which is particularly suitable for Figure 4 the memory cell 410 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, the input INPUT 0, …, INPUT n are received on the vertical control gate lines CG0, …, CG N respectively, and the outputs OUTPUT1 and OUTPUT2 are generated on the source lines SL0 and SL1.

[0173] Figure 21Shows a neuron VMM array 2100, which is particularly suitable for Figure 4 the memory cell 410 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, the inputs INPUT0 to INPUT N are received on the gates of bit line control gates 2901-1, 2901-2 to 2901-(N-1) and 2901-N respectively, and these gates are coupled to bit lines BL0 to BL N . Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0174] Figure 22 Shows a neuron VMM array 2200, which is particularly suitable for Figure 3 the memory cell 310 shown, Figure 5 the memory cell 510 shown, and Figure 7 the memory cell 710 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, the inputs INPUT0,…,INPUT M are received on word lines WL0,…,WL M , and the outputs OUTPUT0,…,OUTPUT N are generated on bit lines BL0,…,BL N respectively.

[0175] Figure 23 Shows a neuron VMM array 2300, which is particularly suitable for Figure 3 the memory cell 310 shown, Figure 5 the memory cell 510 shown, and Figure 7 the memory cell 710 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, the inputs INPUT0 to INPUT M are received on control gates CG0 to CG M . The outputs OUTPUT0,…,OUTPUT N are generated on vertical source lines SL0,…,SL N respectively, where each source line SL i is coupled to the source lines of all memory cells in column i.

[0176] Figure 24 Shows a neuron VMM array 2400, which is particularly suitable for Figure 3 the memory cell 310 shown, Figure 5 the memory cell 510 shown, and Figure 7The memory cell 710 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, the inputs INPUT0 to INPUT M are received on the control gate lines CG0 to CG M The outputs OUTPUT0, …, OUTPUT N are respectively generated on the vertical bit lines BL0, …, BL N where each bit line BL i is coupled to the bit lines of all the memory cells in column i.

[0177] Test circuit and method

[0178] Figure 25 FIG. shows the VMM system 2500. The VMM system 2500 includes a VMM array 2501 (which can be based on any of the previously discussed VMM array designs, such as VMM arrays 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, and 2400 or other VMM array designs), a low-voltage row decoder 2502, a high-voltage row decoder 2503, a column decoder 2504, a column driver 2505, control logic 2506, a bias circuit 2507, an output circuit block 2508, an input VMM circuit block 2509, an algorithm controller 2510, a high-voltage generator block 2511, an analog circuit block 2515, control logic 2516, and test control logic 2517.

[0179] The input circuit block 2509 serves as an interface to the input terminals of the memory array 2501 from external inputs. The input circuit block 2509 can include, but is not limited to, a DAC (Digital-to-Analog Converter), DPC (Digital-Pulse Converter), APC (Analog-Pulse Converter), IVC (Current-Voltage Converter), AAC (Analog-Analog Converter, such as a voltage-voltage scaler), or FAC (Frequency-Analog Converter). The output circuit block 2508 serves as an interface from the memory array to an external interface (not shown). The output circuit block 2508 can include, but is not limited to, an ADC (Analog-to-Digital Converter), APC (Analog-Pulse Converter), DPC (Digital-Pulse Converter), IVC (Current-Voltage Converter), or IFC (Current-Frequency Converter). The output circuit block 2508 can include, but is not limited to, activation functions, normalization circuits, and / or rescaling circuits.

[0180] The low-voltage row decoder 2502 provides a bias voltage for read operations and programming operations, and provides a decoded signal to the high-voltage row decoder 2503. The high-voltage row decoder 2503 provides a high-voltage bias signal for programming operations and erase operations.

[0181] The algorithm controller 2510 provides control functions for bit lines during programming, verification, and erasure operations.

[0182] The high-voltage generator block 2511 includes a charge pump 2512, a charge pump regulator 2513, and a high-voltage generation circuit 2514 that provides multiple voltages required for various programming, erasing, programming verification, and read operations.

[0183] The test control logic 2517 contains various test control circuits for performing the tests described below with reference to Figures 26 to 31 the tests described.

[0184] Figure 26 A reference current source 2600 is shown that is used during a verification operation after a programming operation of one or more non-volatile memory cells or during other types of tests. For example, the reference current source 2600 can be used for the verification operation of a single non-volatile memory cell, or for the verification operation of a column of non-volatile memory cells (e.g., all cells connected to a specific bit line) or some other grouping of non-volatile memory cells.

[0185] The reference current source 2600 includes a buffer mirror 2601 (the buffer mirror includes a buffer operational amplifier 2602 with an output I REF 2607 and a PMOS transistor 2603), an adjustable bias source 2604, and a two-dimensional array 2605 that includes an array of i rows and j columns of devices 2606, where a specific device 2606 is labeled 2606-(row)(column). Here, various combinations of devices 2606 can be activated such that the amount of the reference current I REF 2607 output by the buffer mirror 2601 can be adjusted. As shown, there are 16 devices 2606 in the array 2605, and each device can be implemented by a current mirror. The reference current source 2600 basically converts four digital inputs into a reference current bias whose value is 1 to 16 times that of Ibiasunit, where Ibiasunit is provided from the bias source 2604. The reference current source 2600 is basically a thermometer-encoded digital-to-current converter whose buffered output I REF 2607 has a value corresponding to one of 16 levels, and a specific level responds to four digital inputs, which can be stored in a memory cell in any of the VMM arrays discussed previously.

[0186] For example, the bias source 2604 can provide a current Ibiasunit of 1 nA, which is mirrored into the device 2606. Here, the first row consists of devices 2606-11 to 2606-1j and is enabled sequentially from left to right, one device 2606 at a time. Then the next row is enabled in sequential fashion from left to right to be added to the first row, meaning 5, then 6, then 7, then 8 devices 2606 are enabled. By enabling the devices 2606 sequentially, the transistor mismatch problems associated with conventional binary decoding can be avoided. Then the sum of the enabled devices 2606 is mirrored by the buffer mirror 2601 and the output is the current I REF 2607. The bias source 2604 can provide a range of fine-tunable currents Ibiasunit, such as 50 pA / 100 pA / 200 pA / … / 100 nA. Here, the array 2605 is shown as a 4×4 array, but it should be understood that the array 2605 can have other dimensions, such as 32×32 or 8×32.

[0187] Figure 27 A reference sub-circuit 2700 is shown, which can be used for Figure 26 any one of the devices 2606 in. The reference sub-circuit 2700 includes NMOS transistors 2701 and 2702 configured as shown. Transistor 2702 is a current mirror bias transistor that receives the current Ibiasunit (discussed above with reference to Figure 26 ) at its gate, and transistor 2701 is an enable transistor (to enable the current mirror bias transistor 2702 to be connected to the output node OUTPUT). A current Ibiasunit is provided, for example, from a diode-connected NMOS transistor (similar to transistor 2702) (not shown).

[0188] Figure 28 A sense amplifier 2800 is shown being used with the reference current source 2600 during a verification operation after a programming operation of a non-volatile memory cell, a column of non-volatile memory cells, or some other grouping of non-volatile memory cells, or during another type of test. The sense amplifier 2800 receives the current I Figure 26 discussed above with reference to REF 2607. I REF 2607 can be modeled as a PMOS transistor 2813, where the gate is by VI REF2814 control. The sense amplifier 2800 further includes an inverter 2801, a current source 2802 (which is used to limit the current in the inverter 2801), switches 2803 and 2806, a capacitor 2804, and a cascaded NMOS transistor 2805 (to apply a fixed voltage on the memory bit line). The sense amplifier 2800 receives a current I from the reference current source 2600 REF 2607, which can be, for example, one of the sixteen possible levels stored in the non-volatile memory cells of the VMM array. The sense amplifier 2800 is coupled to the cell 2808, which is the non-volatile memory cell whose content needs to be verified. When the NMOS transistor 2805 is turned on, the cell 2808 consumes the current I CELL . Alternatively, the cell 2808 can be replaced by the column 2809 (for the sake of the drawing, this column will consume a current that will still be referred to as I CELL and which should be the neuron current consumed by the column 2809).

[0189] In one embodiment, I REF 2607 starts from the lowest possible value (for example, the lowest value among the 16 possible levels that can be stored in the cell 2808 or the column 2809), and then increases sequentially to each subsequent level for the verification operation. The switch 2806 can be closed to create an initial state of the capacitor 2804 (such as grounding or precharging the voltage to provide offset cancellation). The switch 2803 can be closed to equalize the input and output of the inverter 2801, thereby removing the offset from the inverter 2801 for comparison during the verification operation. During the verification operation, the switches 2806 and 2803 are opened. If I CELL >= I REF 2607, the voltage on the node 2810 will decrease, which is then capacitively coupled through the capacitor 2804, such that the voltage on the node 2811 decreases, resulting in the inverter output switching to "1", which means the input of the inverter 2801 will be a "0" value and the output of the inverter 2801 will be a "1" value. If I CELL < I REF 2607, the voltage on the node 2810 will increase, which is then capacitively coupled through the capacitor 2804, such that the voltage on the node 2811 increases, resulting in the inverter output switching to "0", which means the input of the inverter 2801 will switch to a "1" value and the output of the inverter 2801 will switch to a "0" value. The value of I REF 2807 at which this occurs corresponds to the value stored in the cell 2808.

[0190] Figure 29AA verification ramp analog-to-digital converter (ADC) 2900 is shown that is used with a reference current source 2600 during a verification operation of a non-volatile memory cell 2930 or a column 2931 after a programming pulse operation (such as to verify whether a memory cell reaches a target current during a weight tuning process) or during another type of test (such as to verify truncated memory bits (e.g., abnormal bits) in a memory array that cannot meet the cell current requirements). I CELL 2906 is an output current from the cell 2930 or the column 2931. The verification ADC 2900 converts I CELL 2906 into a series of digital output bits with an output of output 2940, where the output 2940 indicates the value stored in the cell 2930 or the column 2931.

[0191] The verification ADC 2900 includes an operational amplifier 2901, an adjustable capacitor 2902, an operational amplifier 2904, a counter 2920, and switches 2908, 2909, and 2910. The adjustable capacitor 2902 integrates I CELL 2906 with respect to the current I REF provided by the adjustable current source 2807. During an initialization phase, the switch 2908 is closed. The Vout 2903 of the operational amplifier 2901 and the input to the inverting input of the operational amplifier 2901 will become equal to the value of the reference voltage VREF applied to the non-inverting input of the operational amplifier 2901. Thereafter, the switch 2908 is opened, and during a fixed time period tref, the switch 2910 is closed, and the neuron current I CELL 2906 is integrally up. During the fixed time period tref, Vout 2903 rises, and its slope reflects I CELL 2906 value. Thereafter, during the time period tmeas, by opening the switch 2910 and closing the switch 2909, the constant reference current I REF provided by the adjustable current source 2807 is integrally down (during which Vout drops), where tmeas is the time required to integrally down Vout to VREF.

[0192] When VOUT 2903 > VREF, the output EC 2905 of the operational amplifier 2904 will be high level, and vice versa will be low level. EC 2905 thus generates a pulse, the width of which reflects the time period tmeas, which in turn is proportional to the current I CELL 2906.

[0193] Optionally, the output EC 2905 is input to a counter 2920 that counts the number of received clock pulses 2921 when the output EC 2905 is high and generates an output 2940 that will be a set of digital bits representing a digital count of the number of clock pulses 2921 that occurred when EC 2905 was high, and this number is proportional to I CELL 2906.

[0194] Figure 29B A verification ramp analog-to-digital converter 2950 is shown that includes a current source 2953 (which represents the received neuron current Ineu or the current of a single memory cell), a switch 2954, a variable capacitor 2952, and a comparator 2951 that receives at its non-inverting input the voltage (represented as Vneu) formed across the variable capacitor 2952 and receives at its inverting input a configurable reference voltage Vreframp and generates an output Cout. The circuitry for clearing the voltage across the variable capacitor 2952 is not shown. Vreframp ramps up (increases) in discrete levels with each comparison clock cycle. The comparator 2951 compares Vneu with Vreframp, and thus when Vneu > Vreframp, the output Cout will be "1", and otherwise will be "0". Thus, the output Cout will be a pulse whose width varies in response to the value of Ineu. A larger Ineu will cause Cout to be "1" for a longer period, i.e., the pulse of the output Cout is wider. A digital counter 2960 converts the output Cout into digital output bits DO[n:0] 2970 that reflect the number of clock cycles 2961 for which Cout was a "1" value. Alternatively, the ramp voltage Vreframp is a continuous ramp voltage. A multi-ramp implementation can be implemented to reduce the conversion time by using a coarse-fine ramp conversion algorithm. A first coarse reference ramp reference voltage ramps in a fast manner to figure out the sub-range of each Ineu. Next, a fine reference ramp reference voltage is used separately for each sub-range to convert the Ineu current within the corresponding sub-range. More than two coarse / fine steps or more than two sub-ranges are possible.

[0195] Other ADC architectures can be used as the verification ADC, such as flash ADC, SAR (successive approximation register) ADC, algorithmic ADC, pipelined ADC, Sigma Delta ADC, but not limited to these.

[0196] Figure 30 Shown previously referenced Figure 25An implementation of the described high-voltage generation circuit 2511. The high-voltage generation circuit 2511 can be used with any of the previously discussed VMM arrays. The high-voltage generation circuit 2511 includes a charge pump 2512 and a high-voltage generation circuit 2514. The charge pump 2512 receives an input 3004 and generates a high voltage 3005, which is then provided to high-voltage generators 3002 and 3003. The high-voltage (HV) generator (HVDAC_EG) 3002 is an HV digital-to-analog converter that provides a voltage (denoted as V EG 3008), such as an incremental voltage, that is suitable for application to the erase gate terminal of a split-gate flash memory cell in response to digital bits 3006 and the received high voltage 3005. The high-voltage generator (HVDAC CGSL) 3003 is an HV digital-to-analog converter that provides voltages (denoted as V CG 3009 and V SL 3010), such as incremental voltages, that are suitable for application to the control gate terminal and the source line terminal of a split-gate flash memory cell in response to digital bits 3007 and the received high voltage 3005.

[0197] Figure 31 Shows the VMM system 2500 previously referenced Figure 25 and described but shown here in a test configuration. The test control logic 2517 provides control signals to other components of the VMM system 2500 (shown in Figure 25 but not shown in Figure 31 ) to implement one or more test algorithms 3100, such components as the VMM array 2501, row decoder 2502, column decoder 2504, input block 2509, high-voltage decoder 2503, column driver 2505, high-voltage generation block 2511, analog block 2515, algorithm controller 2510, and output circuit block 2508. The VMM array 2501 receives control signals from the row decoder 2502, whereby one or more rows are asserted within the VMM array 2501. The VMM array 2501 provides signals from one or more bit lines to the column decoder 2504 and then provides outputs from one or more bit lines to the output circuit block 2508. The output circuit block 2508 can include an analog-to-digital converter block (such as the verification ADC 2900 previously referenced Figure 29A or the verification ramp ADC 2950 previously referenced Figure 29B ), which provides a digital output representing the analog current received by the output circuit block 2508 from the VMM array 2501.

[0198] Table 9 contains exemplary values ​​for word lines, control gate lines, erase gate lines, source gate lines, and bit lines within the VMM array 2501 during the following operations, including: program, erase, read, and verify operations performed on individual memory cells; verify neuron and read neuron operations performed on selected bit lines coupled to columns of memory cells; and read array operations whereby each bit line is read (where each bit line is coupled to a column of memory cells).

[0199] Table 9: Exemplary values for operations within VMM array 2501

[0200] WL CG EG SL BL Selected Unselected Selected Unselected Selected Unselected Selected Unselected Selected Unselected Program 0.9V 0v Up to 10.5V 0v Up to 4.5V 0v Up to 4.5V Approximately 0.5v Iprog Vinh Erase 0v 0v 0v 0v 6V - 11.5V 0v 0v 0v 0v 0v Read 1.1V 0v 2.5V 2.5V 2.5V 2.5V 0v 0v 0.6V 0v Verify neuron 1.1V 0v 0V - 1.5V 0v 0V 0v 0v 0v 0.6V 0v Read neuron 1.1V 1.1V 0V - 1.5V 0V - 1.5V 0V 0V 0v 0V 0.6V 0.6V Read array 1.1V 1.1V 0V - 1.5V 0V - 1.5V 0V 0V 0v 0V 0.6V 0v

[0201] Now we will provide reference Figure 31 The test algorithm 3100 shown in FIG. 31 is executed and Figures 32 to 44 The tests are implemented by test control logic 2517 and other components of VMM system 2500, with further details on the types of tests further described in detail in FIG. 25 .

[0202] refer to Figure 32 , the bit line neural read test 3101 measures the values ​​in all memory cells coupled to the bit line simultaneously. That is, the bit line neural read test 3101 reads the neurons in the VMM array. First, the row decoder 2502 asserts all word lines in the array (step 3201). Second, the bit line is selected (asserted) by the column decoder 2504 (step 3202). Third, a read is performed on the bit line, such as by sensing the current received from the bit line by the sense amplifier 2800 (step 3203). Fourth, the value of the selected bit line can be determined by comparing the reference current generated by the reference current source 2600 to determine whether the non-volatile memory cell (i.e., neuron) coupled to the selected bit line contains the expected value (step 3204).

[0203] refer to Figure 33 , the bit line neural measurement test 3102 is similar to the bit line neural read test 3101. The row decoder 2502 asserts all word lines (step 3301). A bit line is selected by the column decoder 2504 (step 3302). The current consumed by the bit line during the read operation is measured (step 3303). Here, unlike the bit line neural read test 3101, the current from the selected bit line is measured without comparison to a reference current.

[0204] refer to Figure 34, during the LSB screening test 3103, the row decoder 2502 asserts all word lines (step 3401), and the column decoder 2504 asserts all bit lines (step 3402). Deep programming is performed on all memory cells in the VMM array 2501 (step 3403). Deep programming will program all memory cells that are beyond the normal programming state used to infer the reading. This deep programming is done with a longer programming time or a higher programming voltage than is typically used in normal operation. The total current received from all bit lines is then measured (step 3404). It is expected that the total current of the deeply programmed array will be much less than the LSB value. In addition, each individual cell is checked to ensure that the current from the individual cell is also below the LSB value, such as 50-100pA. This type of test is suitable for testing during the manufacturing process to quickly identify bad dies.

[0205] refer to Figure 35 During the bit line sampling screening test 3104, a memory cell or a group of memory cells are programmed to a specific level, such as Lx, where x ranges from 1 to N, where N is the total number of levels that can be stored in the cell (e.g., N=16) (step 3501). The bit line current (the current consumed by a cell or a group of cells in the selected bit line, referred to as I BL )K times (step 3502). For example, if K=8, the bit line current is measured 8 times. Then, based on the K measured values ​​(i.e., I BL1 …I BLK )Calculate the average value (I AVG )(Step 3503).

[0206] Next, relative to I AVG Check K current measurements I BL1 …I BLK Each measurement value in (step 3504). If I BLi (where i ranges from i to K)>(I AVG +Threshold 3505) or I BLi <(I AVG -threshold 3506), then the bit line is considered bad. Each cell in the bad bit line is then checked and the bad cell is replaced with a redundant cell (such a cell from a redundant row or redundant column).

[0207] Figure 36 Another embodiment of the bit line sampling screening test 3104 is shown. The voltage V is measured by forcing the current Iref into the bit line at K different times. CG (Step 3601). For example, the voltage V CG until the bit line current matches the fixed Iref and that particular VCG The fixed Iref can be provided by the reference current source 2600, and the operation of verifying whether the bit line current matches the fixed Iref can be performed by the sense amplifier 2800. Then, according to K different V CG values, the average value V AVG is calculated. Next, each of the K measured V AVG voltages is checked with respect to V CG (step 3603). If V CGi (where i ranges from i to K) > (V AVG + threshold 3604) or V CGi < (V AVG - threshold 3605), the bit line is considered bad. Then each cell in the bad bit line is checked, and the bad cells are replaced with redundant cells (redundant rows or redundant columns).

[0208] During the read trip point test 3105, coarse and fine read reference current fine-tuning is performed using different levels of Iref in the read operation. The purpose of the read trip point test 3105 is to figure out whether the selected memory cell can pass a predetermined current percentage target, such as about 40% of the full erase current for erasing the cell or about 5% of the full program current for programming the cell. This can ensure that the memory cell is within the main distribution, rather than within the truncated memory cells or truncated bits (i.e., statistical outliers), because truncated memory cells or truncated bits may cause potential reliability problems during the working life.

[0209] Reference Figure 37 , during the read window check test 3107, the test cell is tested to ensure that it can store each of the N possible levels. First, the cell is programmed to a target value representing one of the N values (step 3701). Next, a verification operation is performed to determine whether the value stored in the cell is within the acceptable value window 3710 around the target value (step 3702). Steps 3701 and 3702 are repeated for each of the N values (step 3703). For each N value, the acceptable window 3710 can be different. If any instance of step 3702 being executed indicates that the value stored in the cell is outside the acceptable value window around the target value, the cell is identified as bad. The read window check test 3107 can be performed by the sense amplifier 2800, the ADC 2900, the ADC 2950, or another component. This may be useful for performing weight tuning on the memory cell. What has been described above has been explained in an embodiment where a fixed window is used for each of the N values centered on the nominal value. It should be understood that in another embodiment, higher and lower thresholds are used for each of the N values, and these thresholds do not have to be the same among all N values, as long as they are within the range.

[0210] Reference Figure 38 , during the read calibration test 3108, the leakage of a single cell or a group of cells (such as cells coupled to bit lines) is measured (step 3801), the measured leakage value (I LEAKAGE )(step 3802), and the measured leakage value is later used during the read operation to compensate for leakage under various combinations of process / voltage / temperature (PVT) (step 3803). In one embodiment, multiple cells are programmed with known values respectively. The word line and the control gate line are set to ground, and the bit line is set to a read bias voltage. A series of different reference currents are injected into the array, and the resulting data readout is read through a sense amplifier, such as the ADC circuit 2900 or 2950 or the sense amplifier 2800. The injection current that produces the best result (compared to the known value programmed into the cell) is stored as I LEAKAGE . Then, I LEAKAGE is applied during the read operation of the same cell, for example, by subtracting the stored leakage level from the converted data during the read operation to compensate for the leakage that occurs within the selected cell.

[0211] Reference Figure 39 , during the read slope test 3109, the I-V slope factors of the control gate voltage with respect to two reference currents, CG1 at current IR1 and CG2 at current IR2, are determined. The first step is to determine the logarithmic slope factor of the selected non-volatile memory cell when the selected non-volatile memory cell is operating in the subthreshold region (step 3901). The second step is to store the logarithmic slope factor (step 3902). The third step is to determine the linear slope factor of the selected non-volatile memory cell when the selected non-volatile memory cell is operating in the linear region (step 3903). The fourth step is to store the linear slope factor (step 3904). The fifth step is to utilize one or more of the logarithmic slope factor and the linear slope factor when programming the selected cell to a target current (step 3905).

[0212] Reference Figure 40 , during the read neuron quality qualification test 3110, the neurons (bit lines) are read without checking the values against expected values. The first step is to measure the current in the bit line and store the measured value (step 4001). The second step is to perform the read virtual neuron test 4010 as described below within a predetermined amount of time, such as the pre-burn time during the quality qualification process. The third step is to measure the current from the bit line (step 4003). The fourth step is to compare the measured current with the stored measured current from step 4001 (step 4004). If the difference is greater than or less than a certain amount, the bit line is considered a bad bit line.

[0213] The read virtual neuron test 4010 includes a series of steps. The first step is for the row decoder to assert all word lines in the array (step 4011). The second step is for the column decoder to assert all bit lines in the array to select all columns of non-volatile memory cells (step 4012). The third step is to perform a read operation on the array without checking the read output (read condition) (step 4013). The read virtual neuron test 4010 is used as a read stress on the array for pre-burn-in purposes.

[0214] Reference Figure 41 , during the soft erase test 3111, the entire array or a sector is tested to check the erase performance of the memory array. The first step is to erase the non-volatile memory cells in the array by applying a series of voltages to the terminals of each non-volatile memory cell in the array, where the voltages in the series of voltages increase with time in a fixed step (step 4101). This erases the cells in an incremental manner, for example, by increasing the voltage on the erase gate in a stepped manner with a step of, for example, 0.5 V or 1 V between 5 V and 12.5 V. Erasing in this way reduces the stress on the memory cells. The second step is to read all non-volatile memory cells to determine the effectiveness of the erase step (step 4102), for example, by determining that the cell current after the erase step 4101 is within an acceptable window around the nominal value. Optionally, a durability test can be performed to determine how many program / erase cycles can be sustained, or a background test can be performed to transition the array to an erased state.

[0215] Reference Figure 42 , during the soft program test 3112, the entire array or a row or a cell is tested. The first step is to program the non-volatile memory cells in the array by applying a series of voltages to the terminals of each non-volatile memory cell in the array, where the voltages in the series of voltages increase with time in a fixed step (step 4201). In an incremental manner, for example, with a step of 10 mV or 0.3 V or 1 V between 3 V and 10 V, the cells are programmed to check the programming performance of the memory array. Programming in this way reduces the stress on the memory cells. The second step is to read all non-volatile memory cells to determine the effectiveness of the programming step (step 4202), for example, by determining that the cell current after the programming step 4201 is within an acceptable window around the nominal value. Optionally, a durability test or a background test can be utilized.

[0216] Reference Figure 43, a read verification test 3106 can be performed. The first step is to program a plurality of non-volatile memory cells to store one of N different values, where N is the number of different levels that can be stored in any non-volatile memory cell (step 4301). The second step is to measure the current consumed by the plurality of non-volatile memory cells (step 4302). The third step is to compare the measured current with a target value (step 4303). The fourth step is to identify the plurality of non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold factor (step 4304).

[0217] Reference Figure 44 , a checkerboard verification test 3113 can be performed, whereby a test pattern is implemented using a checkerboard or pseudo-checkerboard pattern, and sampled levels rather than all possible levels are measured (e.g., 4 levels, L0, Ln, Ln / 4, Ln*3 / 4, rather than all N levels). For example, a pattern can be used to check for the worst-case electric field stress within a memory array (meaning one cell is at a high electric field level and adjacent cells are at a low electric field level).

[0218] In one embodiment, the first step is to program a first group of cells among the plurality of non-volatile memory cells with the level corresponding to the minimum cell current among the N levels (step 4401). The second step is to program a second group of cells among the plurality of non-volatile memory cells with the level corresponding to the maximum cell current among the N levels (step 4402). Each cell in the second group is adjacent to one or more cells in the first group. The third step is to measure the current consumed by the plurality of non-volatile memory cells (step 4403). The fourth step is to compare the measured current with a target value (step 4404). The fifth step is to identify the plurality of non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold (step 4405).

[0219] Table 10 contains other exemplary test patterns of the physical array mapping that can be used during the checkerboard verification test 3113:

[0220] Table 10: Exemplary test patterns

[0221]

[0222] The binning test 3114, the final test 3115, the quality qualification test 3116, and the data retention test 3117 are a test suite that can be performed during the manufacturing and quality qualification processes of wafers, dies, or packaged devices that include the VMM system disclosed herein.

[0223] Sorting tests 3114 can be performed on the wafers during the manufacturing process. In one embodiment, the sorting tests 3114 include the following test suites: First, relatively quick tests are performed to quickly identify bad wafers or dies, such as soft erase test 3111, soft program test 3112, and various stress mode tests (such as erase gate oxide gox, coupled gate oxide cox, source line oxide sol, reverse interference tunneling rtst (tunneling from the floating gate to the word line, interference to unselected rows), massive punchthrough mpt (interference from the source to the drain of unselected rows), read interference rdist (interference from read conditions)). Second, neural test patterns for the top and bottom sectors are performed, such as LSB screening test 3103 and bit line sampling screening 3104. The neural test patterns take much more time than the tests performed during the first step, and some time is saved because bad wafers or dies are screened or identified during the first set of less time-consuming tests.

[0224] Final tests 3115 can be performed on the packaged devices. In one embodiment, the final tests 3115 include the execution of soft erase test 3111 and soft program test 3112. Optionally, test patterns for neural applications can be utilized to reduce the test time instead of full testing, such as testing K out of N levels for M sectors, or testing all N levels for certain sectors (such as the top and bottom sectors).

[0225] During the quality qualification tests 3116, virtual bit line read cycles (which are the execution of read operations without actually determining the content of the read data) are performed, and the endurance tests are completed by applying soft erase test 3111 and soft program test 3112. Bit line tests are performed instead of individual memory cell tests because bit line reads are used during neural memory applications instead of individual memory reads.

[0226] Data retention tests 3117 can include, for example, baking the programmed wafers at a high temperature (such as 250 degrees Celsius) for 24 - 72 hours. In one embodiment, a checkerboard or pseudo-checkerboard test pattern is applied instead of full testing as in digital memory tests. Data retention on the bit line current is checked in the neural mode and read bit line current mode (instead of checking each memory cell as in digital memory). For example, one query is to check if ΔIBL < + / - p%, where ΔIBL is defined as the difference between the measured bit line current and the expected bit line current. (WholeBLmeas mode, software neural network modeling allows a percentage error p% for the target accuracy of the neural network). The ΔIBL for the neural mode is tested to identify if the bit line output current exceeds or is below the target, which is defined herein as a predetermined percentage "p" of the target. Alternatively, each cell can be checked / tested with + / -Δ of the target.

[0227] Other tests can be performed using the hardware and algorithms described herein.

[0228] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (with no intervening material, element, or space therebetween) and "indirectly on" (with intervening material, element, or space therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intervening material, element, or space therebetween) and "indirectly adjacent" (with intervening material, element, or space therebetween), "mounted to" includes "directly mounted to" (with no intervening material, element, or space therebetween) and "indirectly mounted to" (with intervening material, element, or space therebetween), and "electrically coupled to" includes "directly electrically coupled to" (with no intervening material or element electrically connecting the elements together) and "indirectly electrically coupled to" (with intervening material or element electrically connecting the elements together). For example, forming an element "above a substrate" can include directly forming the element on the substrate with no intervening material / element therebetween, and indirectly forming the element on the substrate with one or more intervening material / elements therebetween.

Claims

1. A method for testing analog neural non-volatile memory cells for storing N different values, where N is an integer, the method comprising: Program the cell to a target value representing one of the N values; Verify whether the value stored in the cell is within an acceptable value window around the target value; Repeat the programming step and the reading step for each of the N values; And If any of the verification steps in the verification step indicates that the value stored in the cell is outside the acceptable value window around the target value, identify the cell as bad.

2. The method according to claim 1, wherein each of the non-volatile memory cells in the non-volatile memory cell is a stacked-gate flash memory cell.

3. The method according to claim 1, wherein each of the non-volatile memory cells in the non-volatile memory cell is a split-gate flash memory cell.

4. The method according to claim 1, wherein the array is part of a neural network.

5. A method for testing a plurality of analog neural non-volatile memory cells in a non-volatile memory cell array, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line, and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder, and each bit line is selectively coupled to a column decoder, the method comprising: Program the plurality of non-volatile memory cells to store one of N different values, where N is the number of different levels that can be stored in any non-volatile memory cell; Measure the current consumed by the plurality of non-volatile memory cells; Compare the measured current with a target value; And If the difference between the measured value and the target value exceeds a threshold, identify the plurality of non-volatile memory cells as bad.

6. The method according to claim 5, wherein each of the non-volatile memory cells in the non-volatile memory cell is a stacked-gate flash memory cell.

7. The method according to claim 5, wherein each of the non-volatile memory cells in the non-volatile memory cell is a split-gate flash memory cell.

8. The method according to claim 5, wherein the array is part of a neural network.

9. A method for testing a plurality of analog neural non-volatile memory cells in a non-volatile memory cell array, wherein the memory array is arranged in rows and columns, wherein each row is coupled to a word line, and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder, and each bit line is selectively coupled to a column decoder, the method comprising: Program a first group of cells among the plurality of non-volatile memory cells with the level corresponding to the minimum cell current among the N levels; Program a second group of cells among the plurality of non-volatile memory cells with the level corresponding to the maximum cell current among the N levels, where each cell in the second group is adjacent to one or more cells in the first group; Measure the current consumed by the plurality of non-volatile memory cells; Compare the measured current with a target value;And If the difference between the measured value and the target value exceeds a threshold, identify the plurality of non-volatile memory cells as bad.

10. The method according to claim 9, wherein each non-volatile memory cell in the non-volatile memory cells is a stacked-gate flash memory cell.

11. The method according to claim 9, wherein each non-volatile memory cell in the non-volatile memory cells is a split-gate flash memory cell.

12. The method according to claim 9, wherein the array is part of a neural network.

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