Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The structure comprises a substrate; the electric interconnection layer is located on the substrate and comprises a plurality of signal metal wires and a plurality of redundant metal wires arranged on the peripheries of the signal metal wires, the redundant metal wires are arranged at unequal intervals in the first direction and the second direction, and the first direction is perpendicular to the second direction. A plurality of redundant metal wires are arranged on the periphery of a signal metal wire at unequal intervals along a first direction and a second direction, so that the wiring density of the periphery of the signal metal wire is reduced, the overall distance between the redundant metal wires and the signal metal wire is increased, the overall parasitic coupling capacitance between the redundant metal wires and the signal metal wire is further reduced, and the signal quality is improved. Therefore, the time delay of the circuit is reduced and the performance of the device structure is improved. In addition, compared with equal-interval filling with single density, unequal-interval filling can be freely combined through multiple schemes, that is, more filling schemes exist under the same density, and flexible applicability is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous development of semiconductor manufacturing technology, the feature size of integrated circuits is constantly shrinking. The damascene copper interconnect process has been widely used in semiconductor manufacturing processes and has become the mainstream manufacturing process for the multi-layer interconnect structure of integrated circuits. In the process of manufacturing a copper interconnect structure, planarization of the chip surface is one of the key technologies. So far, the chemical mechanical polishing (CMP) process is the only successful and large-scale used planarization process.

[0003] When the physical design of the chip enters the manufacturability stage, the layout at this time is uneven both in terms of metal density and graphic line width, and it is impossible to ensure the flatness of the wafer surface in the chemical mechanical polishing stage. In order to improve the metal distribution in the chip and make it more uniform, the redundant metal filling technology is a commonly used chemical mechanical polishing planarization enhancement technology.

[0004] However, there are still many problems in the redundant metal filling process in the prior art. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to reduce parasitic coupling capacitance, reduce delay influence and improve the performance of the device structure.

[0006] To solve the above problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; an electrical interconnect layer located on the substrate, the electrical interconnect layer includes a plurality of signal metal lines and a plurality of redundant metal lines arranged around the signal metal lines, and along a first direction and a second direction, the redundant metal lines are arranged at unequal intervals, and the first direction is perpendicular to the second direction.

[0007] Optionally, the substrate includes: a substrate and a device layer located on the substrate, and the device layer includes a plurality of device structures.

[0008] Optionally, the signal metal lines are electrically connected to the device structures, and the redundant metal lines are electrically isolated from the device structures.

[0009] Optionally, the intervals between the plurality of redundant metal lines along the first direction are an arithmetic sequence or a geometric sequence.

[0010] Optionally, the electrical interconnect layer further includes: an interlayer dielectric layer, and the interlayer dielectric layer covers the plurality of signal metal lines and the plurality of redundant metal lines.

[0011] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: forming a substrate; forming an electrical interconnection layer on the substrate, the electrical interconnection layer including a plurality of signal metal lines and a plurality of redundant metal lines arranged around the signal metal lines, and along a first direction and a second direction, the redundant metal lines are arranged at unequal intervals, and the first direction is perpendicular to the second direction.

[0012] Optionally, the substrate includes: a substrate and a device layer located on the substrate, and the device layer includes a plurality of device structures.

[0013] Optionally, the signal metal lines are electrically connected to the device structures, and the redundant metal lines are electrically isolated from the device structures.

[0014] Optionally, the intervals between the plurality of redundant metal lines along the first direction form an arithmetic sequence or a geometric sequence.

[0015] Optionally, the electrical interconnection layer further includes: an interlayer dielectric layer, and the interlayer dielectric layer covers the plurality of signal metal lines and the plurality of redundant metal lines.

[0016] Optionally, the method for forming the electrical interconnection layer includes: forming the interlayer dielectric layer on the substrate; forming a plurality of signal metal grooves and a plurality of redundant metal grooves in the interlayer dielectric layer; forming a metal material layer in the signal metal grooves, in the redundant metal grooves, and on the top surface of the interlayer dielectric layer; performing a planarization process on the metal material layer until the top surface of the interlayer dielectric layer is exposed, to form the plurality of signal metal lines and the plurality of redundant metal lines.

[0017] Optionally, the forming process of the plurality of redundant metal grooves includes: a single mask exposure process, a double mask exposure process, or a quadruple mask exposure process.

[0018] Optionally, the process for performing the planarization process on the metal material layer includes: a chemical mechanical polishing process.

[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0020] In the semiconductor structure of the technical solution of the present invention, by arranging a plurality of the redundant metal lines around the signal metal lines at unequal intervals in the first direction and the second direction, the wiring density around the signal metal lines is reduced, and the overall distance between the redundant metal lines and the signal metal lines is increased, thereby reducing the overall parasitic coupling capacitance between the redundant metal lines and the signal metal lines, so as to reduce the delay of the circuit and improve the performance of the device structure. In addition, compared with the equal-spacing filling of a single density, the unequal-spacing filling can be freely combined through various schemes, that is, there are more filling schemes under the same density, and it has flexible applicability.

[0021] In the method for forming a semiconductor structure of the technical solution of the present invention, by arranging a plurality of the redundant metal lines around the signal metal lines at unequal intervals in the first direction and the second direction, the wiring density around the signal metal lines is reduced, and the overall distance between the redundant metal lines and the signal metal lines is increased, thereby reducing the overall parasitic coupling capacitance between the redundant metal lines and the signal metal lines, so as to reduce the delay of the circuit and improve the performance of the device structure. In addition, compared with the equal-spacing filling of a single density, the unequal-spacing filling can be freely combined through various schemes, that is, there are more filling schemes under the same density, and it has flexible applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic structural diagram of redundant metal lines arranged at equal intervals around signal metal lines;

[0023] Figures 2 to 4 is a schematic structural diagram of each step in the formation process of the semiconductor structure in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] As described in the background art, there are still many problems in the redundant metal filling process in the prior art. The following will be specifically described with reference to the drawings.

[0025] Figure 1 is a schematic structural diagram of redundant metal lines arranged at equal intervals around signal metal lines.

[0026] Please refer to Figure 1, currently, the window-based redundant metal filling algorithm can achieve the homogenization of redundant metal filling, pattern density, and gradient. Based on this algorithm, in order to reduce the huge impact of redundant metal lines 100 on the coupling capacitance of signal metal lines 101 and reduce the delay, there are various corresponding redundant metal filling methods in the prior art. Among them, the amount of redundant metal filling is positively correlated with the filling density and signal delay. In advanced processes, the bottom metal usually adopts the self-aligned multiple exposure technology process, and its process feature is that the routing metal will be arranged unidirectionally at equal intervals. Correspondingly, the redundant metal lines 100 generated by the redundant metal filling algorithm also need to be arranged at equal intervals (as shown in Figure 1 ), to meet the manufacturing requirements of the design rules.

[0027] However, the equal-spacing arrangement of the redundant metal lines 100 will result in a relatively small overall spacing between the redundant metal lines 100 and the signal metal lines 101, thereby increasing the overall parasitic coupling capacitance between the redundant metal lines 100 and the signal metal lines 101. The increase in parasitic coupling capacitance will cause an increase in the delay of the circuit and affect the performance of the device structure.

[0028] On this basis, the present invention provides a semiconductor structure and a method for forming the same. By arranging a plurality of the redundant metal lines around the signal metal lines at unequal intervals in the first direction and the second direction, the wiring density around the signal metal lines is reduced, and the overall spacing between the redundant metal lines and the signal metal lines is increased, thereby reducing the overall parasitic coupling capacitance between the redundant metal lines and the signal metal lines, thereby reducing the delay of the circuit and improving the performance of the device structure. In addition, compared with the equal-spacing filling of a single density, the unequal-spacing filling can be freely combined through various schemes, that is, there are more filling schemes under the same density, and it has flexible applicability.

[0029] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention in detail with reference to the accompanying drawings.

[0030] Figures 2 to 4 is a schematic structural diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0031] Please refer to Figure 2 , and form a substrate.

[0032] The substrate includes: a substrate 200 and a device layer 201 located on the substrate 200, and the device layer 201 includes a plurality of device structures (not shown).

[0033] The device structure includes one or more combinations of a transistor structure, a capacitor structure, an inductor structure, and a resistor structure.

[0034] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate 200 may also be germanium, silicon germanium, silicon carbide, or silicon on insulator (SOI), germanium on insulator (GOI); alternatively, the substrate 200 may also be other materials, such as ternary - quinary compounds like gallium arsenide.

[0035] Please refer to Figure 3 and Figure 4 , Figure 4 is Figure 3 a schematic cross - sectional view along line A - A. An electrical interconnection layer is formed on the substrate. The electrical interconnection layer includes a plurality of signal metal lines 202 and a plurality of redundant metal lines 203 arranged around the signal metal lines. Along the first direction X and the second direction Y, the redundant metal lines 203 are arranged at unequal intervals, and the first direction X is perpendicular to the second direction Y.

[0036] By arranging a plurality of the redundant metal lines 203 at unequal intervals along the first direction X and the second direction Y around the signal metal lines 202, the wiring density around the signal metal lines 202 is reduced, and the overall spacing between the redundant metal lines 203 and the signal metal lines 202 is increased, thereby reducing the overall parasitic coupling capacitance between the redundant metal lines 203 and the signal metal lines 202, so as to reduce the delay of the circuit and improve the performance of the device structure. In addition, compared with the equal - density filling of a single density, the unequal - density filling can be freely combined through various schemes, that is, there are more filling schemes under the same density, which has flexible applicability.

[0037] It should be noted that in this embodiment, a filling scheme with a lower density of unequal intervals can be adopted for the redundant metal lines 203 near the critical path (i.e., the signal metal lines greatly affected by timing delay), and a filling scheme with a higher density of unequal intervals can be adopted for the redundant metal lines 203 in the non - critical path region (i.e., the signal metal lines less affected by timing delay) to achieve the coordinated optimization of density and delay. However, it is necessary to ensure that the metal density under the unequal - interval arrangement scheme is the same as that under the equal - interval arrangement scheme.

[0038] The electrical interconnection layer further includes: an inter - layer dielectric layer 204, and the inter - layer dielectric layer 204 covers a plurality of the signal metal lines 202 and a plurality of the redundant metal lines 203.

[0039] The method for forming the electrical interconnection layer includes: forming the interlayer dielectric layer 204 on the substrate; forming a plurality of signal metal grooves and a plurality of redundant metal grooves (not labeled) in the interlayer dielectric layer 204; forming a metal material layer (not shown) in the signal metal grooves, the redundant metal grooves, and on the top surface of the interlayer dielectric layer 204; performing a planarization process on the metal material layer until the top surface of the interlayer dielectric layer 204 is exposed, thereby forming a plurality of the signal metal lines 202 and a plurality of the redundant metal lines 203.

[0040] The process of performing the planarization process on the metal material layer uses a chemical mechanical polishing process.

[0041] It should be noted that the biggest problem during the planarization process of the copper interconnection structure using the chemical mechanical polishing process is that: the topography height of the chip surface after polishing is closely related to the density of the metal in the layout. Through research, it is found that this is mainly because during the chemical mechanical polishing process, the removal rates of the copper metal and the materials around it are different, resulting in the height of the dielectric layer in the area with denser metal interconnect lines being lower than that of the dielectric layer in the area with sparser metal interconnect lines, and over-grinding the dielectric layer between the metal interconnect lines, forming a sunken area, which seriously reduces the flatness of the chip surface. The non-planarity of the chip surface may cause focusing difficulties in the subsequent lithography process, reducing the lithography resolution and the imaging quality of the pattern. In addition, the non-planarity of the chip surface will also cause the heights of the metal interconnection layer and the dielectric layer to deviate seriously from the standard values, which will have a serious impact on the parasitic parameters of the metal interconnect lines, thereby affecting the chip performance and reducing the chip yield. Since the topography height of the chip surface after polishing is closely related to the density of the interconnect lines in the layout, in order to improve the flatness, a redundant metal fill process is usually adopted, adding the redundant metal lines 203 without logical functions in the blank areas of the layout to meet the requirement of uniform metal density in the layout.

[0042] Since the signal metal lines 202 need to carry out the function of electrical interconnection during the application process of the actual chip, the signal metal lines 202 are electrically connected to the device structure, while the redundant metal lines 203 are only used to balance the metal density in the layout and provide the flatness for the chemical mechanical polishing process. Therefore, the redundant metal lines 203 do not need to be electrically connected to the device structure, that is, the redundant metal lines 203 are electrically isolated from the device structure.

[0043] The formation process of a plurality of the redundant metal grooves includes: a single mask exposure process, a double mask exposure process, or a quadruple mask exposure process.

[0044] In this embodiment, the formation process of a plurality of the redundant metal grooves uses a double mask exposure process.

[0045] The pitch between several of the redundant metal lines 203 along the first direction X is an arithmetic sequence or a geometric sequence.

[0046] Correspondingly, the technical solution of the present invention also provides a semiconductor structure. Please continue to refer to Figure 3 and Figure 4 , including: a substrate; an electrical interconnection layer located on the substrate, the electrical interconnection layer including several signal metal lines 202 and several groups of redundant metal lines 203, and each group of the redundant metal lines 203 is arranged at unequal pitches along the first direction X around several of the signal metal lines 202.

[0047] By arranging several of the redundant metal lines 203 at unequal pitches along the first direction X and the second direction Y around the signal metal lines 202, the wiring density around the signal metal lines 202 is reduced, and the overall pitch between the redundant metal lines 203 and the signal metal lines 202 is increased, thereby reducing the overall parasitic coupling capacitance between the redundant metal lines 203 and the signal metal lines 202, so as to reduce the delay of the circuit and improve the performance of the device structure. In addition, compared with the equal-pitch filling of a single density, the unequal-pitch filling can be freely combined through various schemes, that is, there are more filling schemes under the same density, and it has flexible applicability.

[0048] It should be noted that in this embodiment, a filling scheme with a lower density and unequal pitches of the redundant metal lines 203 can be adopted near the critical path (i.e., the signal metal lines greatly affected by the timing delay), and a filling scheme with a higher density and unequal pitches of the redundant metal lines 203 can be adopted in the non-critical path region (i.e., the signal metal lines less affected by the timing delay) to achieve the coordinated optimization of density and delay. However, it is necessary to ensure that the metal density in the unequal-pitch arrangement scheme is the same as that in the equal-pitch arrangement scheme.

[0049] The substrate includes: a substrate 200 and a device layer 201 located on the substrate 200, and the device layer 201 includes several device structures.

[0050] The device structure includes: one or a combination of a transistor structure, a capacitor structure, an inductor structure, and a resistor structure.

[0051] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate 200 can also be germanium, silicon germanium, silicon carbide, or it can also be silicon on insulator (SOI), germanium on insulator (GOI); or the substrate 200 can also be other materials, such as III-V compounds such as gallium arsenide.

[0052] Since the signal metal line 202 needs to carry out the function of electrical interconnection during the application of the actual chip, the signal metal line 202 is electrically connected to the device structure. The redundant metal line 203 is only used to balance the metal density in the layout and provide the flatness for the chemical mechanical polishing process. Therefore, the redundant metal line 203 does not need to be electrically connected to the device structure, that is, the redundant metal line 203 is electrically isolated from the device structure.

[0053] The pitch between several redundant metal lines 203 along the first direction X forms an arithmetic sequence or a geometric sequence.

[0054] The electrical interconnection layer further includes: an interlayer dielectric layer 204, and the interlayer dielectric layer 204 covers several signal metal lines 202 and several redundant metal lines 203.

[0055] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: Substrate; An electrically interconnecting layer located on the substrate, the electrically interconnecting layer including a plurality of signal metal lines and a plurality of redundant metal lines arranged around the signal metal lines, and along a first direction and a second direction, the redundant metal lines are arranged at unequal intervals, the first direction is perpendicular to the second direction.

2. The semiconductor structure according to claim 1, characterized in that, The substrate includes: a substrate and a device layer located on the substrate, the device layer including a plurality of device structures.

3. The semiconductor structure according to claim 2, characterized in that, The signal metal lines are electrically connected to the device structures, and the redundant metal lines are electrically isolated from the device structures.

4. The semiconductor structure according to claim 1, characterized in that, The intervals between several of the redundant metal lines along the first direction are an arithmetic sequence or a geometric sequence.

5. The semiconductor structure according to claim 1, characterized in that, The electrically interconnecting layer further includes: an interlayer dielectric layer that covers a plurality of the signal metal lines and a plurality of the redundant metal lines.

6. A method for forming a semiconductor structure, characterized in that, Comprising: Forming a substrate; Forming an electrically interconnecting layer on the substrate, the electrically interconnecting layer including a plurality of signal metal lines and a plurality of redundant metal lines arranged around the signal metal lines, and along a first direction and a second direction, the redundant metal lines are arranged at unequal intervals, the first direction is perpendicular to the second direction.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, The substrate includes: a substrate and a device layer located on the substrate, the device layer including a plurality of device structures.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The signal metal lines are electrically connected to the device structures, and the redundant metal lines are electrically isolated from the device structures.

9. The method for forming a semiconductor structure according to claim 6, characterized in that, The intervals between several of the redundant metal lines along the first direction are an arithmetic sequence or a geometric sequence.

10. The method for forming a semiconductor structure according to claim 6, characterized in that, The electrically interconnecting layer further includes: an interlayer dielectric layer that covers a plurality of the signal metal lines and a plurality of the redundant metal lines.

11. The method for forming a semiconductor structure according to claim 10, characterized in that, The method for forming the electrically interconnecting layer includes: forming the interlayer dielectric layer on the substrate; forming a plurality of signal metal grooves and a plurality of redundant metal grooves in the interlayer dielectric layer; forming a metal material layer in the signal metal grooves, in the redundant metal grooves, and on the top surface of the interlayer dielectric layer; performing a planarization process on the metal material layer until the top surface of the interlayer dielectric layer is exposed, to form a plurality of the signal metal lines and a plurality of the redundant metal lines.

12. The method for forming a semiconductor structure according to claim 11, characterized in that, The forming process of the plurality of redundant metal grooves includes: a single mask exposure process, a double mask exposure process, or a quadruple mask exposure process.

13. The method for forming a semiconductor structure according to claim 11, characterized in that, The process for performing the planarization process on the metal material layer includes: a chemical mechanical polishing process.

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