Packaged integrated circuit having package substrate with integrated isolation circuit

Abstract

The invention relates to a packaged integrated circuit having a package substrate with an integrated isolation circuit. A package substrate (202) includes a first metal layer (328, 1906), a second metal layer (324, 1904), an isolation material (314) including the first metal layer (328, 1906) and the second metal layer (324, 1904), an isolation circuit (e.g. 204 in fig. 2), a first plurality of contact pads (350), and a second plurality of contact pads. The isolation circuit (204) includes a first circuit element (306) in the first metal layer (328, 1906) and a second circuit element (308) in the second metal layer, the second circuit element (308) being electrically isolated from the first circuit element (306) by the isolation material (314). The first plurality of contact pads (316, 318) is adapted to be coupled to a first integrated circuit (310) on the package substrate, and includes a first contact pad (318-2) coupled to the first circuit element (306). The second plurality of contact pads (330, 332) is adapted for coupling to a second integrated circuit (320) on the package substrate (202) and includes a second contact pad (332-2) coupled to the second circuit element (308).

Description

[0001] Cross - Reference to Related Applications

[0002] This application is a partial continuation of U.S. patent application Ser. No. 18 / 347,201, filed Jul. 5, 2023, titled “Circuit Support Structure with Integrated Isolation Circuitry,” which is a divisional application of and claims priority to U.S. patent application Ser. No. 17 / 167,753, filed Feb. 4, 2021, titled “Circuit Support Structure with Integrated Isolation Circuit,” which claims priority to U.S. Provisional Patent Application No. 62 / 976,427, filed Feb. 14, 2020, and U.S. Provisional Patent Application No. 63 / 131,407, filed Dec. 29, 2020, all of which are incorporated herein by reference. FIELD OF THE DISCLOSURE

[0003] This application generally relates to semiconductors and, more particularly, to packaged integrated circuits having a package substrate with integrated isolation circuitry. BACKGROUND OF THE DISCLOSURE

[0004] Isolation is often required for interconnected electrical systems to exchange data or power between systems. For example, two systems may be powered by different power supplies that do not share a common ground connection. The two systems may be electrically isolated to prevent current and voltage in one system from negatively affecting the other system, such as by damaging or interfering with the operation of one or more components of the other system. Transformer isolation and capacitor isolation are two methods used. Transformer isolation can be used to exchange power between two systems, and capacitor-based isolation can be used to exchange power or data between two systems. In some applications using isolation circuits, challenges may arise in maintaining voltage isolation, interconnect parasitics, and isolation circuit efficiency. SUMMARY OF THE DISCLOSURE

[0005] The described examples include a package substrate and an integrated circuit package (e.g., a circuit support structure) having an integrated isolation circuit. The described examples also include a method for manufacturing a circuit support structure having an integrated isolation circuit. Integrating or embedding the isolation circuit into the circuit support structure results in a smaller integrated circuit package while maintaining voltage isolation. Additionally, when implementing one or more of the examples described herein, additional benefits may be realized, such as improved efficiency of the integrated isolation circuit, reduced interconnect parasitics, and improved thermal performance.

[0006] In one example, a circuit support structure includes a first metal layer, a second metal layer, an isolation material containing the first and second metal layers, an isolation circuit, a first plurality of contact pads, and a second plurality of contact pads. The isolation circuit includes a first circuit element in the first metal layer and a second circuit element in the second metal layer, and the second circuit element is electrically isolated from the first circuit element by the isolation material. The first plurality of contact pads is adapted to couple to a first integrated circuit on the circuit support structure and includes a first contact pad coupled to the first circuit element. The second plurality of contact pads is adapted to couple to a second integrated circuit on the circuit support structure and includes a second contact pad coupled to the second circuit element.

[0007] In another example, a circuit support structure includes a first metal layer, a second metal layer, a molding compound containing the first and second metal layers and defining a mounting surface of the circuit support structure, an isolation circuit, a first plurality of contact pads, and a second plurality of contact pads. The isolation circuit includes a first circuit element in the first metal layer and a second circuit element in the second metal layer, and the second circuit element is electrically isolated from the first circuit element by the molding compound. The first plurality of contact pads is exposed at the mounting surface and includes a first contact pad coupled to the first circuit element. The second plurality of contact pads is exposed at the mounting surface and includes a second contact pad coupled to the second circuit element.

[0008] In another example, an integrated circuit package includes a circuit support structure, a first integrated circuit, and a second integrated circuit. The circuit support structure includes a first metal layer, a second metal layer, an isolation material containing the first and second metal layers, an isolation circuit, a first plurality of contact pads, and a second plurality of contact pads. The isolation circuit includes a first circuit element in the first metal layer and a second circuit element in the second metal layer, and the second circuit element is electrically isolated from the first circuit element by the isolation material. The first plurality of contact pads includes a first contact pad coupled to the first circuit element. The second plurality of contact pads includes a second contact pad coupled to the second circuit element. The first integrated circuit is on the circuit support structure and coupled to the first plurality of contact pads, and the second integrated circuit is on the circuit support structure and coupled to the second plurality of contact pads.

[0009] In another example, a method of fabricating a circuit support structure having an integrated isolation circuit includes forming first and second circuit elements of the isolation circuit, a first plurality of contact pads including first contact pads, a second plurality of contact pads including second contact pads, and a third plurality of contact pads in a metal layer. The method further includes coupling the first contact pads to the first circuit elements, coupling the second contact pads to the second circuit elements, and coupling some of the first plurality of contact pads and some of the second plurality of contact pads to the third plurality of contact pads. The method further includes encapsulating the metal layer in an isolation material such that the first and second circuit elements are electrically isolated from each other, the first plurality of contact pads and the second plurality of contact pads are exposed at a first surface defined by the isolation material, and the third plurality of contact pads are exposed at a second opposite surface defined by the isolation material.

[0010] In another example, a packaged integrated circuit includes a package substrate including an isolation circuit that includes a first primary side terminal, a second primary side terminal, a first secondary side terminal, and a second secondary side terminal. In at least one example, a first semiconductor die is on the package substrate and coupled to the first primary side terminal and the second primary side terminal. In at least one example, a second semiconductor die is on the package substrate and coupled to the first secondary side terminal and the second secondary side terminal.

[0011] In another example, a packaged integrated circuit includes a package substrate including a first transformer, the package substrate including a first primary winding and a first secondary winding, the first primary winding being coupled between a first primary side terminal and a second primary side terminal, and the first secondary winding being coupled between a first secondary side terminal and a second secondary side terminal. In at least one example, the package substrate includes a second transformer that includes a second primary winding and a second secondary winding, the second primary winding being coupled between a third primary side terminal and a fourth primary side terminal, and the second secondary winding being coupled between a third secondary side terminal and a fourth secondary side terminal. In at least one example, the packaged integrated circuit includes a first semiconductor die on the package substrate and coupled to the first primary side terminal and the second primary side terminal. In at least one example, the packaged integrated circuit includes a second semiconductor die on the package substrate and coupled to the first secondary side terminal and the second secondary side terminal.

[0012] In at least one example, the method includes coupling a first primary winding of a first transformer between a first primary side terminal and a second primary side terminal. The method further includes coupling a first secondary winding of the first transformer between a first secondary side terminal and a second secondary side terminal. The method further includes coupling a second primary winding of a second transformer between a third primary side terminal and a fourth primary side terminal. The method further includes coupling a second secondary winding of the second transformer between a third secondary side terminal and a fourth secondary side terminal, wherein the first transformer and the second transformer are in a package substrate. The method further includes coupling the first primary side terminal and the second primary side terminal to a first semiconductor die on the package substrate. The method further includes coupling the first secondary side terminal and the second secondary side terminal to a second semiconductor die on the package substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] These examples will be more fully understood from the detailed description given below and the accompanying drawings, however, they should not be considered as limiting the present disclosure to the specific examples, but are only for explanation and understanding.

[0014] Figure 1 Schematically depicts an example packaged integrated circuit (IC) having an integrated isolation circuit according to at least one example.

[0015] Figure 2A Schematically depicts another example packaged IC having an integrated isolation circuit according to at least one example, the integrated isolation circuit including inductive and capacitive isolation channels coupled to first and second semiconductor dies.

[0016] Figure 2B Schematically shows a packaged IC having an integrated isolation circuit according to at least one example, the integrated isolation circuit including an inductive isolation channel coupled to first and second semiconductor dies.

[0017] Figure 2C Schematically shows a packaged IC having a third semiconductor die coupled to a second semiconductor die according to at least one example.

[0018] Figure 2D Schematically shows a packaged IC having a third semiconductor die coupled to a second semiconductor die according to at least one example, wherein the data circuit is a separate semiconductor die.

[0019] Figure 3 Schematically shows an isometric view of an example packaged IC having an integrated isolation circuit according to at least one example, the integrated isolation circuit including an inductive channel coupled within the packaged IC without using wire bonding.

[0020] Figure 4 Schematically shows according to at least one exampleFigure 3 Top plan view of an exemplary encapsulated IC as shown.

[0021] Figure 5 Schematically shows, according to at least one example, Figure 3 Side view of the exemplary encapsulated IC as shown.

[0022] Figure 6 Isometric view of another exemplary encapsulated IC with an integrated isolation circuit, according to at least one example, the integrated isolation circuit including inductive channels coupled within the encapsulated IC using wire bonding.

[0023] Figure 7 Schematically shows, according to at least one example, Figure 6 Top plan view of the exemplary encapsulated IC as shown.

[0024] Figure 8 Schematically shows, according to at least one example, Figure 6 Side view of the exemplary encapsulated IC as shown.

[0025] Figure 9 Top plan view depicting another exemplary encapsulated IC with an integrated isolation circuit, according to at least one example, the integrated isolation circuit including inductive channels coupled within the encapsulated IC without using wire bonding.

[0026] Figure 10 Schematically shows, according to at least one example, taken from Figure 9 Partial cross-sectional view of the exemplary encapsulated IC as shown.

[0027] Figure 11 Isometric view of another exemplary encapsulated IC with an integrated isolation circuit, according to at least one example, the integrated isolation circuit including inductive and capacitive isolation channels.

[0028] Figure 12 Is a flowchart of an exemplary method for manufacturing a packaged substrate with an integrated isolation circuit, according to at least one example.

[0029] Figure 13A -B schematically show the circuit model of a capacitive isolation circuit coupled to a differential transmitter and a differential receiver and the equivalent circuit model of a common mode applied across the isolation barrier, according to some examples.

[0030] Figure 13C -D schematically show the circuit model of an inductive isolation circuit coupled to a differential transmitter and a differential receiver and the equivalent circuit model of a common mode applied across the isolation barrier, according to some examples.

[0031] Figure 13E is a curve showing the variation of the common-mode gain with frequency at a differential receiver coupled to a capacitive isolation circuit and an inductive isolation circuit, according to at least one example.

[0032] Figure 14 is a schematic diagram of a data circuit and its corresponding inductive isolation circuit, according to at least one example.

[0033] Figure 15 Schematically shows a top view of a packaged IC according to at least one example, the packaged IC having separate power and data semiconductor dies, three transformers, and a dedicated semiconductor die.

[0034] Figure 16 Schematically shows an isometric top view of another example data transformer under a data semiconductor die, according to at least one example.

[0035] Figure 17 Schematically shows, according to at least one example Figure 15 an isometric bottom view of three transformers.

[0036] Figure 18 Schematically shows an isometric top view of a packaged integrated circuit in which a data transformer is surrounded by power transformers, according to at least one example.

[0037] Figure 19 Schematically shows a cross-sectional view of a packaged IC having a package substrate with three metal layers, according to at least one example.

[0038] Figure 20 Schematically shows an isometric top view of a packaged IC in which the primary and secondary windings of its data transformer partially overlap, according to at least one example.

[0039] Figure 21 Schematically shows, according to at least one example Figure 20 a magnified top view of a packaged IC in which the primary and secondary windings of its data transformer partially overlap.

[0040] Figure 22 Schematically shows an isometric magnified top view of the partially overlapping primary and secondary windings of a data transformer, according to at least one example.

[0041] Figure 23 Schematically shows an isometric magnified top view of the partially overlapping primary and secondary windings of a data transformer, according to at least one example.

[0042] Figure 24 is a flowchart of a method for forming a packaged IC having three transformers, according to at least one example. Detailed Description

[0043] This document describes a packaged integrated circuit (IC) including two or more semiconductor dies, the semiconductor dies being coupled to isolation circuitry (e.g., an isolation barrier) integrated within a package substrate. In at least one example, the package substrate includes three metal layers. In at least one example, the package substrate includes two metal layers. In at least one example, the two or more semiconductor dies include a first semiconductor die having a first power IC and a second semiconductor die having a second power IC, wherein the first semiconductor die is coupled to the second semiconductor die via a power converter that is part of the isolation circuitry. In at least one example, the first semiconductor die and the second semiconductor die include data circuitry coupled via a second set of converters (e.g., data converters) that is also part of the isolation circuitry. According to at least one example, the data circuitry provides bi-directional signaling. In at least one example, the data circuitry can be a separate semiconductor die on the package substrate. In at least one example, the second set of converters is surrounded by or otherwise located within the footprint of the power converter. In at least one example, the second set of converters is located outside the footprint of the power converter. In at least one example, the semiconductor die is a flip-chip die that allows connection to the converter below it with reduced interconnects.

[0044] In at least one example, the data circuitry is used to send and receive signals between the first and second power semiconductor dies to implement a DC-DC converter. In at least one example, the data circuitry can be used for other functions such as telemetry, data signaling, buffering of analog input signals of an analog-to-digital converter, buffering of digital input signals of a digital-to-analog converter, and so on. In at least one example, an additional semiconductor die is located on the package substrate, wherein the additional semiconductor die receives power from the second power semiconductor die and exchanges data with the data circuitry. The additional semiconductor die can be any dedicated semiconductor die or a general-purpose microcontroller.

[0045] By integrating semiconductor dies for power regulation and data transfer with isolation circuitry integrated in a package substrate, the overall size of the packaged IC is reduced. The flip-chip assembly of the semiconductor die allows for more stringent parameter control, which reduces the size or area of the packaged IC, enabling shorter and / or fewer interconnect runs, tighter connections, smaller parasitic capacitance, resistance, and / or inductance, etc. One or more flip-chip dies overlap the converter below the flip-chip die, and this configuration reduces the parasitic capacitance, resistance, and / or inductance involved in connecting the converter to the flip-chip die. The routing on the package substrate is reduced because most signal and power routing can be within the package substrate. The reduction of the parasitic capacitance, resistance, and / or inductance involved in connecting the converter of the isolation circuitry to the bonded assembly allows for customization of the power and data channels according to application requirements and enables higher power transfer efficiency.

[0046] In addition, at least compared to the case of forming the converter winding (or other isolation circuitry) in the metallization layer on the semiconductor die, by placing the converter of the isolation circuitry in the package substrate, which may be much thicker than the converter winding, the vertical spacing between the converter winding and the semiconductor die can be increased. Such an arrangement can reduce the parasitic capacitance between the converter winding and the semiconductor die, which can provide a connection to ground. The reduced parasitic capacitance can increase the quality factor (Q) of the converter. The increased vertical spacing can also reduce eddy currents induced in the semiconductor die by the magnetic field generated by the converter, which can reduce losses and further increase the power or signal transfer efficiency. In addition, as explained below, the converter can also provide improved common-mode transient immunity and improved differential signal matching.

[0047] The flexibility of the routing capabilities of the package substrate also improves the connectivity and signal integrity of the served application-specific ICs. Some example packaged ICs integrate power and bidirectional data communication with minimized crosstalk, enabling them to operate independently, which makes the use of isolated co-packaged devices more flexible. In at least one example, a package substrate with three metal layers uses thicker metal (e.g., copper) traces to increase the efficiency of the power converter. Since the semiconductor die is above the package substrate, the converter in the package substrate produces a higher QF because the windings of the converter are not laterally close to the semiconductor die. Embedding the data converter in the substrate allows for high-frequency signal communication between data integrated circuits. Routing signals and power through a package substrate with three metal layers reduces the interconnect congestion at the top of the substrate, making the packaged integrated circuit smaller because the semiconductor dies in the packaged integrated circuit are placed closer to each other. In at least one example, the converter is arranged within a dual-layer substrate, further reducing the manufacturing cost, vertical dimension, and cost of the packaged IC. The flexible routing in the package substrate allows for better control of the near-field interaction and coupling between the converter and the application-specific integrated circuit.

[0048] In the drawings, like reference numerals always refer to like elements, and the various features are not necessarily drawn to scale. Here, like reference numerals or other reference indicators are used in the drawings to denote features that are the same or similar (in terms of function and / or structure).

[0049] First refer to Figure 1 , which is a block diagram depicting an example packaged IC 100 having an integrated isolation circuit 108. In at least one example, the packaged IC 100 includes a package substrate 102, a semiconductor die 104, and a semiconductor die 106. The semiconductor dies 104 and 106 are mounted to the package substrate 102, which can support the semiconductor dies 104 and 106 as a circuit support structure. As used herein, an IC is a circuit built on a semiconductor substrate such as a silicon wafer. A package substrate, such as a lead frame, is a structure configured to have an IC mounted thereon and configured to provide electrical interconnection between the IC and one or more circuits external to the package substrate.

[0050] According to at least one example of the present specification, the isolation circuit 108 is integrated, formed, or embedded in a layer (not shown) of the package substrate 102, as indicated by the dashed lines. Further, according to at least one example of the present specification, the package substrate 102 includes contact pads (not shown) and may include metal interconnects 110 (four are shown) to enable interconnectivity between the semiconductor dies 104 and 106 and the isolation circuit 108. Each interconnect 110 may represent one or more electrical traces and / or vias.

[0051] In at least one example, the isolation circuit 108 (and other isolation circuit examples according to the present specification) can provide an electrical isolation barrier between two different power domains. In at least one example, the packaged IC 100 represents a DC-DC converter having a transformer as the isolation circuit 108. Thus, the semiconductor die 104 may include a circuit, such as a half-bridge circuit or a full-bridge circuit, and a driver circuit for providing voltage and current from another circuit to the primary winding of the transformer. In an example, the voltage and current are provided from a power supply of a printed circuit board (PCB) on which the package substrate 102 is mounted. The PCB can be used to power devices such as motors or computing devices. The semiconductor die 106 may include a bridge circuit and driver and regulation circuits for receiving voltage and current from the secondary winding of the transformer and providing one or more regulated output voltages and / or currents for use by a load on the PCB. The load can be an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a microcontroller, a processor, etc. In other examples, the semiconductor die 104 and / or 106 may represent a controller circuit, current and voltage sensors, a gate driver for an insulated gate bipolar transistor, a gate driver for a field-effect transistor (FET), etc.

[0052] In at least one example, isolation circuit 108 may include one or more isolation circuits. In at least one example, isolation circuit 108 includes a single transformer, such as Figures 3 - 11 shown. In at least one example, isolation circuit 108 includes a single capacitor. However, in other examples, isolation circuit 108 includes: multiple transformers, such as Figures 15 - 23 shown; multiple capacitors; or a combination of one or more transformers and capacitors, such as Figure 2A and 11 shown.

[0053] Figure 2A Another example of a packaged IC 200 with an integrated isolation circuit 204 is schematically depicted. In at least one example, packaged IC 200 includes a package substrate 202, a primary side circuit 210, and a secondary side circuit 220. In at least one example, primary side circuit 210 and secondary side circuit 220 are semiconductor dies. Semiconductor dies 210 and 220 are mounted to package substrate 202. In at least one example, the package substrate includes a fiberglass-based material that uses etched copper layers and drilled vias instead of plated layers and vias. In at least one example, integrated isolation circuit 204 is integrated into a layer (not shown) of package substrate 202, as indicated by the dashed line. Additionally, package substrate 202 includes contact pads (not shown) and metal interconnects 230 (eight are shown) to enable interconnectivity between semiconductor dies 210 and 220 and integrated isolation circuit 204. Each interconnect 230 may represent one or more electrical traces and / or vias.

[0054] In at least one example, integrated isolation circuit 204 includes both a transformer and a capacitor. That is, integrated isolation circuit 204 includes N transformers 206 and M capacitors 208, where both N and M are integer values of one or greater. Additionally, N and M may be the same or different integer values. In at least one example, integrated isolation circuit 204 includes multiple transformers but no capacitors and can be used to transfer power. In at least one example, integrated isolation circuit 204 includes multiple capacitors but no transformers and can be used to transfer data, power, or a combination of both.

[0055] The primary-side semiconductor die 210 is coupled to the primary winding (not shown) of each of the N converters 206 and includes a driver circuit 212, N primary-side bridges 214 (e.g., half-bridge or full-bridge circuits), and a data circuit 216 (e.g., a digital communicator). The data circuit 216, the driver circuit 212, and the bridges 214 may be on the same semiconductor die or on separate semiconductor dies. The driver circuit 212, the primary-side bridges 214, and the data circuit 216 may use any suitable circuit configuration. Each of the N primary-side bridges 214 is coupled to the primary winding (not shown) of the corresponding one of the N converters 206 through a respective interconnect 230 of the package substrate 202. The driver circuit 212 provides a control function to the primary-side bridges 214. In turn, each of the primary-side bridges 214 provides a voltage to the corresponding one of the N converters 206 using the respective one of the interconnects 230. The current example includes two primary-side bridges 214 and two converters 206, as shown by the two interconnects 230 coupling them therebetween.

[0056] The current example further includes two capacitors 208, as shown by the two interconnects 230 coupling the data circuit 216 and the M capacitors 208. The two capacitors 208 and the interconnects 230 allow two-way data communication, such as Controller Area Network (CAN) or CAN Flexible Data Rate (FD) protocol communication or RS-485 protocol communication. That is, the data circuit 216 may provide a data signal to one of the two capacitors 208 through the respective interconnect 230 and receive a data signal from the other capacitor 208.

[0057] As further shown, the secondary-side semiconductor die 220 includes N secondary-side bridges 222, a driver and output voltage regulation circuit 224, and a data circuit 226 (e.g., a digital communicator). The data circuit 226, the driver circuit 224, and the bridges 222 may be on the same semiconductor die or on separate semiconductor dies. The secondary-side bridges 222, the driver and output voltage regulation circuit 224, and the data circuit 226 may use any suitable circuit configuration. Each of the N secondary-side bridges 222 is coupled to the secondary winding (not shown) of the corresponding one of the N converters 206 through a respective interconnect 230 of the package substrate 202. The driver circuit 224 provides a control function to the secondary-side bridges 222. In turn, each of the secondary-side bridges 222 receives a voltage from the corresponding one of the N converters 206 using the respective one of the interconnects 230. The output voltage regulator (VR) of the circuit 224 receives and regulates the voltage from the secondary-side bridges 222, e.g., using a feedback loop. The current example includes two secondary-side bridges 222 and two converters 206, as shown by the two interconnects 230 coupling them therebetween.

[0058] Figure 2AThe example shown further includes two capacitors 208, as shown by two interconnects 230 coupled between data circuit 226 and the capacitors 208. In at least one example, the two capacitors 208 and the interconnects 230 allow for bidirectional data communication. That is, data circuit 226 can provide a data signal to one of the two capacitors 208 via a respective interconnect 230 and receive a data signal from the other capacitor 208.

[0059] Figure 2B An encapsulated IC 220 with an integrated isolation circuit is schematically shown according to at least one example, the integrated isolation circuit including an inductive isolation channel coupled to a first semiconductor die 210 and a second semiconductor die 220. Here, M capacitors 208 are replaced with M transformers 228. In at least one example, the M transformers 228 have M primary windings and M secondary windings, where the primary windings are coupled to data circuit 216 via interconnects 230 and the secondary windings are coupled to data circuit 226.

[0060] In at least one example, data circuit 216 may provide a first data signal to the primary windings of M converters 228 via respective interconnects 230 and receive a second data signal from the secondary windings of the M converters. In at least one example, the first data signal may originate from an external data source and the second data signal may be for an external data receiver. In at least one example, the number of primary windings of converter 228 is equal to the number of secondary windings of converter 228. In at least one example, the number of primary windings of converter 228 is different from the number of secondary windings of converter 228. In at least one example, converter 228 is smaller in size than converter 206. In at least one example, converter 228 resides within the footprint of converter 206 (e.g., within the footprint of the windings of converter 206). In at least one example, converter 228 is external to the footprint of converter 206. In at least one example, converter 228 may be used for bi-directional or uni-directional data transfer not related to a power converter formed by driver circuit 212, N primary side bridges 214, N secondary side bridges 222, and driver and output VR circuit 224. Such a use of converter 228 for data and power circuits is discussed in U.S. Patent Application No. 17 / 363,470, titled "Data Transfer Through An Isolated Power Converter," filed on June 30, 2021, which is incorporated herein by reference in its entirety. In at least one example, converter 228 is used for bi-directional or uni-directional data transfer directly related to the control of a power converter formed by driver circuit 212, N primary side bridges 214, N secondary side bridges 222, and driver and output VR circuit 224. Converter 228 may include two or more transforms, one for each data or signal line.

[0061] Figure 2C Schematically shows encapsulated IC 240. In Figure 2CIn this case, the primary-side semiconductor die 210 is in the first semiconductor die that includes the data circuit 216, and the secondary-side semiconductor die 220 is in the second semiconductor die that includes the data circuit 226. According to at least one example, the packaged IC 240 further includes a third semiconductor die 242 that is on the package substrate 202 and coupled to the second semiconductor die 220. In at least one example, the third semiconductor die 242 can be mounted on the package substrate 202 before an integrated isolation circuit is formed in the package substrate 202. In at least one example, the third semiconductor die 242 can be electrically connected to the package substrate 202 via bonding wires. In at least one example, the semiconductor die 242 receives data (DataOut) and power (PwrOut) from the semiconductor die 242, both indicated by the interconnect 241. DataOut is the output of the data circuit 226, and PwrOut is the output of the VR circuit 224 of the second semiconductor die 220. In at least one example, the semiconductor die 242 is part of an application specific integrated circuit (ASIC). Examples of ASICs include analog-to-digital converters (ADCs), digital-to-analog converters (DACs), equalizers, digital filters, microcontrollers, etc. The semiconductor die 242 can be flip-chip mounted, wire-bonded, or have any other package mounting technology.

[0062] Figure 2D Schematically shown is a packaged IC 250 having a third semiconductor die 242 coupled to a second semiconductor die 220 according to at least one example, where the data circuits 216 and 226 are separate semiconductor dies from the semiconductor dies 210 and 220. Here, the semiconductor dies 210 and 220 can form a DC-DC converter or power regulation, and the data circuits 216 and 226 provide data communication. The first semiconductor die 210 includes a driver circuit 212 and N primary-side bridges 214. The second semiconductor die 220 includes N secondary-side bridges 222 and a driver and output VR circuit 224.

[0063] In at least one example, the data circuit 216 and the data circuit 226 provide data communication signals (e.g., DataOut) that can be used for digital control or feedback control of the DC-DC converter formed by the first semiconductor die 210 and the second semiconductor die 220. DataOut and DataIn can be bi-directional signals. In at least one example, the data circuit 216 and / or the data circuit 226 provide data communication signals to the semiconductor die 242 and also provide data control signals to the first semiconductor die 210 and the second semiconductor die 220 for feedback control of the DC-DC converter. Figures 14 - 24 Provide Figure 2B -D example circuit and structural details.

[0064] Figures 3 - 5 Schematically shows different views of an example IC package (or packaged IC) 300 having an integrated isolation circuit 304 according to some examples. More specifically, Figure 3 Schematically shows an isometric view of the packaged IC 300 along the XYZ axes. Figure 4 Schematically shows a top plan view of the packaged IC 300 along the XY axes, and Figure 5 Schematically shows a side view of the packaged IC 300 along the YZ axes.

[0065] As shown, the packaged IC 300 includes a package substrate 302 (e.g., a circuit support structure) and two semiconductor dies 310 and 320 mounted on a surface ( Figure 4 400 in) of the package substrate 302. The material, structure, and function of the package substrate 302 may be similar to those of the package substrate 202. In an example, the semiconductor die 310 includes a driver circuit and a primary side bridge circuit, and the semiconductor die 320 includes a secondary side bridge circuit and a driver / output voltage regulation circuit, such as previously described with reference to Figure 2A -D with respect to the primary side semiconductor die 210 (first semiconductor die) and the secondary side semiconductor die 220 (second semiconductor die). In at least one example, the packaged IC 300 further includes a molding compound 312 that encapsulates the semiconductor dies 310 and 320 and the surface 400 of the package substrate 302. In at least one example, the molding compound 312 may have any suitable form, such as bulk molding compound, sheet molding compound, insulating build-up film, etc. In at least one example, the packaged IC 300 including the package substrate 302 and the semiconductor dies 310 and 320 is or forms a flat leadless package, particularly a dual flat no-lead (DFN) package. In at least one example, the contact pads 348 for mounting the packaged IC 300 to an external package substrate are arranged such that the packaged IC 300 forms a quad flat no-lead (QFN) package.

[0066] In at least one example, the encapsulation substrate 302 is configured to include metal layers 322 - 328 and an isolation material 314 that contains or encapsulates the metal layers 322 - 328. In an example, the encapsulation substrate 302 is a multi-layer structure fabricated using a routable lead frame (RLF) technique. As used herein, a metal layer is a layer of metal within which metal components of the encapsulation substrate are formed, such as contact pads, vias, electrical traces, thermal / ground pads, and circuit components of isolation circuits. The metal layers are positioned in planes that are substantially parallel to each other and are substantially planar within the allowable tolerances defined by the technique used to fabricate the encapsulation substrate. Any suitable metal can be used to form the metal layers, such as copper, aluminum, and gold. In this example, the encapsulation substrate 302 includes four metal layers 322 - 328. However, other example encapsulation substrates can include more or fewer metal layers.

[0067] The isolation material 314 is used to electrically isolate the metal layers 322 - 328 and can thus include a dielectric or insulator. The isolation material 314 completely contains some of the metal layers 322 - 328 and partially contains other metal layers 322 - 328. An example of partially containing a metal layer includes when a contact pad formed in the metal layer is exposed at the surface of the encapsulation substrate 302. Additionally, the isolation material 314 defines a mounting or top surface 400 and a surface or bottom surface (not shown) that is opposite the mounting surface 400. In at least one example, the isolation material 314 is a molding compound in any suitable form, such as bulk molding compound, sheet molding compound, insulating build-up film, etc., and can be or include the same or a different type of molding compound as the molding compound 312. In a particular example, the isolation material 314 consists of an Ajinomoto build-up film (ABF). Other isolation materials can be used, such as ceramics or glass fiber-based materials.

[0068] As Figure 3 Further shown, the encapsulation substrate 302 also includes an isolation circuit 304 formed and integrated therein. The isolation circuit 304 can have a similar function as described with reference Figure 2A -D regarding the integrated isolation circuit 204. In this example, the isolation circuit 304 includes a single transformer having a winding 306 (e.g., a primary winding) as a first circuit element and a winding 308 (e.g., a secondary winding) as a second circuit element. Thus, the integrated isolation circuit 304 is also referred to as a transformer 304 herein. In at least one example, the integrated isolation circuit 304 can include a single capacitor having a first set of one or more plates as a first circuit element and a second set of one or more plates as a second circuit element integrated into the encapsulation substrate 302.

[0069] In at least one example, windings 306 and 308 are formed in different ones of the metal layers 322 - 328, as further described below and with referenceFigure 5 Shown. In addition, windings 306 and 308 are electrically isolated using the isolation material 314 of the encapsulation substrate 302, and the isolation material forms an electrical isolation barrier between two different power domains in one specific example. In at least one example, the first semiconductor die 310 is powered using a voltage supplier and a ground connection associated with the first power domain. The second semiconductor die 320 is powered using a different voltage supplier and a ground connection associated with the second power domain. In addition, in at least one example, the isolation material 314, such as molding compound, has a thickness and is of a type that provides an electrical isolation barrier which, in one example, can withstand 5 kilovolts (kV) root mean square (RMS) for 60 seconds and, in another example, can withstand 2.5 kV RMS for 60 seconds. However, different isolation ratings can be achieved at least in part based on the type and thickness of the isolation material 314 used.

[0070] Using molding compound instead of laminate as the isolation material 314 allows for a smaller critical spacing between windings 306 and 308 while maintaining the same voltage insulation and can improve the thermal performance of the isolation circuit 304. In addition, manufacturing the encapsulation substrate 302 using the deployable lead frame technology allows for thicker copper traces (e.g., 30 - 35 microns or thicker, such as 1%, 5%, or 10% thicker) and smaller metal width and spacing (e.g., 30x30 microns 2 or smaller, such as 1%, 5%, or 10% smaller). This can increase the quality factor of the converter 304 and thus improve the efficiency of the converter 304. In addition, integrating the converter 304 into the encapsulation substrate 302 results in a smaller size of the packaged IC (e.g., 5.0x3.0x0.8 millimeters 3 or smaller, such as 1%, 5%, or 10% smaller).

[0071] As used herein, the critical spacing refers to one or more minimum distances between the first and second circuit elements of an isolation circuit (e.g., primary and secondary windings or first and second capacitor plates) that allow a given isolation rating to be achieved without voltage breakdown of the isolation material between the first and second circuit elements. Thus, by using different types of isolation materials 314, such as different types of molding compounds in separate or combined forms, the critical spacing between windings 306 and 308 can be adjusted, for example, to meet the desired creepage and clearance of the packaged IC 300 and to achieve lower creepage and clearance than can be achieved using laminate as the isolation material.

[0072] In at least one example, the encapsulation substrate 302 includes a first plurality of contact pads 316 (one of four is marked) and 318 (individually referred to as contact pads 318-1 and 318-2) for coupling to the semiconductor die 310. In at least one example, the encapsulation substrate 302 further includes a second plurality of contact pads 330 (one of four is marked) and 332 (individually referred to as contact pads 332-1 and 332-2) for coupling to the second semiconductor die 320. More specifically, the contact pads 316, 318, 330, and 332 are formed in a metal layer 328 (e.g., the top metal layer) and are exposed at the mounting surface 400 of the encapsulation substrate 302 for coupling to the semiconductor dies 310 and 320. Thus, the contact pads 316, 318, 330, and 332 are also referred to herein as IC contact pads because they are used to mount or fix and electrically couple the semiconductor dies 310 and 320 to the encapsulation substrate 302.

[0073] The contact pads 316 and 330 are coupled to contact pads 348 (two of eight are marked), which are formed in a metal layer 322 (e.g., the bottom metal layer) and are exposed at the bottom surface (not shown) of the encapsulation substrate 302. For example, in a DFN or QFN implementation of the packaged IC 300, a ground / thermal plane may also be formed in the bottom metal layer 322 such that the thermal performance of the packaged IC 300 can be improved.

[0074] Reference Figure 4 , in this example, the mounting surface 400 and the opposite bottom surface are substantially flat or planar and are substantially parallel to each other within the allowable tolerances of the technology used to fabricate the encapsulation substrate 302. The electrical coupling between the contact pads 316 and 348 and between the contact pads 330 and 348 is implemented using vias 350 (two of eight are marked) formed in the intermediate metal layers 324 and 326 and passing through the isolation material 314. Thus, the contact pads 348 can be used to mount and couple the packaged IC 300 to an external encapsulation substrate, such as a laminated PCB.

[0075] The contact pads 318 and 332 are coupled to the transformer 304. As shown, the contact pad 318-1 forms the first input voltage terminal of the winding 306. The contact pad 318-2 is coupled to the second input voltage terminal 340 of the winding 306 using an electrical trace 338 and two vias ( Figure 5 500 in). As further shown, the contact pad 332-1 is coupled to the first output voltage terminal 352 of the winding 308 using a via 500. The contact pad 332-2 is coupled to the second output voltage terminal 354 of the winding 308 using an electrical trace 346 and a via 500. In at least one example, the vias 500 are formed in the metal layer 326 through the isolation material 314.

[0076] Reference Figure 3 and 4 ,the contact pads 316 and 318 are used to flip-chip mount the semiconductor die 310 onto the mounting surface 400. That is, a contact pad 334 (one of four marked) on the surface of the semiconductor die 310 is mechanically coupled to the contact pad 316, for example, using solder balls (not shown) attachable to the contact pad 334. Similarly, a contact pad 336 on the surface of the semiconductor die 310 is mechanically coupled to the contact pad 318, for example, using solder balls (not shown) attachable to the contact pad 336. The coupling between the contact pads 318 and 336 allows a circuit on the semiconductor die 310, such as a bridge circuit, to be coupled to the primary winding 306 of the transformer 304.

[0077] Additionally, the contact pads 330 and 332 are used to flip-chip mount the semiconductor die 320 onto the mounting surface 400. That is, a contact pad 342 (one of four marked) on the surface of the semiconductor die 320 is mechanically coupled to the contact pad 330, for example, using solder balls (not shown) attachable to the contact pad 342. Similarly, a contact pad 344 on the surface of the semiconductor die 320 is mechanically coupled to the contact pad 332, for example, using solder balls (not shown) attachable to the contact pad 344. The coupling between the contact pads 332 and 344 allows a circuit on the semiconductor die 320, such as a bridge circuit, to be coupled to the secondary winding 308 of the transformer 304. In another example, the semiconductor dies 310 and 320 are mounted to the surface 400 of the package substrate 302 using wire bonding instead of flip-chip mounting.

[0078] As Figure 3 and 4 further shown, the windings 306 and 308 of the transformer 304 partially overlap. Thus, at least a portion of each of the windings 306 and 308 does not overlap. Thus, in this example, as shown in reference Figure 4 shown, the portion of the winding 306 to the left of the dashed line 402 does not overlap. Additionally, the portion of the winding 308 to the right of the dashed line 404 does not overlap. The partial overlap of the windings 306 and 308 allows the semiconductor die 310 to be coupled to the winding 306 and allows the semiconductor die 320 to be coupled to the winding 308 without using wire bonding. The removal of the bond wires in the packaged IC 300 with partially overlapping windings 306 and 308 and flip-chip mounting allows for a reduction in interconnect parasitics in the package, for example, a reduction in parasitic inductance. This alleviates the need to include one or more large decoupling capacitors within the packaged IC 300 or within a system containing the packaged IC 300.

[0079] As Figure 3 and 5As shown, the elements associated with the encapsulation substrate 302 and the converter 304 and coupling the converter 304 to the semiconductor dies 310 and 320 can be formed in two metal layers. That is, the windings 306, the electrical traces 346, and the contact pads 316, 318, 330, and 332 are formed in the top metal layer 328. In addition, the windings 308 and the electrical traces 338 are formed in the metal layer 324. In an example, the spacing between the metal layers 328 and 324 and the removal of the metal layer 326 (except for its use in the vias 350 and 500) allows a vertical isolation spacing of 105 microns or less between the windings 306 and 308 while maintaining a voltage isolation of 2.5 kV RMS for 60 seconds.

[0080] As Figure 3 shown, a first interconnect 361 couples the primary-side winding 306 to the contact pad 318-1 to couple to the first semiconductor die 310. A second interconnect 362 couples the secondary-side winding 308 to the contact pad 332-2 to couple to the second semiconductor die 320. A third interconnect 363 that includes the electrical trace 338 couples the primary-side winding 306 to the contact pad 318-2 to couple to the first semiconductor die 310. A fourth interconnect 364 couples the secondary-side winding 308 to the contact pad 332-1 to couple to the second semiconductor die 320. Any suitable conductive material can be used to form the first interconnect 361, the second interconnect 362, the third interconnect 363, and the fourth interconnect 364. In at least one example, the first interconnect 361 and the second interconnect 362 (which may include the electrical traces 346) are on a first metal layer (e.g., the metal layer 328) of the encapsulation substrate 302, and the third interconnect 363 and the fourth interconnect 364 are on a second metal layer (e.g., the metal layer 324) of the encapsulation substrate 302 that is below the first metal layer.

[0081] Figures 6 - 8 Schematically shown are different views of another example packaged IC 600 having an integrated isolation circuit 604 according to at least some examples. More specifically, Figure 6 schematically shown is an isometric view of the packaged IC 600 along the XYZ axes. Figure 7 schematically shown is a top plan view of the packaged IC 600 along the XY axes, and Figure 8 schematically shown is a side view of the packaged IC 600 along the YZ axes.

[0082] As shown, the packaged IC 600 includes an encapsulation substrate 602 and is mounted to the surface of the encapsulation substrate 602 ( Figure 7Two semiconductor dies 310 and 320 in (400). In at least one example, the package substrate 602 includes isolation circuitry 604 integrated therein. The packaged IC 600 is similar to the packaged IC 300 in some respects, as Figure 3 and 6 indicated by the common reference numerals between. However, in terms of the design of a single transformer of the isolation circuitry 604 (also referred to herein as transformer 604), the package substrate 602 of the packaged IC 600 is different from the package substrate 302 of the packaged IC 300. Additionally, the package substrate 602 is different from the package substrate 302 in terms of how the contact pads 318 and 332 are coupled to the transformer 604 as compared to how the contact pads 318 and 332 are coupled to the transformer 304.

[0083] More specifically, similar to the packaged IC 300, the contact pad 318-1 forms the first input voltage terminal of the winding 606 of the transformer 604. The first interconnect 361 couples the primary side winding 606 to the contact pad 318-1. The contact pad 318-2 is coupled to the second input voltage terminal 640 of the winding 606 using both the third interconnect 363 (which includes the electrical trace 638) and the bond wire 656a (the first bond wire). Additionally, similar to the packaged IC 300, the contact pad 332-1 is coupled to the first output voltage terminal 352 of the winding 608 of the transformer 604 using the fourth interconnect 364 and a via ( Figure 8 in 500). Further, the contact pad 332-2 is coupled to the second output voltage terminal 654 of the secondary side winding 608 using the second interconnect 362 (which includes the electrical trace 646), the bond wire 656b (the second bond wire), and the via 500. The bond wires 656a and 656b are collectively referred to as the bond wire 656.

[0084] Figure 7 The semiconductor dies 310 and 320 are shown flip-chip mounted to the surface 400 of the package substrate 602 in the same manner as they are mounted to the surface 400 of the package substrate 302. However, in contrast, the windings 606 and 608 of the transformer 604 completely overlap. That is, as shown, the outer boundary of the winding 606 is completely contained within or aligned with the outer boundary of the winding 608.

[0085] Furthermore, as Figure 6 and 8As shown, the components associated with the transducer 604 and coupling the transducer 604 to the semiconductor dies 310 and 320 in the encapsulated substrate 602 may be formed in two metal layers. That is, the windings 606, the electrical traces 638 and 646 (the first interconnect 361 and the second interconnect 362), and the contact pads 316, 318, 330, and 332 are formed in the top metal layer 328. Additionally, the winding 308 is formed in the metal layer 324 that is located below the top metal layer 328.

[0086] Compared to the encapsulated IC 300, using bond wires 656 may increase the parasitic inductance in the encapsulated IC 600. However, the fully overlapping windings 606 and 608 may allow the transducer 604 to occupy a smaller area on the encapsulated substrate 602, resulting in a smaller size of the encapsulated IC 600 compared to the encapsulated IC 300. Additionally, Figures 6 - 8 the arrangement of the transducer 604 shown in allows an increase in the coupling within the transducer 604. As a result, compared to Figures 3 - 5 the transducer 304 arrangement shown, this allows for high power transfer and higher DC-DC efficiency.

[0087] Figures 9 - 10 Different views of another example encapsulated IC 900 having an integrated isolation circuit 904 are schematically shown in accordance with at least one example. More specifically, Figure 9 a top plan view of the encapsulated IC 900 is schematically shown, and Figure 10 a partial cross-sectional view taken along the dashed line AA' through the encapsulated IC 900 is schematically shown.

[0088] As shown, the encapsulated IC 900 includes an encapsulated substrate 902 and two semiconductor dies 910 and 920 mounted to the surface 912 of the encapsulated substrate 902. Here, the encapsulated substrate 902 may have similar characteristics and functions to the encapsulated substrate 202. In at least one example, the semiconductor die 910 includes a driver circuit and a primary side bridge circuit, and the semiconductor die 920 includes a secondary side bridge circuit and a driver / output voltage regulation circuit, such as those previously described with reference to Figure 2A -D with respect to the first semiconductor die 210 (e.g., the primary side die) and the second semiconductor die 220 (e.g., the secondary side die). The encapsulated IC 900 further includes a molding compound ( Figure 10 1012) that encapsulates the semiconductor dies 910 and 920 and the surface 912 of the encapsulated substrate 902. In at least one example, the molding compound 1012 may have any suitable form, such as bulk molding compound, sheet molding compound, insulating build-up film, etc.

[0089] In at least one example, the encapsulated substrate 902 is configured to include multiple metal layers (e.g., Figure 101000 - 1004) and an isolation material containing or encapsulating the metal layers 1000 - 1004( Figure 10 1014). In at least one example, the encapsulation substrate 902 is configured to include four metal layers, but Figure 10 only three are shown in the figure. Contact pads 948 may be formed in the fourth metal layer to couple the packaged IC 900 to an external encapsulation substrate, such as a PCB, and thermal / ground pads may also be formed therein. In at least one example, the packaged IC 900 may be composed of more or fewer than four metal layers. The metal layers 1000 - 1004 are positioned in planes that are substantially parallel to each other and are substantially planar within the allowable tolerances defined by the technology used to manufacture the encapsulation substrate 902. Any suitable metal may be used to form the metal layers 1000 - 1004, such as copper.

[0090] The isolation material 1014 is used to electrically isolate the metal layers 1000 - 1004 and may thus comprise a dielectric or insulator. The isolation material 1014 completely contains some of the metal layers 1000 - 1004 and partially contains other metal layers 1000 - 1004. Additionally, the isolation material 1014 defines a mounting or top surface 912 and a surface or bottom surface (not shown) opposite the mounting surface 912. In at least one example, the isolation material 1014 is a molding compound in any suitable form, such as bulk molding compound, sheet molding compound, insulating build-up film, etc., and may be or comprise the same or a different type of molding compound as the molding compound 1012. In at least one example, the isolation material 1014 is composed of ABF.

[0091] As Figure 9 further shown, the encapsulation substrate 902 also includes an isolation circuit 904 formed and integrated therein. In this example, the isolation circuit 904 includes a single transformer having a winding 906 (e.g., a primary winding) as a first circuit element and a winding 908 (e.g., a secondary winding) as a second circuit element. Thus, the isolation circuit 904 is also referred to herein as the transformer 904. As further shown, the windings 906 and 908 of the transformer 904 partially overlap.

[0092] The windings 906 and 908 are formed in different ones of the metal layers 1000 - 1004, as further described below and with reference to Figure 10 shown. Additionally, the windings 906 and 908 are electrically isolated using the isolation material 1014 of the encapsulation substrate 902, which in one example forms an electrical isolation barrier between two different power domains used to separately power the semiconductor dies 910 and 920.

[0093] In at least one example, the encapsulation substrate 902 includes a first plurality of contact pads 916 (one of six is marked) and 918 (individually referred to as contact pads 918-1 and 918-2) for coupling to the semiconductor die 910. In at least one example, the contact pads 916 and 918 are used to flip-chip mount the semiconductor die 910 onto the mounting surface 912, for example, using contact pads and solder balls (not shown) coupled to the surface of the semiconductor die 910. In at least one example, the encapsulation substrate 902 further includes a second plurality of contact pads 930 (one of six is marked) and 932 (individually referred to as contact pads 932-1 and 932-2) for coupling to the semiconductor die 920. In at least one example, the contact pads 930 and 932 are used to flip-chip mount the semiconductor die 920 onto the mounting surface 912, for example, using contact pads and solder balls (not shown) coupled to the surface of the semiconductor die 920.

[0094] In at least one example, the contact pads 916, 918, 930, and 932 are formed in a metal layer 1000 (e.g., the top metal layer) and are exposed at the mounting surface 912 of the encapsulation substrate 902 for coupling to the semiconductor dies 910 and 920. In at least one example, the semiconductor dies 910 and 920 are mounted to the surface 912 of the encapsulation substrate 902 using bond wires instead of flip-chip mounting.

[0095] The contact pads 916 and 930 are coupled to contact pads 948 (two of twelve are marked), which are formed in a bottom metal layer (not shown) and are exposed at the bottom surface (not shown) of the encapsulation substrate 902. In at least one example, the mounting surface 912 and the opposite bottom surface are substantially flat or planar and are substantially parallel to each other within the allowable tolerances of the technology used to fabricate the encapsulation substrate 902. The electrical coupling between the contact pads 916 and 948 and between the contact pads 930 and 948 can be implemented using vias (not shown), which are formed in the intermediate metal layers 1002 and 1004 and pass through the isolation material 1014. Thus, the contact pads 948 can be used to mount and couple the packaged IC 900 to an external encapsulation substrate, such as a laminated PCB.

[0096] Contact pads 918 and 932 are coupled to the transformer 904. As shown, contact pad 918-1 forms the first input voltage terminal of winding 906. Contact pad 918-2 is coupled to the second input voltage terminal 940 of winding 906 using trace 938 and two vias (not shown), since trace 938 is formed in a different metal layer from winding 906. When semiconductor die 910 is mounted to package substrate 902, the mechanical and electrical coupling between contact pads 918 and contact pads (not shown) on the surface of semiconductor die 910 allows a circuit (e.g., a bridge circuit) on semiconductor die 910 to be coupled to winding 906.

[0097] As further shown, contact pad 932-1 is coupled to the first output voltage terminal (not labeled) of winding 908 using a via (not shown), since contact pad 932-1 and winding 908 are formed in different metal layers. Contact pad 932-2 is coupled to the second output voltage terminal 954 of winding 908 using trace 946 and vias 1006 and 1008 through isolation material 1014 Figure 10 When semiconductor die 920 is mounted to package substrate 902, the mechanical and electrical coupling between contact pads 932 and contact pads (not shown) on the surface of semiconductor die 920 allows a circuit (e.g., a bridge circuit) on semiconductor die 920 to be coupled to winding 908.

[0098] As Figure 9 and 10 Partially shown, in this example, the elements of package substrate 902 associated with transformer 904 and coupling transformer 904 to semiconductor dies 910 and 920 are formed in three metal layers. That is, winding 906 and contact pads 916, 918, 930, and 932 are formed in top metal layer 1000, and winding 908 is formed in metal layer 1004. However, trace 938 (which couples contact pad 918-2 to winding 906) and trace 946 (which couples contact pad 932-2 to winding 908) are formed in metal layer 1002 located between metal layers 1000 and 1004.

[0099] Forming the traces (e.g., 938 and 946) in a third metal layer rather than the two metal layers in which contact pads 916, 918, 930, and 932 and windings 906 and 908 are formed allows for greater control over creating critical spacing (e.g., distances S1 and S2) between windings 906 and 908 to meet desired voltage isolation ratings. As shown, S1 is the distance between metal layers 1002 and 1004, and S2 is the distance between metal layers 1000 and 1002. S1 and S2 can be, for example, two of the many spacings present within the packaged IC 900 of the packaged IC, which are controlled to achieve desired isolation ratings or performance.

[0100] Figure 11 An isometric view schematically showing another example packaged IC 1100 with an integrated isolation circuit 1104. As shown, the packaged IC 1100 includes a package substrate 1102 and two semiconductor dies 1110 and 1120 mounted to a surface (not shown) of the package substrate 1102. The package substrate 1102 includes the isolation circuit 1104 integrated therein. The packaged IC 1100 is in some respects similar to the packaged IC 300, as indicated by Figure 3 and 11 the common reference numerals between. However, the design of the semiconductor dies 1110 and 1120 is different from that of the semiconductor dies 310 and 320, and the packaged IC 1100 is different from the packaged IC 300. The design of the isolation circuit 1104 and its coupling to the semiconductor dies 1110 and 1120 is different from that of the isolation circuit 304 and its coupling to the semiconductor dies 310 and 320, and the packaged IC 1100 is also different from the packaged IC 300.

[0101] That is, in the example, Figure 2A -D shown and referenced Figure 2A -D described semiconductor dies 210 and 220 represent semiconductor dies 1110 and 1120. Thus, the semiconductor die 1110 is a primary side circuit that includes a driver circuit, a primary side bridge circuit, and a digital communicator. The semiconductor die 1120 is a secondary side circuit that includes a secondary side bridge circuit, a driver / output voltage regulation circuit, and a digital communicator.

[0102] In addition, compared to the isolation circuit 304 of the packaged IC 300, the isolation circuit 1104 of the packaged IC 1100 not only includes the transformer 304 as an isolation circuit, but also includes two additional isolation circuits, namely capacitors 1112 and 1122. Each of the capacitors 1112 and 1122 has two circuit elements (in this case, two plates) formed in the metal layers 322 - 328. That is, the capacitor 1112 includes a plate 1114 (e.g., a top plate) and a plate 1116 (e.g., a bottom plate), and the plate 1116 is electrically isolated from the plate 1114 by the isolation material 314. The capacitor 1122 includes a plate 1124 (e.g., a top plate) and a plate 1126 (e.g., a bottom plate), and the plate 1126 is electrically isolated from the plate 1124 by the isolation material 314.

[0103] As shown, to reduce the height of the packaged IC 1100, the top plates 1114 and 1124 are formed in the same metal layer 328 as the winding 306. Additionally, the bottom plates 1116 and 1126 are formed in the same metal layer 324 as the winding 308. In at least one example, some or all of the capacitors 1112 and / or 1122 may be formed in one or more metal layers different from the converter 304. The advantage of using techniques such as using a deployable lead frame technique to embed the isolation capacitors 1112 and 1122 in the package substrate 1102 of the packaged IC 1100 is that the capacitors 1112 and 1122 can float relative to the (external) contact pads 348 connected to an external circuit such as a PCB. Compared to other packaged IC solutions, such as where capacitor structures are mounted on the package substrate 1102 together with an IC that requires additional bond wires to external contact pins or pads, the packaged IC 1100 provides greater flexibility in the electrical coupling of the isolation circuit 1104. Additionally, the ability to electrically connect the capacitors 1112 and 1122 without using additional bond wires allows the parasitic capacitance to be reduced. The reduced parasitic capacitance can improve the signal-to-noise ratio and power consumption on the capacitance channel.

[0104] Furthermore, in this example, the capacitors 1112 and 1122 are vertical plate capacitors where the plates are formed parallel to the top and bottom surfaces of the package substrate 1102. However, in another example, one or both of the capacitors 1112 and 1122 may be lateral plate capacitors where each plate is formed in one or more of the layers 322 - 328 and parallel to the side of the package substrate 1102. In other examples, each circuit element of the capacitors 1112 and 1122 may have multiple connected plates, such as finger or edge capacitors.

[0105] Moreover, compared to the package substrate 302, the package substrate 1102 includes two additional contact pads 318 - 3 and 318 - 4 in the first plurality of contact pads for electrically coupling the circuits on the semiconductor die 1110 to the isolation circuit 1104. The package substrate 1102 also includes two additional contact pads 332 - 3 and 332 - 4 in the second plurality of contact pads for electrically coupling the circuits on the semiconductor die 1120 to the isolation circuit 1104. As shown, the contact pad 318 - 3 is coupled to the plate 1114 of the capacitor 1112. The contact pad 318 - 4 is coupled to the plate 1124 of the capacitor 1122. The contact pad 332 - 3 is coupled to the plate 1116 of the capacitor 1112. The contact pad 332 - 4 is coupled to the plate 1126 of the capacitor 1122.

[0106] Thus, when semiconductor die 1110 is flip-chip mounted to package substrate 302, contact pads 336 (two of four are marked) on the surface of semiconductor die 1110 are mechanically coupled to contact pads 318-3 and 318-4, for example using solder balls (not shown) attachable to contact pads 336. The coupling between contact pads 336 and 318-3, 318-4 allows circuits on semiconductor die 1110, such as a digital communicator, to be coupled to the top plates of capacitors 1112 and 1122 to facilitate two-way data communication.

[0107] When semiconductor die 1120 is flip-chip mounted to package substrate 302, contact pads 344 (two of four are marked) on the surface of semiconductor die 1120 are mechanically coupled to contact pads 332-3 and 332-4, for example using solder balls (not shown) attachable to contact pads 344. The coupling between contact pads 344 and 332-3, 332-4 allows circuits on semiconductor die 1120, such as a digital communicator, to be coupled to the bottom plates of capacitors 1112 and 1122 to facilitate two-way data communication.

[0108] As with packaged IC 300, elements associated with isolation circuit 1104 and coupling isolation circuit 1104 to semiconductor dies 1110 and 1120 in package substrate 1102 may be formed in two metal layers. That is, windings 306, plates 1114 and 1124, electrical traces 346, and contact pads 316, 318, 330, and 332 are formed in top metal layer 328. Additionally, windings 308, plates 1116 and 1126, and electrical traces 328 are formed in metal layer 324.

[0109] Figure 12 is a flowchart depicting an example method 1200 for manufacturing a package substrate / circuit support structure with an integrated isolation circuit, which includes blocks 1202-1210, such as package substrates 302, 602, 902, or 1102. However, as a specific example, method 1200 is described in the context of manufacturing Figure 3 package substrate 302. Blocks 1202-1210 of method 1200 need not be performed in the order shown in the flowchart. Additionally, method 1200 may be implemented using wireframe technology and may be performed as part of a process for manufacturing a packaged IC, such as packaged IC 300, 600, 900, or 1100.

[0110] The frame 1202 depicts metal components that form a package substrate in multiple metal layers, such as multiple copper layers. These metal components include first, second, and third pluralities of contact pads and at least first and second circuit elements that isolate circuits, such as windings of a transformer, plates of a capacitor, or both. In at least one example, the first plurality of contact pads are used to electrically and mechanically couple to a first IC mounted to the package substrate. The second plurality of contact pads are used to electrically and mechanically couple to a second IC mounted to the package substrate. The third plurality of (external) contact pads are used to mount and couple the package substrate to an external structure, such as a PCB.

[0111] More specifically, when manufacturing the package substrate 302, four metal layers 322-328 are used. According to the frame 1202, windings 306 and 308 of an isolation circuit (transformer) 304, a first plurality of contact pads 316 and 318, a second plurality of contact pads 330 and 332, and a third plurality of contact pads 348 are formed in two of the four metal layers 324 and 328.

[0112] The frame 1204 depicts coupling a contact pad in the first plurality of contact pads to a first circuit element of the isolation circuit. Thus, when manufacturing the package substrate 302, the contact pad 318 is coupled to the winding 306. That is, the contact pad 318-1 is formed as one voltage input terminal of the winding 306. In addition, a trace 338 is formed in the metal layer 324, and two vias 500 are formed in the metal layer 326 to couple the contact pad 318-2 to another voltage input terminal 340 of the winding 306.

[0113] The frame 1206 depicts coupling a contact pad in the second plurality of contact pads to a second circuit element of the isolation circuit. Thus, when manufacturing the package substrate 302, the contact pad 332 is coupled to the winding 308. That is, a via 500 is formed in the metal layer 326 to couple the contact pad 332-1 to one voltage output terminal 352 of the winding 308. In addition, a trace 346 is formed in the metal layer 324, and vias 500 are formed in the metal layer 326 to couple the contact pad 332-2 to another voltage output terminal 354 of the winding 308.

[0114] The frame 1208 depicts coupling some of the first plurality of contact pads and some of the second plurality of contact pads to the third plurality of contact pads. Thus, when manufacturing the package substrate 302, vias 350 are formed in the metal layers 325 and 326 to couple the contact pad 316 in the first plurality of contact pads and the contact pad 330 in the second plurality of contact pads to the third plurality of contact pads 348.

[0115] The enclosure 1210 depicts enclosing a metal layer in an isolation material such that the first and second circuit elements are electrically isolated from each other, with a first plurality of contact pads and a second plurality of contact pads exposed at a first surface defined by the isolation material, and a third plurality of contact pads exposed at a second opposite surface defined by the isolation material. Thus, in manufacturing the package substrate 302, the metal layers 322 - 328 are enclosed in an isolation material 314, such as a molding compound like ABF. Once enclosed, the isolation material 314 defines a (top / mounting) surface 400 and a (bottom / opposite) surface substantially parallel to the mounting surface 400. The metal layer 328 or portions thereof are exposed at the mounting surface 400, which in this example includes contact pads 316, 318, 330, 332, winding 306, and electrical traces 346. The metal layer 322 or portions thereof are exposed at the opposite surface, which in this example includes contact pad 348. Thus, the semiconductor die 310 and the semiconductor die 320 can be mounted to the package substrate 302, and overmolding 312 can be added to complete the packaged IC 300.

[0116] As Figure 2A and Figure 11 shown, in some examples, the isolation circuitry of a packaged IC can include a pair of capacitors (e.g., capacitors 208, 1112, and 1122) to provide electrical isolation for DC current / voltage while allowing differential AC signals (e.g., data signals) to pass. In some other examples, as Figure 2B , 2C shown in 2D and subsequent figures, the isolation circuitry of a packaged IC can include a transformer (e.g., transformer 228) to provide electrical isolation while allowing differential AC data signals to pass.

[0117] Using a transformer for electrical isolation and differential AC signal transmission can provide various advantages over capacitors. One advantage is improved common - mode transient immunity. Figure 13A FIG. 16 - D is a schematic diagram of the circuit models of a capacitor and a transformer, showing the improvement in common - mode transient immunity provided by the transformer over the capacitor. Specifically, Figure 13A FIGS. 16 - B schematically show the circuit model 1300 of a capacitive isolation circuit 208 (or capacitive isolation channel) coupled to a differential transmitter and a differential receiver according to some examples, and an equivalent circuit model representing the common - mode excitation transfer function applied across the isolation barrier for a common - mode transient at the transmitter or receiver 1320. For simplicity, the capacitive isolation circuit 208 is terminated with a resistive impedance that is different on both sides of the capacitive isolation circuit 208, typically lower on the transmitter (TX) side and higher on the receiver (RX) side. For example, the circuit model 1300 can represent the capacitive isolation structure provided by Figure 11 the capacitors 1112 and 1122.

[0118] Here, the differential TX is modeled by resistors R1 and R3, where R1 is coupled between terminal 1301 and ground 1302, and R3 is coupled between ground 1302 and terminal 1303. The differential RX is modeled by resistors R2 and R4, where R2 is coupled between terminal 1304 and ground 1305, and R4 is coupled between ground 1305 and terminal 1306. In at least one example, the resistance or impedance of R1 and R3 is higher than that of R2 and R4. The capacitive isolation circuit 208 is modeled by capacitors C1 and C2, where capacitor C1 is coupled to nodes 1301 and 1304, and capacitor C2 is coupled to nodes 1303 and 1306.

[0119] The differential signal is input from the transmitter to terminals 1301 and 1303, where the differential signal is differential with respect to the ground on terminal 1302. The output differential signal is received at terminals 1304 and 1306, and this output differential signal is differential with respect to ground 1305. Here, the differential signal current 1307 from the transmitter flows from terminal 1301 to terminal 1304 via capacitor C1, and then flows back to terminal 1303 via resistors R2 and R4 and capacitor C2.

[0120] Figure 13C -D schematically shows a circuit model 1330 of an inductive isolation circuit 228 coupled to a differential transmitter and a differential receiver according to some examples, and an equivalent circuit model representing a common-mode excitation transfer function applied across an isolation barrier for a common-mode transient at the transmitter or receiver 1340. The inductive isolation circuit 228 is modeled by a primary winding (e.g., winding 306) including inductor / coil portions L1 and L2 and a secondary winding (e.g., winding 308) including inductor / coil portions L3 and L4. Inductor L1 and resistor R1 are coupled in parallel between terminal 1331 and a grounded center tap 1332. Inductor L2 and resistor R2 are coupled in parallel between the center tap 1332 and terminal 1333. Inductor L3 and resistor R3 are coupled in parallel between terminal 1334 and center tap 1335. Inductor L4 and resistor R4 are coupled in parallel between center tap 1335 and terminal 1336.

[0121] Differential signals are input from a transmitter to terminals 1331 and 1333, where the differential signals are differential with respect to the center tap 1332. The output differential signals are received at terminals 1334 and 1336, and this output differential signal is differential with respect to the center tap 1335. Here, the current 1338 from the transmitter flows from terminal 1331 to terminal 1334 via inductors L1 and L2. The electromagnetic fields generated by the currents passing through inductors L1 and L2 are coupled to inductors L3 and L4 by magnetic coupling. The corresponding current 1339 flows through inductors L3 and L4 to generate a voltage differential with respect to ground on terminal 1335 at terminals 1334 and 1336.

[0122] Common mode rejection occurs when the voltages on the isolated grounds (nodes 1302 and 1305 of circuit model 1300 and nodes 1332 and 1335 of circuit model 1330) move relative to each other. When compared to ground 1302, the input differential signals on taps 1301 and 1303 cause the output differential signals on taps 1304 and 1306 to move relative to ground 1305 due to common mode rejection or excitation. Such common mode rejection can occur at low frequencies (e.g., 100 MHz or less). Common mode rejection may lead to inefficiencies in DC-DC converters. For example, an enable signal can be transmitted by a bridge driver in data circuit 216 to a bridge receiver in data circuit 226 through a capacitive isolation circuit 208 to turn on or off one or more of the N secondary side bridges 222. The voltage of this enable signal may move up or down at the capacitive isolation circuit 208 due to common mode rejection. This shift of the enable signal may cause noise to be generated at the switching nodes of one or more of the N secondary side bridges 222, which may in turn reduce the efficiency of the DC-DC converter formed by the N primary side bridges 214, the N converters 206, and the N secondary side bridges 222. In at least one example, the inductive isolation circuit 228 reduces common mode rejection and thus improves the efficiency of the DC-DC converter.

[0123] Here, the AC source 1307 indicates interference in signal transmission caused, for example, by common mode rejection or excitation. After exciting the AC source 1307 of the circuit model 1300, the voltages on nodes 1301, 1302, 1303, 1304, 1305, and 1306 move by common mode. Similarly, after exciting the AC source 1307 of the circuit model 1330, the voltages on nodes 1331, 1332, 1333, 1334, 1335, and 1336 move by common mode. This means that the circuit models 1300 and 1330 can be redrawn as equivalent circuit models 1320 and 1340 respectively, assuming that the two half-circuits of the differential channel are the same.

[0124] In at least one example, once the impedance of capacitor C3 is small enough, the equivalent circuit model 1320 representing the capacitive isolation structure has a resistor divider between resistors R5 and R6. In at least one example, the equivalent circuit model 1340 has capacitor C3 in series, which is the parasitic capacitance of the converter across the inductive isolation circuit 228. In the inductive isolation circuit 228, the resistors R5 and R6 of the equivalent circuit model 1320 are replaced with resistor R5 in parallel with inductor L5 and resistor R6 in parallel with inductor L6. The interference provided by the AC source 1307 across resistor R6 (denoted as A1) represents the AC common-mode transient between nodes 1304 and 1306 (or between nodes 1301 and 1303). The magnitude of A1 can be based on the voltage division ratio of the resistor divider between the impedance of R6 and the sum of the impedances of R5, C3, and R6, which can be constant with respect to the signal frequency. For example, this is the case when R5 has a much smaller resistance than R6 and C3 has a low impedance in the considered frequency range.

[0125] On the other hand, the equivalent circuit model 1340 representing the converter includes a resistor divider between the first parallel circuit of resistor R5 and inductor L5 and C3 in series with the second parallel circuit of resistor R6 and inductor L6. The interference provided by the AC source 1307 across resistor R6 and inductor L6 (denoted as A2) represents the common-mode transient between terminals 1334 and 1336 (or between terminals 1331 and 1333). The magnitude of A2 can be based on the voltage division ratio between the combined impedance of R6 and L6 and the sum of the combined impedance of R5 and L5 and the combined impedance of R6 and L6 in series with C3. When R5 has a much smaller resistance than R6 and C3 has a low impedance in the considered frequency range, the parallel connection of L6 with R6 reduces the magnitude of A2, which can become smaller than A1, thus improving the common-mode transient immunity.

[0126] Figure 13E is a curve 1350 showing the variation of the magnitude of A1 (Figure 1351) and the magnitude of A2 (Figure 1352) with frequency at a differential receiver coupled to the capacitive isolation circuit 208 and the inductive isolation circuit 228 according to at least one example. At lower frequencies, inductors L5 and L6 act as short circuits, so the impedance of the inductors becomes much smaller than the impedance of the resistors. Therefore, at lower frequencies, the magnitude of A2 of the circuit model 1340 is lower, as shown in Figure 1352. At higher operating frequencies, the gain A2 increases, which also increases the interference to terminals 1334 and 1336. In contrast, the gain A1 of the equivalent circuit model 1320 is relatively flat and higher at lower frequencies because it does not have inductors, as shown in Figure 1351. In at least one example, the inductive isolation circuit 228 has better common-mode rejection at lower operating frequencies (e.g., 100 MHz or lower) compared to the capacitive isolation circuit 208 and thus has less interference.

[0127] In addition to the improved common-mode transient immunity, the transformer can also provide additional advantages for electrical isolation that are superior to those of capacitors. Specifically, at least compared to the case where capacitors are implemented in the metallization layer on the semiconductor die, due to the relatively large thickness of the package substrate, the vertical spacing between the transformer and the semiconductor die can be increased, which can reduce the parasitic capacitance. Eddy currents caused by the magnetization of the semiconductor die by the transformer can also be reduced. Secondly, matching capacitors is challenging because, in order to match capacitors, the physical size of the capacitors needs to match, while transformer matching is achieved by moving the center tap of the transformer. Therefore, the transformer can provide better matching than capacitors.

[0128] Figure 14 FIG. 1400 is a schematic diagram of a data portion of a packaged IC including data circuits 216 and 226 and their corresponding inductive isolation (e.g., transformer) circuits 228a and 228b according to at least one example. Here, two differential signal paths are coupled to the inductive isolation circuits 228a and 228b to allow bidirectional data communication. In at least one example, data circuit 216 includes transmitter 1417a and receiver 1417b, where transmitter 1417a includes a resonant LC oscillator having an activation mechanism (not shown), and receiver 1417b includes a radio frequency detector having common-mode (CM) rejection. In at least one example, data circuit 226 includes receiver 1426a and transmitter 1426b, where transmitter 1426b includes a resonant LC oscillator having an activation mechanism (not shown), and receiver 1426a includes a radio frequency detector having common-mode (CM) rejection. In at least one example, receiver 1426a receives the differential signal transmitted by transmitter 1417a through inductive isolation circuit 228a. In at least one example, receiver 1417b receives the differential signal transmitted by transmitter 1426b through inductive isolation circuit 228b.

[0129] In some examples, as Figures 15 - 23 shown, inductive isolation circuit 228a includes a primary winding having a first coil portion L1a and a second coil portion L2a and a secondary winding having a third coil portion L3a and a fourth coil portion L4a. Here, "primary" and "secondary" mean two different isolation domains (e.g., two power domains) that are electrically isolated by the isolation circuit. Power / data can flow from the primary side to the secondary side and vice versa. In some examples, all primary windings are coupled to a first power domain, and all secondary windings are coupled to a second power domain. In some examples, different primary windings can be coupled to different first power domains, and different secondary windings can be coupled to different second power domains.

[0130] In Figures 15 - 19In it, L1a and L2a are coupled in series in a figure-eight configuration. In Figures 20 - 23 In it, L1a and L2a are coupled in series in another configuration. Each of the first coil portion L1a and the second coil portion L2a extends from a center tap 1332a having a node shape (e.g., oval, circular, polygonal, etc.), and terminates at a first primary-side terminal 1331a and a second primary-side terminal 1333a, respectively, which are located at the respective centers of the first coil portion L1a and the second coil portion L2a. The center tap 1332a is a tap located between the first coil portion L1a and the second coil portion L2a, and is coupled to a first local ground associated with the data circuit 216. By placing the center tap 1332a at the center of the figure-eight configuration, symmetry can be achieved between the two coils of the first coil portion L1a. The loss of symmetry caused by the offset of the center tap 1332a with respect to the coil portions of the first coil portion L1a can reduce the signal-to-noise ratio. In at least one example, the first primary terminal 1331a is coupled to the first output terminal of the transmitter 1417a, and the second primary terminal 1333a is coupled to the second output terminal of the transmitter 1417a. Here, the capacitor C DIFF is a differential tuning capacitor between the first and second output terminals of the transmitter 1417a, and the capacitor C TX is a common-mode tuning capacitor between the first primary-side terminal 1331a and the first local ground (coupled to the center tap 1332a) and between the second primary-side terminal 1333a and the first local ground. Both C DIFF and C TX can be implemented using lumped-parameter circuit elements or by utilizing parasitics or a combination of the two.

[0131] In some examples, as Figures 15 - 23 shown, the inductive isolation circuit 228a includes a secondary winding having a first coil portion L3a and a second coil portion L4a. In Figures 15 - 19 In it, L3a and L4a are coupled in series in a figure-eight configuration. In Figures 20 - 23In it, L3a and L4a are coupled in series in another configuration. Each of the first coil portion L3a and the second coil portion L4a extends from a center tap 1335a having a node shape and terminates at a first secondary side terminal 1334a and a second secondary side terminal 1336a respectively, which are located at the respective centers of the first coil portion L3a and the second coil portion L4a. The secondary winding is on a different layer of the substrate from the primary winding and can at least partially overlap with the primary winding. The center tap 1335a is coupled between the first coil portion L3a and the second coil portion L4a and is also coupled to a second local ground associated with the data circuit 226. In at least one example, the first secondary side terminal 1334a is coupled to a first input terminal of the receiver 1426a, while the second secondary side terminal 1336a is coupled to a second input terminal of the receiver 1426a. Here, the capacitor C DIFF is a differential tuning capacitor between the first and second input terminals of the receiver 1426a, and the capacitor C RX is a common-mode tuning capacitor between the first secondary side terminal 1334a and the second local ground (coupled to the center tap 1335a) and between the second secondary side terminal 1336a and the first local ground. C DIFF and C TX Both can be implemented using lumped parameter circuit elements or by using parasitic elements or a combination of both.

[0132] In some examples, as Figures 15 - 23 shown, the inductive isolation circuit 228b includes a secondary winding having a first coil portion L1b and a second coil portion L2b, and the first and second coil portions can Figures 15 - 19 be coupled in series in the figure-eight configuration shown in Figures 20 - 23 or in another configuration shown. The secondary winding of the inductive isolation circuit 228b and the secondary winding of the inductive isolation circuit 228a can be coupled to the same second power domain or different power domains. Each of the first coil portion L1b and the second coil portion L2b extends from a center tap 1332b having a node shape and terminates at a first secondary side terminal 1331b and a second secondary side terminal 1333b respectively, which are located at the respective centers of the first coil portion L1b and the second coil portion L2b. The center tap 1332b is coupled between the first coil portion L1b and the second coil portion L2b and is also coupled to a first local ground associated with the data circuit 226. In at least one example, the first secondary side terminal 1331b is coupled to a first input terminal of the transmitter 1426b, while the second secondary side terminal 1333b is coupled to a second input terminal of the transmitter 1426b. Here, the capacitor C DIFF is a differential tuning capacitor between the first and second input terminals of the receiver 1417b, and the capacitor C RXis a common-mode tuning capacitor between the first primary-side terminal 1334b and the first local ground (coupled to the center tap 1335b), and between the second primary-side terminal 1336b and the first local ground of the data circuit 216. C DIFF and C RX Both can be implemented using lumped parameter circuit elements or by leveraging parasitics or a combination of both.

[0133] In some examples, such as Figures 15 - 23 shown, the inductive isolation circuit 228b includes a primary-side winding having a first coil portion L3b and a second coil portion L4b, and the first and second coil portions can be Figures 15 - 19 configured in the number-8 configuration as shown in Figures 20 - 23 or in another configuration as shown in DIFF is a common-mode tuning capacitor between the first and second input terminals of the transmitter 1426b, and the capacitor C TX is a common-mode tuning capacitor between the first secondary-side terminal 1331b and the second local ground (coupled to the center tap 1332b), and between the second primary-side terminal 1333b and the local ground of the data circuit 226. C DIFF and C TX Both can be implemented using lumped parameter circuit elements or by leveraging parasitics or a combination of both.

[0134] In at least one example, such as Figures 20 - 23 shown, the inductive isolation circuit can include an elongated metal interconnect that extends laterally from the center tap outside the footprint of the inductive isolation circuit, and together forms the first and second coil portions of the primary or secondary winding coupled to the metal interconnect such that the metal interconnect is coupled to the primary / secondary winding at at least two locations. The metal interconnect can include matching / balancing branch portions (e.g., as shown in Figures 20 - 22 ), or in the form of a wire (e.g., as shown in Figure 23As shown. For example, the inductive isolation circuit 228a may include a first metal interconnect coupled between the center tap 1332a and the first coil portion L1a and between the center tap 1332a and the second coil portion L2a. The inductive isolation circuit 228a may further include a second metal interconnect coupled between the center tap 1335a and the first coil portion L3a and between the center tap 1335a and the second coil portion L4a. Additionally, the inductive isolation circuit 228b may include a third metal interconnect coupled between the center tap 1332b and the first coil portion L1b and between the center tap 1332b and the second coil portion L2b. The inductive isolation circuit 228b may further include a fourth metal interconnect coupled between the center tap 1335b and the first coil portion L3b and between the center tap 1335b and the second coil portion L4b. As explained below, such an arrangement can improve the matching of differential signals. Additionally, in such an arrangement, the coils and metal interconnects can be implemented in two metal layers. The reduction in the number of metal layers enables the use of thicker metal layers while increasing the vertical spacing between the metal layers, which can reduce the parasitic capacitance and crosstalk between the metal layers.

[0135] Figure 15 A top view of a packaged IC 1500 having separate power and data semiconductor dies, three converters, and a dedicated semiconductor die 242 is schematically shown in accordance with at least one example. Figure 16 An isometric top view of a packaged IC 1500 having a data converter under the data semiconductor die is schematically shown in accordance with at least one example. Figure 17 An isometric bottom view of a packaged IC 1500 having the three converters is schematically shown in accordance with at least one example.

[0136] The packaged IC 1500 may be Figure 2D an example of a packaged IC. The packaged IC 1500 may also be Figure 2B an example of -C. Here, the N converters 206 include a first primary winding 1503 in a first metal layer and a first secondary winding 1504 in a second metal layer, where the second metal layer is below the first metal layer (e.g., the topmost metal layer) of the package substrate 202. In this example, the first primary winding 1503 and the first secondary winding 1504 are concentric windings that are substantially overlapped with each other within the package substrate 202 to obtain higher inductive coupling.

[0137] As referenced Figure 2DAs described, an isolation circuit 204 including N transformers 206 (e.g., a first transformer) is embedded or integrated in a package substrate 202. In at least one example, the package substrate 202 includes three metal layers, which provides flexibility in fabricating concentric windings (a first primary winding 1503 and a first secondary winding 1504) in two different layers of the first transformer 206 to achieve a higher magnetic coupling between the primary and secondary coils of the first transformer 206. The package substrate also allows metal pillars to be integrated between the windings and flip-chip semiconductor dies (e.g., a first semiconductor die 210 and a second semiconductor die 220) above them. Although the semiconductor dies (e.g., a first semiconductor die 210 and a second semiconductor die 220) can be connected to the first transformer 206 below them via wire bonding in at least one example, such wire bonding may introduce additional inductance that can be coupled to the first transformer 206 and cause interference in the isolation function of the first transformer 206.

[0138] In at least one example, the first transformer 206 includes a first primary side terminal 1505a, a second primary side terminal 1505b, a first secondary side terminal 1506a, and a second secondary side terminal 1506b (shown in Figure 17 ). The first primary side terminal 1505a and the second primary side terminal 1505b are the two ends of the first primary winding 1503. The first secondary side terminal 1506a and the second secondary side terminal 1506b are the two ends of the first secondary winding 1504. In at least one example, the first primary winding 1503 is on a first metal layer (e.g., a top metal layer 328), and the second primary winding 1504 is on a second metal layer (e.g., a metal layer 322) below the first metal layer.

[0139] In at least one example, the first semiconductor die 210 is coupled to the first primary side terminal 1505a and the second primary side terminal 1505b. Here, the first primary side terminal 1505a and the second primary side terminal 1505b are below the first semiconductor die 210 and on the topmost layer of the package substrate 202, and the topmost layer allows the first primary side terminal 1505a and the second primary side terminal 1505b to be connected to the die above them via metal pillars. Thus, the routing distance is reduced and the use of intermediate interconnects between the first primary side terminal 1505a and the first semiconductor die 210 and between the second primary side terminal 1505b and the first semiconductor die 210 can be avoided. The metal pillars (e.g., copper pillars or studs) extend vertically (in the z direction) directly from the package substrate 202 to the first semiconductor die 210 or are coupled to solder balls of the first semiconductor die 210.

[0140] In at least one example, the second semiconductor die 220 is coupled to the first secondary-side terminal 1506a and the second secondary-side terminal 1506b. In at least one example, as Figure 15 shown, the second semiconductor die 220 does not overlap with the converter 206. In at least one example, the semiconductor die 220 may also overlap with the converter 206. In at least one example, the first secondary-side terminal 1506a and the second secondary-side terminal 1506b are in a metal layer below the topmost metal layer of the package substrate 202, and are thus connected to the second semiconductor die 220 on the package substrate 202 using intermediate metal interconnects and vias or posts.

[0141] In at least one example, when the first semiconductor die 210 is not directly above the first primary-side terminal 1505a and the second primary-side terminal 1505b, a first metal interconnect 1512 (similar to interconnect 361) is coupled between the first primary-side terminal 1505a of the first primary winding 1503 and the first semiconductor die 210. In at least one example, a third metal interconnect 1513 (similar to interconnect 363) is coupled between the second primary-side terminal 1505b of the first primary winding 1503 and the first semiconductor die 210. In at least one example, a second metal interconnect 362 is coupled between the first secondary-side terminal 1506a of the first secondary winding 1504 and the second semiconductor die 220. In at least one example, a fourth metal interconnect 364 is coupled between the second secondary-side terminal 1506b of the first secondary winding 1504 and the second semiconductor die 220.

[0142] The first primary winding 1503 and the first secondary winding 1504 are electrically isolated from each other using an isolation material (e.g., isolation material 314 or isolation material 1014) of the package substrate 202, and the isolation material forms an electrical isolation barrier between two different power domains of the first semiconductor die 210 and the second semiconductor die 220. In at least one example, the first semiconductor die 210 is powered using a voltage supplier and a ground connection associated with the first power domain. In at least one example, the second semiconductor die 220 is powered using another voltage supplier and a ground connection associated with the second power domain. In at least one example, an isolation material such as molding compound has a thickness and is of a type that provides an electrical isolation barrier that, in one example, can withstand 5 kilovolts (kV) root mean square (RMS) for 60 seconds, and in another example, can withstand 2.5 kV RMS for 60 seconds. Different isolation ratings can be achieved at least in part based on the type and thickness of the isolation material used.

[0143] Using a molding compound instead of a laminate as the isolation material allows for a smaller critical spacing between the first primary winding 1503 and the first secondary winding 1504 while maintaining the same voltage insulation and improving the thermal performance of the isolation circuit 204. In at least one example, the lead frame technology of the package substrate 202 allows for thicker copper traces (e.g., 30 - 35 microns or thicker, such as 1%, 5%, or 10% thicker) and smaller metal width and spacing (e.g., 30x30 microns 2 or less, such as 1%, 5%, or 10% smaller). This can increase the efficiency of the converter 206 by allowing an increase in the quality factor of the converter 206. Additionally, integrating the converter 206 into the package substrate 202 results in a smaller package IC size (e.g., 5.0x3.0x0.8 mm 3 or less, such as 1%, 5%, or 10% smaller).

[0144] In at least one example, the isolation circuit 204 includes an inductive isolation circuit 228 having a set of converters, the set of converters including a second converter 228a including a second primary winding 1507 and a second secondary winding 1508 both having a figure 8 configuration. In at least one example, the second primary winding 1507 and the second secondary winding 1508 are concentric windings that are substantially overlapping with each other within the package substrate 202 to obtain a higher inductive coupling. In at least one example, the second secondary winding 1508 is below the second primary winding 1507 and occupies the same footprint as the second primary winding 1507. The second primary winding 1507 and the second secondary winding 1508 provide data isolation between the data transmitter 1417a and the data receiver 1426a.

[0145] In at least one example, the second transformer 228a of the inductive isolation circuit 228 includes a first primary side terminal 1331a, a second primary side terminal 1333a, a first secondary side terminal 1334a, and a second secondary side terminal 1336a. In at least one example, the second primary winding 1507 is coupled between the first primary side terminal 1331a and the second primary side terminal 1333a, and the second secondary winding 1508 is coupled between the first secondary side terminal 1334a and the second secondary side terminal 1336a. In at least one example, metal posts extend vertically from the first primary side terminal 1331a, the center tap 1332a, and the second primary side terminal 1333a to the receiver 1426a above it to reduce the parasitic capacitance and inductance caused by wire bonding. As shown, at least a portion of the windings of the second transformer 228a overlaps with the data circuit 216 such that the metal posts can be connected to the receiver 1426a. In this example, the second transformer 228a is external to the footprint of the first transformer 206 (or otherwise not surrounded by the first transformer 206), allowing the metal interconnects coupled between the transformer 228a and the data circuit 216 to also be outside the first transformer 206, which can reduce the number of metal layers used to implement the transformers 206 and 228a and the metal interconnects.

[0146] Positioning the transformers 228a and 228b outside the footprint of the transformer 206 can reduce crosstalk between the signals of the three transformers. In an example where the transformer 206 provides power transfer, the transformer 206 can generate a common-mode magnetic field that passes through the transformers 228a and 228b during power transfer. Although the transformers 228a and 228b operate using two figure-8 coils that have differential fields and can be robust against common-mode variations of the magnetic field, such common-mode variations may still perturb the TX and RX operating points. By moving the transformers 228a and 228b outside the footprint of the transformer 206, the common-mode magnetic fields received by the transformers 228a and 228b can become much weaker, which can further reduce the perturbation of the common-mode variations on the TX and RX operating points. Such an arrangement can also further separate the metal layers of the individual transformer 206 from the transformers 228a and 228b, which can reduce the parasitic capacitance of the transformer 206 and increase its quality factor.

[0147] In at least one example, the packaged IC 1500 includes a data circuit 216 (e.g., a third semiconductor die) and a data circuit 226 (e.g., a fourth semiconductor die). The data circuit 216 is coupled to the first primary side terminal 1331a and the second primary side terminal 1333a. The data circuit 226 is coupled to the first secondary side terminal 1334a and the second secondary side terminal 1336a. Data can be transferred from the data circuit 216 to the data circuit 226 via the second transformer 228a.

[0148] Reference Figure 16 and 17 For a packaged substrate 202 including three metal layers, a first primary side terminal 1331a, a second primary side terminal 1333a, a first center tap 1332a, and a second primary winding 1507 of a second transformer 228a can be formed in a first (e.g., top) metal layer and coupled to a data circuit 226 via metal posts. A second secondary winding 1508 of the second transformer 228a can be formed in a second (e.g., middle) metal layer. A first secondary side terminal 1334a, a second secondary side terminal 1336a, and a second center tap 1335a can be formed in a third (e.g., bottom) metal layer and coupled to the second secondary winding 1508 through metal vias. The third metal layer further includes metal interconnects 1702a, 1704a, and 1706a respectively coupled between the data circuit 216 and the first secondary side terminal 1334a, the second center tap 1335a, and the second secondary side terminal 1336a. In at least one example, a metal interconnect 1708 is coupled between the second semiconductor die 210 and the first secondary side terminal 1506a.

[0149] In addition, a first primary winding 1503, a first primary side terminal 1505a, and a second primary side terminal 1505b of the transformer 206 are in the first metal layer. In addition, a first secondary winding 1504, a first secondary side terminal 1506a, and a second secondary side terminal 1506b of the transformer 206 are in the second metal layer. The second secondary side terminal 1506b is coupled to the second semiconductor die 210 via a metal post. In at least one example, the third metal layer further includes a metal interconnect 1708 coupled between the first secondary side terminal 1506a and the second semiconductor die 210.

[0150] In at least one example, the transformer 228 further includes a third transformer 228b, which includes a third secondary winding 1510 and a third primary winding 1511. In at least one example, the third secondary winding 1510 and the third primary winding 1511 are concentric windings that are substantially overlapped with each other within the packaged substrate 202 to obtain higher inductive coupling. In at least one example, the third secondary winding 1510 is coupled between a first secondary side terminal 1331b and a second secondary side terminal 1333b. In at least one example, the third primary winding 1511 is coupled between a first primary side terminal 1334b and a second primary side terminal 1336b. The third metal layer further includes metal interconnects 1702b, 1704b, and 1706b respectively coupled between the data circuit 226 and the second primary side terminal 1336b, the second center tap 1335b, and the first primary side terminal 1334b.

[0151] In at least one example, metal posts extend directly from the first primary side terminal 1331a, the center tap 1332a, and the second primary side terminal 1333a to the transmitter 1417a above it to reduce the parasitic capacitance and inductance caused by wire bonding. As shown, at least a portion of the coil of the third converter 228a overlaps with the data circuit 216 such that the metal posts can be connected to the transmitter 1417a. In at least one example, metal posts extend directly from the first secondary side terminal 1331b, the center tap 1332b, and the second secondary side terminal 1333b to the transmitter 1426b above it to reduce the parasitic capacitance and inductance caused by wire bonding. As shown, at least a portion of the coil of the third converter 228b overlaps with the data circuit 226 such that the metal posts can be connected to the transmitter 1426b.

[0152] Reference Figure 16 and 17 , in at least one example, the second primary winding 1507 includes a first coil portion 1606a, a second coil portion 1606b, and a first center tap 1332a coupled between the first coil portion 1606a and the second coil portion 1606b. Each of the first coil portion 1606a and the second coil portion 1606b extends from the center tap 1332a and terminates at the first primary side terminal 1331a and the second primary side terminal 1333a respectively, which are located at the respective centers of the first coil portion 1606a and the second coil portion 1606b. In at least one example, the first coil portion 1606a and the second coil portion 1606b may have the same turn direction.

[0153] In at least one example, the second secondary winding 1508 includes a first coil portion 1607a, a second coil portion 1607b, and a second center tap 1335a coupled between the first coil portion 1607a and the second coil portion 1607b. Each of the first coil portion 1607a and the second coil portion 1607b extends from the center tap 1335a and terminates at the first secondary side terminal 1334a and the second secondary side terminal 1333a respectively, which are located at the respective centers of the first coil portion 1607a and the second coil portion 1607b. In at least one example, the first coil portion 1607a and the second coil portion 1607b may have the same turn direction.

[0154] In at least one example, each of the first semiconductor die 210 and the second semiconductor die 220 includes a respective half-bridge circuit. In at least one example, each of the data circuits 216 and 226 includes a respective data transmission and data reception circuit. In at least one example, the packaged IC 1500 includes a fifth semiconductor die 242 having power terminals and data terminals. The power terminals are coupled to the second semiconductor die 220, and the data terminals are coupled to the data circuit 226 (e.g., the fourth semiconductor die). As discussed herein, the first semiconductor die 210, the first converter 206, and the second semiconductor die 220 are part of an isolated power converter (e.g., a DC-DC converter).

[0155] Figure 18 An isometric top view schematically showing a packaged IC 1800 in which a data converter is within (or surrounded by) the footprint of a power converter, according to at least one example. In at least one example, the second converter 228a and the third converter 228b are within the footprint of the first converter 206. In at least one example, the first converter 206 includes a first primary winding 1503 formed in the topmost layer of the package substrate 202 and a first secondary winding 1504 below the first primary winding 1503. The first primary winding 1503 has the characteristics and functions of the first primary winding 1503, and it can be larger in size such that the second converters 228a and 228b can be assembled within the footprint of the first converter 206.

[0156] In at least one example, the second semiconductor die 220 is positioned within the footprint of the first converter 228. In at least one example, the data circuits 216 and 226 are part of the first semiconductor die 210 and the second semiconductor die 220, respectively. In at least one example, the first semiconductor die 210 overlaps and is coupled to the first primary winding 1503, the second primary winding 1507, and the third primary winding 1511 (not shown in Figure 18 ). The second semiconductor die 220 is coupled to the first secondary winding 1504, the second secondary winding 1508 (not shown in Figure 18 ), and the third secondary winding 1510. In at least one example, the second converter 228a including the second primary winding 1507 and the second secondary winding 1508 also overlaps the first semiconductor die 210. The coupling of the second converter 228a and the third converter 228b to their respective first semiconductor die 210 and second semiconductor die 220 is similar to that discussed with reference to Figures 15 - 17 . In Figure 18In an example, the first semiconductor die 210 and the second semiconductor die 220 can use the first converter 206 to transfer power to form an isolated DC-DC converter, and use the second converter 228a and the third converter 228b to send control signals (e.g., feedback voltage) to support output current and voltage regulation. The first semiconductor die 210 and the second semiconductor die 220 can also use the second converter 228a and the third converter 228b to send data into and out of the semiconductor die 242, where the data signals and the control signals are interleaved / multiplexed, as described in U.S. Patent Application No. 17 / 363,470, which is incorporated by reference.

[0157] Figure 19 FIG. 4 schematically shows a cross-sectional view of a packaged IC 1900 (an example of the packaged IC 1500) having a package substrate with three metal layers according to at least one example. The functions and features of the packaged IC 1900 are similar to Figure 5 the cross-section of the packaged IC 300 of FIG. 3. Here, three layers are shown with vias between the layers. These layers and vias include via 1 1901, layer 1 1902, via 2 1903, layer 2 1904, via 3 1905, layer 3 1906 (the topmost layer of the package substrate 202) from bottom to top. Via 1 is used to connect the package substrate 202 to a printed circuit board. In at least one example, the converter 206 is formed on layer 3 1906 and layer 2 1904, where the primary winding 1503 is on layer 3 1906 and the secondary winding 1504 is on layer 2 1904.

[0158] In at least one example, the packaged IC 1900 includes a first metal post 1907a coupled between the first metal interconnect 361 and the first semiconductor die 210, and a second metal post 1907b coupled between the third metal interconnect 363 and the first semiconductor die 210. In at least one example, the packaged IC 1900 includes a third metal post 1908a coupled between the second metal interconnect 362 and the second semiconductor die 220 and a fourth metal post 1908b coupled between the fourth metal interconnect 364 and the second semiconductor die 220. These metal posts 1907a, 1907b, 1908a, and 1908b can be made of copper (e.g., copper-copper posts) or any other suitable material. The metal posts 1907a, 1907b, 1908a, and 1908b allow the first semiconductor die 210 and / or the second semiconductor die 226 to partially overlap with the converter 206. Such overlap reduces the overall size of the packaged IC 1900 in the x-y direction.

[0159] In at least one example, the second primary winding 1507 is in the first metal layer 1906 (e.g., the topmost layer of the package substrate 202) and is coupled to either the first semiconductor die 210 or a data circuit 216 (e.g., a third semiconductor die) that overlaps with the second primary winding 1507. In at least one example, the second secondary winding 1508 is in the second metal layer 1904 below the first metal layer 1906. In at least one example, the third metal layer 1902 contains metal interconnects coupled between the second secondary winding 1508 and either the second semiconductor die 220 or a data circuit 226 (e.g., a fourth semiconductor die).

[0160] Figure 20 An isometric top view of a packaged IC 2000 according to at least one example is schematically shown, where the primary and secondary windings of its data converter partially overlap. Figure 21 An enlarged top view of a packaged IC 2000, referred to as a packaged IC 2100, according to at least one example is schematically shown, where the primary and secondary windings of its data converter partially overlap. Figure 22 An isometric view of a packaged IC 2200 (a portion of the packaged IC 2000) according to at least one example is schematically shown, where the primary and secondary windings of its data converter partially overlap.

[0161] The features and functions of the packaged IC 2000 are similar to those of the packaged IC 1500. In at least one example, the package substrate 202 can have three metal layers. In at least one example, to increase the inductance of the converter 206, the first primary winding 1503 can have more windings or turns in the first metal layer compared to the first primary winding 1503 in the packaged IC 1500. Similarly, according to at least one example, the first secondary winding 1504 is concentric with the first primary winding 1503 but has more windings or turns. In at least one example, the second converter 228a and the third converter 228b have different winding patterns and overlapping ratios of their respective primary and secondary windings. In at least one example, the converter 228a includes a second primary winding 2007 and a second secondary winding 2008 that partially overlap each other. The converter 228b includes a third primary winding 2010 and a third secondary winding 2011 that also partially overlap each other. In Figures 20 - 23 this case, the converters 228a and 228b are external to the footprint of the converter 206. In some examples, the converters 228a and 228b can be within the footprint of the converter 206, as in Figure 18 .

[0162] The winding patterns and tap connections for the second converter 228a and the third converter 228b in the packaged IC 2000 are different from those in the packaged IC 1500. As described below,Figures 20 - 24 The winding patterns and tap connections of the transformers 228a and 228b in Figure 20 can improve symmetry. For example, any asymmetry caused by the metal interconnect routing from the first secondary side terminal 1334a, center tap 1335a, and second secondary side terminal 1336a below the second secondary winding 1508 to the data circuit 226 is mitigated by

[0163] the winding pattern and tap positions of the second transformer 228a in Figures 20 - 23 . In at least one example, the same configuration is applied to the third transformer 228b. By achieving more symmetry in routing these taps, common mode rejection is improved.

[0164] In at least one example, the second primary winding 2007 is in one layer (e.g., the topmost metal layer of the package substrate 202), and the second secondary winding 2008 is on a layer below the topmost metal layer. In at least one example, each of the second primary winding 2007 and the second secondary winding 2008 has two windings in a figure-eight configuration. The windings can have an oval shape (as Figures 20 - 23 shown in Figure 21 ), or other winding shapes, such as circular, rectangular, square, etc. Figure 21 and 22 ), or the straight portion of the metal interconnect 2301 in Figure 23 . In at least one example, two coil portions 2017a and 2017b extend from the branch / straight portion to form the second primary winding 2007, where the coil portion 2017a terminates at the first primary side terminal 1331a, and the coil portion 2017b terminates at the second primary side terminal 1333a. The first primary side terminal 1331a and the second primary side terminal 1333a are coupled to the data circuit 216 via a pair of metal interconnects 2104 that are formed in a second metal layer and below the center tap metal interconnect 2101. For example, symmetry / matching can be achieved by, as Figure 21This is achieved by overlapping the pair of metal interconnects 2104 with the branch portions 2101a and 2101b of the center - tapped metal interconnect 2101 or by spacing the pair of metal interconnects 2104 at equal distances from the straight portion of the metal interconnect 2301. In both cases, the pair of metal interconnects 2104 can have a matched capacitive load, which can improve the symmetry and matching between the differential signals on the metal interconnects 2104.

[0165] In at least one example, the center tap 1332a is formed under the data circuit 216 and is coupled to the data circuit 216 by metal posts or pillars (e.g., copper pillars), while the first primary terminal 1331a and the second primary terminal 1333a are remote from the data circuit 216 because the second primary winding 2007 does not overlap the data circuit 216.

[0166] In at least one example, the second secondary winding 2008 has a topology similar or identical to that of the second primary winding 2007, and a portion (e.g., half) of the second primary winding overlaps the second secondary winding 2008. In at least one example, the center tap 1335a is positioned outside the footprint of the transformer 228a and is coupled to the second secondary winding 2008 by a center - tapped metal interconnect 2102 that extends laterally between the transformer 228a and the center tap 1335a. In at least one example, the center - tapped metal interconnect can have Figure 21 and 22 the balanced / matched branch portions 2102a and 2102b as shown, or Figure 23 the straight portion of the metal interconnect 2302. Two coil portions 2018a and 2018b extend from the branch / straight portion to form the second secondary winding 2008, where the coil portion 2018a terminates at the first secondary - side terminal 1334a and the coil portion 2018b terminates at the second secondary - side terminal 1336a. The first secondary - side terminal 1334a and the second secondary - side terminal 1336a are coupled to the data circuit 226 via a pair of metal interconnects 2103 that are formed in the second metal layer and under the center - tapped metal interconnect 2102. For example, symmetry / matching can be achieved by Figure 21 overlapping the pair of metal interconnects 2103 with the branch portions 2102a and 2102b of the center - tapped metal interconnect 2102 as shown or by spacing the pair of metal interconnects 2103 at equal distances from the straight portion of the metal interconnect 2302.

[0167] In at least one example, the transformer 228b has a topology similar to or the same as that of the transformer 228a. For example, the center tap 1332b is positioned outside the footprint of the transformer 228b and is coupled to the third primary winding 2010 through a center tap metal interconnect 2112 that extends laterally between the transformer 228b and the center tap 1332b. The third primary winding 2010 includes coil portions 2027a and 2027b that terminate at a first secondary side terminal 1331b and a second secondary side terminal 1333b, respectively. A pair of metal interconnects 2114 are coupled between the data circuit 226 and the first secondary side terminal 1331b and the second secondary side terminal 1333b. Symmetry / matching can be achieved by overlapping the pair of metal interconnects 2114 with a branch portion of the metal interconnect 2112 or by spacing the pair of metal interconnects 2114 an equal distance from a straight portion of the metal interconnect 2112.

[0168] In addition, the center tap 1335b is also positioned outside the footprint of the transformer 228b and is coupled to the third secondary winding 2011 through a center tap metal interconnect 2111. The third secondary winding 2010 includes coil portions 2028a and 2028b that terminate at a first primary side terminal 1334b and a second primary side terminal 1336b, respectively. A pair of metal interconnects 2116 are coupled between the data circuit 216 and the first primary side terminal 1334b and the second primary side terminal 1336b. Symmetry / matching can be achieved by overlapping the pair of metal interconnects 2116 with a branch portion of the metal interconnect 2111 or by spacing the pair of metal interconnects 2116 an equal distance from a straight portion of the metal interconnect 2111.

[0169] In at least one example, the second primary winding 2007 and the second secondary winding 2008 are electrically isolated using an isolation material (e.g., isolation material 314 or isolation material 1014) of the package substrate 202, and the isolation material forms an electrical isolation barrier between two different power / data domains of the data circuit 216 and the data circuit 226. In at least one example, the data circuit 216 is powered using a voltage supply and a ground connection associated with a first power domain. In at least one example, the data circuit 226 is powered using a different voltage supply and a ground connection associated with a second power domain.

[0170] Using a molding compound instead of a laminate as the isolation material allows for a smaller critical spacing between the second primary winding 2007 and the second secondary winding 2008 while maintaining the same voltage insulation and can improve the thermal performance of the isolation circuit 204.

[0171] Both the transformers 228a and 228b can be formed in two metal layers. For example, as Figure 21 and Figure 22As shown, the second primary winding 2007, the center tap metal interconnect 2101, the metal interconnect 2103, the third primary winding 2010, the center tap metal interconnect 2112, and the metal interconnect 2111 can be formed on a first metal layer (e.g., the top metal layer). The second secondary winding 2008, the center tap metal interconnect 2102, the metal interconnect 2114, the third secondary winding 2011, and the center tap metal interconnect 2111 can be formed on a second metal layer below the first metal layer. The dual-layer configuration is achieved by trading off the coupling between the primary and secondary windings to achieve layout symmetry between the primary and secondary windings, resulting in lower parasitic barrier capacitance and less electromagnetic radiation. In some examples, with the dual-layer configuration, the semiconductor die does not need to be placed on top of the converter, which makes the placement of the metal posts providing electrical connection between the semiconductor die and the converter more flexible, and relaxes the constraints imposed on the semiconductor die size due to the placement of the metal posts.

[0172] Figure 23 An isometric view of a packaged IC 2300 according to at least one example is schematically shown, in which the primary and secondary windings of the data converter partially overlap. Here, the packaged IC 2300 has features and functions similar to those of the packaged IC 2200, where each center tap metal interconnect has a straight portion, and symmetry / matching is achieved by spacing a pair of metal interconnects coupling the primary / secondary side terminals and the data circuit an equal distance from the straight portion, as explained above. Figure 23 The arrangement in [it] makes the converter more compact.

[0173] Figure 24 is a flowchart 2400 of a method of forming a packaged integrated circuit having three converters according to at least one example. The various blocks of the flowchart 2400 are shown in a particular order. The order can be modified. For example, some blocks can be executed before other blocks, and some blocks can be executed in parallel. The flowchart 2400 can be implemented using a wire-bondable lead frame technology and can be executed as part of a process for manufacturing a packaged IC, such as Figures 15 - 23 the packaged IC.

[0174] At block 2401, a first primary winding 1503 of the first transformer 206 is formed and coupled between a first primary side terminal 1505a and a second primary side terminal 1505b. At block 2402, a first secondary winding 1504 of the first transformer 206 is formed and coupled between a first secondary side terminal 1506a and a second secondary side terminal 1506b. At block 2403, a second primary winding 1507 of the second transformer 228a is formed and coupled between a third primary side terminal 1331a and a fourth primary side terminal 1333a. At block 2404, a second secondary winding 1508 of the second transformer 228a is formed and coupled between a third secondary side terminal 1334a and a fourth secondary side terminal 1336a, where the first transformer 206 and the second transformer 228a are in the package substrate 202. In some examples, another semiconductor die (e.g., semiconductor die 242) may be mounted on the package substrate 202 before forming the first transformer 206 and / or the second transformer 228a. In some examples, another semiconductor die (e.g., semiconductor die 242) may be electrically coupled to the package substrate 202 via bonding wires.

[0175] At block 2405, the first primary side terminal 1505a and the second primary side terminal 1505b are coupled to a first semiconductor die 211 on the package substrate 202. At block 2406, the first secondary side terminal 1506a and the second secondary side terminal 1506b are coupled to a second semiconductor die 220 on the package substrate 202.

[0176] In at least one example, the method of flowchart 2400 includes overlapping the first semiconductor die 211 over a portion of the first primary winding 1503 and the first secondary winding 1504. In at least one example, the first semiconductor die 211 is coupled to the first primary side terminal 1505a and the second primary side terminal 1505b via a first metal post (e.g., a copper post). In at least one example, the second semiconductor die 220 is coupled to the first secondary side terminal 1506a and the second secondary side terminal 1506b via a second metal post.

[0177] The following are additional examples provided in view of the above embodiments. Here, one or more features of an example, individually or in combination, may be combined with one or more features of one or more other examples to form other examples that also fall within the scope of the present disclosure. Thus, one embodiment may be combined with one or more other embodiments without changing the scope of the present disclosure.

[0178] Example 1 is an encapsulated integrated circuit, which includes: an encapsulation substrate that includes an isolation circuit, and the isolation circuit includes a first primary-side terminal, a second primary-side terminal, a first secondary-side terminal, and a second secondary-side terminal; a first semiconductor die on the encapsulation substrate and coupled to the first primary-side terminal and the second primary-side terminal; and a second semiconductor die on the encapsulation substrate and coupled to the first secondary-side terminal and the second secondary-side terminal.

[0179] Example 2 is the encapsulated integrated circuit according to any one of the examples herein, particularly Example 1, wherein the encapsulation substrate includes one or more transformers, including a first transformer that includes a first primary winding and a first secondary winding, the first primary winding being coupled between the first primary-side terminal and the second primary-side terminal, and the first secondary winding being coupled between the first secondary-side terminal and the second secondary-side terminal.

[0180] Example 3 is the encapsulated integrated circuit according to any one of the examples herein, particularly Example 2, wherein the encapsulation substrate includes a first metal layer and a second metal layer below the first metal layer, and wherein the first primary winding is in the first metal layer, and the first secondary winding is in the second metal layer.

[0181] Example 4 is the encapsulated integrated circuit according to any one of the examples herein, particularly Example 3, which further includes a first metal interconnect and a second metal interconnect in the first metal layer and a third metal interconnect and a fourth metal interconnect in the second metal layer, wherein: the first metal interconnect is coupled between the first primary-side terminal of the first primary winding and the first semiconductor die; the third metal interconnect is coupled between the second primary-side terminal of the first primary winding and the first semiconductor die; the second metal interconnect is coupled between the first secondary-side terminal of the first secondary winding and the second semiconductor die; and the fourth metal interconnect is coupled between the second secondary-side terminal of the first secondary winding and the second semiconductor die.

[0182] Example 5 is the encapsulated integrated circuit according to any one of the examples herein, particularly Example 4, which further includes a first metal post coupled between the first metal interconnect and the first semiconductor die, a second metal post coupled between the third metal interconnect and the first semiconductor die, a third metal post coupled between the second metal interconnect and the second semiconductor die, and a fourth metal post coupled between the fourth metal interconnect and the second semiconductor die.

[0183] Example 6 is an encapsulated integrated circuit according to any example herein, particularly example 3, further comprising a first metal interconnect, a second metal interconnect, and a third metal interconnect in the first metal layer and a fourth metal interconnect in the second metal layer, wherein: the first metal interconnect is coupled between the first primary side terminal of the first primary winding and the first semiconductor die; the second metal interconnect is coupled between the second primary side terminal of the first primary winding and the first semiconductor die; the third metal interconnect is coupled between the first secondary side terminal of the first secondary winding and the second semiconductor die; and the fourth metal interconnect is coupled between the second secondary side terminal of the first secondary winding and the second semiconductor die.

[0184] Example 7 is an encapsulated integrated circuit according to any example herein, particularly example 6, further comprising a first bonding wire coupled between the second interconnect and the second primary side terminal of the first primary winding and a second bonding wire coupled between the first secondary side terminal of the first secondary winding and the third metal interconnect.

[0185] Example 8 is an encapsulated integrated circuit according to any example herein, particularly example 6, further comprising a first metal post coupled between the first metal interconnect and the first semiconductor die, a second metal post coupled between the second metal interconnect and the first semiconductor die, a third metal post coupled between the third metal interconnect and the second semiconductor die, and a fourth metal post coupled between the fourth metal interconnect and the second semiconductor die.

[0186] Example 9 is an encapsulated integrated circuit according to any example herein, particularly example 2, wherein the encapsulation substrate comprises a first metal layer, a second metal layer, and a third metal layer, the second metal layer being between the first and third metal layers; wherein the first primary winding is in the first metal layer and the first secondary winding is in the second metal layer; wherein the first semiconductor die is coupled to the first primary winding; and wherein the encapsulation substrate comprises a first metal interconnect and a second metal interconnect in the third metal layer, the first metal interconnect being coupled between the first secondary side terminal of the first secondary winding and the second semiconductor die and the second metal interconnect being coupled between the second primary side terminal of the first secondary winding and the second semiconductor die.

[0187] Example 10 is an encapsulated integrated circuit according to any example herein, particularly example 2, wherein the isolation circuit comprises a third primary side terminal, a fourth primary side terminal, a third secondary side terminal, and a fourth secondary side terminal.

[0188] Example 11 is an encapsulated integrated circuit according to any example herein, particularly Example 10, wherein the isolation circuit includes a first capacitor and a second capacitor, the first capacitor being coupled between the third primary-side terminal and the third secondary-side terminal, and the second capacitor being coupled between the fourth primary-side terminal and the fourth secondary-side terminal.

[0189] Example 12 is an encapsulated integrated circuit according to any example herein, particularly Example 10, wherein the one or more transformers include a second transformer, the second transformer including a second primary winding and a second secondary winding, the second primary winding being coupled between the third primary-side terminal and the fourth primary-side terminal, and the second secondary winding being coupled between the third secondary-side terminal and the fourth secondary-side terminal.

[0190] Example 13 is an encapsulated integrated circuit according to any example herein, particularly Example 12, wherein the second transformer is external to the footprint of the first transformer.

[0191] Example 14 is an encapsulated integrated circuit according to any example herein, particularly Example 13, further including a third semiconductor die and a fourth semiconductor die, the third semiconductor die being coupled to the third primary-side terminal and the fourth primary-side terminal, and the fourth semiconductor die being coupled to the third secondary-side terminal and the fourth secondary-side terminal.

[0192] Example 15 is an encapsulated integrated circuit according to any example herein, particularly Example 12, wherein the second transformer is within the footprint of the first transformer.

[0193] Example 16 is an encapsulated integrated circuit according to any example herein, particularly Example 15, wherein the first semiconductor die is coupled to the third primary-side terminal and the fourth primary-side terminal, and the second semiconductor die is coupled to the third secondary-side terminal and the fourth secondary-side terminal.

[0194] Example 17 is an encapsulated integrated circuit according to any example herein, particularly Example 12, wherein the second primary winding includes a first coil portion and a second coil portion coupled to a first center tap; and wherein the second secondary winding includes a third coil portion and a fourth coil portion coupled to a second center tap.

[0195] Example 18 is a packaged integrated circuit according to any example herein, particularly Example 17, wherein: the first and second center taps are within the footprint of the second transformer; the packaged substrate includes a first metal layer, a second metal layer, and a third metal layer, with the second metal layer between the first and third metal layers; the second primary winding is in the first metal layer and is coupled to one of the first semiconductor die or a third semiconductor die that overlaps the second primary winding; the second secondary winding is in the second metal layer; and the third metal layer includes metal interconnects that couple between the second secondary winding and one of the second semiconductor die or a fourth semiconductor die.

[0196] Example 19 is a packaged integrated circuit according to any example herein, particularly Example 17, wherein: the first and second center taps are outside the footprint of the second transformer; the packaged substrate includes a first metal layer and a second metal layer; the first metal layer includes the second primary winding, a first metal interconnect that couples between the first center tap and the second primary winding, and a pair of second metal interconnects that couple between the second secondary winding and one of the second semiconductor die or a third semiconductor die, the third semiconductor die being on the periphery of the second transformer; and the second metal layer includes the second secondary winding, a third metal interconnect that couples between the second center tap and the second secondary winding, and a pair of fourth metal interconnects that couple between the second primary winding and one of the first semiconductor die or a fourth semiconductor die, the fourth semiconductor die being on the periphery of the second transformer.

[0197] Example 20 is a packaged integrated circuit according to any example herein, particularly Example 19, wherein the first metal interconnect includes a first branch portion that overlaps the pair of fourth metal interconnects; and wherein the third metal interconnect includes a second branch portion that overlaps the pair of second metal interconnects.

[0198] Example 21 is a packaged integrated circuit according to any example herein, particularly Example 19, wherein the first metal interconnect includes a first straight portion that is equidistantly spaced from each of the pair of fourth metal interconnects; and wherein the third metal interconnect includes a second straight portion that is equidistantly spaced from each of the pair of second metal interconnects.

[0199] Example 22 is an encapsulated integrated circuit according to any example herein, particularly example 21, wherein the isolation circuit includes a fifth primary side terminal, a sixth primary side terminal, a fifth secondary side terminal, and a sixth secondary side terminal; and wherein the one or more converters include a third converter, the third converter including a third primary winding and a third secondary winding, the third primary winding being coupled between the fifth primary side terminal and the sixth primary side terminal, and the third secondary winding being coupled between the fifth secondary side terminal and the sixth secondary side terminal.

[0200] Example 23 is an encapsulated integrated circuit according to any example herein, particularly example 22, wherein the third converter is external to the footprint of the first converter.

[0201] Example 24 is an encapsulated integrated circuit according to any example herein, particularly example 22, wherein the third converter is internal to the footprint of the first converter.

[0202] Example 25 is an encapsulated integrated circuit according to any example herein, particularly example 12, further including a third semiconductor die and a fourth semiconductor die, the third semiconductor die being coupled to the third primary side terminal and the fourth primary side terminal, and the fourth semiconductor die being coupled to the third secondary side terminal and the fourth secondary side terminal.

[0203] Example 26 is an encapsulated integrated circuit according to any example herein, particularly example 1, wherein the first primary side terminal, the second primary side terminal, the first secondary side terminal, and the second secondary side terminal are on a first surface of the package substrate, and the first and second semiconductor dies are mounted on the first surface; wherein the package substrate further includes first and second metal pads on a second surface of the package substrate opposite the first surface, the first semiconductor die being coupled to at least some of the first metal pads, and the second semiconductor die being coupled to at least some of the second metal pads.

[0204] Example 27 is an encapsulated integrated circuit according to any example herein, particularly example 26, wherein the first metal pads are on a first side of the package substrate, the second metal pads are on a second side of the package substrate opposite the first side, and a first number of the first metal pads is different from a second number of the second metal pads.

[0205] Example 28 is an encapsulated integrated circuit according to any example herein, particularly example 1, wherein the package substrate is part of a lead frame that can be routed.

[0206] Example 29 is a packaged integrated circuit, which includes: a package substrate, which includes: a first converter including a first primary winding and a first secondary winding, the first primary winding being coupled between a first primary-side terminal and a second primary-side terminal, and the first secondary winding being coupled between a first secondary-side terminal and a second secondary-side terminal; and a second converter including a second primary winding and a second secondary winding, the second primary winding being coupled between a third primary-side terminal and a fourth primary-side terminal, and the second secondary winding being coupled between a third secondary-side terminal and a fourth secondary-side terminal; a first semiconductor die on the package substrate and coupled to the first primary-side terminal and the second primary-side terminal; a second semiconductor die on the package substrate and coupled to the first secondary-side terminal and the second secondary-side terminal; a first data circuit on the package substrate and coupled to the third primary-side terminal and the fourth primary-side terminal; and a second data circuit on the package substrate and coupled to the third secondary-side terminal and the fourth secondary-side terminal.

[0207] Example 30 is a packaged integrated circuit according to any example herein, particularly Example 29, wherein the first semiconductor die is coupled to the first primary-side terminal and the second primary-side terminal via a first metal post, and the second semiconductor die is coupled to the first secondary-side terminal and the second secondary-side terminal via a second metal post.

[0208] Example 31 is a packaged integrated circuit according to any example herein, particularly Example 29, wherein the first semiconductor die partially overlaps with the first primary winding and the first secondary winding.

[0209] Example 32 is a packaged integrated circuit according to any example herein, particularly Example 29, wherein the package substrate includes a first metal layer, a second metal layer, and a third metal layer, the second metal layer being between the first and third metal layers; wherein the first primary winding is in the first metal layer, and the first secondary winding is in the second metal layer; wherein the first semiconductor die is coupled to the first primary winding; and wherein the package substrate includes a first metal interconnect and a second metal interconnect in the third metal layer, the first metal interconnect being coupled between a first end of the first secondary winding and the second semiconductor die, and the second metal interconnect being coupled between a second end of the first secondary winding and the second semiconductor die.

[0210] Example 33 is a packaged integrated circuit according to any example herein, particularly Example 29, wherein the second converter is outside the footprint of the first converter.

[0211] Example 34 is an encapsulated integrated circuit according to any example herein, particularly example 33, further comprising a third semiconductor die including the first data circuit and a fourth semiconductor die including the second data circuit, the third semiconductor die being coupled to the third primary side terminal and the fourth primary side terminal, and the fourth semiconductor die being coupled to the third secondary side terminal and the fourth secondary side terminal.

[0212] Example 35 is an encapsulated integrated circuit according to any example herein, particularly example 34, wherein each of the first and second semiconductor dies includes a respective half-bridge circuit or a respective full-bridge circuit, and each of the third and fourth semiconductor dies includes a respective data transmission circuit and a respective data reception circuit.

[0213] Example 36 is an encapsulated integrated circuit according to any example herein, particularly example 34, further comprising a fifth semiconductor die having a power terminal and a data terminal, the power terminal being coupled to the second semiconductor die, and the data terminal being coupled to the fourth semiconductor die.

[0214] Example 37 is an encapsulated integrated circuit according to any example herein, particularly example 29, wherein the second converter is within the footprint of the first converter.

[0215] Example 38 is an encapsulated integrated circuit according to any example herein, particularly example 37, wherein the first semiconductor die includes the first data circuit and is coupled to the third primary side terminal and the fourth primary side terminal, and the second semiconductor die includes the second data circuit and is coupled to the third secondary side terminal and the fourth secondary side terminal.

[0216] Example 39 is an encapsulated integrated circuit according to any example herein, particularly example 38, wherein the first semiconductor die and the second semiconductor die, the first converter and the second converter are part of an isolated power converter.

[0217] Example 40 is an encapsulated integrated circuit according to any example herein, particularly example 29, wherein the second primary winding includes a first coil portion and a second coil portion coupled to a first center tap; and wherein the second secondary winding includes a third coil portion and a fourth coil portion coupled to a second center tap.

[0218] Example 41 is an encapsulated integrated circuit according to any example herein, particularly Example 40, wherein: the first and second center taps are within the footprint of the second transformer; the encapsulation substrate includes a first metal layer, a second metal layer, and a third metal layer, with the second metal layer between the first and third metal layers; the second primary winding is in the first metal layer and is coupled to one of the first semiconductor die or a third semiconductor die that overlaps the second primary winding; the second secondary winding is in the second metal layer; and the third metal layer includes metal interconnects that couple between the second secondary winding and one of the second semiconductor die or a fourth semiconductor die.

[0219] Example 42 is an encapsulated integrated circuit according to any example herein, particularly Example 40, wherein: the first and second center taps are outside the footprint of the second transformer; the encapsulation substrate includes a first metal layer and a second metal layer; the first metal layer includes the second primary winding, a first metal interconnect that couples between the first center tap and the second primary winding, and a pair of second metal interconnects that couple between the second secondary winding and one of the second semiconductor die or a third semiconductor die, with the third semiconductor die on the periphery of the second transformer; and the second metal layer includes the second secondary winding, a third metal interconnect that couples between the second center tap and the second primary winding, and a pair of fourth metal interconnects that couple between the second primary winding and one of the first semiconductor die or a fourth semiconductor die, with the fourth semiconductor die on the periphery of the second transformer.

[0220] Example 43 is an encapsulated integrated circuit according to any example herein, particularly Example 42, wherein the first metal interconnect includes a first branch portion that overlaps the pair of fourth metal interconnects; and wherein the third metal interconnect includes a second branch portion that overlaps the pair of second metal interconnects.

[0221] Example 44 is an encapsulated integrated circuit according to any example herein, particularly Example 42, wherein the first metal interconnect includes a first straight portion that is equidistantly spaced from each of the pair of fourth metal interconnects; and wherein the third metal interconnect includes a second straight portion that is equidistantly spaced from each of the pair of second metal interconnects.

[0222] Example 45 is an encapsulated integrated circuit according to any example herein, particularly Example 29, wherein the first primary-side terminal, the second primary-side terminal, the first secondary-side terminal, and the second secondary-side terminal are on a first surface of the encapsulation substrate, the first and second semiconductor dies are mounted on the first surface; and wherein the encapsulation substrate further includes first and second metal pads on a second surface of the encapsulation substrate opposite the first surface, the first semiconductor die is coupled to at least some of the first metal pads, and the second semiconductor die is coupled to at least some of the second metal pads.

[0223] Example 46 is an encapsulated integrated circuit according to any example herein, particularly Example 45, wherein the first metal pad is on a first side of the encapsulation substrate, the second metal pad is on a second side of the encapsulation substrate opposite the first side, and a first number of the first metal pads is different from a second number of the second metal pads.

[0224] Example 47 is an encapsulated integrated circuit according to any example herein, particularly Example 29, wherein the encapsulation substrate is part of a leadframe that can be laid out.

[0225] Example 48 is an encapsulated integrated circuit according to any example herein, particularly Example 29, wherein the first semiconductor die and the second semiconductor die are flip-chip dies.

[0226] Example 49 is a method that includes: coupling a first primary winding of a first transformer between a first primary-side terminal and a second primary-side terminal; coupling a first secondary winding of the first transformer between a first secondary-side terminal and a second secondary-side terminal; coupling a second primary winding of a second transformer between a third primary-side terminal and a fourth primary-side terminal; coupling a second secondary winding of the second transformer between a third secondary-side terminal and a fourth secondary-side terminal, wherein the first transformer and the second transformer are in an encapsulation substrate; coupling the first primary-side terminal and the second primary-side terminal to a first semiconductor die on the encapsulation substrate; and coupling the first secondary-side terminal and the second secondary-side terminal to a second semiconductor die on the encapsulation substrate.

[0227] Example 50 is the method according to any example herein, particularly Example 49, wherein the first semiconductor die is coupled to the first primary-side terminal and the second primary-side terminal via first metal pillars, and the second semiconductor die is coupled to the first secondary-side terminal and the second secondary-side terminal via second metal pillars.

[0228] Example 51 is a method according to any example herein, particularly Example 49, further comprising overlapping the first semiconductor die over a portion of the first primary winding and the first secondary winding.

[0229] Various modifications may be made to the disclosed examples and their implementations other than those described herein without departing from their scope. Accordingly, the illustrations of the implementations herein are to be considered as examples and not limiting of the scope of the disclosure.

[0230] In this specification, the term "coupled" may cover a connection, communication, or signal path that supports a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B through an intermediate component C, but the intermediate component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0231] In the specification and claims, unless otherwise indicated, the terms "comprising" and "having" and their variations are intended to be inclusive in a manner similar to the term "including". Additionally, the term "couple", "coupled", or "couples" refers to an indirect or direct electrical or mechanical connection.

[0232] Also, in this specification, the recitation "based on" means "at least partially based on". Thus, if X is based on Y, then X may vary with Y and any other factors.

[0233] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0234] As used herein, the terms "terminal", "node", "interconnect", "pin", and "lead" may be used interchangeably. Unless explicitly stated to the contrary, these terms are generally used to denote an interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components or their ends.

[0235] A circuit or device described herein as including particular components can in fact be adapted to be coupled to those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may in fact include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and can be adapted to be coupled to at least some of the passive elements and / or sources, e.g., by an end user and / or a third party, during or after manufacture to form the described structure.

[0236] Although the use of particular transistors is described herein, other transistors (or equivalent devices) can in fact be used with little or no change to the rest of the circuit. For example, field effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs, e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) can be used instead of or in combination with the devices described herein. The transistors can be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device-structure transistors. Additionally, the devices can be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0237] The circuits described herein can be reconfigured to include additional or different components to provide a function that is at least partially similar to the function available before the component replacement. Unless otherwise specified, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can be, respectively, multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can be, respectively, multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0238] Although some of the elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features shown as external to the integrated circuit may be included in the integrated circuit, and / or some of the features shown as internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more of the following circuits: (i) integrated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0239] The use of the phrase "ground" in the above description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "substantially", or "essentially" before a parameter means within + / - 10% of the stated parameter, or if the parameter is zero, then means a reasonable range of values around zero.

Claims

1. A packaged integrated circuit, comprising: A packaging substrate comprising: A first converter comprising a first primary winding and a first secondary winding, wherein the first primary winding is coupled between a first primary-side terminal and a second primary-side terminal, and the first secondary winding is coupled between the first secondary-side terminal and the second secondary-side terminal; as well as a second converter comprising a second primary winding and a second secondary winding, wherein the second primary winding is coupled between the third primary-side terminal and the fourth primary-side terminal, and the second secondary winding is coupled between the third secondary-side terminal and the fourth secondary-side terminal; a first semiconductor die on the package substrate and coupled to the first primary-side terminal and the second primary-side terminal; a second semiconductor die on the package substrate and coupled to the first secondary-side terminal and the second secondary-side terminal; a first data circuit on the package substrate and coupled to the third primary-side terminal and the fourth primary-side terminal; as well as A second data circuit is on the package substrate and coupled to the third secondary side terminal and the fourth secondary side terminal.

2. The packaged integrated circuit of claim 1 , wherein the first semiconductor die is coupled to the first primary-side terminal and the second primary-side terminal via a first metal pillar, and the second semiconductor die is coupled to the first secondary-side terminal and the second secondary-side terminal via a second metal pillar. 3 . The packaged integrated circuit of claim 1 , wherein the first semiconductor die overlaps portions of the first primary winding and the first secondary winding.

4. The packaged integrated circuit of claim 1 , wherein the package substrate comprises a first metal layer, a second metal layer, and a third metal layer, the second metal layer being between the first and third metal layers; wherein the first primary winding is in the first metal layer, and the first secondary winding is in the second metal layer; wherein the first semiconductor die is coupled to the first primary winding; and The packaging substrate includes a first metal interconnect and a second metal interconnect in the third metal layer, the first metal interconnect is coupled between the first end of the first secondary winding and the second semiconductor die, and the second metal interconnect is coupled between the second end of the first secondary winding and the second semiconductor die. 5 . The packaged integrated circuit of claim 1 , wherein the second transformer is external to a footprint of the first transformer.

6. The packaged integrated circuit of claim 5, further comprising a third semiconductor die comprising the first data circuit and a fourth semiconductor die comprising the second data circuit, the third semiconductor die being coupled to the third primary side terminal and the fourth primary side terminal, and the fourth semiconductor die being coupled to the third secondary side terminal and the fourth secondary side terminal. 7 . The packaged integrated circuit of claim 6 , wherein each of the first and second semiconductor dies comprises a respective half-bridge circuit or a full-bridge circuit, and each of the third and fourth semiconductor dies comprises a respective data transmission circuit and a respective data reception circuit. 8 . The packaged integrated circuit of claim 6 , further comprising a fifth semiconductor die having a power terminal and a data terminal, the power terminal coupled to the second semiconductor die, and the data terminal coupled to the fourth semiconductor die.

9. The packaged integrated circuit of claim 1 wherein the second converter is within a footprint of the first converter.

10. The packaged integrated circuit of claim 9, wherein the first semiconductor die includes the first data circuit and is coupled to the third primary side terminal and the fourth primary side terminal, and the second semiconductor die includes the second data circuit and is coupled to the third secondary side terminal and the fourth secondary side terminal. 11 . The packaged integrated circuit of claim 10 , wherein the first and second semiconductor dies, the first converter, and the second converter are parts of an isolated power converter.

12. The packaged integrated circuit of claim 1, wherein the second primary winding comprises a first coil portion and a second coil portion coupled to a first center tap; and Wherein the second secondary winding includes a third coil portion and a fourth coil portion coupled to a second center tap.

13. The packaged integrated circuit of claim 12, wherein: The first and second center taps are within the footprint of the second converter; The packaging substrate comprises a first metal layer, a second metal layer and a third metal layer, wherein the second metal layer is between the first and third metal layers; The second primary winding is in the first metal layer and is coupled to one of the first semiconductor die or a third semiconductor die overlapping the second primary winding; The second secondary winding is in the second metal layer; and The third metal layer includes a metal interconnect coupled between the second secondary winding and one of the second semiconductor die or a fourth semiconductor die.

14. The packaged integrated circuit of claim 12, wherein: The first and second center taps are outside the footprint of the second converter; The packaging substrate comprises a first metal layer and a second metal layer; The first metal layer includes the second primary winding, a first metal interconnect coupled between the first center tap and the second primary winding, and a pair of second metal interconnects coupled between the second secondary winding and one of the second semiconductor die or a third semiconductor die, the third semiconductor die being on a periphery of the second converter; and The second metal layer includes the second secondary winding, a third metal interconnect coupled between the second center tap and the second primary winding, and a pair of fourth metal interconnects coupled between the second primary winding and one of the first semiconductor die or a fourth semiconductor die, the fourth semiconductor die being on the periphery of the second converter.

15. The packaged integrated circuit of claim 14, wherein the first metal interconnection comprises a first branch portion overlapping the pair of fourth metal interconnections; and The third metal interconnection includes a second branch portion overlapping the pair of second metal interconnections.

16. The packaged integrated circuit of claim 14, wherein the first metal interconnect comprises a first straight portion spaced equidistant from each of the pair of fourth metal interconnects; and The third metal interconnection includes a second straight portion that is equidistant from each of the pair of second metal interconnections.

17. The packaged integrated circuit of claim 1, wherein the first primary-side terminal, the second primary-side terminal, the first secondary-side terminal, and the second secondary-side terminal are on a first surface of the package substrate, the first and second semiconductor dies being mounted on the first surface; and The packaging substrate further includes first and second metal pads on a second surface of the packaging substrate opposite to the first surface, the first semiconductor die is coupled to at least some of the first metal pads, and the second semiconductor die is coupled to at least some of the second metal pads.

18. The packaged integrated circuit of claim 17, wherein the first metal pads are on a first side of the packaging substrate, the second metal pads are on a second side of the packaging substrate opposite to the first side, and a first number of the first metal pads is different from a second number of the second metal pads.

19. The packaged integrated circuit of claim 1 wherein the package substrate is a portion of a routable leadframe.

20. The packaged integrated circuit of claim 1, wherein the first semiconductor die and the second semiconductor die are flip-chip dies.

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