Control circuit for switching converter

Abstract

The invention discloses a control circuit for a switching converter. The control circuit comprises a compensation circuit, a slope generation circuit, a comparison circuit and a logic circuit. The switching converter comprises at least one power switch. The present invention relates to a switching converter that converts an input voltage into an output voltage in response to a pulse width modulation (PWM) control signal. The compensation circuit generates a compensation signal in response to an output voltage and a reference signal. The ramp generation circuit generates a ramp signal in response to the PWM control signal. A comparison circuit provides a comparison signal in response to the compensation signal and the ramp signal. The logic circuit provides a PWM control signal in response to the comparison signal and the clock signal. The control circuit generates the ramp signal for the high-frequency switching converter based on the PWM control signal, shortens the settling time of the ramp signal, and improves the transient response of the switching converter.

Description

Technical Field

[0001] The present disclosure relates to a power circuit, and more particularly to a switching converter. Background Art

[0002] Power converters, such as switching regulators, are widely used to supply power to electronic devices. Constant ON-Time (COT) control is widely used in DC / DC voltage converters due to its fast transient response. However, a voltage converter using COT control has a varying and non-constant switching frequency, which makes it difficult to use COT control in application scenarios where the switching frequency must be constant (such as automotive systems). In contrast to COT control, current mode control has a constant switching frequency, but its transient response speed is slow, and in order to perform the current detection function within each switching cycle, the power switch must have a minimum ON duration or a minimum OFF duration.

[0003] Therefore, it is necessary to propose a control circuit and a control method with fast transient response and constant switching frequency. Summary of the Invention

[0004] Therefore, an object of the present disclosure is to solve the above technical problems of the prior art and propose a control circuit for a switching converter.

[0005] According to an embodiment of the present disclosure, a control circuit for a switching converter is proposed, including a compensation circuit, a ramp generation circuit, a comparison circuit, and a logic circuit. The switching converter includes at least one power switch, and the switching converter is configured to convert an input voltage into an output voltage in response to a pulse-width modulation (PWM) control signal. The compensation circuit is configured to generate a compensation signal in response to the output voltage and a reference signal. The ramp generation circuit is configured to generate a ramp signal in response to the PWM control signal. The comparison circuit is configured to provide a comparison signal in response to the compensation signal and the ramp signal. The logic circuit is configured to provide a PWM control signal in response to the comparison signal and a clock signal.

[0006] According to an embodiment of the present disclosure, a control circuit for a switching converter is provided, including a compensation circuit, a ramp generation circuit, a comparison circuit, and a logic circuit. The switching converter includes at least one power switch and is configured to convert an input voltage into an output voltage in response to a pulse-width modulation (PWM) control signal. The compensation circuit is configured to generate a compensation signal in response to a reference signal and a feedback signal representing the output voltage. The ramp generation circuit is configured to generate a ramp signal. The comparison circuit is configured to provide a comparison signal in response to the compensation signal and the ramp signal. The logic circuit is configured to provide a PWM control signal in response to the comparison signal and a clock signal. When the voltage value of the ramp signal reaches the voltage value of the compensation signal, the PWM control signal is at a first level. The PWM control signal is at a second level in response to the clock signal.

[0007] Compared with the conventional technology, the control circuit of the present disclosure generates a ramp signal for a high-frequency switching converter based on a PWM signal, replacing the scheme of detecting the inductor current IL as the ramp signal in the conventional technology, thereby shortening the settling time of the ramp signal and improving the transient response of the switching converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To better understand the present disclosure, the present disclosure will be described in detail with reference to the following drawings:

[0009] Figure 1 A circuit block diagram of a power converter 100 according to an embodiment of the present disclosure;

[0010] Figure 2 A circuit structure diagram of a switching converter 10 with current mode control according to an embodiment of the present disclosure;

[0011] Figure 3 A circuit block diagram of a control circuit 300 for a switching converter 10 according to an embodiment of the present disclosure;

[0012] Figure 4 A circuit block diagram of a ramp generation circuit 400 according to an embodiment of the present disclosure;

[0013] Figure 5 A circuit block diagram of a control circuit 500 for a switching converter 12 according to an embodiment of the present disclosure;

[0014] Figure 6 A circuit structure diagram of a ramp generation circuit 600 according to an embodiment of the present disclosure;

[0015] Figure 7 A schematic diagram of a simulation waveform of a signal of the control circuit 500 according to an embodiment of the present disclosure;

[0016] Figure 8 Schematic diagram of the simulation waveform of the signal of the ramp generation circuit 600 according to an embodiment of the present disclosure;

[0017] Figure 9 Flowchart of the control method 900 of the switching converter according to an embodiment of the present disclosure;

[0018] In the drawings, the same or corresponding reference numerals are used to denote the same or corresponding elements. Detailed implementation manners

[0019] The specific embodiments of the present disclosure will be described in detail below. It should be noted that the embodiments described herein are only for illustrative purposes and are not intended to limit the present disclosure. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those of ordinary skill in the art that: the present disclosure does not have to be practiced with these specific details. In other instances, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring the present disclosure.

[0020] Throughout the specification, references to "one embodiment", "an embodiment", "one example", or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment", "in an embodiment", "one example", or "an example" appearing throughout the specification do not necessarily all refer to the same embodiment or example. Additionally, the particular features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. It should be understood that when an element is referred to as being "coupled to" or "connected to" another element, it can be directly coupled or connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, there are no intervening elements. The same reference numerals indicate the same elements. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0021] Figure 1 Circuit block diagram of the power converter 100 according to an embodiment of the present disclosure. As Figure 1 shown, the power converter 100 includes a switching converter 10, a gate driver 20, a feedback circuit 30, and a loop control circuit 40. The switching converter 10 includes at least one power switch, and the at least one power switch converts the input voltage V IN into the output voltage V OUT。In one embodiment, the switching converter 10 is a buck converter. In another embodiment, the switching converter 10 is a boost converter. In yet another embodiment, the switching converter 10 is a buck-boost converter. However, the present disclosure is not limited thereto. In different embodiments, the switching converter 10 can be any type of switched-mode power converter.

[0022] The feedback circuit 30 receives the output voltage V OUT , and provides a feedback signal V OUT proportional to the output voltage V FB . The loop control circuit 40 receives the feedback signal V FB , and provides a PWM control signal S PWM to the gate driver 20. The gate driver 20, in response to the PWM control signal S PWM , provides a drive signal (e.g., S D ) to at least one power switch of the switching converter.

[0023] Figure 2 FIG. is a circuit structure diagram of a switching converter 10 with current-mode control according to an embodiment of the present disclosure. As Figure 2 shown, the loop control circuit 200 includes a compensation circuit 210, a current-sensing ramp circuit 220, a comparison circuit 230, and a logic circuit 240. The compensation circuit 210 (e.g., an error amplifier) receives the feedback signal V FB and a reference signal V REF , and in response to the feedback signal V FB and the reference signal V REF , generates a compensation signal Comp. The current-sensing ramp circuit 220 senses the inductor current IL and, in response to the inductor current IL, generates a ramp signal Ramp. In some embodiments, a ramp compensation circuit is employed to generate the ramp signal Ramp. The comparison circuit 230 (e.g., a comparator CMP) receives the compensation signal Comp and the ramp signal Ramp, and provides a comparison signal. The logic circuit 240 (e.g., an RS latch) receives the comparison signal and a clock signal Clk, and provides a PWM control signal PWM.

[0024] However, for high-frequency switching converters, using the current detection signal as a ramp signal is not an ideal approach because the current detection signal has a long settling time. Specifically, the automotive radar system needs to use a high-frequency buck converter with a fixed frequency. Since the baseband of the radar system is relatively wide, for example, in the range of several kilohertz to several megahertz, the switching frequency of the power converter should be higher than 12MHz. In one embodiment, the switching frequency of the power converter is 18MHz, and each switching cycle is about 56ns. In such a short time, it is difficult to detect the inductor current IL due to the influence of the settling time. Therefore, instead of detecting the inductor current IL, the present disclosure filters the PWM signal to generate a ramp signal for the high-frequency switching converter.

[0025] Figure 3 FIG. 3 is a circuit block diagram of a control circuit 300 for a switching converter 10 according to an embodiment of the present disclosure. The switching converter 10 includes at least one power switch, which converts an input voltage V IN Converted into output voltage V OUT In one embodiment, the switching converter 10 is a buck converter, in another embodiment, the switching converter 10 is a boost converter, and in yet another embodiment, the switching converter 10 is a buck-boost converter, but the present disclosure is not limited thereto. In different embodiments, the switching converter 10 can be any type of switching power converter.

[0026] like Figure 3 As shown, the feedback circuit 30 receives the output voltage V OUT and provides an output voltage with V OUT Proportional to the feedback signal V FB In one example, a voltage divider (such as a resistor R FB1 and R FB2 ) to get the feedback signal V FB The control circuit 300 receives the feedback signal V FB The PWM control signal SPWM is provided to the gate driver 20. Accordingly, the gate driver 20 provides a driving signal (eg, HSG and LSG) to at least one power switch of the switching converter 10 in response to the PWM control signal SPWM.

[0027] Specifically, the control circuit 300 includes a compensation circuit 310, a ramp generation circuit 320, a comparison circuit 330, and a logic circuit 340. The compensation circuit 310 receives the output voltage V OUT and the reference signal V REF , and in response to the output voltage V OUT and the reference signal V REF, a compensation signal Comp is generated. In one embodiment, the feedback circuit 30 generates a feedback signal V OUT representing the output voltage V FB . The ramp generation circuit 320 receives the PWM control signal SPWM and generates a ramp signal Ramp in response to the PWM control signal SPWM. The comparison circuit 330 receives the compensation signal Comp and the ramp signal Ramp and provides a comparison signal S COM in response to the compensation signal Comp and the ramp signal Ramp. The logic circuit 340 receives the comparison signal S COM and the clock signal Clk and provides the control signal SPWM to the gate driver 20 in response to the comparison signal S COM and the clock signal Clk.

[0028] In one embodiment, when the value of the ramp signal Ramp reaches the value of the compensation signal Comp, the PWM control signal SPWM is at a first level (e.g., the drive signal HSG is high or logic high) to turn on the high-side power switch (e.g., switch M1). In one embodiment, the PWM control signal SPWM is at a second level (e.g., low or logic low) in response to the clock signal Clk to turn off the high-side power switch (e.g., switch M1).

[0029] Figure 4 is a circuit block diagram of a ramp generation circuit 400 according to an embodiment of the present disclosure. As Figure 4 shown, the ramp generation circuit 400 includes a PWM filter circuit 410 and a ramp compensation circuit 420. The PWM filter circuit 410 filters the PWM control signal SPWM to generate a first ramp signal Ramp1. In one embodiment, the PWM filter circuit 410 includes a low-pass filter that converts a square wave into a triangular wave. Therefore, the first ramp signal Ramp1 is in phase with the inductor current IL of the switching converter 10.

[0030] The ramp compensation circuit 420 generates a ramp signal S Clk in response to the first ramp signal Ramp1, the PWM control signal SPWM, and the clock signal S RAMP . The ramp signal S RAMP is a periodic signal with a constant frequency, and its frequency is set by the clock signal S Clk . In one embodiment, the ramp compensation circuit 420 includes a frequency control circuit that generates the ramp signal S RAMP in response to an edge (e.g., rising edge or falling edge) of the clock signal. Therefore, the switching frequencies of the high- and low-side power switches can be effectively locked at a constant frequency set by the clock signal S Clk .

[0031] In one embodiment, the ramp generation circuit 400 further includes a high-pass filter circuit 430. The high-pass filter circuit 430 filters the first ramp signal Ramp1 and generates a second ramp signal. For example, the high-pass filter circuit 430 allows a pure AC signal S AC to pass through, and filters out the DC component of the first ramp signal Ramp1. Since the DC component of the first ramp signal Ramp1 is related to the PWM control signal and is determined by the input voltage V IN and the output voltage V OUT , the second ramp signal (e.g., S AC ) is not affected by load transients, thereby improving the transient response of the switching converter. In one embodiment, the ramp generation circuit 400 further includes a bias circuit 440. The bias circuit 440 receives the first ramp signal Ramp1 and adjusts the DC bias of the first ramp signal Ramp1 (e.g., S DC ) to provide a ramp signal S RAMP (e.g., S RAMP = S AC + S DC ). In one embodiment, the DC bias of the first ramp signal Ramp1 (e.g., S DC ) is proportional to the input voltage V IN (e.g., S DC = k * V IN ).

[0032] Figure 5 is a circuit block diagram of a control circuit 500 for a switching converter 12 according to an embodiment of the present disclosure. Similarly, the switching converter 12 receives an input voltage V IN , and provides an output voltage V L to a load R OUT . The gate driver 22 provides drive signals (e.g., HSG and LSG) to the power switches of the switching converter 12 in response to the PWM control signal SPWM.

[0033] As Figure 5 shown, the control circuit 500 includes a compensation circuit 510, a ramp generation circuit 520, a comparison circuit 530, and a logic circuit 540. The compensation circuit 510 receives a feedback signal V FB and a reference signal V REF , and in response to the feedback signal V FB and the reference signal V REFA compensation signal aCOMP is generated. In one embodiment, the compensation circuit 510 includes an error amplifier. The ramp generation circuit 520 receives the PWM control signal SPWM and provides a ramp signal aRAMP. In one embodiment, the ramp generation circuit 520 further includes a PWM filter circuit 522 and a ramp compensation circuit. In one embodiment, the comparison circuit 530 includes a comparator CMP, which receives the compensation signal aCOMP and the ramp signal aRAMP, and provides a comparison signal dPT. In one embodiment, the logic circuit 540 includes an RS latch. The RS latch receives the comparison signal dPT at the set terminal, receives the clock signal dCLK at the reset terminal, and provides the PWM control signal SPWM to the gate driver 22.

[0034] Figure 6 FIG. 600 is a circuit structure diagram of a ramp generation circuit 600 according to an embodiment of the present disclosure. In one embodiment, the ramp generation circuit 600 can be implemented in Figure 5 the control circuit 500 as shown. In another embodiment, the ramp generation circuit 600 can be implemented in Figure 3 the control circuit 300 as shown. As Figure 6 shown, the ramp generation circuit 600 includes a PWM circuit 610, a PWM filter circuit 630, a high-pass filter circuit 640, a bias circuit 650, and a ramp compensation circuit 660. For a high-frequency switching converter, since the current detection signal has a long settling time, using the current detection signal as the ramp signal is not an ideal way. Instead, the PWM filter circuit 630 is used to filter the PWM control signal to be used as the ramp signal of the high-frequency switching converter. For example, the PWM filter circuit 630 includes a low-pass filter, which converts the PWM control signal into a ramp signal. The resistor R RAMP and the capacitor C RAMP are serially coupled to introduce a zero point in the control loop to increase the phase margin to stabilize the system. Specifically, the first end of the resistor R RAMP receives the PWM control signal SPWM, and the second end of the resistor R RAMP is coupled to the first end of the capacitor C RAMP to provide a first ramp signal Ramp1.

[0035] In one embodiment, the AC regulation circuit 620 regulates the AC amplitude of the PWM control signal. The AC regulation circuit 620 includes, for example, a voltage divider.

[0036] The high-pass filter circuit 640 filters the first ramp signal Ramp1. The high-pass filter circuit 640 includes, for example, a capacitor C HPF and a resistor R HPF , the capacitor C HPF and the resistor R HPFCoupled in series to allow a pure AC signal to pass through, while the DC component of the first ramp signal Ramp1 is filtered out, where the DC component of the first ramp signal Ramp1 is related to the output voltage V OUT Specifically, the first terminal of the capacitor C HPF is coupled to the first terminal of the capacitor C RAMP to receive the first ramp signal Ramp1, and the second terminal of the capacitor C HPF is coupled to the first terminal of the resistor R HPF to provide the second ramp signal S AC .

[0037] In one embodiment, the bias circuit 650 adjusts the DC bias of the ramp signal aV RAMP . In some embodiments, when the input voltage V IN is small and the output voltage V OUT is large, the output voltage of the error amplifier (such as Figure 5 the error amplifier 510 shown) responds to the output voltage V OUT and has a relatively large voltage value. As Figure 5 shown, when the output voltage V OUT is large, the ramp signal Ramp1 is also large, and the value of the compensation signal aCOMP also needs to be relatively large to reach the value of the ramp signal aRAMP. In this case, the error amplifier (such as IN the error amplifier 510 shown) receiving a relatively small input voltage V Figure 5 may not work properly because the output voltage (i.e., the compensation signal aCOMP) exceeds its operating range. In one embodiment, by tracking the input voltage V IN and filtering out the output voltage V OUT , the output voltage value of the error amplifier is also proportional to the input voltage V IN . That is, by setting the DC bias of the ramp signal aV RAMP to k*V IN (i.e., k times the input voltage V IN ), even when the input voltage V IN is low, the PWM comparator (such as Figure 5 the comparison circuit 530 shown) can work properly. Therefore, in the steady state, the output voltage of the error amplifier (such as Figure 5 the error amplifier 510 shown) can be a fixed value and is not affected by the output voltage V OUT of the switching converter 12 and the load current, so that the control circuit 500 has a wider operating range (such as a wider output voltage V OUT ). Since the error amplifier (such as Figure 5The output voltage value of the error amplifier 510 shown is constant, and there is no need to charge or discharge the huge compensation circuit of the error amplifier during the transient process, so that the switching converter 12 has a short transient recovery time.

[0038] The bias circuit 650 includes, for example, an operational amplifier op. In Figure 6 the embodiment shown, the bias circuit 650 further includes transistors M1, M2 and resistors R1, R2. Specifically, the first input terminal of the operational amplifier op receives a bias voltage representing the input voltage (e.g., k*V IN ), the output terminal of the operational amplifier op is coupled to the second terminal of the resistor R HPF and the control terminal of the transistor M1, and the second input terminal of the operational amplifier op is coupled to the second terminal of the transistor M1 and the resistor R1. The control terminal of the transistor M2 is coupled to the first terminal of the resistor R HPF , and the second terminal of the transistor M2 is coupled to the resistor R2 to provide a ramp signal aV RAMP_TOP . The transistors M1, M2 should be the same devices to cancel the gate-source voltage Vgs of the transistors. By removing the gate-source voltage Vgs from the DC bias of the ramp signal aV RAMP_TOP , the DC component of the ramp signal aV RAMP (i.e., k*V IN ) is not affected by process, voltage, and temperature (PVT) variations.

[0039] In one embodiment, the ramp compensation circuit 660 includes a compensation capacitor C SLOPE , a current source I SLOPE , and a control switch S1. The current source I SLOPE provides a charging current. The compensation capacitor C SLOPE is serially coupled with the current source I SLOPE . The first terminal of the compensation capacitor C SLOPE receives the ramp signal S AC through the transistor M2, and the second terminal of the compensation capacitor C SLOPE provides the ramp signal aV RAMP . The control switch S1 is coupled in parallel with the compensation capacitor C SLOPE .

[0040] In Figure 6 the embodiment shown, the current source I SLOPE is coupled between the compensation capacitor C SLOPE and ground to discharge the compensation capacitor C SLOPE . Accordingly, the ramp signal aV RAMP is reset by the control switch S1 and is thereby pulled down to reach the value of the compensation signal aCOMP. However, the present disclosure is not limited thereto. In another embodiment, the ramp signal aV RAMPReset by control switch S1 and then pulled high to reach the value of the compensation signal aCOMP. Accordingly, current source I SLOPE is coupled between the supply voltage and compensation capacitor C SLOPE to charge the compensation capacitor C SLOPE .

[0041] Control switch S1 is controlled in response to the clock signal S Clk . The ramp signal aV RAMP is a periodic signal with a constant frequency, and its frequency is set by the clock signal (such as Figures 2 - 3 the clock signal Clk shown, Figure 4 the clock signal S shown, Clk , or Figure 5 the clock signal dCLK shown). In one embodiment, the signal dRAMP_RST is triggered at the rising edge or falling edge of the clock signal (Clk, S Clk , or dCLK) to reset the ramp signal aV RAMP . In one embodiment, control switch S1 is also controlled in response to the PWM control signal (such as dPWM). For example, control switch S1 is reset by the signal dPWM or the signal dRAMP_RST to achieve constant-frequency operation, thus avoiding the switching frequency being lower than the target value. The compensation capacitor C SLOPE and current source I SLOPE improve the noise tolerance of the circuit. When the switching frequency is high, noise appears on the ramp signal aV RAMP . The noise on the ramp signal aV RAMP may erroneously trigger the PWM comparator, resulting in unexpected behavior, such as false triggering of oscillations. The ramp signal aV RAMP is adjusted by the ramp compensation circuit 660 to make the slope of the ramp signal aV RAMP steeper, improving the noise immunity of the circuit. In one embodiment, the slope of the ramp signal aV RAMP depends on the current source I SLOPE , and the current source I SLOPE is determined by the input voltage V IN and the resistor R OSC . The resistor R OSC is related to the switching frequency. For example, the higher the switching frequency, the smaller the resistance value of the resistor R OSC , and the lower the switching frequency, the larger the resistance value of the resistor R OSC . The value of the current source I SLOPE is proportional to the input voltage V IN to suppress the phase attenuation caused by the high-pass filter circuit. That is, the stability of the circuit is not affected by different input voltages.

[0042] Figure 7Schematic diagram of the simulation waveform of the signal of the control circuit 500 according to an embodiment of the present disclosure. As Figure 5 shown, the ramp signal aRAMP crosses the compensation signal aCOMP at time t1, at which time the pulse signal dPT is triggered, the high-side power switch M1 is turned on, and the low-side power switch M2 is turned off (for example: the PWM control signal SPWM is logic high). At time t2, the clock signal dCLK transitions from logic high to logic low, and the signal dRAMP_RST is triggered. The duration of the signal dRAMP_RST should be long enough (for example 5 ns) to complete the reset of the compensation capacitor C SLOPE . After the compensation capacitor C SLOPE is reset, the signal dMIN_OFF is triggered at time t3. When the signal dMIN_OFF is triggered, the PWM control signal SPWM transitions to logic low, that is, the high-side power switch M1 is turned off and the low-side power switch M2 is turned on.

[0043] Figure 8 Schematic diagram of the simulation waveform of the signal of the ramp generation circuit 600 according to an embodiment of the present disclosure. The PWM filter circuit 630 filters the PWM control signal (such as dPWM) to generate a first ramp signal (such as Ramp1). As Figure 8 shown, the first ramp signal Ramp1 is in phase with the inductor current IL, and the amplitude of the first ramp signal Ramp1 is different from that of the inductor current IL. In one embodiment, the AC adjustment circuit 620 adjusts the amplitude of the first ramp signal Ramp1. The DC bias of the first ramp signal Ramp1 is related to the output voltage V OUT . After the first ramp signal Ramp1 is filtered by the high-pass filter circuit 640 and the DC bias of the first ramp signal Ramp1 is adjusted by the bias circuit 650, a ramp signal aV SLOPE is provided at the first end of the compensation capacitor C RAMP_TOP . As Figure 8 shown, the DC bias of the ramp signal aV RAMP_TOP is proportional to the input voltage V IN (for example equal to k*V IN ).

[0044] Specifically, at time t1, the PWM control signal dPWM transitions to a high level, and the control switch S1 is turned on. At the same time, the compensation capacitor C SLOPE is short-circuited and reset to provide a ramp signal aV RAMP . During the conduction of the high-side power switch M1 (for example, the PWM control signal dPWM is at a high level), the ramp signal aV RAMP follows the ramp signal aV RAMP_TOPincreases as it increases. At time t2, the falling edge of the clock signal dCLK is triggered, and the PWM control signal dPWM transitions to a low level to turn off the high-side power switch M1 of the switch converter 12. Accordingly, the high-side power switch M1 turns off and the low-side power switch M2 turns on. At the same time, the signal dRAMP_RST is triggered by the falling edge of the clock signal dCLK. In one embodiment, to achieve constant frequency control, the control switch S1 is reset by the signal dRAMP_RST. Specifically, during the transient period, the PWM control signal dPWM and the switching frequency may change. For example, during the pulse (e.g., high level) of the signal dRAMP_RST, the control switch S1 is turned on to reset the compensation capacitor C SLOPE , while the ramp signal aV RAMP continues to increase as the ramp signal aV RAMP_TOP increases. After the compensation capacitor C SLOPE is fully reset, at time t3, the control switch S1 turns off. During the period when the high-side power switch M1 is off (e.g., the PWM control signal dPWM is at a low level), the ramp signal aV RAMP decreases as the ramp signal aV RAMP_TOP decreases. Since the control switch S1 is off, the current source I SLOPE discharges the compensation capacitor C SLOPE to generate a ramp signal aV RAMP with a steeper slope to improve the noise immunity.

[0045] In Figure 7 and Figure 8 the illustrated embodiments, for example, at times t1, t2, and t3, the signals are all synchronously switched, which is only for illustration purposes and the present disclosure is not limited thereto. In some embodiments, when switching between different states, the delay time between the signals can be set according to the actual application, and there may also be a delay at the rising edge or falling edge. Therefore, the time points of each signal can be adjusted by applying or not applying the delay time to perform the functions of the control circuit of the present disclosure.

[0046] It should be noted that: in Figure 8 the illustrated embodiment, when the value of the ramp signal aV RAMP reaches the value of the compensation signal aCOMP, the high-side power switch M1 turns on (i.e., the PWM control signal dPWM is at a high level), and the high-side power switch M1 turns off in response to the clock signal dCLK (i.e., the PWM control signal dPWM is at a low level). However, the present invention is not limited thereto. In another embodiment, the high-side power switch M1 turns on in response to the clock signal dCLK and turns off when the value of the ramp signal aV RAMP reaches the value of the compensation signal aCOMP.

[0047] Figure 9FIG. 900 is a flow chart of a control method for a switching converter according to an embodiment of the present disclosure. The switching converter includes at least one power switch that converts an input voltage into an output voltage. The control method 900 includes the following operations. In operation 910, a compensation signal is generated in response to a reference signal and a feedback signal representative of the output voltage. In operation 920, a ramp signal is generated. In operation 930, a comparison signal is provided in response to the compensation signal and the ramp signal. In operation 940, a PWM control signal having a first level is provided to turn on the power switch when the value of the ramp signal reaches the value of the compensation signal. In operation 950, a PWM control signal having a second level is provided to turn off the power switch in response to a clock signal. Although Figure 9 the illustrated flow chart shows sequential operations, those skilled in the art should understand that the above operations can be performed in any order.

[0048] It should be understood that the control circuits and related elements, circuit configurations, signals, and waveforms described or illustrated in the present disclosure are for illustrative purposes only, and the present disclosure is not limited thereto. Those skilled in the art can understand that according to the actual application, the control circuit of the present disclosure can be implemented by any other circuit having a different circuit configuration and controlled by different types of signals accordingly to achieve the corresponding functions. For example, the compensation circuit, ramp circuit, comparison circuit, and logic circuit can be implemented using digital circuits, logic circuits, software, or circuits automatically generated by a hardware description language, or a combination of the above methods.

[0049] Based on the above, the present disclosure provides various control circuits and control methods for switching converters. The control circuit of the present disclosure provides a loop control method for a constant-frequency switching converter. In high-frequency applications, the PWM is filtered to obtain a ramp signal, thereby shortening the settling time of the ramp signal. In addition, the ramp generation circuit further includes a high-pass filter circuit for filtering the DC offset of the ramp signal related to the output voltage and load current, thereby improving the transient response. Further, by tracking the input voltage and using the tracked signal as the DC offset of the ramp signal, the switching converter can operate in a wider operating range (e.g., ranges of input voltage, output voltage, and load current). In addition, the ramp compensation circuit provides a ramp current to increase the noise margin and avoid false triggering oscillations.

[0050] Although the present disclosure has been described with reference to several exemplary embodiments, it should be understood that the terms used are descriptive and exemplary rather than restrictive. Since the present disclosure can be embodied in many forms without departing from the spirit or essence of the disclosure, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be broadly construed within the spirit and scope defined by the appended claims, and therefore all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A control circuit for a switching converter, wherein the switching converter includes at least one power switch, the switching converter is configured to convert an input voltage into an output voltage in response to a pulse-width modulation (PWM) control signal, the control circuit comprising: a compensation circuit configured to generate a compensation signal in response to the output voltage and a reference signal; A ramp generating circuit is configured to generate a ramp signal in response to a PWM control signal; a comparison circuit configured to provide a comparison signal in response to the compensation signal and the ramp signal; as well as The logic circuit is configured to provide a PWM control signal in response to the comparison signal and the clock signal.

2. The control circuit as claimed in claim 1, wherein the DC offset of the ramp signal is proportional to the input voltage. 3 . The control circuit of claim 1 , wherein when the voltage value of the ramp signal reaches the voltage value of the compensation signal, the PWM control signal is at a first level.

4. The control circuit of claim 1, wherein the PWM control signal is at a second level in response to a clock signal.

5. The control circuit of claim 1 , wherein the ramp generating circuit comprises: The PWM filter circuit is configured to filter the PWM control signal to generate a first ramp signal.

6. The control circuit of claim 5, wherein the ramp generating circuit further comprises: The high-pass filter circuit is configured to filter the first ramp signal to generate a second ramp signal.

7. The control circuit as claimed in claim 6, wherein the PWM filter circuit comprises a first resistor and a first capacitor, and the high-pass filter circuit comprises a second capacitor and a second resistor; A first end of the first resistor is configured to receive a PWM control signal, and a second end of the first resistor is coupled to a first end of the first capacitor to provide a first ramp signal; and The first end of the second capacitor is coupled to the first end of the first capacitor to receive the first ramp signal, and the second end of the second capacitor is coupled to the first end of the second resistor to provide a second ramp signal.

8. The control circuit of claim 5, wherein the ramp generating circuit further comprises: The bias circuit is configured to receive the first ramp signal and adjust the DC bias of the first ramp signal to provide the ramp signal.

9. The control circuit of claim 8, wherein the ramp generating circuit further comprises: A second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the first end of the first capacitor to receive the first ramp signal; A second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the second end of the second capacitor to provide a second ramp signal; in The bias circuit comprises: An operational amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the operational amplifier is configured to receive a bias voltage, and the output terminal of the operational amplifier is coupled to the second terminal of the second resistor; A first transistor having a first terminal, a second terminal and a control terminal, wherein the control terminal of the first transistor is coupled to the output terminal of the operational amplifier, and the second terminal of the first transistor is coupled to the second input terminal of the operational amplifier; as well as The second transistor has a first terminal, a second terminal and a control terminal, wherein the control terminal of the second transistor is coupled to the first terminal of the second resistor, and the second terminal of the second transistor is configured to provide a third ramp signal.

10. The control circuit of claim 5, wherein the ramp generating circuit further comprises: The slope compensation circuit is configured to generate the ramp signal in response to a first ramp signal and a clock signal, wherein the ramp signal is a periodic signal with a constant frequency, and the frequency of the ramp signal is set by the clock signal. 11 . The control circuit of claim 10 , wherein the slope compensation circuit is configured to generate the ramp signal in response to a PWM control signal.

12. The control circuit of claim 10, wherein the slope compensation circuit comprises: a current source configured to provide a charging current; a compensation capacitor coupled in series with the current source, wherein the compensation capacitor has a first end and a second end, the first end of the compensation capacitor is coupled to the PWM filter circuit to receive the first ramp signal, and the second end of the compensation capacitor is configured to provide the ramp signal; as well as The control switch is coupled in parallel with the compensation capacitor, wherein the control switch is controlled in response to a clock signal and a PWM control signal.

13. A control circuit for a switching converter, wherein the switching converter includes at least one power switch, the switching converter is configured to convert an input voltage into an output voltage in response to a pulse-width modulation (PWM) control signal, the control circuit comprising: A compensation circuit configured to generate a compensation signal in response to a reference signal and a feedback signal representing an output voltage; A ramp generating circuit configured to generate a ramp signal; a comparison circuit configured to provide a comparison signal in response to the compensation signal and the ramp signal; as well as a logic circuit configured to provide a PWM control signal in response to the comparison signal and the clock signal; in When the voltage value of the ramp signal reaches the voltage value of the compensation signal, the PWM control signal is at a first level; as well as The PWM control signal is at a second level in response to the clock signal.

14. The control circuit of claim 13, wherein the ramp signal is generated in response to a PWM control signal.

15. The control circuit of claim 13, wherein a DC offset of the ramp signal is proportional to an input voltage.

16. The control circuit of claim 13, wherein the ramp generating circuit comprises: The PWM filter circuit is configured to filter the PWM control signal to generate a first ramp signal.

17. The control circuit of claim 16, wherein the ramp generation circuit further comprises: The high-pass filter circuit is configured to filter the first ramp signal to generate a second ramp signal.

18. The control circuit of claim 17, wherein the PWM filter circuit comprises a first resistor and a first capacitor, and the high-pass filter circuit comprises a second capacitor and a second resistor; A first end of the first resistor is configured to receive a PWM control signal, and a second end of the first resistor is coupled to a first end of the first capacitor to provide a first ramp signal; and The first end of the second capacitor is coupled to the first end of the first capacitor to receive the first ramp signal, and the second end of the second capacitor is coupled to the first end of the second resistor to provide a second ramp signal.

19. The control circuit of claim 16, wherein the ramp generating circuit further comprises: The bias circuit is configured to receive the first ramp signal and adjust the DC bias of the first ramp signal to provide the ramp signal.

20. The control circuit of claim 19, wherein the ramp generation circuit further comprises: A second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the first end of the first capacitor to receive the first ramp signal; A second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the second end of the second capacitor to provide a second ramp signal; in The bias circuit comprises: An operational amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the operational amplifier is configured to receive a bias voltage, and the output terminal of the operational amplifier is coupled to the second terminal of the second resistor; A first transistor having a first terminal, a second terminal and a control terminal, wherein the control terminal of the first transistor is coupled to the output terminal of the operational amplifier, and the second terminal of the first transistor is coupled to the second input terminal of the operational amplifier; as well as The second transistor has a first terminal, a second terminal and a control terminal, wherein the control terminal of the second transistor is coupled to the first terminal of the second resistor, and the second terminal of the second transistor is configured to provide a third ramp signal.

21. The control circuit of claim 16, wherein the ramp generation circuit further comprises: The slope compensation circuit is configured to generate the ramp signal in response to a first ramp signal, a clock signal, and a PWM control signal, wherein the ramp signal is a periodic signal with a constant frequency, and the frequency is set by the clock signal.

22. The control circuit of claim 21, wherein the slope compensation circuit comprises: a current source configured to provide a charging current; a compensation capacitor coupled in series with the current source, wherein the compensation capacitor has a first end and a second end, the first end of the compensation capacitor is coupled to the PWM filter circuit to receive the first ramp signal, and the second end of the compensation capacitor is configured to provide the ramp signal; as well as The control switch is coupled in parallel with the compensation capacitor, wherein the control switch is controlled in response to a clock signal and a PWM control signal.

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