DCDC converter

Abstract

On the basis of an existing DCDC converter, an error evaluation circuit and a multiplexer are additionally arranged to control output of a digital compensation circuit, a rapid feedback path is additionally arranged, and in the response period of load abrupt change, the output of the digital compensation circuit is directly changed to be a preset high duty ratio or a preset low duty ratio. And when the load suddenly changes, a response can be quickly made.

Description

Technical Field

[0001] The present invention relates to power supply design technology, and particularly to a DCDC converter. Background Art

[0002] A digitally controlled DCDC (direct current - direct current) converter can provide stronger driving ability and higher conversion efficiency, and thus is preferably applied in high - performance microprocessors. Compared with the analog control method, the digitally controlled DCDC converter has advantages such as strong anti - interference ability, easy transplantation and upgrade.

[0003] Figure 1 Shown is an overall block diagram of a typical digitally controlled DCDC converter. The DCDC converter consists of an internal control module and external discrete devices. The external discrete devices include NMOS transistors, PMOS transistors, inductors, and capacitors, which form a power stage to generate the load operating voltage VDD by controlling the conduction of the MOS transistors. The internal control module includes an error monitoring circuit, an analog - to - digital converter (ADC), a digital compensator, a digital pulse - width modulation circuit (Digital PWM), and a gate driver circuit for driving the external MOS transistors. The error monitoring circuit divides the load operating voltage VDD to obtain a feedback voltage Vfb. The feedback voltage Vfb is compared with a reference voltage Vref to obtain an analog error quantity e[t], and the analog error quantity e[t] is input to the ADC to be converted into an error digital quantity e[n]. The digital compensator is the core of the DCDC digital control. It compensates the error quantity through a control algorithm, calculates the duty cycle d[n] for controlling the complementary MOS transistors. The digital pulse - width modulation circuit (Digital PWM) generates a pulse signal Cpulse with a fixed frequency and a corresponding duty cycle according to the duty cycle d[n], and controls the gates of the external MOS transistors through the gate driver circuit (Gate Driver).

[0004] There are many control algorithms for digital compensator circuits. The PID (proportional - integral - derivative control) algorithm is one of the most widely used and technically mature ones. It has advantages such as simple principle, easy implementation, and mature parameter - tuning strategies. For a continuous control system, the transfer function of the PID algorithm can be expressed as:

[0005] Gcs = Kp+Ki / s+Kd*s;

[0006] Where Kp, Ki, and Kd correspond to the proportional coefficient, integral coefficient, and derivative coefficient respectively. For the digital - control PID algorithm, its control function in the discrete domain can be expressed as:

[0007]

[0008] Figure 2 Shows a basic block diagram of a PID algorithm.

[0009] Due to the characteristics of the PID algorithm itself, when there is a large disturbance in the system, the system has inertia and hysteresis. Under the action of the integral term, there are often large overshoots and long-time fluctuations. Therefore, the dynamic response ability of the DCDC converter controlled by PID is usually poor. When the load suddenly increases or decreases rapidly, large over-drop voltages or overshoot voltages will be generated, and it takes a long time to recover to the steady state. Summary of the Invention

[0010] The technical problem to be solved by the present invention is to provide a DCDC (direct current - direct current) converter that can respond quickly when the load changes suddenly.

[0011] To solve the above technical problem, the DCDC converter provided by the present invention includes an internal control module and an external power stage output circuit;

[0012] The internal control module includes an error monitoring circuit, an analog - to - digital converter, a digital compensation circuit, a multiplexer, an error evaluation circuit, a digital pulse width modulation circuit, and a drive circuit;

[0013] The error monitoring circuit is used to compare the feedback voltage obtained by dividing the load operating voltage output by the external power stage output circuit with the reference voltage to obtain an analog error amount, and the analog error amount is the difference between the reference voltage and the feedback voltage;

[0014] The analog - to - digital converter is used to convert the analog error amount into a digital error amount e[n], where n is a positive integer;

[0015] The digital compensation circuit is used to calculate and output an error duty cycle d[n] according to the digital error amount e[n];

[0016] The error evaluation circuit is provided with an error monitoring window threshold Ew, the input terminal is connected to the digital error amount e[n], one output terminal outputs a CH control signal, and the other output terminal outputs a CL control signal; the error monitoring window threshold Ew is a positive number;

[0017] For the error evaluation circuit, when e[n]>Ew and e[n]–e[n - 1]≥0, the CH control signal is 1 and the CL control signal is 0;

[0018] When e[n]>Ew and e[n]–e[n - 1]<0, both the CH control signal and the CL control signal are 0;

[0019] When e[n] < -Ew and e[n] – e[n-1] ≤ 0, the CL control signal is 1 and the CH control signal is 0;

[0020] When e[n] < -Ew and e[n] – e[n-1] > 0, both the CH control signal and the CL control signal are 0;

[0021] When -Ew ≤ e[n] ≤ Ew, both the CH control signal and the CL control signal are 0;

[0022] For the multiplexer, its three input terminals are respectively connected to the error duty cycle d[n], the preset high duty cycle DH, and the preset low duty cycle DL, and its two control terminals are respectively connected to the CH control signal and the CL control signal;

[0023] For the multiplexer, when both the CH control signal and the CL control signal are 0, the output is the error duty cycle d[n]; when the CH control signal is 1 and the CL control signal is 0, the output is the preset high duty cycle DH; when the CH control signal is 0 and the CL control signal is 1, the output is the preset low duty cycle DL;

[0024] For the digital pulse width modulation circuit, according to the output of the multiplexer, it outputs a PWM pulse signal with a corresponding duty cycle to the drive circuit;

[0025] The drive circuit is used to amplify the PWM pulse signal output by the multiplexer and then output it to the external power stage output circuit;

[0026] The external power stage output circuit includes a power switch tube;

[0027] The external power stage output circuit controls the on / off of the power switch tube according to the output of the drive circuit and outputs the load operating voltage.

[0028] Preferably, the error monitoring window threshold Ew is a configurable variable;

[0029] Both the preset high duty cycle DH and the preset low duty cycle DL are configurable variables.

[0030] Preferably, the digital compensation circuit is a PID compensator.

[0031] Preferably, the control function of the PID compensator in the discrete domain is:

[0032]

[0033] Kp is the proportional coefficient, Ki is the integral coefficient, and Kd is the differential coefficient.

[0034] Preferably, when e[n] > Ew or e[n] < -Ew, the control function of the PID compensator in the discrete domain is:

[0035]

[0036] A is greater than 1.

[0037] Preferably, the external power stage output circuit includes a first PMOS transistor MP1, a first NMOS transistor MN1, a first inductor L1, and a first capacitor C1;

[0038] The source terminal of the first PMOS transistor MP1 is connected to the external operating voltage VEXT;

[0039] The drain terminal of the first PMOS transistor MP1 is shorted to the drain terminal of the first NMOS transistor MN1;

[0040] One end of the first inductor L1 is connected to the drain terminal of the first PMOS transistor MP1, and the other end is connected to one end of the first capacitor C1 and serves as the output terminal of the load operating voltage VDD;

[0041] The other end of the first capacitor C1 is grounded;

[0042] The source terminal of the first NMOS transistor MN1 is grounded;

[0043] The gate terminals of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected to the output terminal of the driving circuit.

[0044] Preferably, the first PMOS transistor MP1, the first NMOS transistor MN1, the first inductor L1, and the first capacitor C1 are discrete devices;

[0045] The internal control module is integrated in the same chip.

[0046] Preferably, the error monitoring circuit includes a first resistor R1 and a second resistor R2;

[0047] The first resistor R1 and the second resistor R2 are connected in series between the output terminal of the load operating voltage and the ground;

[0048] The series connection point of the first resistor R1 and the second resistor R2 serves as the feedback voltage connection point.

[0049] The DCDC (Direct Current - Direct Current) converter of the present invention, based on the existing DCDC converter, adds an error evaluation circuit (Error Estimator) and a multiplexer MUX to control the output of the digital compensation circuit, adds a fast feedback path, and directly changes the output of the digital compensation circuit to a preset high Duty (duty cycle) DH or a preset low Duty (duty cycle) DL during the response period of the load mutation, enabling the DCDC converter to respond quickly when the load mutates. Description of the Drawings

[0050] To more clearly illustrate the technical solution of the present invention, the following briefly introduces the attached drawings required for the present invention. Obviously, the attached drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other attached drawings can also be obtained based on these attached drawings.

[0051] Figure 1 is an overall block diagram of a typical existing digitally controlled DCDC converter;

[0052] Figure 2 is a basic PID algorithm circuit;

[0053] Figure 3 is a schematic diagram of a module of an embodiment of the DCDC converter of the present invention;

[0054] Figure 4 is a functional block diagram of an error evaluation circuit of an embodiment of the DCDC converter of the present invention;

[0055] Figure 5 is the circuit working timing when the load of an embodiment of the DCDC converter of the present invention suddenly changes;

[0056] Figure 6 is a schematic diagram comparing the load current changes of an embodiment of the DCDC converter of the present invention with those of an existing DCDC converter. Detailed implementation manners

[0057] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the attached drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0058] The "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. The terms such as "include" or "comprise" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connect" or "be connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "up", "down", "left", "right" are only used to represent relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0059] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0060] Embodiment 1

[0061] A DCDC (Direct Current to Direct Current) converter, as Figure 3 shown, includes an internal control module and an external power stage output circuit;

[0062] The internal control module includes an error monitoring circuit, an analog-to-digital converter (ADC), a digital compensation circuit, a multiplexer MUX, an error evaluation circuit (Error Estimator), a digital pulse width modulation circuit (Digital PWM), and a drive circuit (Gate Driver);

[0063] The error monitoring circuit is used to compare the feedback voltage Vfb obtained by dividing the load operating voltage VDD output by the external power stage output circuit with the reference voltage Vref to obtain an analog error amount e[t]. The analog error amount e[t] is the difference between the reference voltage Vref and the feedback voltage Vfb;

[0064] The analog-to-digital converter (ADC) is used to convert the analog error amount e[t] into a digital error amount e[n], where n is a positive integer;

[0065] The digital compensation circuit is used to calculate and output an error duty cycle d[n] according to the digital error amount e[n];

[0066] The error evaluation circuit (Error Estimator) is provided with an error monitoring window threshold Ew. Its input terminal is connected to the digital error amount e[n], one output terminal outputs a CH control signal, and the other output terminal outputs a CL control signal; the error monitoring window threshold Ew is a positive number and is a configurable variable.

[0067] As Figure 4 、 Figure 5 shown, for the error evaluation circuit (Error Estimator), when e[n]>Ew and e[n]–e[n-1]≥0, the CH control signal is 1 and the CL control signal is 0;

[0068] When e[n]>Ew and e[n]–e[n-1]<0, both the CH control signal and the CL control signal are 0;

[0069] When e[n]<-Ew and e[n]–e[n-1]≤0, the CL control signal is 1 and the CH control signal is 0;

[0070] When e[n] < -Ew and e[n] – e[n - 1] > 0, both the CH control signal and the CL control signal are 0;

[0071] When -Ew ≤ e[n] ≤ Ew, both the CH control signal and the CL control signal are 0;

[0072] For the multiplexer MUX, its three input terminals are respectively connected to the error duty cycle d[n], the preset high Duty (duty cycle) DH, and the preset low Duty (duty cycle) DL, and its two control terminals are respectively connected to the CH control signal and the CL control signal;

[0073] For the multiplexer MUX, when both the CH control signal and the CL control signal are 0, the output is the error duty cycle d[n]; when the CH control signal is 1 and the CL control signal is 0, the output is the preset high Duty (duty cycle) DH; when the CH control signal is 0 and the CL control signal is 1, the output is the preset low Duty (duty cycle) DL;

[0074] The digital pulse width modulation circuit (Digital PWM) outputs a PWM (pulse width modulation) pulse signal (Cpulse) with a corresponding duty cycle to the drive circuit (Gate Driver) according to the output of the multiplexer MUX;

[0075] The drive circuit (Gate Driver) is used to amplify the PWM pulse signal (Cpulse) output by the multiplexer MUX and then output it to the external power stage (Power stage) output circuit;

[0076] The external power stage (Power stage) output circuit includes a power switch tube;

[0077] The external power stage (Power stage) output circuit controls the on - off of its power switch tube according to the output of the drive circuit (Gate Driver) and outputs the load operating voltage VDD.

[0078] The error monitoring window threshold Ew is a configurable variable.

[0079] The preset high Duty (duty cycle) DH and the preset low Duty (duty cycle) DL are both configurable variables, and usually appropriate values are selected according to the turn - on time of the power switch tube of the external power stage (Power stage) output circuit, the dead time of the drive circuit (Gate Driver), and the magnitudes of the external operating voltage VEXT of the external power stage (Power stage) output circuit and the target value of the load operating voltage VDD.

[0080] When |e[n]| < Ew, both the CH control signal and the CL control signal are 0. At this time, the output of the multiplexer MUX is the output D[n] of the digital compensation circuit. When the load of the DCDC converter suddenly increases and the load operating voltage VDD has a large overvoltage drop, causing e[n] > Ew, the CH control signal changes from 0 to 1 to control the multiplexer MUX to output a preset high Duty value DH, quickly suppressing the continuous decrease of the load operating voltage VDD until the load operating voltage VDD reaches an inflection point and the error digital quantity becomes smaller, that is, when e[n] – e[n-1] < 0, the CH control signal changes from 1 to 0 to make the multiplexer MUX continue to output the output D[n] of the digital compensation circuit, which can effectively suppress the overshoot phenomenon of the load operating voltage VDD.

[0081] Similarly, when the load suddenly decreases and the load operating voltage VDD has a large overshoot voltage, e[n] < -Ew, the change of the CL control signal is also as described above, controlling the output of the multiplexer MUX, and the output D[n] of the digital compensation circuit becomes a preset low Duty value DL until the load operating voltage VDD reaches an inflection point and then changes back to the output D[n] of the digital compensation circuit.

[0082] The DCDC (direct current - direct current) converter of Embodiment 1 adds an error evaluation circuit (Error Estimator) and a multiplexer MUX on the basis of the existing DCDC converter to control the output of the digital compensation circuit, adding a fast feedback path. During the response period of load mutation, the output of the digital compensation circuit is directly changed to a preset high Duty (duty cycle) DH or a preset low Duty (duty cycle) DL, enabling the DCDC converter to respond quickly when the load mutates.

[0083] The working timing of the DCDC (direct current - direct current) converter of Embodiment 1 during load mutation is as Figure 5 shown.

[0084] The comparison of the load current changes between the DCDC (direct current - direct current) converter of Embodiment 1 and the existing DCDC converter is as Figure 6 shown. When there is a 500 mA mutation in the load current, the maximum overvoltage of the existing DCDC converter is 70 mV, and the time required to return to the steady state is 80 us; the maximum overvoltage of the DCDC converter of Embodiment 1 is 35 mV, and the time required to return to the steady state is 45 us.

[0085] Embodiment 2

[0086] Based on the DCDC (direct current - direct current) converter of Embodiment 1, the digital compensation circuit is a PID (proportional - integral - derivative control) compensator.

[0087] Embodiment III

[0088] Based on the DCDC (Direct Current to Direct Current) converter of Embodiment II, the transfer function of the PID compensator is:

[0089] Gcs = Kp + Ki / s + Kd*s;

[0090] Where s is the digital error quantity e[n], Gcs is the error duty cycle d[n], Kp is the proportional coefficient, Ki is the integral coefficient, and Kd is the differential coefficient.

[0091] The control function of the PID compensator in the discrete domain can be expressed as:

[0092]

[0093] Kp is the proportional coefficient, Ki is the integral coefficient, and Kd is the differential coefficient.

[0094] Preferably, when e[n] > Ew or e[n] < -Ew, the control function of the PID compensator in the discrete domain is:

[0095] A is greater than 1. During the response to load mutation, increasing the proportional term coefficient can improve the response speed of the PID itself.

[0096] Embodiment IV

[0097] Based on the DCDC (Direct Current to Direct Current) converter of Embodiment II, the output circuit of the external power stage includes a first PMOS transistor MP1, a first NMOS transistor MN1, a first inductor L1, and a first capacitor C1;

[0098] The source terminal of the first PMOS transistor MP1 is connected to the external operating voltage VEXT;

[0099] The drain terminal of the first PMOS transistor MP1 is short-circuited to the drain terminal of the first NMOS transistor MN1;

[0100] One end of the first inductor L1 is connected to the drain terminal of the first PMOS transistor MP1, and the other end is connected to one end of the first capacitor C1 and serves as the output terminal of the load operating voltage VDD;

[0101] The other end of the first capacitor C1 is grounded;

[0102] The source terminal of the first NMOS transistor MN1 is grounded;

[0103] The gate terminals of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected to the output terminal of the gate driver.

[0104] Preferably, the first PMOS transistor MP1, the first NMOS transistor MN1, the first inductor L1, and the first capacitor C1 are discrete devices; the internal control module is integrated in the same chip.

[0105] The DCDC (direct current to direct current) converter of Embodiment 4 controls the conduction of the first PMOS transistor MP1 and the first NMOS transistor MN1 of the external power stage output circuit through a pulse signal with a fixed frequency and a corresponding duty cycle output by the drive circuit (Gate Driver) to generate the load operating voltage VDD.

[0106] Embodiment 5

[0107] Based on the DCDC (direct current to direct current) converter of Embodiment 1, the error monitoring circuit includes a first resistor R1 and a second resistor R2;

[0108] The first resistor R1 and the second resistor R2 are connected in series between the output terminal of the load operating voltage VDD and the ground;

[0109] The series connection point of the first resistor R1 and the second resistor R2 serves as the connection point of the feedback voltage Vfb.

[0110] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A DCDC converter, characterized in that, It includes an internal control module and an external power stage output circuit; The internal control module includes an error monitoring circuit, an analog-to-digital converter, a digital compensation circuit, a multiplexer, an error evaluation circuit, a digital pulse width modulation circuit, and a drive circuit; The error monitoring circuit is used to compare the feedback voltage obtained by dividing the load operating voltage output by the external power stage output circuit with the reference voltage to obtain an analog error amount, and the analog error amount is the difference between the reference voltage and the feedback voltage; The analog-to-digital converter is used to convert the analog error amount into a digital error amount e[n], where n is a positive integer; The digital compensation circuit is used to calculate and output an error duty cycle d[n] according to the digital error amount e[n]; The error evaluation circuit is provided with an error monitoring window threshold Ew, the input terminal is connected to the digital error amount e[n], one output terminal outputs a CH control signal, and the other output terminal outputs a CL control signal; the error monitoring window threshold Ew is a positive number; In the error evaluation circuit, when e[n]>Ew and e[n]–e[n-1]≥0, the CH control signal is 1 and the CL control signal is 0; When e[n]>Ew and e[n]–e[n-1]<0, both the CH control signal and the CL control signal are 0; When e[n]<-Ew and e[n]–e[n-1]≤0, the CL control signal is 1 and the CH control signal is 0; When e[n]<-Ew and e[n]–e[n-1]>0, both the CH control signal and the CL control signal are 0; When -Ew≤e[n]≤Ew, both the CH control signal and the CL control signal are 0; The multiplexer has three input terminals respectively connected to the error duty cycle d[n], a preset high duty cycle DH, and a preset low duty cycle DL, and two control terminals are respectively connected to the CH control signal and the CL control signal; For the multiplexer, when both the CH control signal and the CL control signal are 0, the output is the error duty cycle d[n]; when the CH control signal is 1 and the CL control signal is 0, the output is the preset high duty cycle DH; when the CH control signal is 0 and the CL control signal is 1, the output is the preset low duty cycle DL; The digital pulse width modulation circuit outputs a PWM pulse signal with a corresponding duty cycle to the drive circuit according to the output of the multiplexer; The drive circuit is used to amplify the PWM pulse signal output by the multiplexer and output it to the external power stage output circuit; The external power stage output circuit includes a power switch tube; The external power stage output circuit controls the on and off of the power switch tube according to the output of the drive circuit and outputs the load operating voltage.

2. The DCDC converter according to claim 1, characterized in that, The error monitoring window threshold Ew is a configurable variable; Both the preset high duty cycle DH and the preset low duty cycle DL are configurable variables.

3. The DCDC converter according to claim 1, characterized in that, The digital compensation circuit is a PID compensator.

4. The DCDC converter according to claim 3, characterized in that, The control function of the PID compensator in the discrete domain is: Kp is the proportional coefficient, Ki is the integral coefficient, and Kd is the differential coefficient.

5. The DCDC converter according to claim 4, characterized in that, When e[n]>Ew or e[n]<-Ew, the control function of the PID compensator in the discrete domain is: A is greater than 1.

6. The DCDC converter according to claim 1, characterized in that, The external power stage output circuit includes a first PMOS transistor (MP1), a first NMOS transistor (MN1), a first inductor (L1), and a first capacitor (C1); The source terminal of the first PMOS transistor (MP1) is connected to the external operating voltage (VEXT); The drain terminal of the first PMOS transistor (MP1) is short-circuited to the drain terminal of the first NMOS transistor (MN1); One end of the first inductor (L1) is connected to the drain terminal of the first PMOS transistor (MP1), and the other end is connected to one end of the first capacitor (C1) and serves as the output terminal of the load operating voltage (VDD); The other end of the first capacitor (C1) is grounded; The source terminal of the first NMOS transistor (MN1) is grounded; The gate terminal of the first PMOS transistor (MP1) and the gate terminal of the first NMOS transistor (MN1) are connected to the output terminal of the driving circuit.

7. The DCDC converter according to claim 6, wherein, The first PMOS transistor (MP1), the first NMOS transistor (MN1), the first inductor (L1), and the first capacitor (C1) are discrete devices; The internal control module is integrated in the same chip.

8. The DCDC converter according to claim 1, wherein, The error monitoring circuit includes a first resistor (R1) and a second resistor (R2); The first resistor (R1) and the second resistor (R2) are connected in series between the output terminal of the load operating voltage and the ground; the series connection point of the first resistor (R1) and the second resistor (R2) serves as the feedback voltage connection point.

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