Push-pull active differential clamping class-E power amplifier

Abstract

The invention discloses a push-pull active differential clamping class-E power amplifier, which comprises a push-pull class-E power amplifier, the push-pull class-E power amplifier comprises a main power switch Q1 and a main power switch Q2 for realizing conversion from direct current to alternating current, and the structures of the main power switches Q1 and Q2 are complementary or symmetrical; two ends of the output differential capacitor CQ1 are respectively connected with the drain electrode and the source electrode of the Q1, two ends of the differential capacitor CQ2 are respectively connected with the drain electrode and the source electrode of the Q2, and two ends of the output differential capacitor CQ are respectively connected with the drain electrode of the Q1 and the drain electrode of the Q2; two ends of the differential capacitor CQ are respectively connected with a load R through a resonant network; the circuit also comprises a push-pull active auxiliary circuit, and the push-pull active auxiliary circuit and the differential capacitor form a clamping circuit. Voltage stress and current stress can be effectively reduced through the active differential capacitor, the power output capacity is improved, ZVS turn-on and soft turn-off can be achieved through the push-pull auxiliary switch in the full-load range, a charging and discharging path is only provided for the differential capacitor, and the characteristic of low power consumption is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics and relates to a push-pull active differential clamped Class-E power amplifier. Background Art

[0002] Class-E power amplifiers are widely used in fields such as communication, wireless power transfer, and induction heating due to their simple structure and control, and the ability to achieve ZVS / ZVDS turn-on. The push-pull Class-E power amplifier has four times the output power capacity of the Class-E power amplifier and has broad application value in these high-power fields; the traditional push-pull Class-E power amplifier has a simple structure and easy drive implementation. It has the advantages of zero voltage switching (ZVS) and zero voltage derivative switching (ZVDS) on the optimal load. Therefore, it has higher output power conversion efficiency and power output ability. Moreover, it adopts a push-pull structure, which can achieve lower harmonic output, and has many advantages such as simple control and high efficiency; it can be widely used in high-power application scenarios of several MHz or even dozens of MHz.

[0003] However, the traditional push-pull Class-E power amplifier has high voltage stress and current stress, which limits its application in actual use. The utilization rate of transistors is low, it is difficult to meet the requirements of higher power, and the selection requirements for MOSFETs are high. There is an urgent need for a new structure of push-pull Class-E power amplifier to solve the problems of high voltage stress, high current stress, and low output power of the traditional push-pull Class-E amplifier.

[0004] To solve the problems of high voltage and current stress of the push-pull Class-E power amplifier (inverter), the common existing method is to add a parallel LC network at both ends of the transistor output. The main solution is to adjust the resonance frequency of the LC network to three times the working frequency of the power amplifier, and the introduced third harmonic will be superimposed on the original fundamental component to form a shape similar to a saddle wave. By this method of introducing harmonics, the problem of high voltage stress is reduced.

[0005] The existing push-pull Class-E power amplifiers mainly have the following disadvantages:

[0006] 1. It has very high voltage stress. When the duty cycle D of the driving signal PWM = 0.5, the voltage across the transistor (MOSFET) at the optimal load is 3.63 VDC. Where VDC is the bus input voltage of the push-pull Class-E power amplifier. When the duty cycle decreases, the voltage stress will increase, and when the load decreases, the voltage stress will also increase.

[0007] 2. It has a relatively high current stress. When the duty cycle D of the driving signal PWM = 0.5, the current stress across the transistor (MOSFET) at the optimal load is 2.86IDC1. Here, IDC1 is the bus current of one of the chokes in the push - pull class - E power amplifier. When the load decreases, the current stress will increase.

[0008] 3. When the push - pull class - E power amplifier is used as an inverter, when transmitting high power, MOSFETs with higher voltage and current are required, which is limited by device selection, and MOSFETs with high voltage and current have higher costs.

[0009] 4. Due to the existence of high voltage stress and current stress, it will limit the maximum power output ability of the push - pull class - E power amplifier. Summary of the Invention

[0010] To solve the above problems, the present invention provides a push - pull active differential - clamped class - E power amplifier. Through the active differential capacitor, the voltage stress and current stress can be effectively reduced, the power output ability can be improved, and the push - pull auxiliary switches can achieve ZVS turn - on and soft turn - off in the full load range, only providing a charging and discharging path for the differential capacitor, and having the characteristic of low power consumption.

[0011] The technical solution adopted by the present invention is a push - pull active differential - clamped class - E power amplifier, including a push - pull class - E power amplifier. The push - pull class - E power amplifier includes main power switches Q1 and Q2 for realizing DC - to - AC conversion. Both Q1 and Q2 are MOSFETs, and their structures are complementary or symmetric; both ends of the output differential capacitor C Q1 are respectively connected to the drain and source of the main power switch Q1, and both ends of the differential capacitor C Q2 are respectively connected to the drain and source of the main power switch Q2. Both ends of the output differential capacitor C Q are respectively connected to the drain of the main power switch Q1 and the drain of the main power switch Q2; both ends of the differential capacitor C Q are respectively connected to the load R through a resonant network;

[0012] It further includes a push - pull active auxiliary circuit, and the push - pull active auxiliary circuit and the differential capacitor form a clamping circuit.

[0013] Furthermore, the push - pull active auxiliary circuit includes two symmetric auxiliary switches S1 and S2. Both S1 and S2 are MOSFETs; the choke coil L m1 is in parallel with the choke coil L m2 , and the input end of the choke coil L m1 is connected to the positive pole of the input bus; the source of the auxiliary switch S1 is connected to the choke coil L m2 m1 ​The output terminal and the drain of the main power switch Q1, and the source of the auxiliary switch S2 is connected to the choke coil L m2 The output terminal and the drain of the main power switch Q2; the choke coil L m1 Is connected to the choke coil L m2 The parallel node with the choke coil L is connected to the negative pole of the clamping differential capacitor C LS The drain connection point of the auxiliary switches S1 and S2 is connected to the positive pole of the differential capacitor C LS The auxiliary switches S1 and S2 are used to clamp the voltage on Q1 or Q2 when the main power switch Q1 or Q2 is turned off.

[0014] Furthermore, the sources of the main power switches Q1 and Q2 are connected and grounded, and the drains of the main power switches Q1 and Q2 are connected to the resonant network.

[0015] Furthermore, the resonant network is composed of resonant capacitors C S1 、C S2 Connected in series with the resonant inductors L1 and L2, and the load R is connected in series with the resonant network. The resonant frequency is the operating frequency of the main power switch Q1, the main power switch Q2, the auxiliary switch S1, and the auxiliary switch S2.

[0016] Furthermore, only one of the main power switches Q1 and Q2 is operating, and only one of the auxiliary switches S1 and S2 is operating. The operating frequencies f of the main power switch Q1, the main power switch Q2, the auxiliary switch S1, and the auxiliary switch S2 are the same, that is, the time period is T.

[0017] Furthermore, the operating timing sequence of the auxiliary switch and the main power switch in the first half cycle is as follows:

[0018] Before the moment t0, the main power switch Q1 is turned off, Q2 is turned on, and the auxiliary switches S1 and S2 are both turned off; at this time, the charge of the differential capacitor C Q1 Has been extracted, the body diode of the main power switch Q1 is turned on, and the voltage at the main power switch Q1 terminal is clamped to nearly 0V;

[0019] At the moment t0, the main power switch Q1 is turned on to achieve ZVS turn-on; the main power switch Q2 is turned off. Due to the existence of the differential capacitors C Q2 And C Q , a ZVS soft turn-off process is achieved; the auxiliary switches S1 and S2 are both in the off state; after the moment t0, the differential capacitors C Q2 And C Q Will be charged;

[0020] At the moment t1, when the capacitor voltages of the differential capacitors C Q2 And C Q Reach When, the body diode D of the auxiliary switch S2S2 is turned on, where is the steady-state voltage value of the differential capacitor C LS , and V DC is the input bus voltage; at this time, the differential capacitors C LS , C Q2 and C Q are charged simultaneously, and the voltage stress of the main power switch Q2 is clamped to with fluctuations up and down;

[0021] At time t2, the auxiliary switch S2 is closed to achieve ZVS turn-on. The differential capacitor C LS continues to be actively charged slowly with i CLs , and i CLs is the input current of the differential capacitor C LS ;

[0022] At time t3, when the input current I Q at one end of the differential capacitor C DC2 connected to the drain of the main power switch Q2 + i0 = 0, the inflowing current will reverse; at this time, the differential capacitors C LS , C Q2 and C Q release the stored charge to the load R simultaneously according to the current ratio, and the voltage stress clamped on the main power switch Q2 reaches the maximum;

[0023] At time t4, the auxiliary switch S2 is turned off. Due to the existence of the differential capacitors C LS and C Q , the ZVS soft turn-off process is achieved; at this time, the differential capacitor C LS stops discharging, and the differential capacitors C Q2 and C Q continue to release charge to the resonant network according to the current ratio, and the voltage stress of the main power switch Q2 starts to decrease at time t4;

[0024] The said current ratio is shown in the following formula:

[0025]

[0026] In the formula, γ and k are the proportionality coefficients of the differential capacitors C Q and relative to C EQ , C EQ is the total equivalent output capacitance value of the main power switches Q1 and Q2; i CQ2 is the current of the differential capacitor C Q2 , i CQ is the current of the differential capacitor C Q , i CLs is the input current of the differential capacitor C LS ;

[0027] At time t5, the charges of the capacitors in differential capacitors C Q2 and C Q are all extracted. When the turn-on timing of the main power switch Q2 has not arrived, i.e., t5 < t6; the differential capacitors C Q2 and C Q are reversely charged until the body diode D Q2 conducts, and the differential capacitors C Q2 and C Q are clamped to stop charging; the voltage of the main power switch Q2 is clamped to 0; when the turn-on timing of the main power switch Q1 arrives, ZVS turn-on is achieved, and the main power switch Q2 achieves ZVS soft turn-off.

[0028] Furthermore, the expression of the maximum voltage stress U Q2 clamped on the main power switch Q2 is as follows:

[0029] U Q2 = V DC + U CLS0 + Δμ

[0030]

[0031] In the formula, Δu is the maximum peak point of the clamped voltage fluctuation, k is the proportionality coefficient of the differential capacitor relative to C EQ , C EQ is the total equivalent output capacitance value of the main power switches Q1 and Q2; i0 is the output current of the resonant network, I DC2 is the average current of the choke coil L m2 ; the voltage stress of the main power switch Q2 is clamped;

[0032] The expression of the current i Q1 of the main power switch Q1 is as follows:

[0033] i Q1 = I DC1 - i0 - i CQ

[0034] In the formula, I DC1 is the average current of the choke coil L m1 , i CQ is the current of the differential capacitor C Q ; the current stress of the main power switch Q1 is weakened.

[0035] Furthermore, when k >> γ, Δμ is negligible, and the maximum voltage stress U Q2 depends on D and Ds, and is theoretically at least 2V DC; D is the duty cycle of the driving waveforms of the main power switches Q1 and Q2, and Ds is the duty cycle of the driving waveforms of the auxiliary switches S1 and S2.

[0036] Further, if there is a non-negligible proportional relationship between k and γ, the current on the differential capacitor is strictly distributed according to the current ratio, and the maximum value of the maximum voltage stress clamped on the main power switch Q2 is U Q2MAX See the following formula:

[0037]

[0038] Increasing κ can reduce the magnitude of the voltage stress;

[0039] When the values of κ and γ are comparable, the differential capacitor C Q has a larger current, so the current flowing through the main power switch Q1 is minimized, thereby reducing the magnitude of the current stress.

[0040] The beneficial effects of the present invention are:

[0041] 1. Aiming at the high voltage stress problem of the traditional push-pull class-E power amplifier, the present invention reduces the voltage stress through a push-pull active auxiliary switch. When the duty cycle D of the driving PWM = 0.5 and the duty cycle DS of the auxiliary switch = 0.48, at the optimal load, the minimum voltage stress that can be achieved across the MOSFET is about 2VDC, which can be reduced by up to 45.5% compared to the traditional case. And the magnitude of the stress hardly changes with the load.

[0042] 2. Aiming at the high voltage stress problem of the traditional push-pull class-E power amplifier, the present invention reduces the current stress or the magnitude of the root mean square of the current through a differential capacitor. When the duty cycle D of the driving PWM = 0.5 and the duty cycle DS of the auxiliary switch = 0.48, at the optimal load, the minimum current stress that can be achieved across the MOSFET is about 2I DC1 or so. It can be reduced by up to 30% compared to the traditional case.

[0043] 3. For the circuit topology of the present invention, the auxiliary switch has zero-voltage-switching (ZVS) turn-on and soft turn-off over the full load range, with small power losses and will not introduce excessive power losses.

[0044] 4. The voltage and current stresses of the circuit topology of the present invention can be adjusted through the proportional relationship of the differential capacitor. Select appropriate voltage and current stress designs according to requirements to further improve the power output ability. Description of the Drawings

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0046] Figure 1 is the circuit topology diagram of the push-pull active differential clamped class-E power amplifier in the embodiment of the present invention.

[0047] Figure 2 is the timing diagram of the working waveform within one period in the embodiment of the present invention.

[0048] Figure 3 is the magnitude of the voltage and current stress under the optimal load of the traditional push-pull class-E power amplifier.

[0049] Figure 4 is the magnitude of the voltage stress with different duty cycles of the circuit topology in the embodiment of the present invention.

[0050] Figure 5 is the magnitude of the voltage stress with different γ values of the circuit topology in the embodiment of the present invention.

[0051] Figure 6 is the magnitude of the voltage stress with different κ values of the circuit topology in the embodiment of the present invention.

[0052] Figure 7 is the magnitude of the voltage and current stress with different small ratios of γ and κ of the circuit topology in the embodiment of the present invention.

[0053] Figure 8 is the physical diagram of the prototype of the circuit topology in the embodiment of the present invention.

[0054] Figure 9 is the circuit topology diagram of the traditional push-pull class-E power amplifier. Detailed implementation manners

[0055] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in combination with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0056] The circuit topology of the push-pull active differential clamped class-E power amplifier proposed in the embodiment of the present invention is as shown in the attached Figure 1 , 8 The push-pull active differential clamping auxiliary circuit includes two MOSFETs (S1 and S2), and the clamping differential capacitor CLS and the differential capacitance (C Q1 , C Q2 and C Q ) of the output. L m1 and L m2 are the input chokes, which provide a stable current input for the power amplifier. The MOSFETs (Q1 and Q2) in the main power section form a push - pull complementary output. C S1 , C S2 , L1 and L2 form a series resonant network, and the resonant frequency is the operating frequency of Q1, Q2, S1 and S2. V DC is the input bus voltage, and C r1 is the filter capacitor of the input bus voltage. R is the load of the push - pull active differential clamped class - E power amplifier. Where I DC is the bus input current, I DC1 and I DC2 are the input currents of the chokes. i0 is the output current of the resonant network.

[0057] The MOSFETs (Q1 and Q2) are the main power switches for realizing DC - to - AC conversion, and the MOSFETs (S1 and S2) are the auxiliary switches for clamping the voltages on Q1 or Q2 when Q1 or Q2 is turned off.

[0058] As Figure 1 shown, the push - pull active differential clamped class - E power amplifier has circuit structure symmetry, so the basic circuit parameters also have symmetry, as shown in the following formula:

[0059]

[0060] C S1 , C S2 are the resonant capacitors of the output network respectively; C Q1 , C Q2 represent the capacitances of Q1 and Q2 respectively; I DC is the input bus current, I DC1 is the average current of the choke L m1 , I DC2 is the average current of the choke L m2 ; L1, L2 represent the resonant inductances of the output network respectively; L m1 and L m2 are the input chokes.

[0061] The working timing waveform of one cycle is as shown in Appendix Figure 2 . Among them, D is the duty cycle of the driving waveforms of Q1 and Q2, and Ds is the duty cycle of the driving waveforms of the auxiliary switches S1 and S2. Only one of Q1, Q2 and S1, S2 is working, and the operating frequencies f are the same and complementary, that is, the time period is T. The specific operation process is as follows:

[0062] Mode 0: Before time t0, the main power switch Q1 is off and Q2 is on, and the auxiliary switches S1 and S2 are both off. At this time, the charge of C Q1 has been extracted, the body diode of the MOS transistor Q1 conducts, and the voltage at the Q1 terminal is clamped to nearly 0V.

[0063] Mode 1: At time t0, Q1 will turn on, achieving ZVS turn-on. Q2 will turn off. Due to the existence of the output differential capacitors C Q2 and C Q , a ZVS soft turn-off process can be achieved. S1 and S2 are both in the off state. During t0 - t1, the capacitors C Q2 and C Q will be charged. The current at point AB satisfies the following relationship:

[0064]

[0065] where i Q1 , i Q2 are the currents of Q1 and Q2 respectively, and i CQ , i CQ2 and i CQ1 are the currents of the differential capacitors C Q , C Q2 and C Q1 respectively. i CLs is the input current of the differential capacitor C LS . The positive reference direction of the current is the positive associated direction.

[0066] Mode 2: At time t1, when the capacitor voltages of C Q2 and C Q reach , the body diode D S2 of the auxiliary switch S2 will conduct, where is the steady-state voltage value of the capacitor C LS . At this time, C LS , C Q2 and C Q will be charged simultaneously, and the voltage stress of Q2 will be clamped to the up and down fluctuations of . The peak value of the fluctuation depends on the proportional relationship between the capacitors C LS and C Q , C Q2 and C Q1 . Let C Q2 = C Q1 = (1 - γ)C EQ , C Q = γC EQ and At node B, according to Equation (2), Kirchhoff's current law, and the charge and discharge relationship of the capacitor, the differential capacitance current satisfies the following relationship:

[0067]

[0068] C EQ is the total equivalent output capacitance value of Q1 and Q2; γ and κ are the proportionality coefficients of the differential capacitance C Q and relative to C EQ respectively, and are configured proportionally according to the actual voltage stress requirements in the application. For example: if only the voltage stress needs to be considered, then κ can be set much larger than γ; if more consideration is given to low current stress and the voltage stress also needs to be reduced, then the values of κ and γ can be designed to be of the same order of magnitude. Figure 6 and Figure 7 are shown, and are proportionally configured according to the actual voltage stress requirements in the application. For example: if only the voltage stress needs to be considered, then κ can be set much larger than γ; if more consideration is given to low current stress and the voltage stress also needs to be reduced, then the values of κ and γ can be designed to be of the same order of magnitude.

[0069] Mode 3: At time t2, the auxiliary switch S2 will close, achieving ZVS turn-on, and the capacitor C LS will continue to be actively charged slowly with i CLs . During the time from t1 to t2, C LS will be charged. As follows:

[0070]

[0071] represents the transient voltage value of the differential capacitance C LS during the time from t1 to t2; U CLS0 represents the steady-state voltage value of the differential capacitance C LS .

[0072] Mode 4: At time t3, when the input current I DC2 at point B + i0 = 0, the inflowing current will reverse.

[0073] At this time, C LS , C Q2 and C Q will simultaneously release the stored charge to the load R according to the current ratio shown in Equation (3). At this time, the voltage stress clamped on Q2 will reach the maximum, which can be expressed as shown in (5), and Δu is the maximum peak point of the clamped voltage fluctuation. The current of Q1 will be clamped or weakened by i CQ . As follows:

[0074]

[0075] i Q1 represents the current of Q1, and U Q2 is the maximum voltage stress clamped on Q2.

[0076] Mode 5: At time t4, the auxiliary switch S2 will turn off. Due to the existence of the differential capacitors C LS and C Q , the ZVS soft turn-off process can be achieved. At this time, the clamping differential capacitor C LS stops discharging. The output differential capacitors C Q2 and C Q will continue to release charge to the resonant network at the current ratio, and the voltage stress of Q2 will start to decrease at time t4. The current ratio is as follows:

[0077] i CQ2 :i CQ =γ:(1 - γ) (6)

[0078] i CQ and i CQ2 represent the currents of the differential capacitors C Q and C Q2 .

[0079] Mode 6: At time t5, the charges of the capacitors in the output differential capacitors C Q2 and C Q are all extracted. When the turn-on timing of Q2 has not arrived, that is, t5 < t6. The differential capacitors C Q2 and C Q are reversely charged until the body diode D Q2 conducts, and C Q2 and C Q are clamped to stop charging. The voltage of Q2 is clamped to 0. When the turn-on timing of Q1 arrives, ZVS turn-on will be achieved, and ZVS soft turn-off of Q2 will be achieved.

[0080] The second half cycle is the working timing of the auxiliary switch S1 and the main power switch Q1, which will be the same as the above and will not be elaborated here.

[0081] As can be seen from Equation (5), the voltage stress of the MOSFETs is clamped and the current stress is weakened, achieving the purpose of reducing stress. The magnitude of the voltage stress U Q2 of Q2 depends on the magnitudes of U CLS0 and Δμ, and the current stress i Q1 of Q1 depends on i CQ . Therefore, ultimately, the proportional relationship of the differential capacitors will play a dominant role. By adjusting the proportional relationship, the voltage stress and current stress can be adjusted; when the κ value is larger, a smaller voltage stress can be obtained, but the weakening of the current stress is limited; when κ < γ (such as Figure 7 , when the κ value is 0.1, the current stress is smaller at this time, approximately a square wave), the smaller the κ value, the smaller the current stress that can be obtained. If κ and γ are of the same order of magnitude, then both the voltage and current stresses can be reduced.

[0082] Therefore, there will be two cases:

[0083] Case 1: When κ >> γ, U can be obtained according to the volt-second balance relationship on the choke coil as follows: CLS0 , as follows:

[0084]

[0085] Therefore, the maximum voltage stress of MOSFETs can be expressed as in Equation (8). It can be seen that when κ >> γ, Δμ can be ignored, and the maximum voltage stress depends on D and Ds, and theoretically, the minimum value that can be achieved is 2V. DC .

[0086]

[0087] t0 is the starting time of one cycle of working timing after the system enters the steady state, and usually it can be set to 0.

[0088] As in Equation (5), the root mean square value of the current stress will be weakened at time t4 - t5, reducing the root mean square value of the current and the stress magnitude.

[0089] Case 2: If there is a non-negligible proportional relationship between κ and γ, the current on the differential capacitor will be strictly distributed according to Equation (3). Therefore, according to I DC2 + i0(t) = 0, U can be obtained as shown in the following equation: CLS0 , as shown in the following equation:

[0090]

[0091] Therefore, the maximum voltage stress on MOSFETs can be expressed as shown in Equation (10). It can be seen that the voltage stress will mainly depend on the magnitude of the κ value. Increasing κ can reduce the magnitude of the voltage stress.

[0092]

[0093] The current stress of MOSFETs follows the proportional relationship of the current between the differential capacitors. When the values of κ and γ are comparable, then there will be a larger current in the differential capacitor C Q . Therefore, the current flowing through Q1 can be reduced to the minimum, reducing the magnitude of the current stress.

[0094] As described in the above six modes of a half cycle, the topology proposed in the embodiments of the present invention has the load values of zero voltage switching (ZVS) and zero voltage derivative switching (ZVDS) of the traditional push-pull class-E power amplifier. The push-pull auxiliary switch can achieve the process of full auxiliary range ZVS turn-on and soft turn-off, which is independent of the load size and will not introduce excessive losses due to the introduction of the auxiliary circuit. The embodiments of the present invention adopt a combination of active clamped and differential capacitance, which can not only reduce the voltage stress, but also reduce the current stress and the root mean square value of the current, taking into account the requirements of both; since the voltage stress and current stress of the MOS transistor are reduced, the power output capacity of the push-pull class-E inverter can be improved. The embodiments of the present invention control the flow direction of the differential capacitance through the push-pull active auxiliary circuit, and can reduce the voltage and current stress of the MOS transistor by designing the proportional relationship of the differential capacitance, and then can reasonably configure the voltage stress, current stress and power output capacity according to the actual engineering requirements. This configuration method is mainly determined according to the proportional relationship of the differential capacitance.

[0095] Figure 3 is the waveform diagram of the voltage and current stress of the traditional push-pull class-E power amplifier at D = 0.5 and the optimal load. It can be seen that the voltage stress reaches 3.62V DC , and the current stress reaches 2.86I DC2 .

[0096] Figure 4 is the voltage stress magnitude of the circuit topology of the embodiments of the present invention at κ = 1000 and γ = 0.9 with different duty cycles Ds. It can be seen that the larger the duty cycle, the lower the voltage stress.

[0097] Figure 5 is the voltage stress magnitude of the circuit topology of the embodiments of the present invention at κ = 1000, Ds = 0.3 and different γ values. It can be seen that the larger the γ value, the lower the root mean square value of the current stress.

[0098] Figure 6 is the voltage stress magnitude of the circuit topology of the embodiments of the present invention at Ds = 0.3, γ = 0.9 and different κ values. It can be shown that the larger the κ value, the lower the voltage stress.

[0099] Figure 7 is the voltage and current stress magnitude of the circuit topology of the embodiments of the present invention at Ds = 0.3 with different small ratios of γ and κ. It can be seen that when the ratios of γ and κ are equivalent, the current stress is the smallest.

[0100] In the embodiments of the present invention, both the voltage and current stresses are lower than those of the traditional push-pull class-E power amplifier. The circuit structure of the embodiments of the present invention can reduce the voltage stress to a maximum of twice the bus voltage, and the current stress can be reduced to a minimum of twice the bus current. On the basis of the minimum stress reduction, it also has a low root-mean-square current, which can reduce the loss of the MOS transistor. At the same time, compared with the traditional structure, the maximum current stress is stable with the change of the load.

[0101] Therefore, the push-pull active differential clamped class-E power amplifier circuit proposed in the embodiments of the present invention can effectively reduce the voltage and current stresses, and can configure the magnitudes of the voltage and current stresses according to the actual application requirements. At the same time, the main switch can also have the zero-voltage switching characteristic, and the auxiliary switch can have the zero-voltage switching characteristic in the full load range.

[0102] The push-pull active differential clamped class-E power amplifier in the embodiments of the present invention has high application value. It has practical potential value in high-frequency plasma, electromagnetic heating, wireless power transmission, and communication occasions. The circuit topology structure proposed in the embodiments of the present invention can be used as a power transmitter to convert direct current into alternating current for transmission. Since the push-pull active differential clamped class-E power amplifier has lower voltage and current stresses, the requirement of higher power transmission can be realized. For example, in a magnetic coupling wireless power transmission system, it can be used as an inverter at the transmitting end. Compared with the traditional class-D inverter, it can avoid the influence of the dead zone effect, and the MOSFET has no floating drive, so a simpler drive can be realized. Compared with the traditional class-E inverter, it can achieve higher power transmission. And it has lower voltage and current stresses, which is more conducive to the selection of devices and the reduction of the overall machine cost. At the same time, since the auxiliary circuit of the push-pull active differential clamped class-E power amplifier has the soft-switching characteristic in the full load range, it can also meet the requirements of high-frequency power amplifiers or inverters to ensure high-efficiency conversion. In induction heating, it can meet the requirements of greater power and higher frequency, and provide the power output capacity of the whole machine.

[0103] The traditional push-pull class-E power amplifier (inverter) such as Figure 9As shown, a control method is usually adopted to obtain the optimal load point to avoid drastic changes in voltage stress; or harmonics are injected to reduce the peak value. However, the above methods are difficult to meet the requirements of higher power output at high frequencies and also take into account the inherent advantages and high-efficiency output ability of class-E power amplifiers. In the embodiment of the present invention, a push-pull active auxiliary circuit and a differential capacitor are added to the traditional push-pull class-E power amplifier (inverter) to form a clamping circuit, which actively reduces stress as much as possible. Considering the inherent advantages of class-E power amplifiers, the advantages and high-efficiency output ability existing in the class-E power amplifier itself cannot be damaged. The additionally introduced circuit realizes load-independent soft-switching operation to ensure the lowest power consumption. By combining the push-pull auxiliary circuit and the differential capacitor, the voltage and current stresses are reduced, the power output ability is improved, and the inherent advantages and high-efficiency output ability of class-E power amplifiers are taken into account.

[0104] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A push-pull active differential clamped class E power amplifier, comprising a push-pull class E power amplifier, wherein the push-pull class E power amplifier comprises main power switches Q1 and Q2 for realizing DC to AC conversion, wherein Q1 and Q2 are both MOSFETs and have complementary or symmetrical structures; characterized in that: Output differential capacitance C Q1 The two ends of are connected to the drain and source of the main power switch Q1 respectively, and the differential capacitor C Q2 The two ends of are connected to the drain and source of the main power switch Q2 respectively, and the output differential capacitor C Q The two ends of are connected to the drain of the main power switch Q1 and the drain of the main power switch Q2 respectively; the differential capacitor C Q The two ends of are connected to the load R through the resonant network; The invention also comprises a push-pull active auxiliary circuit, wherein the push-pull active auxiliary circuit and the differential capacitor form a clamping circuit.

2. A push-pull active differential clamped class E power amplifier according to claim 1, characterized in that: The push-pull active auxiliary circuit includes two symmetrical auxiliary switches S1 and S2, both of which are MOSFETs; a choke coil L m1 With choke L m2 parallel connection, and the choke L m1 With choke L m2 The input end of the auxiliary switch S1 is connected to the positive electrode of the input bus; the source of the auxiliary switch S1 is connected to the choke coil L m1 The output terminal and drain of the main power switch Q1, the source of the auxiliary switch S2 are connected to the choke coil L m2 The output terminal and the drain of the main power switch Q2; the choke coil L m1 With choke L m2 The parallel node of the clamping differential capacitor C LS The negative electrode of the auxiliary switches S1 and S2 is connected to the drain connection point of the differential capacitor C LS The auxiliary switches S1 and S2 are used to clamp the voltage on Q1 or Q2 when the main power switch Q1 or Q2 is disconnected.

3. A push-pull active differential clamped class E power amplifier according to claim 1, characterized in that: The sources of the main power switches Q1 and Q2 are connected to the ground, and the drains of the main power switches Q1 and Q2 are connected to the resonant network.

4. A push-pull active differential clamped class E power amplifier according to claim 1, characterized in that: The resonant network consists of a resonant capacitor C S1 , C S2 The resonant network is composed of a resonant inductor L1 and a resonant inductor L2 in series, a load R is connected in series with the resonant network, and the resonant frequency is the operating frequency of the main power switch Q1, the main power switch Q2, the auxiliary switch S1 and the auxiliary switch S2.

5. A push-pull active differential clamped class E power amplifier according to claim 2, characterized in that: Only one of the main power switches Q1 and Q2 is working, and only one of the auxiliary switches S1 and S2 is working. The main power switches Q1, Q2, auxiliary switches S1 and S2 have the same working frequency f, that is, the time period is T.

6. A push-pull active differential clamped class E power amplifier according to claim 2, characterized in that: The working sequence of the auxiliary switch and the main power switch in the first half cycle is: Before time t0, the main power switch Q1 is off, Q2 is on, and the auxiliary switches S1 and S2 are both off. At this time, the differential capacitor C Q1 The charge has been extracted, the body diode of the main power switch Q1 is turned on, and the voltage at the terminal of the main power switch Q1 is clamped to nearly 0V; At t0, the main power switch Q1 is closed to achieve ZVS turn-on; the main power switch Q2 is turned off, due to the differential capacitor C Q2 and C Q The existence of ZVS soft shutdown process is realized; the auxiliary switches S1 and S2 are both in the off state; After t0, the differential capacitance C Q2 and C Q will be charged; At time t1, when the differential capacitance C Q2 and C Q The capacitor voltage reaches When the auxiliary switch S2's body diode D S2 is turned on, where is the differential capacitance C LS The steady-state voltage value, V DC is the input bus voltage; at this time, the differential capacitor C LS , C Q2 and C Q are charged simultaneously, and the voltage stress of the main power switch Q2 is clamped to The ups and downs of At t2, the auxiliary switch S2 is closed to achieve ZVS turn-on, and the differential capacitor C LS Continue with i CLs Slow active charging, i CLs is the differential capacitance C LS Input current; At time t3, when the differential capacitance C Q The input current I connected to the drain of the main power switch Q2 DC2 +i0=0, the inflow current will be reversed; at this time, the differential capacitance C LS , C Q2 and C Q At the same time, the stored charge is released to the load R in proportion to the current, and the voltage stress clamped on the main power switch Q2 reaches the maximum; At time t4, the auxiliary switch S2 is turned off, and due to the differential capacitance C LS and C Q The existence of ZVS soft shutdown process is realized; at this time, the differential capacitor C LS Stop discharging, the differential capacitor C Q2 and C Q The charge continues to be released to the resonant network in proportion to the current, and the voltage stress of the main power switch Q2 begins to decrease at time t4; The current ratio is shown in the following formula: Where γ and κ are the differential capacitance C Q and Relative to C EQ The proportionality coefficient, C EQ is the total equivalent output capacitance of the main power switches Q1 and Q2; i CQ2 is the differential capacitance C Q2 The current, i CQ is the differential capacitance C Q The current, i CLs is the differential capacitance C LS Input current; At time t5, the charges of the capacitors in differential capacitors C Q2 and C Q are all extracted. When the turn-on timing of main power switch Q2 has not arrived, i.e., t5 < t6; differential capacitors C Q2 and C Q are reversely charged until body diode D Q2 conducts, and differential capacitors C Q2 and C Q are clamped to stop charging; the voltage of main power switch Q2 is clamped to 0; when the turn-on timing of main power switch Q1 arrives, ZVS turn-on is achieved, and ZVS soft turn-off of main power switch Q2 is achieved.

7. A push-pull active differential clamped class E power amplifier according to claim 6, characterized in that: The maximum voltage stress U clamped on the main power switch Q2 Q2 The expression is as follows: IN Q2 =V DC +U CLS0 +Δμ Where Δu is the maximum peak value of the clamping voltage fluctuation, and κ is the differential capacitance. Relative to C EQ The proportionality coefficient, C EQ is the total equivalent output capacitance of the main power switches Q1 and Q2; i0 is the output current of the resonant network, I DC2 is the choke L m2 The average current of the main power switch Q2 is clamped; The main power switch Q1 current i Q1 The expression is as follows: I Q1 =I DC1 -i0-i CQ In the formula, I DC1 is the choke L m1 The average current, i CQ is the differential capacitance C Q The current stress of the main power switch Q1 is weakened.

8. A push-pull active differential clamped class E power amplifier according to claim 7, characterized in that: When κ>>γ, Δμ is negligible and the maximum voltage stress U Q2 Depends on D and Ds, theoretically minimum 2V DC ; D is the driving waveform duty cycle of the main power switches Q1 and Q2, and Ds is the driving waveform duty cycle of the auxiliary switches S1 and S2.

9. A push-pull active differential clamped class E power amplifier according to claim 7, characterized in that: If there is a non-negligible proportional relationship between κ and γ, the current on the differential capacitor is strictly distributed according to the current ratio, and the maximum value of the maximum voltage stress clamped on the main power switch Q2 is U Q2MAX See the following formula: Increasing κ can reduce the magnitude of voltage stress; When the values ​​of κ and γ are equal, the differential capacitance C Q There is a larger current, so the current flowing through the main power switch Q1 is minimized, thereby reducing the current stress.

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