Low-power-consumption high-precision ring amplifier adopting novel dead zone embedded structure and suitable for high supply voltage process
By introducing a new dead-band embedded structure into the ring amplifier, the problem of slow establishment speed of ring amplifiers under high power supply voltage processes is solved, and the effect of low power consumption, high precision and rapid establishment is achieved.
Patent Information
- Application Number
- CN202510224582.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-06-17
AI Technical Summary
Under high power supply voltage processes, the establishment speed of the ring amplifier is limited, resulting in a longer conversion time of the ADC.
The ring amplifier with a new dead-band embedded structure is adopted to gradually increase the size of the dead-band during the establishment process, and the slew rate of the switching capacitor amplifier in the early stage of establishment and stabilize at the end of establishment.
A higher settling speed of the ring amplifier is achieved, reducing power consumption while maintaining high accuracy and stability.
Smart Images
Figure CN120165653A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to integrated circuit technology, and particularly to a ring amplifier. Background Art
[0002] In the past few decades, the semiconductor industry has developed rapidly, the technology of digital circuits has become increasingly powerful, and the integration degree of chips has been continuously improved. Digital circuits are widely used in fields such as medical treatment, aerospace, measurement, communication, and audio and video processing due to their high speed, high precision, high reliability, and the increasingly perfect EDA technology, and have occupied a dominant position. However, in people's daily lives, most of the signals they come into contact with, such as sound, are analog signals. Therefore, digital signal devices must be able to effectively communicate with the analog environment. Such devices that can achieve the interconnection between the digital world and the analog world are called data converters, which are mainly divided into analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). Among them, ADCs are widely used in many electronic devices, such as the ADC that converts electrocardiogram signals into digital signals in an electrocardiograph. The performance of the ADC directly affects the signal quality after the analog signal enters the digital system, and thus may affect the performance of the entire digital system.
[0003] At present, ADCs can be divided into high-precision ADCs and high-speed ADCs according to the level of the input frequency. High-speed ADCs are mainly used in communication, satellite images and other scenarios, and time-interleaved and pipelined architectures can be adopted. High-precision ADCs are mainly applied in sensors, medical detection, audio, industrial detection and other fields. Due to their high-precision characteristics, sigma-delta or successive approximation register (SAR) ADCs are mainly used. Among them, the sigma-delta ADC can achieve a maximum precision of 24 bits or 32 bits by means of oversampling and quantization noise shaping techniques. However, due to its oversampling characteristics, the higher the precision, the higher the order of shaping and the higher the sampling rate are required. Therefore, it is difficult to increase its signal bandwidth. Secondly, the sigma-delta ADC will exhibit the phenomenon of idle tones under certain input conditions, which will cause harmonics in the output spectrum, and the noise shaping function depends on the memory ability of the circuit. In some scenarios, such as multiplexing multiple sensors with one ADC, it is not suitable for use. On the contrary, the SAR ADC has no circuit memory, has the characteristic of sampling and converting one by one, can be applied in multiplexing scenarios, and the digital codeword output does not need to be processed by a decimation filter like the sigma-delta. Although the maximum precision of the SAR ADC is not as high as that of the sigma-delta ADC, it has a high degree of digitization and a simple structure. Its speed, power consumption and area are improved with the progress of CMOS technology and the reduction of transistor feature size. Moreover, the SAR ADC can be combined with the pipelined ADC to obtain the pipelined SAR ADC, which can increase the sampling rate while maintaining the original precision.
[0004] The residue amplifier is a crucial module in a pipelined SAR ADC. The errors introduced by the previous-stage ADC can be resolved by setting inter-stage redundancy or the redundancy of the next-stage ADC. Due to the amplification of the residue amplifier, the corresponding input-referred errors of the next-stage ADC will be suppressed, while the errors introduced by the residue amplifier will be directly reflected in the output codeword of the next stage. For an ideal residue amplifier, the output voltage is equal to the input voltage multiplied by the gain. However, in reality, due to non-ideal factors such as the limited gain, non-linearity, offset voltage, and noise of the operational amplifier, there will be certain errors in the output of the residue amplifier. Since open-loop operational amplifiers generally have non-linearity problems, to ensure good linearity, most residue amplifiers adopt a switched-capacitor structure as feedback. Since the larger the gain of the operational amplifier, the smaller the gain error of the residue amplifier, the operational amplifier usually adopts a cascode structure to increase the gain. This structure belongs to a static amplifier with high power consumption. Moreover, the charging of the load capacitor by this operational amplifier is like a kind of establishment based on the RC constant. For a relatively large load capacitor, the establishment speed needs to be increased to ensure small establishment errors, which means reducing the RC constant and increasing the bandwidth of the operational amplifier. And high bandwidth means high gm and high power consumption, so there is a trade-off between power consumption and load capacitance. Also, the residue amplifier based on the cascode amplifier needs to charge the feedback capacitor and the load during amplification. Within a certain establishment time, the higher the establishment degree, the smaller the time constant. The smaller the time constant means the higher the noise bandwidth, so there is a design trade-off between establishment error and noise.
[0005] As described above, the residual amplifier based on the cascode amplifier has problems such as high power consumption, a trade-off in design between power consumption and load capacitance, settling error, and noise. The ring amplifier can avoid these problems to a certain extent. The ring amplifier generally adopts a three-stage inverter structure. The first two stages of inverters can use the gated clock technique to reduce power consumption. Due to the insertion of the dead zone in the last stage, there is only dynamic power consumption during amplification, and the static power consumption is very low. Therefore, the power consumption of the ring amplifier is lower than that of the cascode amplifier. Secondly, the charging of the load capacitance by the ring amplifier is like a digital circuit. Each time of charge and discharge, only one of the NMOS and PMOS of the third-stage inverter works. This charging method is more power-saving because only dynamic power consumption is consumed. Moreover, precisely because of this, for a relatively large load capacitance, the transistors in the third stage can also be made relatively small, which means that the load of the second stage can be small enough to be negligible, decoupling the internal power consumption of the amplifier (the power consumption of the first and second stages) from the size of the switched-capacitor load. In addition, the ring amplifier contributes very little noise to the entire ADC system. This benefits from the fact that the frequency of the output pole after the ring amplifier stabilizes is very low, the bandwidth of the entire amplifier is very small, the noise of the internal transistors of the amplifier is greatly attenuated, and the noise charge on the load capacitance is very small, which solves the problem of the trade-off between settling error and noise to a certain extent.
[0006] However, one disadvantage of the ring amplifier is that in order to ensure a relatively high sub-pole frequency for the first two stages of inverters to ensure stability, the output impedance of the first two stages must be reduced, which means increasing current and power consumption. If the ring amplifier is to be used in a high supply voltage process, in order to reduce power consumption, Paper A "10-mW 16-b 15-MS / s Two-Step SAR ADC With 95-dB DR Using Dual-Dead zone Ring Amplifier" adopts the structure as Figure 1 shown, which allows the transistors of the first two stages of inverters to use core transistors and be powered by a low supply voltage (1.8V) to reduce power consumption, and allows the transistors of the third-stage inverter to use high-voltage transistors and be powered by a high supply voltage (3.3V) to ensure a relatively high output swing. Due to the low supply voltage of the second-stage inverter, the output swing is small, and the dead zone insertion structure needs to adopt Figure 1The capacitor level conversion structure shown in the figure is used to embed a sufficiently large dead zone to ensure that the third-stage transistor can enter the cut-off state at the end of the setup period and ensure the stability of the ring amplifier. However, this means that the gate-source voltage of the third-stage transistor is also attenuated by the voltage converted by the capacitor at the beginning of the setup period. In addition, the output swing of the second-stage inverter is originally small, which will make the third-stage inverter transistor charge and discharge the load capacitor very slowly at the beginning of the setup period, slowing down the setup speed of the residual amplifier. The reduction in setup speed means that the residual amplifier needs a longer setup time to avoid the deterioration of the setup error, and the conversion time of the ADC becomes longer. To compensate for this, the width-to-length ratio of the third-stage inverter can be increased, but this means that the load capacitance of the second-stage inverter increases, and the secondary pole is pushed inward, requiring more power consumption to push the secondary pole back. Therefore, at a lower power consumption, Figure 1 It is difficult to achieve a high speed in building a structure. Summary of the invention
[0007] Given that Figure 1 The problem that the ring amplifier used in the high power supply voltage process has a limited establishment speed under small power consumption is shown in the figure. The present invention provides a low power consumption and high precision ring amplifier suitable for the high power supply voltage process with a novel dead zone embedding structure, such as Figure 2 As shown, this ring amplifier can make the size of the embedded dead zone, that is, the voltage stored on the third and fourth capacitors, gradually increase from zero to a value determined by the resistance of the first to fourth resistors during the establishment process, so as to avoid the attenuation of the gate-source voltage of the third-stage transistor by the voltage converted by the capacitor at the initial stage of the establishment, so that the switch capacitor amplifier can maintain a relatively high slew rate at the initial stage of the establishment. At the same time, since the size of the dead zone gradually increases during the establishment process, the main pole of the amplifier is pushed inward, and the switch capacitor amplifier can tend to be stable at the end of the establishment. With the help of this structure, even if the width-to-length ratio of the transistor of the last-stage inverter is relatively low and the power consumption of the second-stage inverter is low, a higher establishment speed of the ring amplifier can be achieved. Although this dead zone embedded structure adds a resistor to the output end of the second-stage inverter, because this resistor and the output impedance of the second-stage inverter are in a parallel relationship, the secondary point of the ring amplifier will not be pushed inward, and as long as the resistance of this resistor is large enough, generally speaking, several thousand ohms, the gain of the ring amplifier will not be affected.
[0008] The technical solution adopted by the present invention to solve the technical problem is to provide a low-power consumption and high-precision ring amplifier suitable for high power supply voltage process using a novel dead zone embedded structure, characterized in that it includes an amplification unit and a bias unit.
[0009] The amplification unit adopts a ring amplifier structure including three - stage inverters. All three - stage inverters adopt the auto - zero technology to reduce the offset voltage of the amplifier. The first two - stage inverters adopt the technologies of low - supply - voltage power supply and gated power supply, which can reduce the static power consumption of the ring amplifier. A novel dead - zone embedding structure is added between the second - stage inverter and the third - stage inverter. This structure can make the dead - zone of the switched - capacitor amplifier with this amplification unit as the operational amplifier increase gradually from zero to a fixed value during the settling process, enabling the ring amplifier to tend to be stable at the end of the settling period while increasing the slew rate at the beginning of the settling period, decoupling the gain and speed of the amplifier to a certain extent. The third - stage inverter also utilizes the condition of high - supply - voltage and adopts the cascode technology to improve the gain of the amplifier. The bias unit consists of two current mirrors and two transistors in diode - connected configuration, which can provide a bias voltage for the cascode transistor of the third stage of the amplification unit.
[0010] The said amplification unit has an input terminal VIN, an output terminal OUT, an auto - zero control terminal AZ, and an auto - zero control terminal gated - power - supply control terminal bias - voltage terminals Vbn, Vbp, power - supply terminals VDDL and VDDH, and a ground - level terminal VSS. If V(VSS), V(VDDL), and V(VDDH) represent the voltages of the ground - level terminal VSS, the power - supply terminal VDDL, and the power - supply terminal VDDH respectively, then V(VDDL)>V(VSS), V(VDDH)>V(VSS), V(VDDL)<V(VDDH). The input terminal VIN is connected to the upper plate of the first capacitor. The output terminal OUT is connected to the drains of the sixth and seventh transistors. The voltage received by the auto - zero control terminal AZ is used to control the closing and opening of the first, second, fifth, and sixth switches S1, S2, S5, S6. When V(AZ) is at a high level, the first, second, fifth, and sixth switches are closed, otherwise they are open. The auto - zero control terminal The voltage received is used to control the closing and opening of the third and fourth switches S3, S4, When it is at a high level, the third and fourth switches are closed, otherwise they are open. The gated - power - supply control terminal The voltage received is used to control the closing and opening of the seventh and eighth switches S7, S8, When it is at a high level, the seventh and eighth switches are closed, and vice versa. The bias voltage terminals Vbn and Vbp are respectively connected to the gates of the seventh transistor and the sixth transistor. The power supply terminal VDDL is connected to the sources of the first and third transistors, the ground level terminal VSS is connected to the sources of the second, fourth, and eighth transistors and the fourth resistor, and the power supply terminal VDDH is connected to the source of the fifth transistor and the second resistor. The lower plate of the first capacitor is connected to one end of the first switch, the other end of the first switch is connected to the upper plate of the second capacitor, the gates of the first and second transistors are both connected to the lower plate of the first capacitor, and the lower plate of the first capacitor is also connected to the ground level terminal VSS through the seventh switch S7. The drain of the first transistor is connected to the drain of the second transistor and both are connected to the upper plate of the second capacitor. The lower plate of the second capacitor is connected to one end of the second switch, the other end of the second switch is connected to the upper plates of the third and fourth capacitors, the gates of the third and fourth transistors are both connected to the lower plate of the second capacitor, and the lower plate of the second capacitor is also connected to the power supply terminal VDDL through the seventh switch S8. The drain of the third transistor is connected to the drain of the fourth transistor and both are connected to the upper plates of the third and fourth capacitors. The upper plate of the third capacitor is connected to the gate of the fifth transistor, the third capacitor is in parallel with the first resistor, the upper plate of the fourth capacitor is connected to the gate of the eighth transistor, the fourth capacitor is in parallel with the third resistor, the gate of the fifth transistor is connected to one end of the second resistor through the third switch, the other end of the second resistor is connected to the power supply terminal VDDH, the gate of the eighth transistor is connected to one end of the fourth resistor through the fourth switch, the other end of the fourth resistor is connected to the ground level terminal VSS, the gate of the fifth transistor is connected to the output terminal OUT through the fifth switch, the gate of the eighth transistor is connected to the output terminal OUT through the sixth switch, the drain of the fifth transistor is connected to the source of the sixth transistor, and the drain of the eighth transistor is connected to the source of the seventh transistor. The first, third, fifth, and sixth transistors of the amplification unit are P-type MOS transistors, and the second, fourth, seventh, and eighth transistors are N-type MOS transistors.
[0011] The bias unit has a power supply terminal VDDH, a ground level terminal VSS, an output terminal Vbn, and an output terminal Vbp. Among them, the power supply terminal VDDH is connected to the sources of the ninth, thirteenth, fifteenth, and nineteenth transistors, the ground level terminal VSS is connected to the sources of the twelfth, eighteenth, and twenty-second transistors, and the negative terminal of the first current source, the output terminal Vbn is connected to the drain of the eleventh transistor, and the output terminal Vbp is connected to the drain of the twentieth transistor. The gate of the ninth transistor is connected to the drain of the thirteenth transistor, the drain of the ninth transistor is connected to the source of the tenth transistor, the gate of the tenth transistor is connected to the drain of the fourteenth transistor, the drain of the tenth transistor is connected to the gate and drain of the eleventh transistor, the source of the eleventh transistor is connected to the drain of the twelfth transistor, the gate of the thirteenth transistor is connected to the drain of the thirteenth transistor and the gate of the fifteenth transistor, the drain of the thirteenth transistor is connected to the source of the fourteenth transistor, the gate of the fourteenth transistor is connected to the drain of the fourteenth transistor, the gate of the sixteenth transistor, and the positive terminal of the first current source, the drain of the fifteenth transistor is connected to the source of the sixteenth transistor, the drain of the sixteenth transistor is connected to the drain and gate of the seventeenth transistor, and the gate of the twenty-first transistor, the source of the seventeenth transistor is connected to the drain and gate of the eighteenth transistor and the gate of the twenty-second transistor, the drain of the nineteenth transistor is connected to the source of the twentieth transistor, the drain of the twentieth transistor is connected to the gate of the twentieth transistor, the drain of the twenty-first transistor, and the gate of the nineteenth transistor, the source of the twenty-first transistor is connected to the drain of the twenty-second transistor. The ninth, tenth, thirteenth, fourteenth, fifteenth, sixteenth, nineteenth, and twentieth transistors of the bias unit are P-type MOS transistors, and the eleventh, twelfth, seventeenth, eighteenth, twenty-first, and twenty-second transistors are N-type MOS transistors.
[0012] As described above, the low-power and high-precision ring amplifier applicable to high-power supply voltage processes with the novel dead zone embedding structure provided by the present invention is different from the traditional ring amplifier. In the present invention, an automatic zeroing technique is adopted for all three-stage inverters. By closing the first, second, fifth, and sixth switches, the input and output of the inverter are short-circuited, so as to store the difference between the inverter flip point voltage and the common-mode voltage on the capacitor, thereby reducing the offset voltage of the amplifier. In other previous ring amplifiers, part of the automatic zeroing is only applied to the first two stages or the first stage, and the offset voltage of the third stage is still not cancelled. Another part of the automatic zeroing method is to short-circuit the input and output of the ring amplifier to cancel the offset voltage of the three-stage inverter. However, since the feedback coefficient of this method is 1 and the phase margin is low, there may be problems with loop stability. On the contrary, the automatic zeroing method of the present invention not only realizes the zeroing of the three-stage inverter, making the offset voltage as low as possible, but also does not have problems with loop stability.
[0013] The first two stages of inverters adopt the technique of gated power supply. When the amplifier is not working, by closing the seventh and eighth switches, the input of the first-stage inverter is set to the ground level, and the input of the second-stage inverter is set to the power supply level. At this time, the current of the first two stages of inverters is close to zero, which can reduce the static power consumption of the ring amplifier. At the same time, since the output of the first-stage inverter is at the power supply level at this time, the charge stored in the second capacitor is zero, and the charge that the first-stage inverter needs to charge it during the auto-zero phase is reduced, improving the establishment speed of auto-zero. This gated power supply technique does not require adding gated transistors to the inverter branch, will not introduce parasitic resistance, and avoids reducing the secondary point frequency and amplifier speed.
[0014] A new dead zone embedding structure is added between the second-stage inverter and the third-stage inverter. During the auto-zero phase, due to the closing of the fifth and sixth switches, the voltage difference between the third and fourth capacitors is set to the difference between the switching voltages of the second-stage inverter and the third-stage inverter. After the auto-zero phase ends and enters the amplification phase, since the voltages of the third and fourth capacitors are the difference between the switching voltages of the second-stage inverter and the third-stage inverter, the output of the second-stage inverter can be transmitted to the input of the third-stage inverter without attenuation at the beginning of the establishment of the amplification phase, achieving a higher slew rate of the third-stage inverter at the beginning of establishment. During the establishment process, due to the closing of the third and fourth switches, the second-stage inverter continuously charges the third and fourth capacitors until the voltage difference of the third capacitor is equal to the value determined by the resistor voltage division structure of the first and second resistors, and the voltage difference of the fourth capacitor is equal to the value determined by the resistor voltage division structure of the third and fourth resistors. Therefore, the dead zone voltage of this ring amplifier will continuously increase during the establishment process, making the ring amplifier tend to be stable at the end of establishment while increasing the slew rate at the beginning of establishment. By setting the resistance values of the first to fourth resistors, the final size of this dead zone voltage can be set. As long as the dead zone size is large enough, the transistor of the third-stage inverter can enter the cut-off region under various PVT conditions at the end of establishment, so that the ring amplifier can maintain the stability during establishment under various PVT conditions. Since this dead zone embedding structure increases the slew rate at the beginning of establishment, under the same slew rate requirement, the aspect ratio of the transistor of the third-stage inverter can be made relatively small. At the same secondary point frequency, the power consumption of the second-stage inverter can be reduced, decoupling the power consumption and establishment speed of the amplifier to a certain extent. And since the aspect ratio of the transistor of the third-stage inverter can be relatively small, the length of the transistor can be slightly increased to improve the gain while maintaining a relatively high establishment speed.
[0015] The third-stage inverter also utilizes the condition of high power supply voltage and adopts the cascode technique to improve the gain of the amplifier. The gate bias voltage of the cascode transistor is provided by a bias unit, and the bias unit is composed of two current mirrors and two transistors connected in diode configuration.
[0016] It is worth mentioning that the low-power high-precision ring amplifier with a novel dead zone embedding structure applicable to high supply voltage processes provided by the present invention not only exhibits the advantage of fast settling speed in high supply voltage processes, but also shows the advantage of fast settling speed in low supply voltage processes such as 65nm and 28nm. Figure 3 Two dead zone embedding structures of ring amplifiers commonly used in low supply voltage processes are shown. Structure (a) is similar to Figure 1 the structure, the difference is that the supply voltages of the three stages are equal, and it also has the defect of low slew rate at the initial stage of settling. Structure (b) is a self-biased structure with PVT stability. The resistor R1 therein can be not only a resistor but also a transmission gate. Compared with (a), this structure has a higher slew rate at the initial stage of settling. Because at the initial stage of settling, the second-stage transistor charges and discharges the gate of the third-stage transistor, and the current flowing through the resistor R1 is very small, which is equivalent to a very small voltage in the dead zone, and the gate-source voltage of the third-stage transistor is not attenuated. Therefore, the charging and discharging speed of the third-stage transistor to the load capacitor is high. However, if the embedded dead zone is large, at the same power consumption, the resistance value of the resistor R1 is relatively large. In this case, in the middle stage of settling, due to the large resistance value of the resistor R1, the sub-pole frequency at the output end of the second-stage inverter is low, the delay of the second-stage inverter increases, and the attenuation speed of the oscillation of the ring amplifier is slow and it is difficult to stabilize. In contrast, the low-power high-precision ring amplifier with a novel dead zone embedding structure applicable to high supply voltage processes provided by the present invention not only does not have the problem of low slew rate at the initial stage of settling of structure (a), but also avoids the problem of slow oscillation attenuation speed in the middle stage of settling of structure (b). Because of its high slew rate at the initial stage of settling and fast oscillation attenuation speed in the middle stage of settling, the required settling time is short and the settling speed is high. Description of the Drawings
[0017] Figure 1 is the circuit diagram of the ring amplifier applicable to high supply voltage processes used in the paper "A 10-mW 16-b 15-MS / s Two-Step SAR ADC With 95-dB DR Using Dual-Dead zone Ring Amplifier".
[0018] Figure 2 is the circuit diagram of the low-power high-precision ring amplifier with a novel dead zone embedding structure applicable to high supply voltage processes.
[0019] Figure 3 is the circuit diagram of two dead zone embedding structures of ring amplifiers commonly used in low supply voltage processes.
[0020] Figure 4The circuit structure diagram of a low-power and high-precision ring amplifier with a new dead zone embedding structure suitable for high supply voltage processes applied to a pipelined SAR ADC, as well as the timing diagram of the switches in the circuit diagram. Detailed implementation
[0021] See Embodiment 2 Figure 1 , Figure 2 and Figure 3 .
[0022] This embodiment is Figure 2 A comparison between a low-power and high-precision ring amplifier with a new dead zone embedding structure suitable for high supply voltage processes shown in Figure 1 and Figure 3 the ring amplifier shown.
[0023] Figure 1 The circuit diagram of the ring amplifier adopted in the paper "A10-mW 16-b 15-MS / s Two-Step SAR ADC With 95-dB DR Using Dual-Dead zone Ring Amplifier" suitable for high supply voltage processes. This ring amplifier has an input terminal VIN, an auto-zero control terminal AZ, bias voltage input terminals Vbn and Vbp, a power supply terminal VDDL, a power supply terminal VDDH, a ground level terminal VSS, and an output terminal OUT. Among them, the gate of the first transistor is connected to the input terminal, the source is connected to the power supply terminal VDDL, the drain is connected to the upper plate of the first capacitor; the gate of the second transistor is connected to the input terminal, the source is connected to the ground level terminal VSS, the drain is connected to the upper plate of the first capacitor; the gate of the third transistor is connected to the lower plate of the first capacitor, the source is connected to the power supply terminal VDDL, the drain is connected to the upper plate of the second capacitor; the gate of the fourth transistor is connected to the lower plate of the first capacitor, the source is connected to the ground level terminal VSS, the drain is connected to the upper plate of the second capacitor; the first switch connects the lower plate of the first capacitor to the drain of the third transistor, the upper plate of the third capacitor is connected to the upper plate of the second capacitor, the lower plate of the second capacitor is connected to the bias voltage input terminal Vbp through the second switch, the lower plate of the third capacitor is connected to the bias voltage input terminal Vbn through the third switch; the gate of the fifth transistor is connected to the lower plate of the second capacitor, the source is connected to the power supply terminal VDDH, the drain is connected to the output terminal; the gate of the sixth transistor is connected to the lower plate of the third capacitor, the source is connected to the ground level terminal VSS, the drain is connected to the output terminal. Among them, the first, third, and fifth transistors are PMOS transistors, and the second, fourth, and sixth transistors are NMOS transistors. The voltage received by the auto-zero control terminal AZ is used to control the closing and opening of the first, second, and third switches S1, S2, and S3. When V(AZ) is at a high level, the first, second, and third switches are closed, otherwise they are open.
[0024] Figure 1 The shown ring amplifier is used in a two-step pipelined successive approximation ADC with a TSMC 180nm manufacturing process. To reduce power consumption, the transistors of the first two inverters in the ring amplifier use core transistors and are powered by a low supply voltage (1.8V) to reduce power consumption. The transistors of the third inverter use high-voltage transistors and are powered by a high supply voltage (3.3V) to ensure a high output swing. Due to the low supply voltage of the second inverter, the output swing is small, and the dead zone embedding structure needs to use Figure 1 the capacitance level conversion structure shown, which consists of the second and third capacitors and the second and third switches, to embed a sufficiently large dead zone to ensure that the third-stage transistor can enter the cut-off state at the end of the establishment, ensuring the stability of the ring amplifier. However, this means that the gate-source voltage of the third-stage transistor is also attenuated by the voltage converted by the capacitor at the beginning of the establishment. Coupled with the small output swing of the second inverter itself, this will make the charging and discharging speed of the third-stage inverter transistor to the load capacitance very slow at the beginning of the establishment, slowing down the establishment speed of the residue amplifier. The reduction of the establishment speed means that the residue amplifier needs a longer establishment time to avoid the deterioration of the establishment error, and the conversion time of the ADC becomes longer. To make up for this, the aspect ratio of the third-stage inverter transistor can be increased, but this means that the load capacitance of the second inverter increases, the secondary pole is pushed inwards, and more power consumption is required to push the secondary pole outwards. Therefore, at low power consumption, Figure 1 it is very difficult to achieve a relatively high establishment speed for the structure.
[0025] Figure 2 Shown is a low-power and high-precision ring amplifier applicable to high supply voltage processes with a novel dead zone embedding structure according to the present invention. This ring amplifier alleviates to a certain extent Figure 1 the problem that the establishment speed of the shown ring amplifier is slow at low power consumption. Figure 2 The amplification unit of the structure uses a ring amplifier structure including three-stage inverters. All three-stage inverters adopt auto-zero technology to reduce the offset voltage of the amplifier; the first two inverters adopt the technology of low supply voltage power supply and gated power supply, which can reduce the static power consumption of the ring amplifier; a novel dead zone embedding structure is added between the second inverter and the third inverter. This structure can make the dead zone of the switched-capacitor amplifier using this amplification unit as an operational amplifier gradually increase from zero to a fixed value during the establishment process, making the ring amplifier tend to be stable at the end of the establishment while increasing the slew rate at the beginning of the establishment, decoupling the gain and speed of the amplifier to a certain extent; the third inverter also utilizes the condition of high supply voltage and adopts the cascode technology to improve the gain of the amplifier. The bias unit consists of two current mirrors and two transistors connected in diode configuration, which can provide a bias voltage for the cascode transistor of the third stage of the amplification unit.
[0026] The amplification unit has an input terminal VIN, an output terminal OUT, an auto-zero control terminal AZ, and an auto-zero control terminal a gated power control terminal bias voltage terminals Vbn, Vbp, power supply terminals VDDL and VDDH, and a ground level terminal VSS. If V(VSS), V(VDDL), and V(VDDH) respectively represent the voltages of the ground level terminal VSS, the power supply terminals VDDL and VDDH, then V(VDDL)>V(VSS), V(VDDH)>V(VSS), V(VDDL)<V(VDDH). The input terminal VIN is connected to the upper plate of the first capacitor, the output terminal OUT is connected to the drains of the sixth and seventh transistors, and the voltage received by the auto-zero control terminal AZ is used to control the closing and opening of the first, second, fifth, and sixth switches S1, S2, S5, S6. When V(AZ) is at a high level, the first, second, fifth, and sixth switches are closed, and vice versa. The auto-zero control terminal The voltage received is used to control the closing and opening of the third and fourth switches S3, S4, When it is at a high level, the third and fourth switches are closed, and vice versa. The gated power control terminal The voltage received is used to control the closing and opening of the seventh and eighth switches S7, S8, When it is at a high level, the seventh and eighth switches are closed, and vice versa. The bias voltage terminals Vbn and Vbp are respectively connected to the gates of the seventh transistor and the sixth transistor. The power supply terminal VDDL is connected to the sources of the first and third transistors, the ground level terminal VSS is connected to the sources of the second, fourth, and eighth transistors and the fourth resistor, the power supply terminal VDDH is connected to the source of the fifth transistor and the second resistor. The lower plate of the first capacitor is connected to one end of the first switch, the other end of the first switch is connected to the upper plate of the second capacitor, the gates of the first and second transistors are both connected to the lower plate of the first capacitor, and the lower plate of the first capacitor is also connected to the ground level terminal VSS through the seventh switch S7. The drain of the first transistor is connected to the drain of the second transistor and is both connected to the upper plate of the second capacitor. The lower plate of the second capacitor is connected to one end of the second switch, the other end of the second switch is connected to the upper plates of the third and fourth capacitors, the gates of the third and fourth transistors are both connected to the lower plate of the second capacitor, and the lower plate of the second capacitor is also connected to the power supply terminal VDDL through the seventh switch S8. The drain of the third transistor is connected to the drain of the fourth transistor and is both connected to the upper plates of the third and fourth capacitors. The upper plate of the third capacitor is connected to the gate of the fifth transistor, the third capacitor is in parallel with the first resistor, the upper plate of the fourth capacitor is connected to the gate of the eighth transistor, the fourth capacitor is in parallel with the third resistor, the gate of the fifth transistor is connected to one end of the second resistor through the third switch, the other end of the second resistor is connected to the power supply terminal VDDH, the gate of the eighth transistor is connected to one end of the fourth resistor through the fourth switch, the other end of the fourth resistor is connected to the ground level terminal VSS, the gate of the fifth transistor is connected to the output terminal OUT through the fifth switch, the gate of the eighth transistor is connected to the output terminal OUT through the sixth switch, the drain of the fifth transistor is connected to the source of the sixth transistor, and the drain of the eighth transistor is connected to the source of the seventh transistor. The first, third, fifth, and sixth transistors of the amplification unit are P-type MOS transistors, and the second, fourth, seventh, and eighth transistors are N-type MOS transistors.
[0027] The bias unit has a power supply terminal VDDH, a ground level terminal VSS, an output terminal Vbn, and an output terminal Vbp. Among them, the power supply terminal VDDH is connected to the sources of the ninth, thirteenth, fifteenth, and nineteenth transistors, the ground level terminal VSS is connected to the sources of the twelfth, eighteenth, and twenty-second transistors, and the negative terminal of the first current source. The output terminal Vbn is connected to the drain of the eleventh transistor, and the output terminal Vbp is connected to the drain of the twentieth transistor. The gate of the ninth transistor is connected to the drain of the thirteenth transistor, the drain of the ninth transistor is connected to the source of the tenth transistor, the gate of the tenth transistor is connected to the drain of the fourteenth transistor, the drain of the tenth transistor is connected to the gate and drain of the eleventh transistor, the source of the eleventh transistor is connected to the drain of the twelfth transistor, the gate of the thirteenth transistor is connected to the drain of the thirteenth transistor and the gate of the fifteenth transistor, the drain of the thirteenth transistor is connected to the source of the fourteenth transistor, the gate of the fourteenth transistor is connected to the drain of the fourteenth transistor, the gate of the sixteenth transistor, and the positive terminal of the first current source. The drain of the fifteenth transistor is connected to the source of the sixteenth transistor, the drain of the sixteenth transistor is connected to the drain and gate of the seventeenth transistor, and the gate of the twenty-first transistor. The source of the seventeenth transistor is connected to the drain and gate of the eighteenth transistor and the gate of the twenty-second transistor. The drain of the nineteenth transistor is connected to the source of the twentieth transistor, the drain of the twentieth transistor is connected to the gate of the twentieth transistor, the drain of the twenty-first transistor, and the gate of the nineteenth transistor. The source of the twenty-first transistor is connected to the drain of the twenty-second transistor. The ninth, tenth, thirteenth, fourteenth, fifteenth, sixteenth, nineteenth, and twentieth transistors of the bias unit are P-type MOS transistors, and the eleventh, twelfth, seventeenth, eighteenth, twenty-first, and twenty-second transistors are N-type MOS transistors.
[0028] As described above, the low-power and high-precision ring amplifier applicable to high-power supply voltage processes with the novel dead zone embedding structure provided by the present invention is different from the traditional ring amplifier. In the present invention, the automatic zero adjustment technology is adopted for all three-stage inverters. By closing the first, second, fifth, and sixth switches, the input and output of the inverter are short-circuited, so that the difference between the inverter flip point voltage and the common-mode voltage is stored on the capacitor, thereby reducing the offset voltage of the amplifier. In other previous ring amplifiers, part of the automatic zero adjustment is only applied to the first two stages or the first stage, and the offset voltage of the third stage is still not cancelled. Another part of the automatic zero adjustment method is to short-circuit the input and output of the ring amplifier to cancel the offset voltage of the three-stage inverter. However, since the feedback coefficient of this method is 1, the phase margin is low, and there may be problems with loop stability. On the contrary, the automatic zero adjustment method of the present invention not only realizes the zero adjustment of the three-stage inverter, making the offset voltage as low as possible, but also does not have problems with loop stability.
[0029] The first two stages of inverters adopt the technique of gated power supply. When the amplifier is not working, by closing the seventh and eighth switches, the input of the first-stage inverter is set to the ground level, and the input of the second-stage inverter is set to the power supply level. At this time, the current of the first two stages of inverters is close to zero, which can reduce the static power consumption of the ring amplifier. At the same time, since the output of the first-stage inverter is at the power supply level at this time, the charge stored in the second capacitor is zero, and the charge that the first-stage inverter needs to charge it during the auto-zeroing stage is reduced, improving the establishment speed of auto-zeroing. This gated power supply technique does not require adding gated transistors to the inverter branch, will not introduce parasitic resistance, and avoids reducing the secondary point frequency and amplifier speed.
[0030] A novel dead zone embedding structure is added between the second-stage inverter and the third-stage inverter. During the auto-zeroing stage, due to the closing of the fifth and sixth switches, the voltage difference between the third and fourth capacitors is set to the voltage difference between the switching voltages of the second-stage inverter and the third-stage inverter. After the auto-zeroing stage ends and enters the amplification stage, since the voltages of the third and fourth capacitors are the voltage difference between the switching voltages of the second-stage inverter and the third-stage inverter, the output of the second-stage inverter can be transmitted to the input of the third-stage inverter without attenuation at the initial stage of the establishment of the amplification stage, achieving a higher slew rate of the third-stage inverter at the initial stage of establishment. During the establishment process, due to the closing of the third and fourth switches, the second-stage inverter continuously charges the third and fourth capacitors until the voltage difference of the third capacitor is equal to the value determined by the resistor voltage division structure of the first and second resistors, and the voltage difference of the fourth capacitor is equal to the value determined by the resistor voltage division structure of the third and fourth resistors. Therefore, the dead zone voltage of this ring amplifier will continuously increase during the establishment process, making the ring amplifier tend to be stable at the end of establishment while improving the slew rate at the initial stage of establishment. By setting the resistance values of the first to fourth resistors, the final size of this dead zone voltage can be set. As long as this dead zone size is large enough, the transistors of the third-stage inverter can enter the cut-off region under various PVT conditions at the end of establishment, so that the ring amplifier can maintain the stability during establishment under various PVT conditions. Since this dead zone embedding structure improves the slew rate at the initial stage of establishment, under the same slew rate requirement, the aspect ratio of the transistors of the third-stage inverter can be made relatively small. At the same secondary point frequency, the power consumption of the second-stage inverter can be reduced, decoupling the power consumption and establishment speed of the amplifier to a certain extent. Moreover, since the aspect ratio of the transistors of the third-stage inverter can be relatively small, the length of the transistors can be slightly increased to improve the gain while maintaining a relatively high establishment speed.
[0031] The third-stage inverter also utilizes the condition of high power supply voltage and adopts the cascode technique to improve the gain of the amplifier. The gate bias voltage of the cascode transistor is provided by a bias unit, and the bias unit consists of two current mirrors and two transistors connected in diode configuration.
[0032] It is worth mentioning that the low-power and high-precision ring amplifier with a novel dead zone embedding structure suitable for high supply voltage processes provided by the present invention not only shows the advantage of fast settling speed in high supply voltage processes, but also shows the advantage of fast settling speed in low supply voltage processes such as 65nm and 28nm. Figure 3 Two dead zone embedding structures of ring amplifiers commonly used in low supply processes are shown. Structure (a) is similar to Figure 1 the structure of, and the power supply voltages of the three stages are equal. It also has the defect of low slew rate at the initial stage of establishment. Structure (b) is a self-biased structure with PVT stability. The resistor R1 therein can be not only a resistor but also a transmission gate. Compared with structure (a), the slew rate at the initial stage of establishment is higher. Because at the initial stage of establishment, the second-stage transistor charges and discharges the gate of the third-stage transistor, and the current flowing through the resistor R1 is very small, which is equivalent to a very small dead zone voltage. The gate-source voltage of the third-stage transistor is not attenuated. Therefore, the charging and discharging speed of the third-stage transistor to the load capacitor is high. However, if the embedded dead zone is large, at the same power consumption, the resistance value of the resistor R1 is relatively large. In this case, in the middle stage of establishment, due to the large resistance value of the resistor R1, the sub-pole frequency at the output end of the second-stage inverter is low, the delay of the second-stage inverter increases, and the attenuation speed of the oscillation of the ring amplifier is slow and it is difficult to stabilize. In contrast, the low-power and high-precision ring amplifier with a novel dead zone embedding structure suitable for high supply voltage processes provided by the present invention not only does not have the problem of low slew rate at the initial stage of establishment of structure (a), but also avoids the problem of slow oscillation attenuation speed in the middle stage of establishment of structure (b). Because its slew rate at the initial stage of establishment is high and the oscillation attenuation speed in the middle stage of establishment is fast, the required establishment time is short and the establishment speed is high.
[0033] See Embodiment 2 Figure 4 。
[0034] Embodiment 2 describes how to apply the low-power and high-precision ring amplifier with a novel dead zone embedding structure suitable for high supply voltage processes as a residue amplifier in a pipelined SAR ADC.
[0035] The circuit structure diagram of applying the low-power and high-precision ring amplifier with a novel dead zone embedding structure suitable for high supply voltage processes to a pipelined SAR ADC and the timing diagram of the switches in the circuit diagram are as Figure 4As shown, this structure simulates the situation where the ring amplifier is applied as a residue amplifier inside a pipelined SAR ADC. Among them, the capacitor Cs is equivalent to the CDAC of the previous-stage SAR ADC, the capacitor Cfb is equivalent to the feedback capacitor of the switched-capacitor residue amplifier, and the capacitor CL is equivalent to the CDAC of the next-stage SAR ADC; the lower plate of the capacitor Cs is connected to two switches, and the other ends of the two switches are respectively connected to Vin and Vin-res, where Vin represents the input signal of the previous-stage ADC, and res represents the residue after the previous-stage ADC has completed quantization of the input signal Vin. The upper plate of the capacitor Cs is connected to the common-mode voltage VCM through one switch and to the input terminal VIN of the ring amplifier through another switch; the input terminal VIN of the ring amplifier is connected to the common-mode voltage VCM through one switch; the upper plate of the capacitor Cfb is connected to the upper plate of the capacitor Cs, and the lower plate is connected to the lower plate of CL. The upper plate of the capacitor Cfb is also connected to the common-mode voltage VCM and the output terminal OUT of the ring amplifier through two switches respectively; the upper plate of the capacitor CL is connected to the common-mode voltage VCM. Among them, the common-mode voltage is equal to the average value of the voltage of the power supply terminal VDDH and the ground level terminal VSS. The control timing of the above-mentioned switches is as Figure 4 shown in the right half. This timing simulates the situation of normal operation of a pipelined SAR ADC. When φ1 and φ 1e are at high level, the previous-stage SAR ADC samples the input signal on the lower plate. That is to say, the lower plate of the capacitor Cs is connected to the input signal source, and the upper plate is connected to VCM. The voltage value of the capacitor tracks the change of the input signal. At the same time, the lower plate of the capacitor Cfb is connected to the common-mode voltage VCM, and the charge stored in Cfb is reset to zero. Then φ 1e becomes low level, the upper plate of the capacitor Cs is disconnected from VCM, and then φ1 becomes low level, and the lower plate of Cs is disconnected from the input signal. In this way, the voltage of the input signal at the moment when φ 1e becomes low level is stored in Cs; then the SAR ADC starts quantization. After quantization for a period of time, the gated power control terminal becomes low level, and the first two stages of the ring amplifier are adjusted from the sleep state to the working state. After that, the ring amplifier performs auto-zeroing, and the auto-zeroing control terminal AZ becomes high level, Becomes low level, the input terminals VIN and VCM of the ring amplifier are connected, and the states of the switches controlled by the auto-zero control terminal inside the ring amplifier also change. This operation is equivalent to storing the offset voltage of the ring amplifier relative to VCM in the capacitor inside the ring amplifier, and the input offset voltage in the subsequent amplification stage can be greatly reduced. While the ring amplifier is auto-zeroing, the previous-stage SAR ADC is still quantifying. After the auto-zeroing is completed, the ADC quantization is also completed. The process of ADC quantization is equivalent to connecting the lower plate of the capacitor Cs to the voltage corresponding to the quantized codeword. Since the difference between the voltage corresponding to the codeword and the input signal Vin is the residual RES of the ADC, when the ring amplifier enters the amplification stage, that is, when φ2 becomes high level, the lower plate of Cs is connected to Vin - res. At the same time, the input terminal VIN of the ring amplifier is connected to the upper plate of Cs, and the lower plate of Cfb, that is, the lower plate of CL, is connected to the output terminal OUT of the ring amplifier. According to the charge conservation of the capacitor, theoretically the voltage at the output terminal OUT of the ring amplifier will gradually build up to wherein is the gain of the residue amplifier. After φ2 becomes low level, the sampling switch of the CDAC of the subsequent-stage SAR ADC is disconnected, and the voltage is stored on CL and serves as the input signal of the subsequent-stage SAR ADC. Then the subsequent-stage SAR ADC starts to quantify. For the sake of simplicity, the comparator and SAR logic of the previous-stage SAR ADC, and the sampling switch of the subsequent-stage SAR ADC are not shown in the figure.
[0036] The above embodiments only illustratively explain the principles and effects of the present invention, rather than limiting the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. For example, although the cascode structure of the last-stage inverter of the amplification unit can improve the gain, it reduces the output swing. If the output swing is more important than the gain in practical applications, then the cascode transistor and the bias unit can be removed; another example is that if both the previous-stage ADC and the subsequent-stage ADC are fully differential ADCs, then the first two inverters can be changed to a fully differential structure, and then a dead zone embedding structure and the third-stage inverter are respectively connected to the positive and negative outputs of the second-stage inverter. Due to the advantages of this amplifier, such as being applicable to high supply voltage processes, fast settling speed, low power consumption, low offset voltage, and high gain, it can be used as the residue amplifier of a high-speed, high-precision, and high-energy-efficiency pipelined SAR ADC and applied to high-tech fields such as biological detection, Internet of Things, and industrial process control.
Claims
1. A low-power, high-precision ring amplifier for high-supply voltage processes using a novel dead-zone embedded structure, It is characterized in that It includes an amplification unit and a bias unit. The amplification unit adopts a ring amplifier structure including three-stage inverters. The three-stage inverters all adopt automatic zeroing technology to reduce the offset voltage of the amplifier. The first two stages of inverters adopt low power supply voltage and gated power supply technology to reduce the static power consumption of the ring amplifier. A new dead zone embedded structure is added between the second-stage inverter and the third-stage inverter. This structure can make the dead zone of the switched capacitor amplifier using this amplification unit as the operational amplifier gradually increase from zero to a fixed value during the establishment process, so that the ring amplifier tends to be stable at the end of the establishment period while improving the slew rate at the beginning of the establishment period, and to a certain extent decouple the amplifier's establishment speed, gain, and power consumption; The third-stage inverter also utilizes the condition of high power supply voltage and adopts common source and common gate technology to improve the gain of the amplifier. The bias unit is composed of two current mirrors and two diode-connected transistors, and can provide a bias voltage for the third-stage common-gate transistor of the amplification unit.
2. The low-power consumption and high-precision ring amplifier with a novel dead zone embedded structure suitable for high power supply voltage process according to claim 1, characterized in that: The amplification unit has an input terminal VIN, an output terminal OUT, an auto-zero control terminal AZ, and an auto-zero control terminal a gated power supply control terminal bias voltage terminals Vbn, Vbp, power supply terminals VDDL and VDDH, and a ground level terminal VSS. If V(VSS), V(VDDL), and V(VDDH) respectively represent the voltages of the ground level terminal VSS, the power supply terminals VDDL and VDDH, then V(VDDL)>V(VSS), V(VDDH)>V(VSS), and V(VDDL)<V(VDDH). The input terminal VIN is connected to the upper plate of the first capacitor, the output terminal OUT is connected to the drains of the sixth and seventh transistors, and the voltage received by the auto-zero control terminal AZ is used to control the closing and opening of the first, second, fifth, and sixth switches S1, S2, S5, and S6. When V(AZ) is at a high level, the first, second, fifth, and sixth switches are closed, otherwise they are open. The auto-zero control terminal receives a voltage that is used to control the closing and opening of the third and fourth switches S3 and S4, and when it is at a high level, the third and fourth switches are closed, otherwise they are open. The gated power supply control terminal receives a voltage that is used to control the closing and opening of the seventh and eighth switches S7 and S8, and when it is at a high level, the seventh and eighth switches are closed, otherwise they are open. The bias voltage terminals Vbn and Vbp are respectively connected to the gates of the seventh and sixth transistors. The power supply terminal VDDL is connected to the sources of the first and third transistors, the ground level terminal VSS is connected to the sources of the second, fourth, and eighth transistors and the fourth resistor, and the power supply terminal VDDH is connected to the source of the fifth transistor and the second resistor. The lower plate of the first capacitor is connected to one end of the first switch, the other end of the first switch is connected to the upper plate of the second capacitor, the gates of the first and second transistors are connected to the lower plate of the first capacitor, the lower plate of the first capacitor is also connected to the ground level terminal VSS through the seventh switch S7, the drain of the first transistor is connected to the drain of the second transistor, and both are connected to the upper plate of the second capacitor. The lower plate of the second capacitor is connected to one end of the second switch, the other end of the second switch is connected to the upper plates of the third and fourth capacitors, the gates of the third and fourth transistors are connected to the lower plate of the second capacitor, the lower plate of the second capacitor is also connected to the power supply terminal VDDL through the seventh switch S8, the drain of the third transistor is connected to the drain of the fourth transistor, and both are connected to the upper plates of the third and fourth capacitors. The upper plate of the third capacitor is connected to the gate of the fifth transistor, the third capacitor is connected to the first resistor in parallel, the upper plate of the fourth capacitor is connected to the gate of the eighth transistor, the fourth capacitor is connected to the third resistor in parallel, the gate of the fifth transistor is connected to one end of the second resistor through the third switch, the other end of the second resistor is connected to the power supply terminal VDDH, the gate of the eighth transistor is connected to one end of the fourth resistor through the fourth switch, the other end of the fourth resistor is connected to the ground level terminal VSS, the gate of the fifth transistor is connected to the output terminal OUT through the fifth switch, the gate of the eighth transistor is connected to the output terminal OUT through the sixth switch, the drain of the fifth transistor is connected to the source of the sixth transistor, and the drain of the eighth transistor is connected to the source of the seventh transistor. The first, third, fifth and sixth transistors of the amplifying unit are P-type MOS tubes, and the second, fourth, seventh and eighth transistors are N-type MOS tubes.
3. The low-power consumption and high-precision ring amplifier with a novel dead zone embedded structure suitable for high power supply voltage process according to claim 1, characterized in that: The bias unit has a power supply terminal VDDH, a ground level terminal VSS, an output terminal Vbn, and an output terminal Vbp. The power supply terminal VDDH is connected to the sources of the ninth, thirteenth, fifteenth, and nineteenth transistors, the ground level terminal VSS is connected to the sources of the twelfth, eighteenth, and twenty-second transistors, and the negative terminal of the first current source, the output terminal Vbn is connected to the drain of the eleventh transistor, and the output terminal Vbp is connected to the drain of the twentieth transistor. The gate of the ninth transistor is connected to the drain of the thirteenth transistor, the drain of the ninth transistor is connected to the source of the tenth transistor, the gate of the tenth transistor is connected to the drain of the fourteenth transistor, the drain of the tenth transistor is connected to the gate and drain of the eleventh transistor, the source of the eleventh transistor is connected to the drain of the twelfth transistor, the gate of the thirteenth transistor is connected to the drain of the thirteenth transistor and the gate of the fifteenth transistor, the drain of the thirteenth transistor is connected to the source of the fourteenth transistor, the gate of the fourteenth transistor is connected to the drain of the fourteenth transistor, the gate of the sixteenth transistor is connected to the drain of the sixteenth transistor, and the gate of the A positive terminal of a current source is connected, the drain of the fifteenth transistor is connected to the source of the sixteenth transistor, the drain of the sixteenth transistor is connected to the drain and gate of the seventeenth transistor, and the gate of the twenty-first transistor is connected, the source of the seventeenth transistor is connected to the drain and gate of the eighteenth transistor, and the gate of the twenty-second transistor, the drain of the nineteenth transistor is connected to the source of the twentieth transistor, the drain of the twentieth transistor and the gate of the twentieth transistor, the drain of the twenty-first transistor and the gate of the nineteenth transistor are connected, and the source of the twenty-first transistor and the drain of the twenty-second transistor are connected. The ninth, tenth, thirteenth, fourteenth, fifteenth, sixteenth, nineteenth and twentieth transistors of the bias unit are P-type MOS tubes, and the eleventh, twelfth, seventeenth, eighteenth, twenty-first and twenty-second transistors are N-type MOS tubes.