Power-on reset circuit

Abstract

A power-on reset (POR) circuit includes a first transistor and a transistor stack. The first transistor generates an enable voltage based on a first supply voltage. The enable voltage is a reduced pattern of the first supply voltage and ramps up based on a ramp-up of the first supply voltage. The transistor stack generates a control voltage. The control voltage is a reduced pattern of the enable voltage and ramps up based on the ramp-up of the enable voltage. The control voltage delays ramping of the enable voltage such that the enable voltage ramps up to a first threshold voltage associated with the transistor stack for a first time period. In addition, when the enable voltage exceeds the first threshold voltage at the end of the first time period, a reset signal generated by the POR circuit is asserted.

Description

Technical Field

[0001] The present disclosure generally relates to electronic circuits, and more particularly, to a power-on reset circuit. Background Art

[0002] Integrated circuits (ICs) include various functional circuits that are crucial for their operation. Such functional circuits require a supply voltage higher than a predefined value to ensure accurate execution of the operation. A power-on reset (POR) circuit is typically included in an IC to generate a reset signal when the IC is powered on. The reset signal introduces a delay for reliable initialization of the functional circuits. However, to achieve the desired delay, additional components are added to the POR circuit, resulting in an increase in the overall size and complexity of the POR circuit. Additionally, the additional components consume power, thereby reducing the compatibility of such POR circuits with low-power ICs. Summary of the Invention

[0003] In one embodiment, a circuit may include a power-on reset (POR) circuit. The POR circuit may include a first transistor, a first capacitor, a transistor stack, and logic circuitry. The first transistor may include a first current terminal, a control terminal, and a second current terminal. The first current terminal of the first transistor may be configured to receive a first supply voltage from a first supply voltage terminal. The control terminal of the first transistor may be configured to receive a control voltage. Additionally, the second current terminal of the first transistor may be configured to generate an enabling voltage. The first capacitor may be coupled between the second current terminal of the first transistor and a second supply voltage terminal. The transistor stack may include a first supply terminal configured to receive the first supply voltage, a second supply terminal configured to receive the second supply voltage, and an input terminal coupled to the second current terminal of the first transistor and configured to receive the enabling voltage. Additionally, the transistor stack may include a first output terminal that may be coupled to the control terminal of the first transistor and may be configured to generate the control voltage. The transistor stack may further include a second output terminal that may be configured to generate a trigger voltage based on the first supply voltage and the enabling voltage. The logic circuitry may be coupled to the second current terminal of the first transistor and the second output terminal of the transistor stack and may be configured to receive the enabling voltage and the trigger voltage. The logic circuitry may further be configured to generate a reset signal based on the enabling voltage and the trigger voltage.

[0004] In some embodiments, the transistor stack may further include a stack of transistors of a first conduction type and a stack of transistors of a second conduction type, wherein the stack of transistors of the first conduction type and the stack of transistors of the second conduction type may be connected together at a first output node, and wherein the first output node may correspond to the second output terminal of the transistor stack such that the trigger voltage may be generated at the first output node.

[0005] In some embodiments, the transistor stack may further include a second transistor and a third transistor. The second transistor may include a control terminal, a first current terminal, and a second current terminal. The control terminal of the second transistor may be configured to receive an enabling voltage. The first current terminal of the second transistor may be coupled to the control terminal of the first transistor, wherein the first current terminal of the second transistor may correspond to the first output terminal of the transistor stack. The third transistor may include a control terminal, a first current terminal, and a second current terminal. The control terminal of the third transistor may be configured to receive an enabling voltage. Additionally, the second current terminal of the third transistor may be coupled to the first current terminal of the second transistor.

[0006] In some embodiments, the transistor stack may further include a fourth transistor and a fifth transistor. The fourth transistor may include a control terminal, a first current terminal, and a second current terminal. The control terminal of the fourth transistor may be configured to receive an enabling voltage. The first current terminal of the fourth transistor may be configured to receive a first supply voltage, wherein the first current terminal of the fourth transistor may correspond to the first supply terminal of the transistor stack. Additionally, the fifth transistor may include a control terminal, a first current terminal, and a second current terminal. The control terminal of the fifth transistor may be configured to receive an enabling voltage. The first current terminal of the fifth transistor may be coupled to the second current terminal of the fourth transistor. Additionally, the second current terminal of the fifth transistor may be coupled to the second current terminal of the second transistor and may be configured to generate a trigger voltage, wherein the coupling between the second current terminals of the second transistor and the fifth transistor may correspond to the second output terminal of the transistor stack.

[0007] In some embodiments, the transistor stack further includes a sixth transistor, which may include a control terminal, a first current terminal, and a second current terminal. The control terminal of the sixth transistor may be configured to receive an enabling voltage, wherein the coupling between the control terminals of the second, third, fourth, fifth, and sixth transistors that receive the enabling voltage may correspond to the input terminal of the transistor stack. The first current terminal of the sixth transistor may be configured to receive a second supply voltage, wherein the first current terminal of the sixth transistor may correspond to the second supply terminal of the transistor stack. The second current terminal of the sixth transistor may be coupled to the first current terminal of the third transistor.

[0008] In some embodiments, the circuit may further include a first feedback transistor and a second feedback transistor. The first feedback transistor may include a control terminal, a first current terminal, and a second current terminal. The control terminal of the first feedback transistor may be coupled to the second current terminal of the fifth transistor. The first current terminal of the first feedback transistor may be coupled to the second current terminal of the fourth transistor. The second current terminal of the first feedback transistor may be configured to receive a second supply voltage. The control terminal of the second feedback transistor may be coupled to the second current terminal of the fifth transistor. The first current terminal of the second feedback transistor may be coupled to the first current terminal of the third transistor. The second current terminal of the second feedback transistor may be configured to receive a first supply voltage.

[0009] In some embodiments, the circuit may further include a second capacitor coupled between the first current terminal of the second transistor and the second supply voltage terminal, wherein the first capacitor may be charged based on a voltage difference between an enabling voltage at the second current terminal of the first transistor and the second supply voltage at the second supply voltage terminal, and wherein the second capacitor may be charged based on a voltage difference between a control voltage at the first current terminal of the second transistor and the second supply voltage at the second supply voltage terminal.

[0010] In some embodiments, the logic circuit may include a first logic gate coupled to the second output terminal of the transistor stack and configured to receive a trigger voltage. The first logic gate may be further configured to generate a first output voltage based on the trigger voltage, wherein the first output voltage may be an inverted form of the trigger voltage. The logic circuit may further include a second logic gate coupled to the first logic gate and the second current terminal of the first transistor and configured to receive the first output voltage and an enabling voltage. The second logic gate may be further configured to generate a reset signal based on the first output voltage and the enabling voltage, wherein the reset signal may be asserted when the first output voltage is equal to the first supply voltage and the enabling voltage is higher than the second supply voltage.

[0011] In some embodiments, the reset signal may be a logical "AND" of the enabling voltage and the first output voltage.

[0012] In another embodiment, the circuit may include a power-on reset (POR) circuit. The POR circuit may include a first transistor and a transistor stack. The first transistor may include a first current terminal, a control terminal, and a second current terminal. The first current terminal of the first transistor may be configured to receive a first supply voltage from a first supply voltage terminal. The control terminal of the first transistor may be configured to receive a control voltage. The second current terminal of the first transistor may be configured to generate an enable voltage. The transistor stack may be coupled to the second current terminal and the control terminal of the first transistor, wherein the transistor stack may be configured to receive the enable voltage. The transistor stack may be further configured to generate a control voltage and a trigger voltage, wherein when the enable voltage is less than a first threshold voltage associated with the transistor stack, the control voltage may increase based on an increase in the enable voltage, and the trigger voltage may remain higher than a second supply voltage, wherein when the control voltage increases, the enable voltage may ramp up to the first threshold voltage within a first time period, and wherein when the enable voltage equals the first threshold voltage at the end of the first time period, the trigger voltage may drop to the second supply voltage, thereby asserting a reset signal of the POR circuit.

[0013] In some embodiments, the circuit may further include logic circuitry, the logic circuitry may be coupled to the transistor stack and the second current terminal of the first transistor, wherein the logic circuitry may be configured to receive the trigger voltage and the enable voltage. The logic circuitry may be further configured to generate a reset signal based on the trigger voltage and the enable voltage.

[0014] In some embodiments, when the control voltage increases, a rate of increase of a voltage difference between (i) the first supply voltage at the first current terminal of the first transistor and (ii) the control voltage at the control terminal of the first transistor may decrease from a first rate to a second rate, and wherein when the first supply voltage is less than a second threshold voltage of the first transistor, the rate of increase of the voltage difference between the first supply voltage at the first current terminal and the control voltage at the control terminal may be at the first rate.

[0015] In some embodiments, when the rate of increase of the voltage difference between the first supply voltage at the first current terminal and the control voltage at the control terminal decreases from the first rate to the second rate, a rate of change of an attribute of the first transistor may change.

[0016] In some embodiments, the attribute of the first transistor may be one of a group consisting of resistance, impedance, admittance, and reactance.

[0017] In some embodiments, a transistor stack may include a stack of transistors of a first conduction type that may be coupled to a first transistor, and wherein the stack of transistors of the first conduction type may be configured to receive an enable voltage. The stack of transistors of the first conduction type may be further configured to pull down a control voltage to a second supply voltage when the enable voltage is equal to a first threshold voltage, wherein when the control voltage may be pulled down to the second supply voltage, the enable voltage may ramp up to a first supply voltage during a second time period.

[0018] In some embodiments, the stack of transistors of the first conduction type may include a second transistor and a third transistor. The second transistor may include a control terminal, a first current terminal, and a second current terminal. The control terminal of the second transistor may be configured to receive the enable voltage. The first current terminal of the second transistor may be coupled to the control terminal of the first transistor. The third transistor may include a control terminal, a first current terminal, and a second current terminal. The control terminal of the third transistor may be configured to receive the enable voltage. Additionally, the second current terminal of the third transistor may be coupled to the first current terminal of the second transistor.

[0019] In some embodiments, the transistor stack may further include a stack of transistors of a second conduction type that is coupled to the first transistor, wherein the stack of transistors of the second conduction type may be configured to receive the first supply voltage and the enable voltage. The stack of transistors of the second conduction type may be further configured to generate a trigger voltage based on the first supply voltage and the enable voltage, wherein when the enable voltage may be less than the first threshold voltage, the trigger voltage is equal to the first supply voltage, and when the trigger voltage may drop to the second supply voltage, the enable voltage may be higher than the first threshold voltage.

[0020] In some embodiments, the stack of transistors of the second conduction type includes a fourth transistor and a fifth transistor. The fourth transistor may include a control terminal, a first current terminal, and a second current terminal. The control terminal of the fourth transistor may be configured to receive the enable voltage. The first current terminal of the fourth transistor may be configured to receive the first supply voltage. Additionally, the fifth transistor may include a control terminal, a first current terminal, and a second current terminal. The control terminal of the fifth transistor may be configured to receive the enable voltage. The first current terminal of the fifth transistor may be coupled to the second current terminal of the fourth transistor. Additionally, the second current terminal of the fifth transistor may be coupled to the second current terminal of the second transistor and may be configured to generate the trigger voltage.

[0021] In some embodiments, the stack of transistors of the first conduction type may further include a sixth transistor that includes a control terminal, a first current terminal, and a second current terminal. The control terminal of the sixth transistor may be configured to receive the enable voltage. The first current terminal of the sixth transistor may be configured to receive the second supply voltage terminal. The second current terminal of the sixth transistor may be coupled to the first current terminal of the third transistor.

[0022] In some embodiments, the circuit further includes a first capacitor and a second capacitor. The first capacitor may be coupled between a second current terminal of the first transistor and a second supply voltage terminal, wherein the first capacitor may be charged based on a voltage difference between an enabling voltage at the second current terminal of the first transistor and the second supply voltage at the second supply voltage terminal. The second capacitor may be coupled between a first current terminal of the second transistor and the second supply voltage terminal, wherein the second capacitor may be charged based on a voltage difference between a control voltage at the first current terminal of the second transistor and the second supply voltage at the second supply voltage terminal, and wherein the control voltage may be adjusted based on the charging of the second capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following detailed description of embodiments of the present disclosure will be better understood when read in conjunction with the accompanying drawings. The present disclosure is illustrated by way of example and is not limited by the drawings, in which like reference numerals indicate like elements.

[0024] Figure 1 FIG. shows a schematic block diagram of a circuit such as an integrated circuit (IC) according to an embodiment of the present disclosure;

[0025] Figure 2 shows a schematic circuit diagram of a power-on reset (POR) circuit of an IC according to an embodiment of the present disclosure Figure 1 of;

[0026] Figure 3 FIG. represents a timing diagram showing the operation of the POR circuit of an IC according to an embodiment of the present disclosure Figure 1 of at a first slew rate of a first supply voltage;

[0027] Figure 4 FIG. represents a timing diagram showing the operation of the POR circuit of an IC according to an embodiment of the present disclosure Figure 1 of at a second slew rate of the first supply voltage; and

[0028] Figure 5 FIG. represents a timing diagram showing the rate of change of a changing property of a first transistor of the POR circuit of an IC according to an embodiment of the present disclosure Figure 1 of and the voltage difference between the first supply voltage at the first current terminal and the control voltage at the control terminal. DETAILED DESCRIPTION

[0029] The detailed description of the drawings is intended as a description of embodiments of the present disclosure and is not intended to represent the only form in which the present disclosure may be practiced. It should be understood that the same or equivalent functions may be implemented by different embodiments that are intended to be covered within the spirit and scope of the present disclosure.

[0030] Overview:

[0031] A power-on reset (POR) circuit generates a reset signal based on the power supply (e.g., supply voltage) to an integrated circuit (IC) including the POR circuit. During the ramp-up of the supply voltage, when the supply voltage exceeds a predetermined threshold, the reset signal transitions from a de-asserted state (e.g., logic low state) to an asserted state (e.g., logic high state). When the reset signal is de-asserted, various components of the integrated circuit (IC) are typically inoperable (e.g., can be in a standby mode), and when the reset signal is asserted, various components of the integrated circuit (IC) can become operable specifically. Conventional POR circuits are designed using a combination of various components to enable the generation of the reset signal after a desired time delay. Typically, in a POR circuit, a low-impedance path is formed between the supply voltage and the ground terminal during the steady state of the supply voltage. Therefore, when the supply voltage is in the steady state, the POR circuit consumes a steady-state current, resulting in an increase in static power consumption. When the supply voltage exceeds the predetermined threshold during the ramp-up of the supply voltage, a POR circuit designed to reduce static power consumption cannot provide the desired snapback level accuracy when generating the reset signal. Additionally, the reset signal may be asserted due to leakage current in the POR circuit, thereby generating a false assertion of the reset signal.

[0032] Various embodiments of the present disclosure disclose an IC that includes a power supply, a POR circuit, and a functional circuit. When a first supply voltage is higher than a predefined value, the POR circuit can generate a reset signal to ensure the accurate execution of related operations of the functional circuit. This predefined value of the first supply voltage is referred to as the snapback value. The POR circuit may include a first transistor, a transistor stack, and a logic circuit. The first transistor generates an enabling voltage based on the first supply voltage such that the enabling voltage ramps up based on the ramp-up of the first supply voltage. The transistor stack generates a control voltage and a trigger voltage based on the enabling voltage and the first supply voltage. Additionally, the logic circuit can generate a reset signal based on the enabling voltage and the trigger voltage.

[0033] When the enable voltage is below a first threshold voltage associated with a transistor stack, the control voltage ramps based on a ramp of the enable voltage, and the trigger voltage remains above a second supply voltage. Based on the ramp of the control voltage, the enable voltage ramps up to the first threshold voltage within a first time period. At the end of the first time period, the trigger voltage drops to the second supply voltage, thereby asserting a reset signal. Thus, during the ramp-up of the first supply voltage, when the first supply voltage is less than a trip-off value, the reset signal is de-asserted. The ramp rate of the enable voltage is controlled by the control voltage such that the enable voltage exceeds the first threshold voltage when the first supply voltage exceeds the trip-off value at the end of the first time period, and the reset signal transitions from a de-asserted state to an asserted state. When the enable voltage exceeds the first threshold voltage, the control voltage is pulled to the second supply voltage (e.g., ground voltage) by the transistor stack. Additionally, during the steady state of the first supply voltage, the enable voltage is equal to the first supply voltage, and the trigger voltage and the control voltage are equal to the second supply voltage.

[0034] Compared to a conventional POR circuit, the POR circuit of the present disclosure utilizes a smaller number of delay elements to generate a reset signal with a desired time delay (e.g., the first time period). Additionally, compared to a conventional POR circuit, the POR circuit can achieve the same trip-off level accuracy over a wide range of ramp rates of the first supply voltage and over a wide temperature range while occupying a smaller footprint. During the steady state of the first supply voltage, the control voltage and the trigger voltage are at the second supply voltage, and the enable voltage is equal to the first supply voltage. In other words, in the POR circuit of the present disclosure, a low impedance path between the power supply and the second first supply voltage terminal (e.g., ground terminal) is prevented during the steady state. Thus, consumption of non-zero steady state current by the POR circuit is prevented. Accordingly, the power consumption of the IC of the present disclosure is significantly reduced compared to the power consumed by a conventional POR circuit. Thus, the POR circuit of the present disclosure provides higher efficiency and is more compact than a conventional POR circuit. When the reset signal is asserted based on the enable voltage and the trigger voltage, the impact of leakage current from the logic circuit on the assertion of the reset signal is minimized. Thus, the POR circuit of the present disclosure is significantly robust across process, voltage, and temperature (PVT) variations and different supply ramp rates.

[0035] Figure 1 FIG. shows a schematic block diagram of a circuit 100 such as an integrated circuit (IC) 100 according to an embodiment of the present disclosure. The IC 100 may include a power supply 102, a power-on reset (POR) circuit 104, and a functional circuit 106. The IC 100 may be implemented in a power regulator, a digital signal processing system, a system-on-chip (SoC), a communication system, etc. Although Figure 1The power supply 102, POR circuit 104, and functional circuit 106 are shown implemented on the IC 100, but the scope of the present disclosure is not limited thereto. In various other embodiments, some of the circuits may be external to the IC 100. For example, in some embodiments, the power supply 102 may be external to the IC 100.

[0036] The power supply 102 may be configured to generate a first supply voltage VDD. In one example, the first supply voltage VDD is equal to 2.4 volts (V). However, in various other embodiments, the first supply voltage VDD may have other values.

[0037] The POR circuit 104 may be configured to ensure reliable initialization of the functional circuit 106 such that the functional circuit 106 can operate in a known and stable state. The POR circuit 104 may be coupled to the power supply 102 and a second supply voltage terminal. In one embodiment, the second supply voltage terminal may be a ground terminal. The POR circuit 104 may be configured to receive the first supply voltage VDD from the power supply 102 and generate a reset signal RST when the first supply voltage VDD is higher than a predefined value. The first supply voltage VDD is selected to be higher than the predefined value to ensure that the functional circuit 106 can receive the first supply voltage VDD at a desired level. In the ongoing description, the predefined value of the first supply voltage VDD may be referred to as the trip value. In one embodiment, during the ramp-up of the first supply voltage VDD, when the first supply voltage VDD is less than the trip value, the reset signal RST is de-asserted (e.g., the reset signal RST is in a logic low state). When the first supply voltage VDD exceeds the trip value, the reset signal RST transitions from the de-asserted state to the asserted state (e.g., logic high state). Additionally, the reset signal RST remains asserted during the remainder of the ramp-up and during the steady state of the first supply voltage VDD (e.g., when the first supply voltage VDD is constant). The trip value may remain substantially stable across different ramp-up rates of the first supply voltage VDD. The POR circuit 104 may utilize a relatively small number of delay elements to generate a reset signal RST with a desired time delay, thereby occupying a smaller footprint compared to conventional POR circuits. For example, the POR circuit 104 may occupy 40% less footprint compared to a conventional POR circuit.

[0038] Embodiments of the POR circuit 104 may not be limited to any particular complementary metal-oxide-semiconductor (CMOS) technology and may be used in any standard CMOS technology. Examples of standard CMOS technologies may include 40 nanometer (nm) CMOS, 22 nm CMOS, 14 nm CMOS, 7 nm CMOS, etc. In an exemplary embodiment, the POR circuit 104 may be compatible with a wide range of ramp rates (e.g., 100 microseconds (μs) - 100 milliseconds (ms)). Additionally, the POR circuit 104 may be able to detect the dropout value (e.g., 0.85 V) of the first supply voltage VDD with high precision (e.g., 5 sigma) at a wide range of ramp rates. Additionally, the POR circuit 104 may occupy only an area of 0.008 square millimeters (mm2). Additionally, during the steady state of the first supply voltage VDD, all voltages and signals of the POR circuit 104 are equal to the first supply voltage VDD or the second supply voltage VSS. Thus, the POR circuit 104 is prevented from consuming non-zero steady-state (e.g., static) current. In combination with Figure 2 and 3 POR circuit 104 is explained in detail.

[0039] The functional circuit 106 may be coupled to the power supply 102, the POR circuit 104, and the second supply voltage terminal. The functional circuit 106 may include suitable circuitry that may be configured to perform one or more operations. For example, the functional circuit 106 may be configured to receive the first supply voltage VDD and the reset signal RST from the power supply 102 and the POR circuit 104, respectively. Based on the asserted state of the reset signal RST, the functional circuit 106 may additionally be configured to perform one or more operations associated therewith. Additionally, based on the de-asserted state of the reset signal RST, the functional circuit 106 may be inoperable (e.g., may be in a standby mode). Thus, the reset signal RST ensures that the functional circuit 106 is operable when the first supply voltage VDD is within the desired range (e.g., above the dropout value).

[0040] In one embodiment, the functional circuit 106 is an example functional circuit that may utilize the reset signal RST to perform the operations of the functional circuit 106. However, the scope of the present disclosure is not limited thereto. In various other embodiments, without departing from the scope of the present disclosure, the reset signal RST may be utilized by various other functional circuits of the IC 100. Examples of the functional circuit 106 may include analog circuits, application-specific integrated circuits (ASICs), digital circuits, memory circuits, sensors, input / output circuits, processor circuits, communication circuits, or any combination thereof.

[0041] The scope of the present disclosure is not limited to the second power supply voltage terminal being a low power supply voltage terminal. In other embodiments, the second power supply voltage VSS of the second power supply voltage terminal may correspond to a non-zero value (e.g., -1V, 1V, or the like).

[0042] Figure 2 FIG. 4 shows a schematic circuit diagram of a POR circuit 104 according to an embodiment of the present disclosure. The POR circuit 104 may include a delay circuit 202, a hysteresis circuit 204, and a logic circuit 206.

[0043] Delay circuit 202:

[0044] The delay circuit 202 may be coupled to a first power supply voltage terminal and a second power supply voltage terminal. The delay circuit 202 may be configured to receive a first power supply voltage VDD. The delay circuit 202 may be further configured to generate an enable voltage EV such that the enable voltage EV ramps up based on the ramp-up of the first power supply voltage VDD. The delay circuit 202 may include a first transistor T1 and a first capacitor 208.

[0045] The first transistor T1 may be coupled to the first power supply voltage terminal (e.g., the power supply 102). Examples of the first transistor T1 may include a bipolar junction transistor (BJT), a field effect transistor (FET), an insulated gate bipolar transistor (IGBT), etc. In one embodiment, the first transistor T1 corresponds to a p-channel metal oxide semiconductor (PMOS) transistor. The first transistor T1 may include a first current terminal, a second current terminal, and a control terminal. In the present disclosure, the first current terminal and the second current terminal of the transistor correspond to the source terminal and the drain terminal of the transistor, respectively, and the control terminal corresponds to the gate terminal of the transistor.

[0046] The first current terminal of the first transistor T1 may be coupled to the first power supply voltage terminal. The first current terminal of the first transistor T1 may be configured to receive the first power supply voltage VDD from the first power supply voltage terminal. The second current terminal of the first transistor T1 may be configured to generate the enable voltage EV when the first power supply voltage VDD crosses the threshold voltage of the first transistor T1. Additionally, the control terminal of the first transistor T1 may be configured to receive a control voltage VC.

[0047] The first capacitor 208 can be coupled between the second current terminal of the first transistor T1 and the second supply voltage terminal. The first capacitor 208 can be charged based on the voltage difference between the enable voltage EV at the second current terminal of the first transistor T1 and the second supply voltage VSS at the second supply voltage terminal. Based on the charging of the first capacitor 208, the slew rate at which the enable voltage EV rises to the first threshold voltage associated with the hysteresis circuit 204 is adjusted. In other words, the capacitance associated with the first capacitor 208 can control the slew rate at which the enable voltage EV rises to the first threshold voltage. For example, a capacitor having 10 picofarads (pF) can be utilized instead of a capacitor having 5 pF to further delay the slew rate at which the enable voltage EV rises to the first threshold voltage when the first supply voltage VDD ramps up at a fast rate (e.g., less than 10 μs). The first threshold voltage of the hysteresis circuit 204 can be the voltage level at which the output of the hysteresis circuit 204 drops below the second supply voltage VSS.

[0048] The enable voltage EV ramps up based on the ramp-up of the first supply voltage VDD. The enable voltage EV is generated based on and lower than the first supply voltage VDD until the first supply voltage VDD ramps up and reaches a steady state and the first capacitor 208 is charged. In one embodiment, the enable voltage EV is equal to the difference between the first supply voltage VDD and the threshold voltage of the first transistor T1 (hereinafter referred to as the "second threshold voltage") until the first supply voltage VDD ramps up and reaches a steady state and the first capacitor 208 is charged. When the control voltage VC increases, the rate of increase of the voltage difference between (i) the first supply voltage VDD at the first current terminal of the first transistor T1 and (ii) the control voltage VC at the control terminal of the first transistor T1 (e.g., gate-to-source voltage) decreases. For example, initially, the rate of increase of the voltage difference between the first supply voltage VDD and the control voltage VC is at a first rate. Additionally, when the control voltage VC increases, the rate of increase of the voltage difference between the first supply voltage VDD and the control voltage VC is at a second rate such that the first rate is greater than the second rate.

[0049] An attribute can be associated with the first transistor T1 such that the attribute can vary based on the voltage difference between the first supply voltage VDD at the first current terminal of the first transistor T1 and the control voltage VC at the control terminal of the first transistor T1. Additionally, the rate of change of the attribute associated with the first transistor T1 can be changed based on the change in the rate of increase of the voltage difference between the first supply voltage VDD and the control voltage VC. An example of the attribute of the first transistor T1 is one from the group consisting of resistance, impedance, admittance, and reactance. Based on the rate of change of the attribute, the slew rate associated with the enable voltage EV can be delayed. For example, the enable voltage EV can slew up to the first threshold voltage in the first time period. Additionally, the first time period can be equal to the time required for the first supply voltage VDD to exceed the trip-off value. In one embodiment, the rate of change of the attribute refers to the rate of decrease of the on-resistance (e.g., channel resistance) associated with the first transistor T1.

[0050] Hysteresis circuit 204:

[0051] The hysteresis circuit 204 can be coupled to the first supply voltage terminal, the delay circuit 202, and the second supply voltage terminal. The hysteresis circuit 204 can include a stack of transistors T2 - T6, a first feedback transistor 210, and a second feedback transistor 212.

[0052] The stack of transistors T2 - T6 can include a first supply node S1, a second supply node S2, an input node P1, a first output node O1, and a second output node O2. The first supply node S1 can be coupled to the first supply voltage terminal. Additionally, the first supply node S1 can be configured to receive the first supply voltage VDD. The second supply node S2 can be coupled to the second supply voltage terminal. Additionally, the second supply node S2 can be configured to receive the second supply voltage VSS.

[0053] The input node P1 can be coupled to the delay circuit 202 (e.g., the input node P1 can be coupled to the second current terminal of the first transistor T1). Additionally, the input node P1 can be configured to receive the enable voltage EV. The first output node O1 can be coupled to the delay circuit 202. Additionally, the first output node O1 can be configured to generate the control voltage VC. The second output node O2 can be configured to generate a trigger voltage TV such that when the enable voltage EV is less than the first threshold voltage, the trigger voltage TV can follow the first supply voltage VDD.

[0054] The stack of transistors T2 - T6 can be configured to pull down the control voltage VC to the second supply voltage VSS when the enable voltage EV is equal to the first threshold voltage associated with the stack of transistors T2 - T6 (e.g., the first threshold voltage associated with the hysteresis circuit 204).

[0055] The stack of transistors T2 - T6 may further include a stack of transistors of a first conduction type and a stack of transistors of a second conduction type. In one embodiment, the stack of transistors of the first conduction type may correspond to a stack of n-channel metal oxide semiconductor (NMOS) transistors, and the stack of transistors of the second conduction type may correspond to a stack of PMOS transistors. Additionally, the stack of transistors of the first conduction type and the stack of transistors of the second conduction type may be connected together at an output node. The output node may correspond to the second output node O2 of the transistor stack such that a trigger voltage TV may be generated at the first output node.

[0056] The stack of transistors of the first conduction type may include the second transistor T2 and the third transistor T3. The stack of transistors of the second conduction type may include the fourth transistor T4 and the fifth transistor T5. Additionally, the stack of transistors of the first conduction type may include the sixth transistor T6. Each of the second transistor T2, the third transistor T3, and the sixth transistor T6 may include a first current terminal, a control terminal, and a second current terminal.

[0057] The control terminal of the second transistor T2 may be coupled to the second current terminal of the first transistor T1. The control terminal of the second transistor T2 may be configured to receive an enable voltage EV. The first current terminal of the second transistor T2 may be coupled to the control terminal of the first transistor T1. Additionally, the first current terminal of the second transistor T2 may be configured to generate a control voltage VC when the enable voltage EV (e.g., the voltage difference between the enable voltage EV at the control terminal of the second transistor T2 and the control voltage VC at the first current terminal of the second transistor T2) crosses the third threshold voltage of the second transistor T2 (e.g., 0.7V). Additionally, the control voltage VC may be generated based on the parasitic capacitance between the second current terminal of the first transistor T1 and the first current terminal of the second transistor T2 (e.g., the parasitic capacitance between the control terminal and the first current terminal of the second transistor T2). In one embodiment, the parasitic capacitance may be generated due to the physical overlap between the gate electrode and the source region of the second transistor T2. When the enable voltage EV is applied to the control terminal of the second transistor T2, an electric field may extend into the source region, thereby generating the control voltage VC.

[0058] The control terminal of the third transistor T3 may be coupled to the second current terminal of the first transistor T1. Additionally, the control terminal of the third transistor T3 may be configured to receive the enable voltage EV. The second current terminal of the third transistor T3 may be coupled to the first current terminal of the second transistor T2.

[0059] The fourth transistor T4 and the fifth transistor T5 may include a first current terminal, a control terminal, and a second current terminal.

[0060] The first current terminal of the fourth transistor T4 may be coupled to the first supply voltage terminal. Additionally, the first current terminal of the fourth transistor T4 may be configured to receive the first supply voltage VDD. The control terminal of the fourth transistor T4 may be coupled to the second current terminal of the first transistor T1 and be configured to receive the enable voltage EV. The first current terminal of the fifth transistor T5 may be coupled to the second current terminal of the fourth transistor T4. The control terminal of the fifth transistor T5 may be coupled to the second current terminal of the first transistor T1 and be configured to receive the enable voltage EV. The second current terminal of the fifth transistor T5 may be coupled to the second current terminal of the second transistor T2. Additionally, the second current terminal of the fifth transistor T5 may be configured to generate the trigger voltage TV when the enable voltage EV is less than the first threshold voltage. In one embodiment, the second current terminal of the fourth transistor T4 may be configured to generate a first intermediate voltage (not shown) such that the first intermediate voltage is equal to the first supply voltage VDD.

[0061] The control voltage VC may ramp up as the enable voltage EV ramps up (since negligible current may flow from the first terminal of the second transistor T2 to the second current terminal of the third transistor T3). Additionally, based on the control voltage VC, the rate of increase of the voltage difference (e.g., gate-to-source voltage) between the first supply voltage VDD at the first current terminal of the first transistor T1 and the control voltage VC at the control terminal of the first transistor T1 decreases (e.g., from a first rate to a second rate). Thus, the rate of change of the property associated with the first transistor T1 decreases. In one embodiment, the coupling between the control terminals of the second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 that receive the enable voltage EV corresponds to the input node P1 of the stack of transistors T2 - T6. The first current terminal of the fourth transistor T4 corresponds to the first supply node S1 of the stack of transistors T2 - T6. Additionally, the first current terminal of the second transistor T2 corresponds to the first output node O1 of the stack of transistors T2 - T6 such that the control terminal and the second current terminal of the first transistor T1 are coupled across the first output node O1 and the input node P1 of the stack of transistors T2 - T6, respectively. Additionally, the coupling between the second current terminals of the second transistor and the fifth transistor corresponds to the second output node O2 of the stack of transistors T2 - T6.

[0062] The control terminal of the sixth transistor T6 can be coupled to the second current terminal of the first transistor T1. Additionally, the control terminal of the sixth transistor T6 can be configured to receive an enable voltage EV. The second current terminal of the sixth transistor T6 can be coupled to the first current terminal of the third transistor T3. Additionally, the second current terminal of the sixth transistor T6 can be configured to receive a voltage (e.g., a second intermediate voltage (not shown)) from the second feedback transistor 212. Additionally, the first current terminal of the sixth transistor T6 can be coupled to the second power supply voltage terminal. The first current terminal of the sixth transistor T6 can be configured to receive a second power supply voltage VSS (e.g., a ground voltage).

[0063] The first feedback transistor 210 and the second feedback transistor 212 can include a first current terminal, a control terminal, and a second current terminal.

[0064] The control terminal of the first feedback transistor 210 can be coupled to the second current terminals of the fifth transistor T5 and the second transistor T2. The control terminal of the first feedback transistor 210 can be configured to receive a trigger voltage TV. The first current terminal of the first feedback transistor 210 can be coupled to the second current terminal of the fourth transistor T4. The first current terminal of the first feedback transistor 210 can be configured to receive a first intermediate voltage. Additionally, the second current terminal of the first feedback transistor 210 can be coupled to the second power supply voltage terminal. The second current terminal of the first feedback transistor 210 can be configured to receive a second power supply voltage VSS (e.g., a ground voltage).

[0065] The first feedback transistor 210 can be configured to remain in an off state (e.g., a non-conducting state) when the enable voltage EV is less than a first threshold voltage. Additionally, the first feedback transistor 210 can be configured to turn on (e.g., remain in a conducting state) when the enable voltage EV exceeds the first threshold voltage. The first feedback transistor 210 can additionally be configured to drive the first intermediate voltage at the first current terminal of the fifth transistor T5 to the second power supply voltage VSS. In one embodiment, the second current terminal of the first feedback transistor 210 can be coupled to the first current terminal of the sixth transistor T6. The coupling between the second current terminal of the first feedback transistor 210 and the first current terminal of the sixth transistor T6 corresponds to the second power supply node S2 of the stack of transistors T2 - T6.

[0066] The control terminal of the second feedback transistor 212 can be coupled to the second current terminals of the fifth transistor T5 and the second transistor T2. The second current terminal of the second feedback transistor 212 can be coupled to the first power supply voltage terminal. The second current terminal of the second feedback transistor 212 can be configured to receive the first power supply voltage VDD. The first current terminal of the second feedback transistor 212 can be coupled to the first current terminal of the third transistor T3. Additionally, the first current terminal of the second feedback transistor 212 can be configured to generate a second intermediate voltage (not shown) such that the second intermediate voltage is equal to the first power supply voltage VDD.

[0067] The second feedback transistor 212 can be configured to remain in an on state (e.g., conducting state) when the enable voltage EV is less than the first threshold voltage. The second feedback transistor 212 can additionally be configured to drive the voltage at the second current terminal of the sixth transistor T6 to the first power supply voltage VDD. Additionally, the second feedback transistor 212 can be configured to remain in an off state (e.g., non-conducting state) when the enable voltage EV exceeds the first threshold voltage.

[0068] The POR circuit 104 can additionally include a second capacitor 218. The second capacitor 218 can be coupled between the first current terminal of the second transistor T2 and the second power supply voltage terminal.

[0069] The second capacitor 218 can be charged based on the voltage difference between the control voltage VC at the first current terminal of the second transistor T2 and the second supply voltage VSS at the second supply voltage terminal. In one embodiment, when the first supply voltage VDD ramps up at a relatively fast rate (e.g., less than 10 μs), the second capacitor 218 can be further charged at a certain rate such that the control voltage VC initially remains close to the second supply voltage VSS. Based on the charging of the second capacitor 218, the ramp-up of the control voltage VC can be adjusted. For example, a capacitor with 10 picofarads (pF) can be used instead of a capacitor with 5 pF to delay the ramp rate of the control voltage VC when the first supply voltage VDD ramps up at a faster rate. Additionally, when the enable voltage EV exceeds the first threshold voltage, the third transistor T3 and the sixth transistor T6 can be turned on, such that the control voltage VC is pulled down to the second supply voltage VSS. Additionally, the trigger voltage TV can drop to the second supply voltage VSS. Based on the trigger voltage TV and the enable voltage EV, the reset signal RST can be asserted. In one embodiment, the first supply voltage VDD crosses the trip value at the moment when the control voltage VC is pulled down to the second supply voltage VSS, such that the reset signal RST is asserted. Additionally, the property of the first transistor T1 decreases (e.g., the on-resistance of the first transistor T1 decreases), such that the ramp rate of the enable voltage EV is accelerated. For example, initially, the ramp rate of the enable voltage EV is at a third rate. Additionally, when the property of the first transistor T1 decreases, the ramp rate of the enable voltage EV is accelerated to a fourth rate, such that the fourth rate is greater than the third rate.

[0070] Although it is mentioned that the moment when the first supply voltage VDD crosses the trip value is the same as the moment when the control voltage VC is pulled down to the second supply voltage VSS, in various other embodiments, the moment when the first supply voltage VDD crosses the trip value and the moment when the control voltage VC is pulled down to the second supply voltage VSS can be different.

[0071] Logic circuit 206:

[0072] The logic circuit 206 can be coupled between the first supply voltage terminal and the second supply voltage terminal. The logic circuit 206 can be configured to receive the first supply voltage VDD and the second supply voltage VSS. Additionally, the logic circuit 206 can be coupled to the delay circuit 202 and the hysteresis circuit 204. The logic circuit 206 can be configured to receive the trigger voltage TV and the enable voltage EV. The logic circuit 206 can be further configured to generate the reset signal RST based on the trigger voltage TV and the enable voltage EV, such that when the enable voltage EV is higher than the second supply voltage VSS and the trigger voltage TV drops to the second supply voltage VSS, the reset signal RST is asserted.

[0073] The logic circuit 206 may include a first logic gate 214 and a second logic gate 216. The first logic gate 214 may be coupled between a first supply voltage terminal and a second supply voltage terminal. The first logic gate 214 may be further coupled to the second output node O2 of the hysteresis circuit 204 (e.g., between the second current terminal of the fifth transistor T5 and the second current terminal of the second transistor T2). The first logic gate 214 may be configured to receive a trigger voltage TV. The first logic gate 214 may be further configured to generate a first output voltage F1 such that the first output voltage F1 is equal to one of the first supply voltage VDD and the second supply voltage VSS. In one embodiment, the first logic gate 214 is an inverter such that the first output voltage F1 is the inverted form of the trigger voltage TV. For example, when the trigger voltage TV drops to the second supply voltage VSS, the first output voltage F1 is equal to the first supply voltage VDD. Alternatively, when the trigger voltage TV is higher than the second supply voltage VSS, the first output voltage F1 drops to the second supply voltage VSS.

[0074] The second logic gate 216 may be coupled between a first supply voltage terminal and a second supply voltage terminal. The second logic gate 216 may be further coupled to the first logic gate 214 and the second current terminal of the first transistor T1. The first logic gate 214 may be configured to receive the first output voltage F1 from the first logic gate 214 and an enable voltage EV from the first transistor T1. The second logic gate 216 may be further configured to generate a reset signal RST. In one embodiment, the second logic gate 216 is an "AND" gate such that the reset signal RST is the logical "AND" of the enable voltage EV and the first output voltage F1. For example, when the first output voltage F1 is equal to the first supply voltage VDD and the enable voltage EV is higher than the second supply voltage VSS, the reset signal RST is asserted.

[0075] In operation:

[0076] Initially, during the ramp-up period of the first supply voltage VDD (e.g., when the first supply voltage VDD ramps up from 0V), the first transistor T1 is turned off, and the enable voltage EV and the control voltage VC are at 0V. Additionally, the fourth transistor T4 may turn on as the first supply voltage VDD ramps up, such that the voltage difference (e.g., gate-to-source voltage) between the first supply voltage VDD at the first current terminal of the fourth transistor T4 and the enable voltage EV at the control terminal of the fourth transistor T4 is less than the fourth threshold voltage (e.g., -0.2V) of the fourth transistor T4. Additionally, the fifth transistor T5 may turn on such that the trigger voltage TV is equal to the first supply voltage VDD. The first feedback transistor 210 may turn off when the voltage at the first current terminal of the first feedback transistor 210 is equal to the voltage at the control terminal of the first feedback transistor 210 (e.g., the first supply voltage VDD). Additionally, the second feedback transistor 212 turns on when the voltage at the second current terminal of the second feedback transistor 212 is equal to the voltage at the control terminal of the second feedback transistor 212 (e.g., the first supply voltage VDD). The second feedback transistor 212 may be configured to generate a second intermediate voltage equal to the first supply voltage VDD such that the first supply voltage VDD can be received at the second current terminal of the sixth transistor T6.

[0077] When the trigger voltage TV is higher than the second supply voltage VSS (e.g., 0V), the first output voltage F1 may drop to the second supply voltage VSS. In an exemplary scenario, during the ramp-up period of the first supply voltage VDD, based on the leakage current from the first logic gate 214, the first output voltage F1 is equal to the first supply voltage VDD. The second logic gate 216 may assert the reset signal RST only when the first output voltage F1 is equal to the first supply voltage VDD and the enable voltage EV is higher than the second supply voltage VSS. In other words, the second logic gate 216 can prevent the unintended assertion of the reset signal RST.

[0078] When the first supply voltage VDD further ramps up and crosses the second threshold voltage, the first transistor T1 may generate the enable voltage EV. The first capacitor 208 may be charged based on the voltage difference between the enable voltage EV and the second supply voltage VSS. Based on the enable voltage EV crossing the third threshold voltage of the second transistor T2 and the parasitic capacitance between the control terminal and the first current terminal of the second transistor T2, the control voltage VC may be generated. As the enable voltage EV ramps up, the control voltage VC may ramp up. Additionally, based on the control voltage VC, the rate of increase of the voltage difference (e.g., gate-to-source voltage) between the first supply voltage VDD at the first current terminal of the first transistor T1 and the control voltage VC at the control terminal of the first transistor T1 decreases. Therefore, the rate of decrease of the on-resistance associated with the first transistor T1 (e.g., the rate at which the on-resistance of the first transistor T1 decreases) changes.

[0079] When the enabling voltage EV ramps up and crosses the first threshold voltage, the second transistor T2, the third transistor T3, and the sixth transistor T6 can be turned on, such that the control voltage VC is pulled down to the second supply voltage VSS and the trigger voltage TV drops to the second supply voltage VSS (e.g., the trigger voltage TV drops to the ground voltage). When the voltage at the control terminal of the first feedback transistor 210 is equal to the second supply voltage VSS (e.g., the ground voltage), the first feedback transistor 210 can be turned on. The first feedback transistor 210 can drive the voltage at the first current terminal of the fifth transistor T5 to the second supply voltage VSS.

[0080] The first logic gate 214 can generate a first output voltage F1 based on the trigger voltage TV dropping to the second supply voltage VSS, such that the first output voltage F1 is equal to the first supply voltage VDD. Additionally, the second logic gate 216 can receive the first output voltage F1 from the first logic gate 214, and receive the enabling voltage EV from the first transistor T1. When the first output voltage F1 is equal to the first supply voltage VDD and the enabling voltage EV is higher than the second supply voltage VSS, the second logic gate 216 can assert the reset signal RST.

[0081] The scope of the present disclosure is not limited to the delay circuit 202, the hysteresis circuit 204, and the logic circuit 206 implemented in the above manner. In various other embodiments, the delay circuit 202, the hysteresis circuit 204, and the logic circuit 206 can be implemented using different or additional components without departing from the scope of the present disclosure.

[0082] Figure 3 Depicts a timing diagram 300, which shows the operation of the POR circuit 104 according to an embodiment of the present disclosure at a first slew rate of the first supply voltage VDD.

[0083] The timing diagram 300 shows the first supply voltage VDD ramping at a first slew rate (e.g., at this time the first supply voltage VDD ramps from 0V to 2.4V in 1 ms).

[0084] At time I0, the IC 100 is powered on. The first transistor T1 is off, and the enabling voltage EV and the control voltage VC are at 0V. Additionally, the fourth transistor T4 and the fifth transistor T5 can be off.

[0085] During time period I0 - I1, the first supply voltage VDD may ramp up. When the first supply voltage VDD ramps up and crosses the second threshold voltage, the first transistor T1 may generate an enable voltage EV. When the enable voltage EV follows the first supply voltage VDD and is a reduced form of the first supply voltage VDD, the enable voltage EV ramps up during time period I0 - I1. Additionally, the enable voltage EV remains less than the first supply voltage VDD. Based on the enable voltage EV crossing the third threshold voltage of the second transistor T2 and the parasitic capacitance between the control terminal and the first current terminal of the second transistor T2, a control voltage VC may be generated. The control voltage VC follows the enable voltage EV and is a reduced form of the enable voltage EV. The control voltage VC ramps up during time period I0 - I1 and is less than the enable voltage EV. Additionally, the fourth transistor T4 may turn on as the first supply voltage VDD ramps up, such that the voltage difference (e.g., gate - to - source voltage) between the first supply voltage VDD at the first current terminal of the fourth transistor T4 and the enable voltage EV at the control terminal of the fourth transistor T4 is less than the fourth threshold voltage (e.g., - 0.2V) of the fourth transistor T4. Additionally, the fifth transistor T5 may turn on such that the trigger voltage TV is equal to the first supply voltage VDD.

[0086] When the voltage at the first current terminal of the first feedback transistor 210 is equal to the voltage at the control terminal of the first feedback transistor 210 (e.g., the first supply voltage VDD), the first feedback transistor 210 may turn off. Additionally, when the voltage at the second current terminal of the second feedback transistor 212 is equal to the voltage at the control terminal of the second feedback transistor 212 (e.g., the first supply voltage VDD), the second feedback transistor 212 turns on. The second feedback transistor 212 may be configured to generate a second intermediate voltage equal to the first supply voltage VDD such that the second current terminal of the sixth transistor T6 may receive the first supply voltage VDD.

[0087] When the trigger voltage TV is higher than the second supply voltage VSS (e.g., the first supply voltage VDD), the first output voltage F1 may be at the second supply voltage VSS (e.g., 0V). In an exemplary scenario, during the ramp - up of the first supply voltage VDD, based on the leakage current from the first logic gate 214, the first output voltage F1 is equal to the first supply voltage VDD. The second logic gate 216 may assert the reset signal RST only when the first output voltage F1 is equal to the first supply voltage VDD and the enable voltage EV is higher than the second supply voltage VSS. In other words, the second logic gate 216 may prevent the unintended assertion of the reset signal RST.

[0088] At time I1, the first supply voltage VDD exceeds the first threshold voltage. The enable voltage EV can ramp up to the first threshold voltage during a first time period such that the first time period can correspond to time period I0 - I2.

[0089] The first capacitor 208 can be charged based on the voltage difference between the enable voltage EV and the second supply voltage VSS. As the enable voltage EV ramps up, the control voltage VC can ramp up. Additionally, based on the control voltage VC, the rate of increase of the voltage difference (e.g., gate-to-source voltage) between the first supply voltage VDD at the first current terminal of the first transistor T1 and the control voltage VC at the control terminal of the first transistor T1 decreases. Accordingly, the rate of change of the property associated with the first transistor T1 (e.g., the rate of the on-resistance of the first transistor T1) changes.

[0090] At time I2, the enable voltage EV exceeds the first threshold voltage. In other words, the first supply voltage VDD may exceed the trip-off value at time I2. Additionally, the second transistor T2, the third transistor T3, and the sixth transistor T6 can be turned on such that the control voltage VC is pulled down to the second supply voltage VSS. Additionally, the trigger voltage TV can drop to the second supply voltage VSS (e.g., the trigger voltage TV drops to the ground voltage). When the voltage at the control terminal of the first feedback transistor 210 equals the second supply voltage VSS (e.g., the ground voltage), the first feedback transistor 210 can be turned on. The first feedback transistor 210 can drive the voltage at the first current terminal of the fifth transistor T5 to the second supply voltage VSS.

[0091] The first logic gate 214 can generate a first output voltage F1 based on the trigger voltage TV dropping to the second supply voltage VSS such that the first output voltage F1 equals the first supply voltage VDD. Additionally, the second logic gate 216 can receive the first output voltage F1 from the first logic gate 214 and receive the enable voltage EV from the first transistor T1. When the first output voltage F1 equals the first supply voltage VDD and the enable voltage EV is higher than the second supply voltage VSS, the second logic gate 216 can assert the reset signal RST.

[0092] During time I2 - I3, the first capacitor 208 may not be fully charged. Accordingly, the enable voltage EV is a reduced form of the first supply voltage VDD. Additionally, the control voltage VC and the trigger voltage TV are at the second supply voltage VSS. Additionally, the first output voltage F1 equals the first supply voltage VDD.

[0093] Beyond time I3, the first capacitor 208 can be fully charged, and the control voltage VC is at the second supply voltage VSS, such that the enable voltage EV is equal to the first supply voltage VDD. The reset signal RST remains at the logic high state. Additionally, the control voltage VC remains at the second supply voltage VSS.

[0094] Figure 4 Represents timing diagram 400, which shows the operation of the POR circuit 104 according to an embodiment of the present disclosure at a second slew rate of the first supply voltage VDD.

[0095] Timing diagram 400 shows that the first supply voltage VDD ramps (e.g., at this time the first supply voltage VDD ramps from 0V to 2.4V in 25 ms) at a second slew rate.

[0096] At time I0, the IC 100 is powered on. The first transistor T1 is off, and the enable voltage EV and the control voltage VC are at 0V. Additionally, the fourth transistor T4 and the fifth transistor T5 can be off.

[0097] During the time period I0 - I1, the first supply voltage VDD can ramp up. When the first supply voltage VDD can further ramp up and crosses the second threshold voltage, the first transistor T1 can generate the enable voltage EV. When the enable voltage EV follows the first supply voltage VDD and is a reduced form of the first supply voltage VDD, the enable voltage EV ramps up during the time period I0 - I1. Additionally, the enable voltage EV remains less than the first supply voltage VDD. Based on the enable voltage EV crossing the third threshold voltage of the second transistor T2 and the parasitic capacitance between the control terminal and the first current terminal of the second transistor T2, the control voltage VC can be generated. The control voltage VC follows the enable voltage EV and is a reduced form of the enable voltage EV, the control voltage VC ramps up during the time period I0 - I1 and is less than the enable voltage EV. Additionally, the fourth transistor T4 can turn on as the first supply voltage VDD ramps up, such that the voltage difference (e.g., gate - to - source voltage) between the first supply voltage VDD at the first current terminal of the fourth transistor T4 and the enable voltage EV at the control terminal of the fourth transistor T4 is less than the fourth threshold voltage of the fourth transistor T4 (e.g., - 0.2V). Additionally, the fifth transistor T5 can turn on such that the trigger voltage TV is equal to the first supply voltage VDD.

[0098] When the voltage at the first current terminal of the first feedback transistor 210 is equal to the voltage at the control terminal of the first feedback transistor 210 (e.g., the first supply voltage VDD), the first feedback transistor 210 can be turned off. Additionally, when the voltage at the second current terminal of the second feedback transistor 212 is equal to the voltage at the control terminal of the second feedback transistor 212 (e.g., the first supply voltage VDD), the second feedback transistor 212 is turned on. The second feedback transistor 212 can be configured to generate a second intermediate voltage equal to the first supply voltage VDD such that the second current terminal of the sixth transistor T6 can receive the first supply voltage VDD.

[0099] When the trigger voltage TV is higher than the second supply voltage VSS, the first output voltage F1 can drop to the second supply voltage VSS. In an exemplary scenario, during the ramp-up of the first supply voltage VDD, based on the leakage current from the first logic gate 214, the first output voltage F1 is equal to the first supply voltage VDD. The second logic gate 216 can assert the reset signal RST only when the first output voltage F1 is equal to the first supply voltage VDD and the enable voltage EV is higher than the second supply voltage VSS. In other words, the second logic gate 216 can prevent the unintended assertion of the reset signal RST.

[0100] At time I1, the first supply voltage VDD exceeds the first threshold voltage. The enable voltage EV can ramp up to the first threshold voltage in the first time period such that the first time period can correspond to the time period I0 - I2.

[0101] The first capacitor 208 can be charged based on the voltage difference between the enable voltage EV and the second supply voltage VSS. As the enable voltage EV ramps up, the control voltage VC can ramp up. Additionally, based on the control voltage VC, the rate of increase of the voltage difference (e.g., gate-to-source voltage) between the first supply voltage VDD at the first current terminal of the first transistor T1 and the control voltage VC at the control terminal of the first transistor T1 decreases. Thus, the rate of change of the property associated with the first transistor T1 (e.g., the rate of the on-resistance of the first transistor T1) changes.

[0102] At time I2, the enable voltage EV exceeds the first threshold voltage. In other words, the first supply voltage VDD may exceed the trip value at time I2. Additionally, the second transistor T2, the third transistor T3, and the sixth transistor T6 may be turned on, such that the control voltage VC is pulled down to the second supply voltage VSS and the trigger voltage TV drops to the second supply voltage VSS (e.g., the trigger voltage TV drops to ground voltage). When the voltage at the control terminal of the first feedback transistor 210 equals the second supply voltage VSS (e.g., ground voltage), the first feedback transistor 210 may be turned on. The first feedback transistor 210 may drive the voltage at the first current terminal of the fifth transistor T5 to the second supply voltage VSS.

[0103] The first logic gate 214 may generate a first output voltage F1 based on the trigger voltage TV dropping to the second supply voltage VSS, such that the first output voltage F1 equals the first supply voltage VDD. Additionally, the second logic gate 216 may receive the first output voltage F1 from the first logic gate 214, and receive the enable voltage EV from the first transistor T1. When the first output voltage F1 equals the first supply voltage VDD and the enable voltage EV is higher than the second supply voltage VSS, the second logic gate 216 may assert the reset signal RST.

[0104] Between times I2 - I3, the first capacitor 208 may not be fully charged. Accordingly, the enable voltage EV is a reduced form of the first supply voltage VDD. Additionally, the control voltage VC and the trigger voltage TV are at the second supply voltage VSS. Additionally, the first output voltage F1 equals the first supply voltage VDD.

[0105] Beyond time I3, the first capacitor 208 may be fully charged, and the control voltage VC is at the second supply voltage VSS, such that the enable voltage EV equals the first supply voltage VDD. The reset signal RST remains in the logic high state. Additionally, the control voltage VC remains at the second supply voltage VSS.

[0106] Figure 5 Depicts a timing diagram 500 that shows the rate of change of the varying attributes of the first transistor T1 and the voltage difference between the first supply voltage VDD at the first current terminal and the control voltage CV at the control terminal, in accordance with an embodiment of the present disclosure.

[0107] At time I0, the IC 100 is powered on. The first transistor T1 is turned off, and the enable voltage EV and the control voltage VC are at 0V. Additionally, the fourth transistor T4 and the fifth transistor T5 may be turned off.

[0108] At times I0 - I1, the rate of increase of the voltage difference between the first supply voltage VDD at the first current terminal of the first transistor T1 and the control voltage VC at the control terminal of the first transistor T1 is at a first rate. Additionally, the rate of change of the property associated with the first transistor T1 is at a fifth rate.

[0109] At times I1 - I2, the rate of increase of the voltage difference between the first supply voltage VDD at the first current terminal of the first transistor T1 and the control voltage VC at the control terminal of the first transistor T1 decreases from the first rate to a second rate. Consequently, the rate of change of the property associated with the first transistor T1 (e.g., the rate of the on - resistance of the first transistor T1) changes to a sixth rate.

[0110] Beyond time I2, the control voltage CV is pulled to the second supply voltage VSS. Thus, the voltage difference between the first supply voltage VDD at the first current terminal of the first transistor T1 and the control voltage VC at the control terminal of the first transistor T1 is equal to the first supply voltage VDD. Additionally, as the voltage difference between the first supply voltage VDD at the first current terminal of the first transistor T1 and the control voltage VC at the control terminal of the first transistor T1 rises, the property of the first transistor T1 gradually decreases.

[0111] The scope of the present disclosure is not limited to the delay circuit 202, hysteresis circuit 204, and logic circuit 206 implemented in the manner described above. In various other embodiments, the delay circuit 202, hysteresis circuit 204, and logic circuit 206 can be implemented using different or additional components without departing from the scope of the present disclosure.

[0112] Compared with a conventional POR circuit, the POR circuit 104 occupies less area on the IC 100. The conventional POR circuit provides the same trip level accuracy as the POR circuit 104, a time delay over a wide range of the first supply voltage VDD (e.g., 2.4V - 5.5V), and a ramp rate of the first supply voltage VDD (e.g., 100 μs - 100 ms). Additionally, the POR circuit 104 maintains the trip level accuracy and the time delay within a wide temperature range (e.g., -40°C to 125°C). During the steady state of the first supply voltage VDD, the signal level generated by the POR circuit 104 matches one of the first supply voltage VDD and the second supply voltage VSS (e.g., ground voltage). In other words, in the POR circuit 104 of the present disclosure, a low impedance path between the first supply voltage terminal and the second supply voltage terminal is prevented during the steady state. Therefore, the consumption of non-zero steady state current by the POR circuit 104 is prevented. As a result, the power consumed by the IC 100 of the present disclosure is significantly lower than the power consumed by an IC including a conventional POR circuit. Thus, the POR circuit 104 of the present disclosure is significantly more efficient and compact than a conventional POR circuit. Since the reset signal RST is asserted based on the enable voltage EV and the first output voltage F1, the influence of the leakage current on the assertion of the reset signal RST is minimized. Therefore, the POR circuit 104 of the present disclosure is significantly robust across process, voltage, and temperature (PVT) and different supply ramp rates.

[0113] In the present disclosure, the term "assert" is used to mean placing a signal in an active state. For example, for a low-active signal, the signal is in a logic low state when asserted, and for a high-active signal, the signal is in a logic high state when asserted.

[0114] Although various embodiments of the present disclosure have been illustrated and described, it should be clear that the present disclosure is not limited to these embodiments. Many modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure as described in the claims. Additionally, unless otherwise specified, terms such as "first" and "second" are used arbitrarily to distinguish the elements described by these terms. Therefore, these terms do not necessarily intend to indicate a temporal precedence or other precedence ordering of these elements.

Claims

1. A circuit, characterized in that: include: A power-on reset (POR) circuit comprising: A first transistor comprising: a first current terminal configured to receive a first supply voltage from a first supply voltage terminal; a control terminal configured to receive a control voltage; and a second current terminal configured to generate an enable voltage; a first capacitor coupled between the second current terminal and a second supply voltage terminal of the first transistor; A transistor stack comprising: A first power supply terminal, configured to receive the first power supply voltage; A second power supply terminal configured to receive a second power supply voltage; an input terminal coupled to the second current terminal of the first transistor and configured to receive the enable voltage; a first output terminal coupled to the control terminal of the first transistor and configured to generate the control voltage; and a second output terminal configured to generate a trigger voltage based on the first supply voltage and the enable voltage; and a logic circuit coupled to the second current terminal of the first transistor and to the second output terminal of the transistor stack and configured to: receiving the enable voltage and the trigger voltage; and A reset signal is generated based on the enable voltage and the trigger voltage.

2. The circuit according to claim 1, characterized in that The transistor stack further comprises a stack of transistors of a first conductivity type and a stack of transistors of a second conductivity type, The stack of the first conductivity type transistors and the stack of the second conductivity type transistors are connected together at a first output node, and The first output node corresponds to the second output terminal of the transistor stack, so that the trigger voltage is generated at the first output node.

3. The circuit according to claim 1, characterized in that The transistor stack further comprises: A second transistor comprising: a control terminal configured to receive the enabling voltage; a first current terminal coupled to the control terminal of the first transistor, wherein the first current terminal of the second transistor corresponds to the first output terminal of the transistor stack; and a second current terminal; and A third transistor comprising: a control terminal configured to receive the enabling voltage; a first current terminal; and A second current terminal is coupled to the first current terminal of the second transistor.

4. The circuit according to claim 1, characterized in that The logic circuit comprises: a first logic gate coupled to the second output terminal of the transistor stack and configured to: receiving the trigger voltage; and generating a first output voltage based on the trigger voltage, wherein the first output voltage is an inverted version of the trigger voltage; and a second logic gate coupled to the first logic gate and the second current terminal of the first transistor and configured to: receiving the first output voltage and the enable voltage; and The reset signal is generated based on the first output voltage and the enable voltage, wherein the reset signal is asserted when the first output voltage is equal to the first supply voltage and the enable voltage is higher than the second supply voltage.

5. A circuit, characterized in that: include: A power-on reset (POR) circuit comprising: A first transistor comprising: a first current terminal configured to receive a first supply voltage from a first supply voltage terminal; a control terminal configured to receive a control voltage; and a second current terminal configured to generate an enable voltage; and a transistor stack coupled to the second current terminal and the control terminal of the first transistor, wherein the transistor stack is configured to: receiving the enabling voltage; and generating the control voltage and the trigger voltage, (i) wherein the control voltage increases based on an increase in the enable voltage when the enable voltage is less than a first threshold voltage associated with the transistor stack, and the trigger voltage remains higher than the second supply voltage, (ii) wherein the enable voltage ramps up to the first threshold voltage within a first time period as the control voltage increases, and (iii) wherein when the enable voltage is equal to the first threshold voltage at the end of the first time period, the trigger voltage drops to the second supply voltage, to assert the reset signal of the POR circuit.

6. The circuit according to claim 5, characterized in that When the control voltage increases, the rate of increase of the voltage difference between (i) the first supply voltage at the first current terminal of the first transistor and (ii) the control voltage at the control terminal of the first transistor decreases from a first rate to a second rate, and when the first supply voltage is less than a second threshold voltage of the first transistor, the rate of increase of the voltage difference between the first supply voltage at the first current terminal and the control voltage at the control terminal is at the first rate.

7. The circuit according to claim 5, characterized in that The transistor stack comprises a stack of first conductivity type transistors coupled to the first transistor, and wherein the stack of first conductivity type transistors is configured to: receiving the enabling voltage; and The control voltage is pulled down to the second supply voltage when the enable voltage is equal to the first threshold voltage, wherein the enable voltage is ramped up to the first supply voltage within a second time period when the control voltage is pulled down to the second supply voltage.

8. The circuit according to claim 7, characterized in that The stack of transistors of the first conductivity type comprises: A second transistor comprising: a control terminal configured to receive the enabling voltage; a first current terminal coupled to the control terminal of the first transistor and configured to generate the control voltage; and a second current terminal; and A third transistor comprising: a control terminal configured to receive the enabling voltage; a first current terminal; and A second current terminal is coupled to the first current terminal of the second transistor.

9. The circuit according to claim 8, characterized in that The transistor stack further comprises a stack of second conductivity type transistors coupled to the first transistor, and wherein the stack of second conductivity type transistors is configured to: receiving the first supply voltage and the enable voltage; as well as The trigger voltage is generated based on the first supply voltage and the enable voltage, wherein When the enable voltage is less than the first threshold voltage, the trigger voltage is equal to the first supply voltage, and when the trigger voltage drops to the second supply voltage, the enable voltage is higher than the first threshold voltage.

10. The circuit according to claim 9, characterized in that The stack of the second conductivity type transistors comprises: a fourth transistor comprising: a control terminal configured to receive the enabling voltage; a first current terminal configured to receive the first supply voltage; and a second current terminal; and a fifth transistor comprising: a control terminal configured to receive the enabling voltage; a first current terminal coupled to the second current terminal of the fourth transistor; and The second current terminal is coupled to the second current terminal of the second transistor and is configured to generate the trigger voltage.

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