Communication method and related device

Abstract

The invention provides a communication method and a related device. The decoding performance can be improved. The method comprises the steps that a check matrix of a target SC-LDPC code is acquired, the number of rows of the check matrix is M, the number of columns of the check matrix is N, the value of an element is 0 or 1, and the check matrix of the target SC-LDPC code comprises a second matrix composed of the ith row to the (i + (Z + 1) * m-1) th in the M rows and the 0th column to the (n-1) th column in the N columns, the second matrix is obtained by sequentially arranging (Z + 1) third matrixes with the row number of m and the column number of n according to rows, Z third matrixes exist in the (Z + 1) third matrixes, and the number K of the elements 1 included in the Z third matrixes and the number L of the elements 1 included in the second matrix meet the following relation: K / L = Z * z%; and on the basis of the check matrix coding information bit of the target SC-LDPC code, obtaining a first SC-LDPC code word.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a communication method and related devices. Background Art

[0002] Low density parity check (LDPC) codes are linear block codes with sparse parity check matrices. LDPC codes not only have good performance approaching the Shannon limit, but also have low decoding complexity and flexible structures, and thus have been a research hotspot in the field of channel coding in recent years. As a type of structured LDPC codes, quasi-cyclic LDPC (QC-LDPC) codes have been well applied in some communication systems, for example, in the new radio access technology (NR) of the 5th generation (5G) communication system, due to advantages such as simple description, easy construction, and saving storage space.

[0003] However, currently, the QC-LDPC codes in the 5G-NR standard have error floors, and there are also limitations on the decoding parallelism, resulting in low decoding performance of the QC-LDPC codes in the actual application process and making it difficult to meet the encoding and decoding requirements of high-reliability and high-throughput services in future communication systems. Summary of the Invention

[0004] This application provides a communication method and related devices to improve the decoding performance.

[0005] In a first aspect, this application provides a communication method, which can be applied to a first communication device. For example, the first communication device can be a terminal device or a network device, or can also be a component (such as a chip, a chip system, etc.) configured in the terminal device or the network device, or can also be a logic module or software capable of implementing all or part of the functions of the terminal device or the network device. This application makes no limitation thereto.

[0006] Exemplarily, the method includes: obtaining a parity check matrix of a target spatially coupled low density parity check (SC-LDPC) code, where the parity check matrix of the target SC-LDPC code is obtained from a preset parity check matrix of the SC-LDPC code based on a target code rate and the length of information bits; encoding the information bits based on the parity check matrix of the target SC-LDPC code to obtain a first SC-LDPC codeword.

[0007] Example 1: The parity check matrix of the target SC-LDPC code is a part intercepted from the preset parity check matrix of the SC-LDPC code based on the target code rate and the length of information bits.

[0008] Among them, the number of rows of the check matrix of the preset SC-LDPC code is M, and the number of columns is N. The values of the elements in the check matrix of the preset SC-LDPC code are 0 or 1. Alternatively, the number of rows of the check matrix of the target SC-LDPC code is M, and the number of columns is N. The values of the elements in the check matrix of the target SC-LDPC code are 0 or 1.

[0009] Example 2: The check matrix of the preset SC-LDPC code is included in the first mapping relationship. This mapping relationship indicates the correspondence between at least one code rate, the length of at least one information bit, and the check matrix of at least one preset SC-LDPC code. That is, the check matrix of the target SC-LDPC code is determined based on the target code rate, the length of the information bit, and the first mapping relationship.

[0010] Among them, the number of rows of the check matrix of the target SC-LDPC code is M, and the number of columns is N. The values of the elements in the check matrix of the target SC-LDPC code are 0 or 1.

[0011] Combining Example 1 and Example 2, the first matrix composed of the 0th row to the (M - 1)th row among the M rows and the 0th column to the (n - 1)th column among the N columns includes a second matrix with ((Z + 1)*m) rows and n columns. The elements of the jth column to the (j + n - 1)th column among the N columns are obtained by cyclically shifting the first matrix downward by ((j / n)*m) rows; the second matrix is the matrix composed of the ith row to the (i + (Z + 1)*m - 1)th row in the first matrix. All other elements in the first matrix except the second matrix are 0. The second matrix is obtained by arranging (Z + 1) third matrices with m rows and n columns in sequence by rows. Among the (Z + 1) third matrices, there are Z third matrices. The relationship between the number K of elements 1 included in the Z third matrices and the number L of elements 1 included in the second matrix satisfies the following relationship: K / L = Z*z%, K / L ≤ 50%, (L - K) ≥ (K / Z), or the number of remaining elements 1 in the second matrix except the K elements 1 included in the Z third matrices is greater than or equal to the number of elements 1 included in at least one of the Z third matrices.

[0012] The above Z is an integer greater than 0, z is an integer less than or equal to 100*R, or z is an integer less than or equal to 100*(1 - R), where R is the target code rate or the maximum code rate or the minimum code rate supported by the check matrix of the preset SC-LDPC code. i is an integer greater than or equal to 0 and less than or equal to (M - (Z + 1)*m), j = n, 2*n,..., y*n; (y + 1) = N / n, M is divisible by m, and n, m, and y are all integers greater than 1.

[0013] Based on this method, the first communication device (the device for encoding) encodes information bits by using the parity-check matrix of the obtained target SC-LDPC code to obtain a first SC-LDPC codeword. The second communication device (the device for decoding) also decodes the first SC-LDPC codeword by using the parity-check matrix of the target SC-LDPC code. Since there is a coupling characteristic among multiple second matrices included in the parity-check matrix of the target SC-LDPC code, better error performance can be obtained. In addition, the parity-check matrix of the target SC-LDPC code increases the decoding parallelism, enabling fast decoding and obtaining better decoding performance.

[0014] Combined with the first aspect, in some implementation manners of the first aspect, the first SC-LDPC codeword includes Q groups of encoded bits. Each group of encoded bits in the Q groups of encoded bits includes a group of information bits and a group of parity bits. Each group of information bits in the Q groups of information bits includes A information bits, and each group of parity bits in the Q groups of parity bits includes B parity bits. A and B are integers greater than 0, and Q = N / n.

[0015] Combined with the first aspect, in some possible implementation manners of the first aspect, the method further includes: reordering the Q groups of encoded bits included in the first SC-LDPC codeword to obtain a second SC-LDPC codeword; interleaving and modulating the second SC-LDPC codeword to obtain a plurality of modulation symbols; and transmitting the plurality of modulation symbols.

[0016] Among them, the Q groups of information bits and the Q groups of parity bits included in the second SC-LDPC codeword satisfy any of the following characteristics:

[0017] The Q groups of information bits are located before the Q groups of parity bits;

[0018] The q groups of encoded bits that are used as the decoding starting point in the Q groups of encoded bits are located before other groups of encoded bits;

[0019] The q groups of encoded bits that are used as the decoding starting point in the Q groups of encoded bits are located before other groups of encoded bits, and the information bits in each group of encoded bits are located before the parity bits; or,

[0020] The q groups of encoded bits that are used as the decoding starting point in the Q groups of encoded bits are located before other groups of encoded bits, and the information bits in the q groups of encoded bits are located before the parity bits in the q groups of encoded bits, where q is an integer greater than 0 and less than or equal to Q.

[0021] Exemplarily, the positions of the other groups of coded bits in the second SC-LDPC codeword are arranged in ascending order of a first distance, where the first distance refers to the number of groups of coded bits between each group of coded bits in the other groups of coded bits and the q groups of coded bits in the first SC-LDPC codeword.

[0022] Exemplarily, the information bits in the other groups of coded bits are located before the parity bits in the other groups of coded bits.

[0023] Optionally, reordering the Q groups of coded bits to obtain a second SC-LDPC codeword includes: using a first row-column interleaver to perform interleaving processing on the first SC-LDPC codeword to obtain the second SC-LDPC codeword, where the number of rows of the first row-column interleaver is Q and the number of columns is (A + B).

[0024] Among them, interleaving refers to the process of inputting the first SC-LDPC codeword row by row into the first row-column interleaver and then reading out the first SC-LDPC codeword column by column.

[0025] Optionally, reordering the Q groups of coded bits to obtain a second SC-LDPC codeword includes: reordering the Q groups of coded bits based on the decoding method of the first SC-LDPC codeword to obtain the second SC-LDPC codeword.

[0026] In Example 1, the decoding method is two-way sliding window decoding, and the q groups of coded bits are the first group of coded bits and the Qth group of coded bits in the first SC-LDPC codeword.

[0027] In Example 2, the decoding method is parallel sliding window decoding, q is an integer greater than 2 and less than or equal to Q, and the q groups of bits are the groups of coded bits that serve as the decoding starting point among the Q groups of bits.

[0028] It can be understood that the above decoding method can be indicated by a second communication device (for example, a decoding device) to the first communication device.

[0029] Optionally, interleaving and modulating the second SC-LDPC codeword to obtain a plurality of modulation symbols includes: using a second row-column interleaver to perform interleaving processing on the second SC-LDPC codeword to obtain a third SC-LDPC codeword, where the number of rows of the second row-column interleaver is P and the number of columns is D, D = ceil((A + B) * Q / P), P is the modulation order; mapping P consecutive bits in the third SC-LDPC codeword to one modulation symbol in sequence to obtain a plurality of modulation symbols, where ceil() represents rounding up.

[0030] Second aspect, the present application provides a communication method, which can be applied to a second communication device. For example, the second communication device can be a terminal device or a network device, or can also be a component (such as a chip, a chip system, etc.) configured in the terminal device or the network device, or can also be a logic module or software capable of implementing all or part of the functions of the terminal device or the network device. The present application does not make any limitation in this regard.

[0031] Exemplarily, the method includes: receiving a plurality of modulation symbols; demodulating and processing the plurality of modulation symbols to obtain a first SC-LDPC codeword; obtaining a parity-check matrix of a target SC-LDPC code, where the parity-check matrix of the target SC-LDPC code is obtained from a preset parity-check matrix of the SC-LDPC code based on a target code rate and a length of information bits; and decoding the first SC-LDPC codeword based on the parity-check matrix of the target SC-LDPC code to obtain the information bits.

[0032] For the description of the parity-check matrix of the target SC-LDPC code and the preset parity-check matrix of the SC-LDPC code, reference can be made to the description in the first aspect above, and details are not repeated here.

[0033] Based on this method, a first communication device (for example, a decoding device) demodulates and processes the received modulation symbols to obtain a first SC-LDPC codeword, and uses the parity-check matrix of the target SC-LDPC code for encoding information bits on the first communication device side to decode the first SC-LDPC codeword. Since there is a coupling feature among multiple second matrices of the parity-check matrices of the target SC-LDPC codes obtained by the first communication device and the second communication device, better error performance can be obtained. At the same time, the parity-check matrix of the target SC-LDPC code increases the decoding parallelism and can achieve fast decoding, resulting in better decoding performance.

[0034] In combination with the second aspect, in some possible implementation manners of the second aspect, the demodulating and processing the plurality of modulation symbols to obtain a first SC-LDPC codeword includes: demodulating the plurality of modulation symbols to obtain a third SC-LDPC codeword, where the third SC-LDPC codeword includes (Q*A) information bits and (Q*B) parity bits; performing deinterleaving processing on the third SC-LDPC codeword to obtain a second SC-LDPC codeword, where the second SC-LDPC codeword includes Q groups of information bits and Q groups of parity bits, each group of information bits in the Q groups of information bits includes A information bits, each group of parity bits in the Q groups of parity bits includes B parity bits, A and B are integers greater than 0, and Q = N / n; reordering the Q groups of information bits and Q groups of parity bits in the second SC-LDPC codeword to obtain the first SC-LDPC codeword, where the first SC-LDPC codeword includes Q groups of encoded bits, and each group of encoded bits in the Q groups of encoded bits includes a group of information bits and a group of parity bits.

[0035] Wherein, deinterleaving is the inverse process of interleaving. For example, using a second row-column interleaver to perform deinterleaving processing on the third SC-LDPC codeword to obtain a second SC-LDPC codeword, where the number of rows of the second row-column interleaver is P, the number of columns is D, D = ceil((A + B)*Q / P), and P is the modulation order. Performing deinterleaving processing on the third SC-LDPC codeword means inputting the third SC-LDPC codeword column by column into the second row-column interleaver and reading out the second SC-LDPC codeword row by row.

[0036] In combination with the second aspect, in some possible implementation manners of the second aspect, the reordering the Q groups of information bits and Q groups of parity bits in the second SC-LDPC codeword to obtain the first SC-LDPC codeword includes: using a first row-column interleaver to perform deinterleaving processing on the second SC-LDPC codeword to obtain the first SC-LDPC codeword, where the number of rows of the first row-column interleaver is Q and the number of columns is (A + B).

[0037] It can be understood that the above sorting manner can be indicated by a first communication device (for example, an encoding device) to a second communication device.

[0038] In combination with the first and second aspects, in some implementation manners, the K elements 1 included in the fourth matrix are evenly distributed among the L elements 1 included in the fifth matrix, the fourth matrix is the sum of the Z third matrices, and the fifth matrix is the sum of the (Z + 1) third matrices.

[0039] In other words, the K elements 1 included in the fourth matrix are evenly selected (or equally spaced selected) from the L elements 1 included in the fifth matrix.

[0040] Optionally, the K elements 1 may be randomly selected from the L elements 1.

[0041] Exemplarily, the fifth matrix includes at least K elements 1 with different numbers of rows and columns, and the elements 1 included in the fourth matrix belong to the at least K elements 1 with different numbers of rows and columns.

[0042] Exemplarily, the fifth matrix includes at least K' elements 1 with different numbers of rows and columns, and the fourth matrix includes the at least K' elements 1 with different numbers of rows and columns, where K' is an integer greater than 0 and less than K.

[0043] Combining the first and second aspects, in some implementations, the elements 1 included in each of the Z third matrices are evenly distributed among the K elements 1 included in the fourth matrix.

[0044] In other words, the elements 1 included in each of the Z third matrices are evenly selected (or equally spaced) from the L elements 1 included in the fourth matrix.

[0045] Optionally, the elements 1 included in each of the Z third matrices are randomly selected from the L elements 1 included in the fourth matrix, and the positions of the elements 1 included in any two third matrices in the fourth matrix are different.

[0046] In a third aspect, the present application provides a communication device, including modules or units for implementing the methods in any of the above aspects and any possible implementation manners of any aspect. It should be understood that each module or unit can implement the corresponding functions by executing a computer program.

[0047] In a fourth aspect, the present application provides a communication device, including a processor for executing the methods described in any of the above aspects and any possible implementation manners of any aspect.

[0048] The device may further include a memory for storing instructions and data. The memory is coupled to the processor, and when the processor executes the instructions stored in the memory, the methods described in the above aspects can be implemented.

[0049] The device may further include a communication interface for communicating the device with other devices. Exemplarily, the communication interface may be a transceiver, a circuit, a bus, a module, or other types of communication interfaces.

[0050] In a fifth aspect, the present application provides a chip system, which includes at least one processor for supporting the implementation of the functions involved in any of the above aspects and any possible implementation manner of any aspect. For example, receiving or processing the data and / or information involved in the above method.

[0051] In a possible design, the chip system further includes a memory for storing program instructions and data, and the memory is located inside or outside the processor.

[0052] The chip system may be composed of chips or may include chips and other discrete devices.

[0053] In a sixth aspect, the present application provides a computer-readable storage medium including a computer program, which, when running on a computer, enables the computer to implement the methods in any of the above aspects and any possible implementation manner of any aspect.

[0054] In a seventh aspect, the present application provides a computer program product, which includes a computer program (which may also be referred to as code or instruction), and when the computer program is run, enables the computer to execute the methods in any of the above aspects and any possible implementation manner of any aspect.

[0055] In an eighth aspect, the present application provides a communication system, which includes the aforementioned first communication device and second communication device. Among them, the first communication device is used to execute the methods in the first aspect and any possible implementation manner in the first aspect, and the second communication device is used to execute the methods in the second aspect and any possible implementation manner in the second aspect.

[0056] It should be understood that the third to eighth aspects of the present application correspond to the technical solutions of the first or second aspect of the present application, and the beneficial effects obtained by each aspect and the corresponding feasible implementation manners are similar and will not be elaborated here. Description of the Drawings

[0057] Figure 1 is a schematic diagram of the architecture of a communication system applicable to the method provided in the embodiments of the present application;

[0058] Figure 2 is a schematic diagram of signal processing provided in the embodiments of the present application;

[0059] Figure 3 is a schematic flowchart of the communication method provided in the embodiments of the present application;

[0060] Figures 4 to 6 is a schematic diagram of the manner of selecting K elements 1 provided in the embodiments of the present application;

[0061] Figures 7 to 9It is a schematic diagram of the connection relationship between multiple variable nodes and multiple check nodes provided by an embodiment of the present application;

[0062] Figure 10 It is a schematic diagram of the first SC-LDPC codeword provided by an embodiment of the present application;

[0063] Figure 11 It is a schematic diagram of the interleaving process provided by an embodiment of the present application;

[0064] Figure 12 It is a schematic diagram of a method for determining the third SC-LDPC codeword provided by an embodiment of the present application;

[0065] Figure 13 and Figure 14 It is a schematic block diagram of the device provided by an embodiment of the present application. Detailed implementation manners

[0066] Next, the technical solutions in the present application will be described with reference to the accompanying drawings.

[0067] For the convenience of understanding the embodiments of the present application, the following points are first explained:

[0068] First, in the embodiments of the present application, the use of prefix words such as "first" and "second" is only for facilitating the differential description of different things belonging to the same name category, and does not restrict the order, size, or quantity of things. For example, "the first communication device" and "the second communication device" are only different devices, and do not limit the quantity or priority relationship of the devices; for another example, "the first SC-LDPC codeword" and "the second SC-LDPC codeword" are only different codewords, and there is no size relationship or priority relationship between the two.

[0069] Second, in the embodiments of the present application, "send" and "receive" represent the direction of signal transmission. For example, "sending multiple modulation symbols to the second communication device" can be understood as the destination of the multiple modulation symbols is the second communication device, which may include directly sending through the air interface, or indirectly sending through the air interface by other units or modules. "Receiving multiple modulation symbols from the first communication device" can be understood as the source of the multiple modulation symbols is the first communication device, which may include directly receiving from the first communication device through the air interface, or indirectly receiving from the first communication device through the air interface by other units or modules. "Send" can also be understood as the "output" of the chip interface, and "receive" can also be understood as the "input" of the chip interface.

[0070] In other words, the sending and receiving can be carried out between devices, for example, between a second communication device and a first communication device; or can be carried out within a device, for example, through a bus, a trace or an interface between components, modules, chips, software modules or hardware modules within the device.

[0071] It can be understood that before the information is sent from the source end to the destination end, necessary processing may be performed, such as encoding, modulation, etc. After the destination end receives the information from the source end, corresponding processing can also be performed, such as decoding, demodulation, etc., so as to interpret the valid information from the source end. Similar expressions in this application can be understood similarly and will not be elaborated here.

[0072] Third, in the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects, but does not exclude the case where it represents a "and" relationship between the front and rear associated objects. The specific meaning represented can be understood in combination with the context. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b, or c can represent: a, b, c; a and b; a and c; b and c; or a, b, and c. Where a, b, and c can be single or multiple.

[0073] Fourth, the tables in the embodiments of the present application are only examples. The values of the information in each table are only for illustration and can be configured as other values, which are not limited in this application. Each table does not limit the protection scope of the present application. For example, appropriate deformation adjustments can be made based on the above-mentioned tables, such as splitting, merging, etc. Also, for example, the parameter names shown in the titles of each table can also use other names understandable by the communication device, and the value or representation method of its parameters can also be other values or representation methods understandable by the communication device. Again, for example, when implementing the above-mentioned tables, other data structures can also be used, such as arrays, queues, containers, stacks, linear lists, pointers, linked lists, trees, graphs, structures, classes, heaps, hash tables or hash maps, etc.

[0074] Fifth, in the embodiments of the present application, descriptions such as "when...", "in the case of...", "if", and "when" all refer to the situation where the device (e.g., the first device or the second device) will perform corresponding processing under certain objective circumstances, rather than limiting time, and it is not required that the device (e.g., the network device or the terminal device) must have a judgment action when implemented, nor does it mean that there are other limitations.

[0075] Sixth, the predefined in the present application can be understood as: define, pre-define, store, pre-store, pre-negotiate, pre-configure, solidify, or pre-burn.

[0076] The technical solutions provided by the present application can be applied to various communication systems, such as: Long Term Evolution (LTE) system, LTE Frequency Division Duplex (FDD) system, LTE Time Division Duplex (TDD), Sidelink (SL) communication system, Worldwide Interoperability for Microwave Access (WiMAX) communication system, 5th Generation (5G) mobile communication system or New Radio Access Technology (NR), satellite communication system, etc. Among them, the 5G mobile communication system can include Non-Standalone (NSA) and / or Standalone (SA).

[0077] The technical solutions provided by the present application can also be applied to future communication systems, such as the 6th Generation (6G) mobile communication system, etc. The present application does not limit this.

[0078] The Radio Access Network (RAN) device in the present application is a device with wireless transceiver functions. The RAN device can provide wireless communication function services and can connect the terminal to the wireless network. The RAN device can be a node in the radio access network, simply referred to as a RAN node.

[0079] In a possible scenario, the RAN node can be a base station (BS), an evolved NodeB (eNodeB), a transmission reception point (TRP), a home evolved NodeB (or home Node B, HNB), an access point (AP) of wireless fidelity (Wi-Fi), a mobile switching center, a next-generation NodeB (gNB) in a 5G mobile communication system, a next-generation NodeB in a 6G mobile communication system, or a base station in a future mobile communication system, etc. The RAN node can also be a device that undertakes the base station function in a device-to-device (D2D) communication system, a vehicle-to-everything (V2X) communication system, a machine-to-machine (M2M) communication system, and an Internet of Things (IoT) communication system, etc. The RAN node can also be an RAN node in a non-terrestrial network (NTN), that is, the RAN node can be deployed on a high-altitude platform or a satellite. The RAN node can be a macro base station, a micro base station or an indoor station, or a relay node or a donor node, etc., or a radio controller in a cloud radio access network (CRAN) scenario, a node in an open radio access network (O-RAN or ORAN) scenario, etc. Optionally, the RAN node can also be a server, a wearable device, a vehicle or an in-vehicle device, etc. For example, the RAN node in V2X technology can be a road side unit (RSU). Of course, the RAN node can also be a node in the core network.

[0080] In another possible scenario, multiple RAN nodes cooperate to assist a terminal in achieving wireless access, and different RAN nodes respectively implement some functions of a base station. For example, the RAN node can be a central unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU), etc. The CU and the DU can be set separately, or can also be included in the same network element, such as a baseband unit (BBU). The RU can be included in a radio frequency device or a radio frequency unit, such as included in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH).

[0081] In different systems, the CU (or CU-CP and CU-UP), DU, or RU may also have different names, but those skilled in the art can understand their meanings. For example, in the ORAN system, the CU can also be called an open CU (O-CU), the DU can also be called an open DU (O-DU), the CU-CP can also be called an open CU-CP (O-CU-CP), the CU-UP can also be called an open CU-UP (O-CU-UP), and the RU can also be called an open RU (O-RU).

[0082] Among them, any one of the CU (or CU-CP, CU-UP), DU, and RU can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module. That is to say, the radio access network device in this application can be a virtualized device. For example, it can be implemented by general hardware and instantiated virtualization functions, or by dedicated hardware and instantiated virtualization functions. Among them, the general hardware can be a server, such as a cloud server.

[0083] The terminal device in this application can also be called a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile platform, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, or a user device.

[0084] A terminal device can be a device that provides voice / data connectivity to users. For example, it can be a handheld device, a vehicle-mounted device, etc. with wireless connection capabilities. Currently, some examples of terminal devices can be: mobile phones, tablets, computers with wireless transceiver functions (such as laptops, handheld computers, etc.), mobile internet devices (MIDs), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, drones, wireless terminals in remote medical, wireless terminals in smart grid, wireless terminals in transportation safety, wireless terminals in smart city, wireless terminals in smart home, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication functions, computing devices or other processing devices connected to a wireless modem, vehicle-mounted devices, wearable devices, terminal devices in a 5G network, or terminal devices in a future evolved public land mobile network (PLMN), etc.

[0085] Among them, wearable devices can also be called wearable intelligent devices, which is the general term for devices developed by applying wearable technology to the intelligent design of daily wear, such as glasses, gloves, watches, clothing, shoes, etc. Wearable devices are portable devices that are directly worn on the body or integrated into the user's clothes or accessories. Wearable devices are not only a kind of hardware device, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable intelligent devices include those with complete functions and large sizes that can achieve complete or partial functions without relying on a smartphone, such as smart watches or smart glasses, etc., and those that only focus on a certain type of application function and need to cooperate with other devices such as smartphones, such as various smart bracelets and smart jewelry for physical sign monitoring.

[0086] In addition, the terminal device can also be a terminal device in an IoT system. IoT is an important part of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, so as to realize an intelligent network of human-machine interconnection and object-object interconnection. IoT technology can achieve massive connections, deep coverage, and power saving for terminals through, for example, narrow band (NB) technology.

[0087] In addition, the terminal device can also include sensors such as intelligent printers, train detectors, and gas stations. Its main functions include collecting data (for some terminal devices), receiving control information and downlink data from network devices, and transmitting electromagnetic waves to transmit uplink data to network devices.

[0088] The terminal device in this application can be a virtualized device. For example, it can be implemented through general hardware and instantiated virtualization functions, or through dedicated hardware and instantiated virtualization functions. Among them, the general hardware can be a server, such as a cloud server.

[0089] It should be understood that this application does not limit the specific forms of the radio access network device and the terminal device.

[0090] Figure 1 It is a schematic diagram of the architecture of the communication system 100 applicable to the method provided in the embodiments of this application. As Figure 1 shown, the communication system 100 includes a radio access network 10 and a core network 20. Optionally, the communication system 100 can also include the Internet 30. Among them, the radio access network 10 can include at least one radio access network device (such as Figure 1 110a and 110b in Figure 1 ), and can also include at least one terminal (such as

[0091] 120a - 120j in

[0092] Communication can be carried out between a radio access network device and a terminal, between radio access network devices, and between terminals through licensed spectrum, through unlicensed spectrum, or through both licensed and unlicensed spectrum simultaneously; communication can be carried out through spectrum below 6 gigahertz (GHz), through spectrum above 6 GHz, or through both spectrum below 6 GHz and spectrum above 6 GHz simultaneously. Embodiments of the present application do not limit the spectrum resources used for wireless communication.

[0093] Among them, the radio access network device can be a base station deployed in the air, such as a satellite base station 110a; or it can be a base station deployed indoors, such as a micro base station or an indoor station 110b.

[0094] The terminal can be a terminal deployed in the air, such as Figure 1 the helicopter or drone 120i in; or it can be a terminal deployed on the ground, such as Figure 1 the mobile phones 120a, 120e, 120f, and 120j, the vehicle 120b, the computer 120g, the printer 120h, etc. in.

[0095] The radio access network device and the terminal can be in a fixed position or movable. For example, the radio access network device and the terminal can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on the water; or they can be deployed on airplanes, balloons, and artificial satellites in the air.

[0096] The roles of the radio access network device and the terminal can be relative. For example, Figure 1 the helicopter or drone 120i in can be configured as a mobile base station. For those 120j that access the radio access network 10 through 120i, 120i is a base station; but for 110a, 120i is a terminal, that is, communication between 110a and 120i is carried out through a radio air interface protocol. Of course, communication between 110a and 120i can also be carried out through an interface protocol between radio access network devices. At this time, relative to 110a, 120i is also a base station. Therefore, the radio access network device and the terminal can both be uniformly referred to as communication devices. Figure 1 110a, 110b, and 120a - 120j in can be referred to as communication devices with their respective corresponding functions, such as communication devices with base station functions or communication devices with terminal functions.

[0097] It should be understood that Figure 1 it is only a schematic diagram, and other devices can also be included in this communication system, such as wireless relay devices and wireless backhaul devices, which are not drawn in Figure 1 the figure.

[0098] To facilitate the understanding of the embodiments of the present application, the following briefly describes the processing procedure at the physical layer in conjunction with Figure 2 a simple illustration of the processing procedure at the physical layer.

[0099] It should be understood that Figure 2 the processing procedure of the signal shown in

[0100] can be executed by a network device or a terminal device, and the present application does not make any limitation thereto. Figure 2 As shown in Figure 1 when the communication device #1 (which can be, for example, the access network device or the terminal device shown in A-1 sends information data, it can divide the information data from the upper layer (for example, the media access control (MAC) layer) into multiple transport blocks (TBs) according to the size of the transport block supported by the system, and add CRC checksums p0, p1, p2, p3, …, p L-1 to each transport block a0, a1, a2, a3, …, a B-1 to obtain a sequence b0, b1, b2, b3, …, b A-1 , where B = A + L, and a0, a1, a2, a3, …, a B-1 is also referred to as the payload of the transport block. If the size of the transport block b0, b1, b2, b3, …, b after adding the checksum exceeds the maximum code block length, the transport block needs to be divided into several code blocks (CBs). Each code block may include several bits in the transport block and may also include the CRC check bits of these bits, such as CRC check bits with a length of 24 bits. Padding bits may also be included in the code block to make the code block length meet the block length requirement. For example, taking LPDC coding as an example, the code block length meets an integer multiple of the extension factor.

[0101] The communication device #1 can perform channel coding on each code block. For example, using LDPC coding, the corresponding coded code block can be obtained. The information bits in the present application are the above-mentioned code blocks. Each coded code block may include multiple pre-coded information bits and parity bits generated by coding in the code block, which can be collectively referred to as coded bits in the present application. The sequence composed of multiple coded bits can be referred to as a coded bit sequence.

[0102] The communication device #1 can save the above-mentioned coded bit sequence in the circular buffer of the communication device #1 for rate matching. The communication device #1 can select a segment of coded bits from the circular buffer, perform interleaving processing, and then perform modulation processing to map them to modulation symbols, and send a signal carrying the modulation symbol.

[0103] In an embodiment of the present application, the length of the encoded bit sequence may refer to the length of the bit sequence output after the transport block is segmented into code blocks and LDPC-encoded. More specifically, after the transport block is segmented into code blocks and LDPC-encoded, it is stored in a cyclic buffer, and then from a specified position in the buffer, a specified length of bit data is continuously read out, and the padding bits are automatically skipped.

[0104] Communication device #2 (which may be, for example, Figure 1 the access network device or the terminal device shown in

[0105] After demodulating and deinterleaving the received modulation symbols, communication device #2 may save the soft values of the received encoded bits at corresponding positions in the soft information buffer. If a retransmission occurs, communication device #2 combines and saves the soft values of the encoded bits for each retransmission in the soft information buffer. Here, the combination means that if the positions of the encoded bits received twice are the same, the soft values of the encoded bits received twice are combined.

[0106] It should be understood that the process of communication device #2 processing the received modulation symbols to obtain the information sequence can be regarded as the inverse process of the process of communication device #1 processing the information data to be transmitted to obtain the encoded bit sequence. Among them, communication device #1 and communication device #2 may communicate using wireless technology or wired technology, or optical communication, optical disc reading, or hard disk reading. For example, when communication device #1 sends a signal, communication device #1 is the sending device. In an embodiment of the present application, the sending device may be referred to as an encoding device; when communication device #2 receives a signal, communication device #2 is the receiving device. In an embodiment of the present application, the receiving device may be referred to as a decoding (or, decoding) device. For example, communication device #1 may be the first communication device in the present application, and communication device #2 may be the second communication device in the present application.

[0107] For ease of understanding, first, a brief introduction to the relevant concepts involved in the present application is given.

[0108] 1. Code word: A sequence composed of a series of binary 0 / 1 data input by the information source. This information sequence is divided into message packets of a fixed length. Each message packet is denoted as u and consists of f information bits or f information bits. The encoder converts each message packet u into a binary d-dimensional vector v (d > f) according to a certain established rule. This d-dimensional vector v is called the code word or code vector of the message packet u, and its bit length is d.

[0109] 2. Block code: Each message packet has f information bits, that is, it can carry 2f different messages, each message corresponding to a codeword, so there are 2 f codewords. The 2 f vectors composed of codewords are called block codes.

[0110] 3. Linear block code: In a block code, there is a one-to-one correspondence between all messages h and codewords v, that is, any different messages must correspond to different codewords, which is called a linear block code, denoted as a linear (d, f) code. A (d, f) linear block code can be understood as encoding an information sequence of length f to obtain an encoded bit sequence of length d.

[0111] Mathematically, a (d, f) linear code is an f-dimensional subspace of the vector space composed of all binary n-dimensional vectors, that is, f linearly independent codewords (g1, g2... g f ) can be found such that each codeword in the (d, f) linear code can be represented by a linear combination of these f vectors, that is, v = u1g1 + … + u k g f . Its matrix expression is as follows:

[0112]

[0113] Among them, bold lowercase letters represent vectors, bold uppercase letters represent matrices, u = (u0, u1…, u f-1 ) is the message sequence, v = (v0, v1…, v d-1 ) is the encoded codeword, G is called the generator matrix of the code set, which is composed of k linearly independent d-dimensional vectors, and its elements are 0 or 1.

[0114] The parity-check matrix H is the inverse matrix of the generator matrix in the binary sense, that is, H(uG) T = 0. During decoding, relying on this check relationship, errors can be detected and corrected.

[0115] 4. Interleaving: It is a processing method that changes the order of the bit sequence, and can also be called permutation, aiming to combat burst interference. After interleaving, the original burst interference in a piece becomes random single interference, which is beneficial for decoding.

[0116] 5. LDPC Code: A linear block code with a sparse parity-check matrix, characterized in that the parity-check matrix of the LDPC code has a low density of non-zero elements (i.e., the number of non-zero elements is small compared to the number of rows and columns). Due to the sparsity of the parity-check matrix of the LDPC code, a relatively large minimum distance is generated, and at the same time, the decoding complexity is reduced. The error correction ability of this code is very close to the theoretical maximum value (i.e., the Shannon limit).

[0117] 6. QC-LDPC Code: A subclass of LDPC. The parity check matrix of QC-LDPC is obtained by expanding a base matrix.

[0118] As a type of structured LDPC code, this QC-LDPC code has been well applied in some communication systems, such as 5G NR, due to its advantages of simple description, easy construction, and saving storage space.

[0119] However, due to problems in the short code design and error floor of QC-LDPC in the 5G-NR standard, for example, the decoding performance of short codes with a length less than 128 is poor, and the error floor of codewords of any length appears at a block error rate (BLER) = 10 -6 . In addition, when high throughput is pursued, the decoding parallelism needs to be increased. Since the input scale of LDPC long code decoding is large, the scheduling complexity is extremely high, and the decoder is prone to routing congestion. To avoid routing congestion, the input length of the decoder needs to be in the range of 1000 - 2000 bits (bit), which limits the code length and causes the coding gain to decrease by at least 0.6 decibels (dB). At the same time, the number of decoding iterations and the length of decoding soft information both need to be significantly reduced to improve the decoding rate, which results in the coding gain decreasing by at least 0.8 dB. Therefore, the current parity-check matrix of QC-LDPC codes is difficult to meet the coding requirements of high reliability and high throughput for 5.5G / 6G services.

[0120] In view of this, the embodiments of the present application provide a communication method and related device. In this method, the first communication device and the second communication device complete encoding and decoding through the parity-check matrix of the SC-LDPC code. The sub-parity-check matrices of the parity-check matrix of the SC-LDPC code have a coupling characteristic, and good error performance can be obtained. In addition, compared with the parity-check matrix of the QC-LDPC code, the parity-check matrix of the SC-LDPC code increases the decoding parallelism and can achieve fast decoding to obtain better decoding performance.

[0121] The following combines Figure 3 , and details the method provided by the embodiments of the present application. This method 300 can be applied to Figure 1 the communication system shown, but the embodiments of the present application are not limited thereto.

[0122] In Figure 3 the flowchart shown, the method is described from the perspective of the interaction of communication devices. However, the execution subject of the method is not limited in this application. For example, Figure 3 the first communication device in Figure 3 can be a terminal device or a network device, or can also be a component (such as a chip, a chip system, etc.) configured in a terminal device or a network device, or can also be a logic module or software capable of implementing all or part of the functions of a terminal device or a network device; and for another example,

[0123] Figure 3 is a schematic flowchart of a method 300 for generating a parity check matrix provided in an embodiment of this application. As Figure 3 shown, the method 300 may include S301 to S308. Each step in the method 300 will be introduced in detail below.

[0124] S301, the first communication device obtains the parity check matrix of the target SC-LDPC code.

[0125] In a possible implementation, the parity check matrix of the target SC-LDPC code is intercepted from a preset parity check matrix of the SC-LDPC code based on the target code rate and the length of the information bits.

[0126] Wherein, the number of rows of the preset parity check matrix of the SC-LDPC code is M, the number of columns is N, and the values of the elements in the preset parity check matrix of the SC-LDPC code are 0 or 1; or, the number of rows of the parity check matrix of the target SC-LDPC code is M, the number of columns is N, and the values of the elements in the preset parity check matrix of the SC-LDPC code are 0 or 1.

[0127] In another possible implementation, the parity check matrix of the target SC-LDPC code is determined based on the target code rate, the length of the information bits, and a first mapping relationship.

[0128] Wherein, the first mapping relationship indicates the corresponding relationship between at least one code rate, at least one information bit length, and at least one parity check matrix of the SC-LDPC code; the number of rows of the parity check matrix of the target SC-LDPC code is M, the number of columns is N, the values of the elements in the parity check matrix of the target SC-LDPC code are 0 or 1, and both M and N are integers greater than 1.

[0129] In the above two possible implementation manners, the 0th row to the (M - 1)th row in the M rows, and the 0th column to the (n - 1)th column in the N columns form a first matrix, and the elements in the jth column to the (j + n - 1)th column in the N columns are obtained by cyclically shifting the first matrix downward by ((j / n) * m) rows; the first matrix includes a second matrix with ((Z + 1) * m) rows and n columns, and the second matrix is a matrix formed by the i-th row to the (i + (Z + 1) * m - 1)th row in the first matrix. All other elements in the first matrix except the second matrix are 0. Z is an integer greater than 0, i is an integer greater than or equal to 0 and less than or equal to (M - (Z + 1) * m), j = n, 2 * n,..., y * n; (y + 1) = N / n, M is divisible by m, and n, m, and y are all integers greater than 1.

[0130] Among them, the above second matrix is obtained by arranging (Z + 1) third matrices with m rows and n columns in sequence by rows. Among the (Z + 1) third matrices, there are Z third matrices. The relationship between the number K of elements 1 included in the Z third matrices and the number L of elements 1 included in the first matrix satisfies the following relationship: K / L = Z * z%, K / L ≤ 50%, (L - K) ≥ (K / Z), or the number of remaining elements 1 in the second matrix except the K elements 1 included in the Z third matrices is greater than or equal to the number of elements 1 included in at least one of the Z third matrices.

[0131] z is an integer less than or equal to 100 * R, or z is an integer less than or equal to 100 * (1 - R). It should be understood that when M and N are the number of rows and columns of the parity-check matrix of the target SC-LDPC code respectively, R is the target code rate, or R is the maximum code rate or the minimum code rate supported by the parity-check matrix of the SC-LDPC code included in the above first mapping relationship; when M and N are the number of rows and columns of the parity-check matrix of the preset SC-LDPC code respectively, the above R is the maximum code rate or the minimum code rate supported by the parity-check matrix of the preset SC-LDPC code.

[0132] The above second matrix is obtained by arranging (Z + 1) third matrices with m rows and n columns in sequence by rows. It can be understood that the second matrix is composed of (Z + 1) third matrices with m rows and n columns. That is, starting from the 0th row of the second matrix, the matrix formed by every m rows of elements is called a third matrix, and (Z + 1) third matrices are obtained.

[0133] It can be understood that the length of the above information bits can be replaced with a target code length. For example, the parity-check matrix of the target SC-LDPC code is determined based on the target code rate, the length of the information bits, and the first mapping relationship, which indicates the correspondence between at least one code rate, at least one code length, and at least one parity-check matrix of the SC-LDPC code.

[0134] In the parity-check matrix of the target SC-LDPC in this application, the elements from the j-th column to the (j + n - 1)-th column among the N columns are obtained by cyclically shifting the first matrix downward by ((j / n) * m) rows. Since the position range of the non-zero elements in the first matrix is known, the position range of the non-zero elements in the parity-check matrix of the target SC-LDPC can be obtained. Therefore, the parity-check matrix of the target SC-LDPC code has a lower decoding scheduling complexity.

[0135] Optionally, the above Z third matrices are summed to obtain a fourth matrix; the above Z + 1 third matrices are summed to obtain a fifth matrix. Among them, the K elements included in the fourth matrix are evenly distributed among the L elements 1 included in the fifth matrix.

[0136] It can be understood that the number of rows and columns of the fifth matrix and the fourth matrix is the same (the number of rows is m, and the number of columns is n).

[0137] It should be noted that in this application, summing multiple matrices refers to summing multiple matrices modulo 2. For example, summing the above Z third matrices modulo 2.

[0138] Through the following example, the meaning of uniform distribution is introduced. Exemplarily, the K elements 1 included in the fourth matrix are arranged in sequence according to the order of the matrix columns to obtain a second list, and the length of this second list is K; similarly, the L elements 1 included in the fifth matrix are arranged in sequence according to the order of the matrix columns to obtain a first list, and the length of this first list is L. Take any three adjacent elements 1 from the second list and determine the positions of these three adjacent elements 1 in the fourth matrix. For example, the positions of the three elements 1 in the fourth matrix are (m1, n1), (m2, n2), and (m3, n3). Then determine the positions of the three elements 1 at the positions (m1, n1), (m2, n2), and (m3, n3) in the fifth matrix in the first list: position 1, position 2, position 3, and the number of elements 1 included between position 1 and position 2 is the same as the number of elements 1 included between position 2 and position 3. It should be understood that the elements 1 included in the above fifth matrix and fourth matrix can also be arranged by rows.

[0139] In other words, the K elements 1 included in the above fourth matrix are evenly selected from the L elements 1 included in the above fifth matrix. The following combines Figure 4 and Figure 5 , to introduce the method of this uniform selection.

[0140] As shown in (a) and (b) of Figure 4 , and (a) and (b) of Figure 5 : The fifth matrix has 4 rows and 4 columns, and includes 8 element 1s. If 4 element 1s need to be evenly selected from the 8 element 1s included in the fifth matrix, then the fourth matrix needs to include 4 element 1s.

[0141] Example 1: Arrange the 8 element 1s in the fifth matrix by column and number them in sequence, and the fifth matrix as shown in (a) and (b) of Figure 4 can be obtained.

[0142] For the fifth matrix shown in (a) of Figure 4 , starting from number ① to select element 1, and selecting one element 1 every other element 1, then the numbers corresponding to the sequentially selected element 1s are ①, ③, ⑤, ⑦ respectively; update the unselected element 1s in the fifth matrix to element 0, and the fourth matrix shown in (a) of Figure 4 can be obtained.

[0143] As shown in (b) of Figure 4 , starting from number ② to select element 1, and selecting one element 1 every other element 1, then the numbers corresponding to the sequentially selected element 1s are ②, ④, ⑥, ⑧ respectively; update the unselected element 1s in the fifth matrix to element 0, and the fourth matrix shown in (b) of Figure 4 can be obtained.

[0144] Example 2: Arrange the 8 element 1s in the fifth matrix by row and number them in sequence, and the fifth matrix as shown in (a) and (b) of Figure 5 can be obtained.

[0145] Similarly, for the fifth matrix shown in (a) of Figure 5 , starting from number ① to select element 1, and selecting one element 1 every other element 1, then the numbers corresponding to the sequentially selected element 1s are ①, ③, ⑤, ⑦ respectively; update the unselected element 1s in the fifth matrix to element 0, and the fourth matrix shown in (a) of Figure 5 can be obtained.

[0146] As shown in (b) of Figure 5 , starting from number ② to select element 1, and selecting one element 1 every other element 1, then the numbers corresponding to the sequentially selected element 1s are ②, ④, ⑥, ⑧ respectively; update the unselected element 1s in the fifth matrix to element 0, and the fourth matrix shown in (b) of Figure 5 can be obtained.

[0147] It can be understood that the present application does not limit the selection manner of the K elements 1 included in the fourth matrix. For example, the K elements 1 can be randomly selected; for another example, when the fifth matrix includes at least K elements 1 with different row numbers and column numbers, the K elements 1 can be randomly selected from the at least K elements 1 with different row numbers and column numbers in the fifth matrix, or when the fifth matrix includes at least K'(K' is an integer greater than 0 and less than K) elements 1 with different row numbers and column numbers, the K elements 1 include the at least K'(K' is an integer greater than 0 and less than K) elements 1 with different row numbers and column numbers.

[0148] It should be noted that when uniformly selecting K elements from L elements, if x = L / K and x is an integer, one element 1 can be selected from every (x - 1) elements 1 among the L elements to obtain L elements 1; if x = L / K and x is not an integer, one element 1 can be selected from every element 1 first, and then randomly or uniformly select elements 1 from the remaining elements 1 to obtain L elements 1. Among them, represents rounding up.

[0149] Exemplarily, the following combines Figure 6 to introduce the manner of selecting K elements 1 from L elements 1.

[0150] As Figure 6 shown in (a) of, the number of rows of the fifth matrix is 4 and the number of columns is 4. The fifth matrix includes 8 elements 1, and the 8 elements 1 include multiple groups of elements 1, and each group of elements 1 includes 4 elements 1 with different row numbers and column numbers. In Figure 6 the fifth matrix shown, the elements 1 identified by the same number belong to one group.

[0151] Example 1, if it is necessary to randomly select 4 elements 1 from the 8 elements 1 included in the fifth matrix, then one group of elements 1 can be randomly selected from the 8 elements as the elements 1 included in the fourth matrix.

[0152] As Figure 6 shown in (a) of, the fifth matrix includes 3 groups of elements 1, and the 4 elements 1 included in each group of elements 1 have different row numbers and column numbers. If the group of elements 1 identified by number ① is used as the 4 elements 1 to be selected, the fourth matrix shown in (b) of can be obtained; if the group of elements 1 identified by number ② is used as the 4 elements 1 to be selected, the fourth matrix shown in (c) of can be obtained; if the group of elements 1 identified by number ③ is used as the 4 elements 1 to be selected, the one shown in Figure 6 can be obtained as shown in (c) of; if the group of elements 1 identified by number ③ is used as the 4 elements 1 to be selected, the one shown in Figure 6 can be obtained as shown in (c) of; if the group of elements 1 identified by number ③ is used as the 4 elements 1 to be selected, the one shown inFigure 6 The fourth matrix shown in (d) in

[0153] Example 2: If it is necessary to randomly select 6 out of the 8 element 1s to be included in the fifth matrix, then a group of element 1s can be randomly selected from the 8 element 1s, and two element 1s can be randomly selected or evenly selected from the remaining element 1s except for the selected group of element 1s as the element 1s included in the fourth matrix.

[0154] Example 3: If it is necessary to randomly select 2 out of the 8 element 1s to be included in the fifth matrix, then a group of element 1s can be randomly selected from the 8 element 1s, and two element 1s can be randomly selected or evenly selected from within this group of element 1s as the element 1s included in the fourth matrix.

[0155] Optionally, the element 1s included in each of the above Z third matrices are evenly distributed among the K element 1s included in the fourth matrix.

[0156] Similarly, if Z = 2, the third matrix #1 and the third matrix #2 can be obtained. Arrange the element 1s included in the third matrix #1 in sequence according to the matrix columns to obtain a list 1 with a length of K1 (K1 is an integer greater than 0 and less than K); arrange the element 1s included in the third matrix 2 in sequence according to the matrix columns to obtain a list 2 with a length of K2 (K2 = K - K1); randomly select two element 1s from list 2, but it is necessary to ensure that the positions of the elements selected from list 1 in list 1 are the same as the positions of the elements selected from list 2 in list 2. For example, they are both at position 1 and position 2 in the list. If the positions of the two element 1s selected from list 1 in the third matrix 1 are (ml, nl) and (m2, n2) respectively, and the positions of the two element 1s selected from list 2 in the third matrix 2 are (m3, n3) and (m4, n4) respectively, then determine the positions of the four element 1s at positions (ml, nl), (m2, n2), (m3, n3) and (m4, n4) in the fourth matrix in the second list: position 1, position 2, position 3, position 4, and the element 1s included between position 1 and position 3 are the same as the element 1s included between position 2 and position 4. It should be understood that the element 1s included in the above third matrix 1, third matrix 2 and fourth matrix can also be arranged by rows.

[0157] Optionally, the element 1s included in each of the Z third matrices are randomly distributed among the K element 1s included in the fourth matrix.

[0158] In other words, after determining K elements 1 and the value of Z, the encoding device or the decoding device can divide the K elements 1 into Z groups, and the number of elements 1 included in each group can be the same or different. If the K elements 1 are arranged in rows (or columns), and each group includes multiple elements 1, the elements 1 included in each group among the K elements 1 can be consecutive or non-consecutive.

[0159] S302, the first communication device encodes information bits based on the parity-check matrix of the target SC-LDPC code to obtain a first SC-LDPC codeword.

[0160] Among them, the length of the information bits is the same as the length of the information bits used to determine the parity-check matrix of the target SC-LDPC code.

[0161] In a possible implementation, the above-mentioned preset parity-check matrix of the SC-LDPC code or the parity-check matrix of the target SC-LDPC code can also be determined through the following steps 1 to 4. It should be understood that steps 1 to 4 can be executed by the encoding device or by the decoding device.

[0162] Step 1, based on the code rate R and the length l of the information bits, determine matrix 1. The number of rows of this matrix 1 is a, the number of columns is b, the values of the elements in matrix 1 are 0 or 1, and matrix 1 includes Y elements 1, R = 1 - a / b, l = k * b, k is an integer greater than 0, and a, b, and Y are all integers greater than 1.

[0163] If each row of matrix 1 can correspond to a check node and each column corresponds to a variable node, the element 0 in matrix 1 indicates that the corresponding variable node and check node are not connected, and the element 1 in matrix 1 indicates that the corresponding variable node and check node are connected. Or rather, each element 1 in matrix 1 corresponds to an edge, and each edge connects the variable node corresponding to the column where the element 1 is located and the check node corresponding to the row where the element 1 is located. Since matrix 1 includes Y elements 1, matrix 1 includes Y edges.

[0164] In a possible implementation, the above-mentioned determination of matrix 1 based on the code rate R and the length l of the information bits includes: determining matrix 5 based on the code rate R and the length l of the information bits, the number of rows of this matrix is (a / D), the number of columns is (b / D), and this matrix 5 includes (Y / D) edges, D is an integer greater than 1; using the quasi-cyclic (QC) algorithm to expand matrix 5 to obtain the above-mentioned matrix 1, and D is the expansion coefficient.

[0165] The above-mentioned matrix 1 can be understood as the fifth matrix in this application.

[0166] Step 2: Based on Matrix 1, obtain a Matrix 2 and Z Matrices 3. The Matrix 2 and the Z Matrices 3 have the same number of rows and the same number of columns. The number of rows is a and the number of columns is b for both the Matrix 2 and the Z Matrices 3, and the sum of the Matrix 2 and the Z Matrices 3 is Matrix 1.

[0167] Among them, Matrix 2 is the matrix corresponding to Matrix 1 after removing W edges out of Y edges. Each of the Z Matrices 3 includes at least one edge, and at least one edge belongs to the W edges. Any two of the Z Matrices 3 include different edges, and W / Y = Z*z%.

[0168] In a possible implementation, the W edges can be selected at equal intervals (or called evenly selected) from the Y edges. Or rather, the W Element 1s are selected at equal intervals from the Y Element 1s included in Matrix 1.

[0169] For the specific selection method, reference can be made to the relevant descriptions in the foregoing Figure 4 and Figure 5 and will not be elaborated here.

[0170] In a possible implementation, the Element 1s included in each Matrix 3 are selected at equal intervals (or called evenly selected) from the W Element 1s. For the specific selection method, reference can be made to the relevant descriptions in the foregoing Figure 6 and will not be elaborated here.

[0171] The above Matrix 2 and Z Matrices 3 can be understood as (Z + 1) Third Matrices in this application. Among them, the Z Matrices 3 can be understood as the Z Third Matrices in this application.

[0172] Step 3: Based on Matrix 2 and Z Matrices 3, obtain Matrix 4. The number of rows of Matrix 4 is ((Z + 1)*a), and the number of columns is (b*F).

[0173] Matrix 4 is the matrix obtained by arranging Matrix 2 and Z Matrices 3 in sequence by rows. This application does not limit the arrangement order of Matrix 2 and Z Matrices 3. It should be understood that the arrangement order of Matrix 2 and Z Matrices 3 can be predefined. The following gives three arrangement orders:

[0174] Example 1: If Matrix 2 is denoted as H2, and the Z Matrices 3 are respectively denoted as: H 31 , H 32 , …, H 3Z , and Matrix 4 is denoted as: H4. H4 satisfies:

[0175]

[0176] Example 2: If Matrix 2 is denoted as H2, and the Z Matrices 3 are respectively denoted as: H 31 , H 32 , …, H 3Z, the matrix 4 is denoted as: H4. H4 satisfies:

[0177]

[0178] Example 3, if the matrix 2 is denoted as H2, and Z matrices 3 are respectively denoted as: H 31 , H 32 , …, H 3Z , the matrix 4 is denoted as: H4. H4 satisfies:

[0179]

[0180] Step 4, determine the coupling chain length k, and place k matrices 4 in sequence according to a preset manner to obtain the parity-check matrix of the SC-LDPC code.

[0181] In the parity-check matrix of the SC-LDPC code, all positions other than the k matrices 4 are 0.

[0182] The number of columns of the parity-check matrix of the SC-LDPC code is k times the number of columns of matrix 3, and the number of rows is (k + Z) times the number of rows of matrix 3. For example, if matrix 3 has 5 columns, then the number of columns of the parity-check matrix of the SC-LDPC code is 5 * k. Another example, if matrix 3 has 3 rows, then the number of columns of the parity-check matrix of the SC-LDPC code is 3 * (k + Z).

[0183] In a possible implementation, this step 4 may include: expanding matrix 4 using the QC algorithm to obtain matrix 5, where the number of rows of matrix 5 is ((Z + 1) * a * F), the number of columns is (b * F), and F is the expansion coefficient; determining the coupling chain length k; placing matrix 5 in sequence according to the preset positions to obtain the parity-check matrix of the SC-LDPC code.

[0184] The above matrix 4 and matrix 5 can be understood as the second matrix in this application.

[0185] Next, taking the number of check nodes a = 3, the number of variable nodes b = 6, and the number of edges Y = 12 included in matrix 1 as an example, combined with Figures 7 to 9 introduce in detail the process of obtaining the parity-check matrix of the SC-LDPC code. It should be understood that this matrix 1 is the matrix expanded by the QC algorithm.

[0186] As Figure 7 shown, number the 3 check nodes in sequence to obtain check node a1, check node a2, and check node a3. Number the 6 variable nodes in sequence to obtain variable node b1, variable node b2, variable node b3, variable node b4, variable node b5, and variable node b6. Among them, a1 is respectively connected to b1, b2, b4, b5, a2 is respectively connected to b1, b3, b4, b6, and a3 is respectively connected to b2, b3, b5, b6, obtaining 12 edges.

[0187] Based on Figure 7 From the 3 check nodes, 6 variable nodes shown, and the connection relationships between the check nodes and the variable nodes, matrix 1 can be obtained, denoted as H1:

[0188]

[0189] Among them, matrix 1 includes 12 elements 1.

[0190] Taking R = 0.4 and z = 25 as an example, according to the relationship satisfied between W and Y: W / Y = Z*z%, W = 6 can be obtained. From Figure 7 Among the 12 edges shown, 6 edges are selected at equal intervals to be disconnected. For example, select to disconnect the connection between a1 and b1, disconnect the connection between a1 and b2, disconnect the connection between a2 and b3, disconnect the connection between a1 and b4, disconnect the connection between a1 and b5, and disconnect the connection between a2 and b6, and the connection diagram of the variable nodes and the check nodes as shown Figure 8 can be obtained.

[0191] Based on Figure 8 From the 3 check nodes, 6 variable nodes shown, and the connection relationships between the check nodes and the variable nodes, matrix 2 can be obtained, denoted as H2:

[0192]

[0193] Among them, matrix 2 includes 6 elements 1. This H2 can be understood as the remaining third matrix among the (Z + 1) third matrices in this application except for Z third matrices.

[0194] Taking Z = 2 as an example, from Figure 7 Among the 6 disconnected edges, 3 edges are selected at equal intervals: the connection between a1 and b1, the connection between a2 and b3, and disconnect the connection between a1 and b5, and the connection diagram of the variable nodes and the check nodes as shown in (a) of Figure 9 can be obtained; from Figure 7 Among the 6 disconnected edges, 3 edges are selected at equal intervals: the connection between a1 and b2, the connection between a1 and b4, and the connection between a2 and b6, and the connection diagram of the variable nodes and the check nodes as shown in (b) of Figure 9 can be obtained.

[0195] Based on Figure 9 From the connection relationships of the 3 check nodes, 6 variable nodes shown in (a) and (b) and the connection relationships between the check nodes and the variable nodes, two matrix 3s can be obtained, denoted as H 31 and H 32 :

[0196]

[0197] Among them, each matrix 3 includes 6 elements 1. This H 31 and H 32 can be understood as the Z third matrices in this application.

[0198] Based on the above matrix 2 and two matrices 3, matrix 4 can be obtained, denoted as H4:

[0199]

[0200] Among them, this matrix 4 includes 12 elements 1, which is the same as the number of elements 1 included in matrix 1. This matrix 4 can be understood as the second matrix in this application.

[0201] Exemplarily, when the coupling chain length k = 3, the parity-check matrix of the SC-LDPC code can be obtained, denoted as H5:

[0202]

[0203] Among them, the number of rows of H2, H 31 , H 32 are the same, and the number of columns are the same; "0" represents a matrix of all 0s, and the number of rows is the same as that of H2, and the number of columns is the same as that of H2; the matrix composed of the first-column elements can be understood as the first matrix in this application.

[0204] Optionally, the first communication device encodes the information with a length of l based on the parity-check matrix of the target SC-LDPC code to obtain the first SC-LDPC codeword, including: the first communication device divides the information bits with a length of l into Q (Q = N / n) groups; and encodes the Q groups of information bits based on the parity-check matrix of the target SC-LDPC code to obtain the first SC-LDPC codeword including Q groups of encoded bits, and each group of encoded bits in the Q groups of encoded bits includes a group of information bits and a group of parity bits.

[0205] Among them, each group of information bits includes at least one information bit, and the number of information bits included in any two groups of information bits among the Q groups of information bits can be the same or different.

[0206] Exemplarily, when the number of information bits included in the Q groups of information bits are the same, each group of information bits includes A (A = l / Q) information bits, and each group of parity bits in the Q groups of parity bits includes B (B = n - l / Q) parity bits, and A and B are integers greater than 0.

[0207] It can be understood that the A information bits can be arranged continuously.

[0208] It can also be understood that among each group of encoded bits in the above Q groups of encoded bits, the information bits are located before the parity bits. In other words, when the first communication device encodes the Q groups of information bits, each group of information bits corresponds to the first A columns of each first matrix.

[0209] Exemplarily, if the Q groups of encoded bits in the first SC-LDPC codeword are sequentially numbered continuously starting from 1, then any parity bit in the q-th group of encoded bits in the Q groups of encoded bits has a parity relationship with at least one group of encoded bits in the consecutive p groups of encoded bits before the q-th group of encoded bits, where q is an integer greater than 1 and less than Q, and p is an integer greater than 0 and less than p.

[0210] It can be understood that the consecutive p groups of encoded bits before the q-th group of encoded bits refer to the (q - 1)-th group of encoded bits to the (q - p)-th group of encoded bits.

[0211] Next, taking Q = 4, A = 4, and B = 2 as an example (that is, the first SC-LDPC codeword includes 4 groups of encoded bits, each group of encoded bits includes 4 information bits and 2 parity bits), in combination with Figure 10 introduce the first SC-LDPC codeword.

[0212] As Figure 10 shown, the first SC-LDPC codeword is: 101011 010100 100101 011010. Among them, the first group of information bits in the first group of encoded bits is: 1010, and the first group of parity bits is: 11; the second group of information bits in the second group of encoded bits is: 0101, and the second group of parity bits is: 00; the third group of information bits in the third group of encoded bits is: 1001, and the third group of parity bits is: 01; the fourth group of information bits in the fourth group of encoded bits is: 0110, and the fourth group of parity bits is: 10.

[0213] Exemplarily, when q = 3 and p = 2, it is obtained that any parity bit 01 in the third group of encoded bits has a parity relationship with at least one group of encoded bits in the second group of encoded bits (010100) and the third group of encoded bits (100101).

[0214] Optionally, after S302, the method 300 may further include: S303 to S305.

[0215] S303, the first communication device reorders the Q groups of encoded bits in the first SC-LDPC codeword to obtain a second SC-LDPC codeword.

[0216] The second SC-LDPC codeword includes Q groups of information bits and Q groups of parity bits, and the positional relationship between the Q groups of information bits and the Q groups of parity bits in the second SC-LDPC codeword satisfies any one of the following characteristics 1 to 5:

[0217] Feature 1: The Q-group information bits are located before the Q-group check bits.

[0218] Combined with Figure 10 the first SC-LDPC codeword shown, the second SC-LDPC codeword can be: 1010 0101 10010110 11 00 01 10.

[0219] Feature 2: The q-group encoded bits that serve as the decoding starting point among the Q-group encoded bits are located before the other group encoded bits.

[0220] Combined with Figure 10 the first SC-LDPC codeword shown, when q = 2 and the decoding starting points are the first group encoded bits and the fourth group encoded bits respectively, the second SC-LDPC codeword can be: 1010 11 0110 10 0101 00 1001 01, or: 11 1010 10 0110 01 1001 100110.

[0221] Feature 3: The q-group encoded bits that serve as the decoding starting point among the Q-group encoded bits are located before the other group encoded bits, and the information bits in each group of encoded bits are located before the check bits.

[0222] Optionally, the information bits in the other group encoded bits in Feature 3 are located before the check bits in the other group encoded bits.

[0223] Combined with Figure 10 the first SC-LDPC codeword shown, when q = 2 and the decoding starting points are the first group encoded bits and the fourth group encoded bits respectively, the second SC-LDPC codeword can be: 1010 11 0110 10 0101 00 1001 01.

[0224] Feature 4: The q-group encoded bits that serve as the decoding starting point among the Q-group encoded bits are located before the other group encoded bits, and the information bits in the q-group encoded bits are located before the check bits in the q-group encoded bits.

[0225] Combined with Figure 10 the first SC-LDPC codeword shown, when q = 2 and the decoding starting points are the first group encoded bits and the fourth group encoded bits respectively, the second SC-LDPC codeword can be: 1010 0110 11 10 1001 01 0110 10.

[0226] Or, among the Q groups of coded bits, for the q groups of coded bits that are the decoding starting points, the information bits are before the information bits of other groups of coded bits, the parity bits of the q groups of coded bits are before the parity bits of other groups of coded bits, and the information bits of the Q groups of coded bits are before the parity bits.

[0227] Combined with Figure 10 Taking the first SC-LDPC codeword shown as an example, when q = 2 and the decoding starting points are the first group of coded bits and the fourth group of coded bits respectively, the second SC-LDPC codeword can be: 1010 0110 0101 1001 11 10 00 01.

[0228] The above-mentioned other groups of coded bits refer to the remaining groups of coded bits in the Q groups of coded bits except the q groups of coded bits. Or rather, the above-mentioned other groups of coded bits refer to the groups of coded bits that are not the decoding starting points in the Q groups of coded bits.

[0229] Optionally, the positional relationship between the above-mentioned other groups of coded bits satisfies: the other groups of coded bits are arranged in ascending order of the first distance, and the first distance refers to the number of groups of coded bits separated between each group of coded bits in the other groups of coded bits and the q groups of coded bits in the first SC-LDPC codeword.

[0230] Or rather, among the other groups of coded bits, the r groups of coded bits adjacent to the q groups of coded bits are before the s groups of coded bits not adjacent to the q groups of coded bits, and among the s groups of coded bits, the y groups of coded bits adjacent to the r groups of coded bits are before the w groups of coded bits not adjacent to the r groups of coded bits, and so on until all the Q groups of coded bits are arranged. Among them, s, r, y, and w are all integers greater than or equal to 0 and less than Q.

[0231] Exemplarily, if the decoding starting points in the first SC-LDPC codeword are the first group of coded bits and the Qth group of coded bits, then the (2t - 1)th group of coded bits in the Q groups of information bits of the second SC-LDPC codeword is the tth group of coded bits in the Q groups of coded bits of the first SC-LDPC codeword, and the tth group of coded bits in the Q groups of coded bits of the second SC-LDPC codeword is the (Q - t + 1)th group of coded bits in the Q groups of information bits of the first SC-LDPC codeword, where t = 1, 2,..., ceil(Q / 2), and ceil() represents rounding up.

[0232] In a possible implementation, the first communication device reorders Q groups of encoded bits in the first SC-LDPC codeword to obtain a second SC-LDPC codeword, including: the first communication device uses a first row-column interleaver to perform interleaving processing on the first SC-LDPC codeword to obtain a second SC-LDPC codeword, where the number of rows of the first row-column interleaver is Q and the number of columns is (A + B).

[0233] Taking the following Figure 10 as an example of the first SC-LDPC codeword shown, combined with Figure 11 introduce the process of obtaining the second SC-LDPC using the first row-column interleaver.

[0234] As Figure 11 shown, given Q = 4 and A + B = 6, it can be obtained that the number of rows of the first row-column interleaver is 4 and the number of columns is 6. Write the 24 bits in the first SC-LDPC codeword into the second row-column interleaver in sequence from left to right, and then read out the bits of each column from top to bottom, the second SC-LDPC codeword that can be obtained is: 1010 0101 1001 0110 1001 1010. Based on the first row-column interleaver, in the second SC-LDPC codeword obtained, all information bits are arranged before all parity bits.

[0235] In another possible implementation, the first communication device reorders Q groups of encoded bits in the first SC-LDPC to obtain a second SC-LDPC codeword, including: the first communication device reorders the Q groups of encoded bits based on the decoding method of the first SC-LDPC codeword to obtain a second SC-LDPC codeword.

[0236] Among them, the decoding methods include bidirectional sliding window decoding and parallel sliding window decoding. Bidirectional sliding window decoding means that the second communication device performs sliding window decoding from the encoded bit groups at the beginning and the end of the first SC-LDPC codeword towards the middle encoded bit groups; parallel sliding window decoding means that the second communication device performs sliding window decoding from multiple encoded bit groups among the Q groups of encoded bits included in the first SC-LDPC codeword.

[0237] Optionally, the decoding method is bidirectional sliding window decoding, and the q groups of encoded bits are the first group of encoded bits and the Qth group of encoded bits in the first SC-LDPC codeword.

[0238] Exemplarily, the first communication device can cyclically shift the first SC-LDPC codeword backward by the length of one group of encoded bits to place the Qth group of encoded bits and the first group of encoded bits before the other encoded bit groups.

[0239] This application does not limit the arrangement order of two groups of coded bits serving as the decoding starting point. For example, the first group of coded bits may be before the fourth group of coded bits, or the fourth group of coded bits may be before the first group of coded bits.

[0240] Optionally, when the decoding method is parallel sliding window decoding, q is an integer greater than 2 and less than or equal to Q, and the q groups of coded bits are the q groups of coded bits among the Q groups of coded bits serving as the decoding starting point.

[0241] It can be understood that the starting point of parallel sliding window decoding can be indicated by the second communication device to the first communication device; or, the starting point of parallel sliding window decoding is predefined.

[0242] Exemplarily, the decoding starting point predefined by the protocol or indicated by signaling may be: one or more bit positions. The one or more bit positions may be determined by the bit length, and the bit length may be the distance from the starting bit of the SC-LDPC codeword or the distance from the ending bit of the SC-LDPC codeword; or, the one or more bit positions may also be determined by a ratio, and the ratio may be a ratio relative to the code length. For example, it may be at half of the code length or a quarter of the code length.

[0243] This application does not limit the arrangement order among multiple groups of coded bits serving as the decoding starting point. For example, if the multiple groups of coded bits are the first group of coded bits and the third group of coded bits respectively, the first group of coded bits may be before the fourth group of coded bits, or the fourth group of coded bits may be before the first group of coded bits.

[0244] S304, the first communication device interleaves and modulates the second SC-LDPC codeword to obtain a plurality of modulation symbols.

[0245] Among them, interleaving means processing the second SC-LDPC codeword by using a row-column interleaver, that is, writing the second SC-LDPC codeword into the row-column interleaver row by row and reading out the written second SC-LDPC codeword column by column.

[0246] Modulation refers to the process of mapping every consecutive P bits among all the bits included in the second SC-LDPC codeword to a modulation symbol, and each bit in the second SC-LDPC codeword needs to be mapped, and each bit can only be mapped once. Here, P is the modulation order, which is related to the modulation method. For example, when modulating the third SC-LDPC codeword using 256 Quadrature Amplitude Modulation (QAM), P = 8; or when modulating the third SC-LDPC codeword using 64QAM, P = 6. The relevant description of obtaining the modulation order based on the modulation method can refer to the existing description and will not be elaborated here. It should be understood that the first communication device can also use other modulation methods (such as phase shift keying modulation, etc.) to modulate the second SC-LDPC codeword.

[0247] It should be noted that in S304, when reordering the Q groups of coded bits in the first SC-LDPC, the position of the important bits in the second SC-LDPC is related to the reliability of the bit sub-channels among the multiple bits corresponding to each symbol of the selected modulation method. For example, among the multiple bits corresponding to each symbol, the bits in the front have higher reliability and the bits in the back have lower reliability, then the important bits in the Q groups of coded bits need to be arranged before the unimportant bits; or among the multiple bits corresponding to each symbol, the bits in the front have lower reliability and the bits in the back have higher reliability, then the important bits in the Q groups of coded bits need to be arranged after the unimportant bits. That is to say, the arrangement order of the Q groups of coded bits in the second SC-LDPC codeword is determined based on the selected modulation method.

[0248] In a possible implementation, the above-mentioned first communication device interleaves and modulates the second SC-LDPC codeword, including: the first communication device can use a second row-column interleaver to perform interleaving processing on the second SC-LDPC codeword to obtain a third SC-LDPC codeword; map the consecutive P bits in the second SC-LDPC codeword in sequence to a modulation symbol to obtain multiple modulation symbols.

[0249] Among them, the third SC-LDPC codeword includes (Q * A) information bits and (Q * B) parity bits, the number of rows of the second row-column interleaver is P, and the number of columns is D = ceil((A + B) * Q / P).

[0250] It can be understood that each bit in the first SC-LDPC codeword can only be mapped to one modulation symbol. Or rather, the bits mapped on different modulation symbols among the above-mentioned multiple modulation symbols are different.

[0251] Next, taking the modulation method as 256QAM as an example, combined with Figure 12The first SC-LDPC codeword shown is introduced, and the process of obtaining the third SC-LDPC through interleaving and modulation is described.

[0252] As Figure 12 shown, for 256QAM, the modulation order P = 8, D = ceil((4 + 2) * 4 / 8) = 3. The number of rows of the second row-column interleaver is 8, and the number of columns is 3. If the 4 groups of coded bits in the first SC-LDPC codeword shown Figure 10 are reordered, the second SC-LDPC codeword obtained can be: 1010 0101 1001 0110 11 00 01 10; and then continue to use the row-column interleaver with 8 rows and 3 columns to perform interleaving processing on the second SC-LDPC codeword, that is, write the 24 bits in the second SC-LDPC codeword into the row-column interleaver in sequence from left to right, and then read out the bits of each column from top to bottom, the third SC-LDPC codeword obtained can be: 1000000100101101 11111100.

[0253] After that, the first communication device uses 256QAM to modulate the third SC-LDPC codeword obtained in the manner shown Figure 11 to obtain 3 modulation symbols. Among them, 10000001 corresponds to one symbol, 00101101 corresponds to one symbol, and 11111100 corresponds to one symbol.

[0254] For 256QAM, each modulation symbol can correspond to 8 bit channels, and among these 8 bit channels, the reliability of the bit channels in the front position is higher than that of the bit channels in the back position. Since the important bit positions in the above-mentioned second SC-LDPC codeword are arranged in the front, through modulating the third SC-LDPC codeword, the important bits can be modulated onto the bit channels with higher reliability.

[0255] In the embodiments of the present application, by reordering the Q groups of coded bits in the first SC-LDPC codeword, arranging the relatively important bits in the Q groups of coded bits before the unimportant bits to obtain the second SC-LDPC, and then performing interleaving and modulation on the second SC-LDPC, in this way, the important bits in the first SC-LDPC codeword can be mapped onto the bits with higher reliability among the P bits corresponding to the modulation symbol, improving the decoding performance.

[0256] S305, the first communication device sends multiple modulation symbols to the second communication device. Correspondingly, the second communication device receives the multiple modulation symbols from the first communication device.

[0257] Optionally, after S305, the method 300 may further include: S306 to S308.

[0258] S306, the second communication device demodulates and deinterleaves a plurality of modulation symbols to obtain a second SC-LDPC codeword.

[0259] Among them, demodulation is the inverse process of modulation, which refers to the process of demodulating a plurality of modulation symbols into a plurality of bits. Deinterleaving is the inverse process of interleaving, that is, writing the plurality of bits obtained by demodulation into a row-column interleaver column by column and reading out the written plurality of bits row by row. Therefore, it will not be elaborated here.

[0260] For the description of the second SC-LDPC codeword, reference may be made to the relevant description above, and it will not be elaborated here.

[0261] S307, the second communication device reorders the second SC-LDPC codeword to obtain a first SC-LDPC codeword.

[0262] The process shown in S307 is the inverse process of S303 above.

[0263] It can be understood that the first communication device can indicate to the second communication device the arrangement method of obtaining the second SC-LDPC codeword from the first SC-LDPC codeword, so that the second communication device can, after obtaining the second SC-LDPC codeword, restore the first SC-LDPC codeword based on the indicated arrangement method.

[0264] For the description of the first SC-LDPC codeword, reference may be made to the relevant description above, and it will not be elaborated here.

[0265] In a possible implementation, the second communication device may use a first row-column interleaver to deinterleave the second SC-LDPC codeword to obtain the first SC-LDPC codeword, and the number of rows of the first row-column interleaver is Q and the number of columns is (A + B).

[0266] In another possible implementation, the second communication device may reorder the Q groups of information bits and Q groups of parity bits included in the second SC-LDPC codeword based on the decoding method of the first SC-LDPC codeword to obtain the first SC-LDPC codeword.

[0267] S308, the second communication device decodes the first SC-LDPC codeword based on the parity-check matrix of the target SC-LDPC code to obtain an information ratio.

[0268] Optionally, after S308, the method 300 further includes S309: The second communication device obtains the parity-check matrix of the target SC-LDPC code and decodes the first SC-LDPC codeword based on the parity-check matrix of the target SC-LDPC code.

[0269] Among them, the process by which the second communication device obtains the parity-check matrix of the target SC-LDPC code can refer to the relevant description in S301 above, which will not be elaborated here. It should be noted that the target code rate and the length of the information bits for which the second communication device is used to obtain the parity-check matrix of the target SC-LDPC code can be indicated by the first communication device to the second communication device.

[0270] In the embodiments of the present application, the first communication device (for example, an encoding device) encodes the information bits through the obtained parity-check matrix of the target SC-LDPC code to obtain a first SC-LDPC codeword. The decoding device also decodes the first SC-LDPC codeword by using the parity-check matrix of the target SC-LDPC code. Since there is a coupling characteristic between the sub-parity-check matrices of the parity-check matrix of the target SC-LDPC code obtained by the first communication device and the decoding device, better error performance can be obtained. At the same time, the parity-check matrix of the target SC-LDPC code increases the decoding parallelism, can achieve fast decoding, and can obtain better decoding performance.

[0271] The above describes the method provided by the embodiments of the present application in detail. The following combines Figure 13 and Figure 14 to describe the device provided by the embodiments of the present application in detail.

[0272] Figure 13 and Figure 14 are schematic diagrams of possible devices provided by the embodiments of the present application. These devices can be used to implement the functions of the first communication device or the second communication device in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0273] Figure 13 is a schematic block diagram of the device provided by the embodiments of the present application. As Figure 13 shown, the device 1300 includes a processing module 1310. Optionally, the device 1300 may further include a transceiver module 1320.

[0274] A possible design is that the device 1300 is used to implement the function of the first communication device in the method embodiment shown above Figure 3 above.

[0275] Exemplarily, the processing module 1310 is configured to: obtain a parity-check matrix of a target SC-LDPC code, where the parity-check matrix of the target SC-LDPC code is obtained from a preset parity-check matrix of the SC-LDPC code based on a target code rate and a length of information bits; encode the information bits based on the parity-check matrix of the target SC-LDPC code to obtain a first SC-LDPC codeword.

[0276] Optionally, the processing module 1310 is further configured to: reorder the Q groups of coded bits to obtain a second SC-LDPC codeword; and perform interleaving and modulation on the second SC-LDPC codeword to obtain a plurality of modulation symbols; the transceiver module 1320 is configured to: transmit the plurality of modulation symbols.

[0277] Optionally, the processing module 1310 is further configured to: perform interleaving processing on the first SC-LDPC codeword by using a first row-column interleaver to obtain the second SC-LDPC codeword, where the number of rows of the first row-column interleaver is Q and the number of columns is (A + B).

[0278] Optionally, the processing module 1310 is further configured to: reorder the Q groups of coded bits based on the decoding method of the first SC-LDPC codeword to obtain the second SC-LDPC codeword.

[0279] For a more detailed description of the above transceiver module 1310 and processing module 1320, reference can be directly made to the relevant descriptions in the Figure 3 corresponding embodiments shown, which will not be elaborated here.

[0280] Another possible design is that the apparatus 1300 is used to implement the functions of the second communication apparatus in the method embodiment shown above Figure 3 in the foregoing.

[0281] Exemplarily, the transceiver module 1320 is configured to: receive a plurality of modulation symbols; the processing module 1310 is configured to: demodulate and process the plurality of modulation symbols to obtain a first SC-LDPC codeword; obtain a parity-check matrix of a target SC-LDPC code, where the parity-check matrix of the target SC-LDPC code is obtained from a preset parity-check matrix of the SC-LDPC code based on a target code rate and a length of information bits; and decode the first SC-LDPC codeword based on the parity-check matrix of the target SC-LDPC code to obtain the information bits.

[0282] Optionally, the processing module 1310 is further configured to: demodulate the plurality of modulation symbols to obtain a third SC-LDPC codeword, where the third SC-LDPC codeword includes (Q * A) information bits and (Q * B) parity bits; and perform deinterleaving processing on the third SC-LDPC codeword to obtain a second SC-LDPC codeword, where the second SC-LDPC codeword includes Q groups of information bits and Q groups of parity bits, and Q = N / n.

[0283] Optionally, the processing module 1310 is further configured to: perform deinterleaving processing on the second SC-LDPC codeword by using a first row-column interleaver to obtain the first SC-LDPC codeword, where the number of rows of the first row-column interleaver is Q and the number of columns is (A + B).

[0284] Optionally, the processing module 1310 is further configured to: reorder the Q groups of information bits and the Q groups of parity bits based on the decoding method of the first SC-LDPC codeword to obtain the first SC-LDPC codeword.

[0285] For a more detailed description of the above transceiver module 1310 and processing module 1320, reference can be directly made to Figure 3 the relevant descriptions in the illustrated embodiments, which will not be elaborated here.

[0286] It should be noted that the apparatus 1300 may include a sending module but not a receiving module. Alternatively, the apparatus 1300 may include a receiving module but not a sending module. Specifically, it depends on whether the above-described solution executed by the apparatus 1300 includes a sending action and a receiving action. It can be understood that since the apparatus 1300 has a communication function, it can also be referred to as a communication apparatus.

[0287] Figure 14 is another schematic block diagram of the apparatus provided in the embodiments of the present application. As Figure 14 shown, the apparatus 1400 includes one or more processors 1410. The processor 1410 may be a general-purpose processor or a dedicated processor, etc. For example, it may be a baseband processor or a central processing unit. The baseband processor may be used to process communication protocols and communication data, and the central processing unit may be used to control the apparatus (such as, the first communication apparatus, the second communication apparatus, or a chip, etc.), execute software programs, and process data of the software programs.

[0288] Optionally, in one design, the processor 1410 may include a program (which may also be referred to as code or instructions sometimes), and the program may be run on the processor 1410 such that the apparatus 1400 executes the method performed by the first communication apparatus or the second communication apparatus in the above method embodiments. In another possible design, the apparatus 1400 includes a circuit ( Figure 14 not shown), and the circuit is used to implement the functions of the first communication apparatus or the second communication apparatus in the above method embodiments.

[0289] Exemplarily, the processor 1410 may be used to execute computer programs or instructions in the memory to implement Figure 3 the steps performed by the first communication apparatus or the second communication apparatus in any one of the method embodiments shown in the illustrated embodiments.

[0290] Optionally, the apparatus 1400 may include one or more memories 1420, on which there are programs (sometimes also referred to as code or instructions), and the programs may be run on the processor 1410 such that the apparatus 1400 executes the method performed by the first communication apparatus or the second communication apparatus in the above embodiments.

[0291] Optionally, an artificial intelligence (AI) module may be included in the processor 1410 and / or the memory 1420. The AI module is used to implement AI-related functions. The AI module may be implemented in a software, hardware, or a combination of software and hardware manner. For example, the AI module may include a radio intelligent controller (RIC) module. For example, the AI module may be a near real-time RIC or a non-real-time RIC.

[0292] Optionally, data may also be stored in the processor 1410 and / or the memory 1420. The processor and the memory may be provided separately or integrated together.

[0293] Optionally, the apparatus 1400 may further include a communication interface 1430. The processor 1410 is sometimes also referred to as a processing unit and controls the apparatus (such as a first communication apparatus or a second communication apparatus). The communication interface 1430 is sometimes also referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., and is used to implement the transceiver function of the apparatus.

[0294] Optionally, the apparatus 1400 further includes a communication interface 1430. The processor 1410 and the communication interface 1430 are coupled to each other. It can be understood that the communication interface 1430 may be a transceiver or an input / output interface.

[0295] It can be understood that since the apparatus 1400 has a communication function, it can also be referred to as a communication apparatus.

[0296] When the apparatus 1400 is used to implement Figure 3 the method, the processor 1410 is used to execute the functions of the above-mentioned processing unit, and the communication interface 1430 is used to execute the functions of the above-mentioned transceiver module. Whether the communication interface 1430 is used for sending or receiving specifically depends on whether the apparatus 1400 performs a sending action or a receiving action in the solution it executes.

[0297] When the above-mentioned apparatus 1400 is a chip applied to a first communication apparatus, the chip implements the functions of the first communication apparatus in the above method embodiment. The chip of the first communication apparatus receives a signal from other modules (such as a radio frequency module or an antenna) in the first communication apparatus, and the signal may be sent by a second communication apparatus to the first communication apparatus; or, the chip of the first communication apparatus sends a signal to other modules (such as a radio frequency module or an antenna) in the first communication apparatus, and the signal may be sent by the first communication apparatus to the second communication apparatus.

[0298] When the above device 1400 is a chip applied to a second communication device, the chip implements the functions of the second communication device in the above method embodiments. The chip of the second communication device receives signals from other modules (such as a radio frequency module or an antenna) in the second communication device, and the signals may be sent by a first communication device to the second communication device; alternatively, the chip of the second communication device sends signals to other modules (such as a radio frequency module or an antenna) in the second communication device, and the signals may be sent by the second communication device to the first communication device.

[0299] It can be understood that when the device 1400 is a first communication device or a second communication device, the communication interface 1430 may be a transceiver, which may specifically include a transmitter and a receiver. The transmitter is used to send signals, and the receiver is used to receive signals. When the device 1400 is a chip applied to a first communication device or a second communication device, the communication interface 1430 may be an input / output circuit, where the input circuit can be used for receiving, and the output interface can be used for sending.

[0300] It should be noted that the above method embodiments can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method embodiments can be completed by the integrated logic circuit in the hardware of the processor or by instructions in software form.

[0301] The above processor may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0302] The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0303] The memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include but not be limited to these and any other suitable types of memory.

[0304] The present application also provides a computer-readable medium, on which a computer program is stored, and when the computer program is executed by a computer, it implements the functions of the above method embodiments.

[0305] The present application also provides a computer program product containing instructions, and when the computer program product is executed by a computer, it implements the functions of the above method embodiments.

[0306] The method provided in the above embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product may include one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that includes one or more integrated available media. The available medium may be a magnetic medium (such as a floppy disk, hard disk, magnetic disk), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0307] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0308] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0309] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other may be through some interfaces. The indirect couplings or communication connections of devices or units may be in electrical, mechanical, or other forms.

[0310] The unit described as a separation component may or may not be physically separated. The component shown as a unit may or may not be a physical unit, that is, it may be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0311] In addition, each functional unit in various embodiments of the present application may be integrated into one processing unit, may exist separately as individual physical units, or two or more units may be integrated into one unit.

[0312] If the above-mentioned function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories, random access memories, magnetic disks, or optical discs that can store program codes.

[0313] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, and all of them should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A communication method, characterized in that, Including: Obtain a parity-check matrix of a target spatially coupled low-density parity-check (SC-LDPC) code, where the parity-check matrix of the target SC-LDPC code is obtained from a parity-check matrix of a preset SC-LDPC code based on a target code rate and the length of information bits; the number of rows of the parity-check matrix of the preset SC-LDPC code is M, the number of columns is N, and the values of the elements in the parity-check matrix of the preset SC-LDPC code are 0 or 1, or the number of rows of the parity-check matrix of the target SC-LDPC code is M, the number of columns is N, and the values of the elements in the parity-check matrix of the target SC-LDPC code are 0 or 1; Among them, in the first matrix composed of the 0th row to the (M - 1)th row among the M rows and the 0th column to the (n - 1)th column among the N columns, there is a second matrix with ((Z + 1)*m) rows and n columns. The elements in the jth column to the (j + n - 1)th column among the N columns are obtained by circularly shifting the first matrix downward by ((j / n)*m) rows. The second matrix is a matrix composed of the ith row to the (i + (Z + 1)*m - 1)th row in the first matrix. All other elements in the first matrix except the second matrix are 0. The second matrix is obtained by arranging (Z + 1) third matrices with m rows and n columns in sequence by rows. Among the (Z + 1) third matrices, there are Z third matrices. The relationship between the number K of elements 1 included in the Z third matrices and the number L of elements 1 included in the second matrix satisfies the following relationship: K / L = Z*z%, (L - K) ≥ (K / Z), or the number of remaining elements 1 in the second matrix except the K elements 1 included in the Z third matrices is greater than or equal to the number of elements 1 included in at least one of the Z third matrices; Z is an integer greater than 0, z is an integer less than or equal to 100*R, or z is an integer less than or equal to 100*(1 - R), R is the target code rate or the maximum code rate or the minimum code rate supported by the parity-check matrix of the preset SC-LDPC code, i is an integer greater than or equal to 0 and less than or equal to (M - (Z + 1)*m), j = n, 2*n,..., y*n; (y + 1) = N / n, M is divisible by m, and n, m, and y are all integers greater than 1; Encode the information bits based on the parity-check matrix of the target SC-LDPC code to obtain a first SC-LDPC codeword.

2. The method according to claim 1, characterized in that, The K elements 1 included in the fourth matrix are evenly distributed among the L elements 1 included in the fifth matrix. The fourth matrix is the sum of the Z third matrices, and the fifth matrix is the sum of the (Z + 1) third matrices.

3. The method according to claim 2, characterized in that, Each of the Z third matrices includes elements 1 that are evenly distributed among the K elements 1 included in the fourth matrix.

4. The method according to any one of claims 1 to 3, characterized in that, The first SC-LDPC codeword includes Q groups of coded bits. Each group of coded bits in the Q groups of coded bits includes a group of information bits and a group of parity bits. Each group of information bits in the Q groups of information bits includes A information bits, and each group of parity bits in the Q groups of parity bits includes B parity bits. A and B are integers greater than 0, and Q = N / n.

5. The method according to claim 4, characterized in that, The method further includes: Reordering the Q groups of coded bits to obtain a second SC-LDPC codeword. The Q groups of information bits and the Q groups of parity bits included in the second SC-LDPC codeword satisfy any one of the following characteristics: The Q groups of information bits are located before the Q groups of parity bits; The q groups of coded bits that are used as the decoding starting point in the Q groups of coded bits are located before the other groups of coded bits; The q groups of coded bits that are used as the decoding starting point in the Q groups of coded bits are located before the other groups of coded bits, and the information bits in each group of coded bits are located before the parity bits; or, The q groups of coded bits that are used as the decoding starting point in the Q groups of coded bits are located before the other groups of coded bits, and the information bits in the q groups of coded bits are located before the parity bits in the q groups of coded bits. q is an integer greater than 0 and less than or equal to Q; Interleaving and modulating the second SC-LDPC codeword to obtain a plurality of modulation symbols; Transmitting the plurality of modulation symbols.

6. The method according to claim 5, characterized in that, The positions of the other groups of coded bits in the second SC-LDPC codeword are arranged in ascending order of a first distance. The first distance refers to the number of groups of coded bits separated between each group of coded bits in the other groups of coded bits and the q groups of coded bits in the first SC-LDPC codeword.

7. The method according to claim 5, characterized in that, The information bits in the other groups of coded bits are located before the parity bits in the other groups of coded bits.

8. The method according to any one of claims 5 to 7, characterized in that, The reordering the Q groups of coded bits to obtain a second SC-LDPC codeword includes: Using a first row-column interleaver to perform interleaving processing on the first SC-LDPC codeword to obtain the second SC-LDPC codeword. The number of rows of the first row-column interleaver is Q, and the number of columns is (A + B).

9. The method according to any one of claims 5 to 7, characterized in that, The reordering the Q groups of coded bits to obtain a second SC-LDPC codeword includes: Reordering the Q groups of coded bits based on the decoding method of the first SC-LDPC codeword to obtain the second SC-LDPC codeword.

10. The method according to claim 9, characterized in that, The decoding method is bidirectional sliding window decoding, and the q groups of coded bits are the first group of coded bits and the Qth group of coded bits in the first SC-LDPC codeword.

11. The method according to claim 9, characterized in that, The decoding method is parallel sliding window decoding. q is an integer greater than 2 and less than or equal to Q, and the q groups of coded bits are the groups of coded bits used as the decoding starting point in the Q groups of coded bits.

12. A communication method, characterized in that, Includes: Receiving a plurality of modulation symbols; Demodulating and processing the plurality of modulation symbols to obtain a first SC-LDPC codeword; Obtain the parity-check matrix of the target SC-LDPC code, where the parity-check matrix of the target SC-LDPC code is obtained from the parity-check matrix of a preset SC-LDPC code based on the target code rate and the length of the information bits; the number of rows of the parity-check matrix of the preset SC-LDPC code is M, the number of columns is N, and the values of the elements in the parity-check matrix of the preset SC-LDPC code are 0 or 1, or the number of rows of the parity-check matrix of the target SC-LDPC code is M, the number of columns is N, and the values of the elements in the parity-check matrix of the target SC-LDPC code are 0 or 1; Among them, the first matrix composed of the 0th row to the (M - 1)th row among the M rows and the 0th column to the (n - 1)th column among the N columns includes a second matrix with ((Z + 1)*m) rows and n columns. The elements of the jth column to the (j + n - 1)th column among the N columns are obtained by cyclically shifting the first matrix downward by ((j / n)*m) rows. The second matrix is a matrix composed of the ith row to the (i + (Z + 1)*m - 1)th row in the first matrix. All other elements in the first matrix except the second matrix are 0. The second matrix is obtained by arranging (Z + 1) third matrices with m rows and n columns in sequence by rows. Among the (Z + 1) third matrices, there are Z third matrices. The relationship between the number K of elements 1 included in the Z third matrices and the number L of elements 1 included in the second matrix satisfies the following relationship: K / L = Z*z%, (L - K) ≥ (K / Z), or the number of remaining elements 1 in the second matrix except the K elements 1 included in the Z third matrices is greater than or equal to the number of elements 1 included in at least one of the Z third matrices; Z is an integer greater than 0, z is an integer less than or equal to 100*R, or z is an integer less than or equal to 100*(1 - R), R is the target code rate or the maximum or minimum code rate supported by the parity-check matrix of the preset SC-LDPC code, i is an integer greater than or equal to 0 and less than or equal to (M - (Z + 1)*m), j = n, 2*n,..., y*n; (y + 1) = N / n, M is divisible by m, and n, m, and y are all integers greater than 1; Decode the first SC-LDPC codeword based on the parity-check matrix of the target SC-LDPC code to obtain the information bits.

13. The method according to claim 12, wherein The K elements 1 included in the fourth matrix are evenly distributed among the L elements 1 included in the fifth matrix. The fourth matrix is the sum of the Z third matrices, and the fifth matrix is the sum of the (Z + 1) third matrices.

14. The method according to claim 13, wherein The elements 1 included in each of the Z third matrices are evenly distributed among the K elements 1 included in the fourth matrix.

15. The method according to any one of claims 12 to 14, wherein The first SC-LDPC codeword includes Q groups of coded bits. Each group of coded bits in the Q groups of coded bits includes a group of information bits and a group of parity bits. Each group of information bits in the Q groups of information bits includes A information bits, and each group of parity bits in the Q groups of parity bits includes B parity bits. A and B are integers greater than 0, and Q = N / n.

16. The method according to claim 15, wherein Demodulating and processing the plurality of modulation symbols to obtain a first SC-LDPC codeword includes: Demodulating the plurality of modulation symbols to obtain a third SC-LDPC codeword, where the third SC-LDPC codeword includes (Q*A) information bits and (Q*B) parity bits; Performing an interleaving process on the third SC-LDPC codeword to obtain a second SC-LDPC codeword, where the second SC-LDPC codeword includes Q groups of information bits and Q groups of parity bits; Reordering the Q groups of information bits and the Q groups of parity bits in the second SC-LDPC codeword to obtain the first SC-LDPC codeword.

17. The method according to claim 16, wherein Any one of the following characteristics is satisfied between the Q groups of information bits and the Q groups of parity bits in the second SC-LDPC codeword: The Q groups of information bits are located before the Q groups of parity bits; q groups of coded bits that are the decoding starting point in the Q groups of coded bits are located before other groups of coded bits; q groups of coded bits that are the decoding starting point in the Q groups of coded bits are located before other groups of coded bits, and the information bits in each group of coded bits are located before the parity bits; or, q groups of coded bits that are the decoding starting point in the Q groups of coded bits are located before other groups of coded bits, and the information bits in the q groups of coded bits are located before the parity bits in the q groups of coded bits.

18. The method according to claim 17, wherein The positions of the other groups of coded bits in the second SC-LDPC codeword are arranged in ascending order of a first distance. The first distance refers to the number of groups of coded bits separated between each group of coded bits in the other groups of coded bits and the q groups of coded bits in the first SC-LDPC codeword.

19. The method according to claim 17, wherein The information bits in the other groups of coded bits are located before the parity bits in the other groups of coded bits.

20. The method according to any one of claims 16 to 19, wherein Reordering the Q groups of information bits and the Q groups of parity bits in the second SC-LDPC codeword to obtain the first SC-LDPC codeword includes: Using a first row-column interleaver to perform an interleaving process on the second SC-LDPC codeword to obtain the first SC-LDPC codeword. The number of rows of the first row-column interleaver is Q, and the number of columns is (A + B).

21. The method according to any one of claims 16 to 19, wherein Reordering the Q groups of information bits and the Q groups of parity bits in the second SC-LDPC codeword to obtain the first SC-LDPC codeword includes: Based on the decoding method of the first SC-LDPC codeword, reordering the Q groups of information bits and the Q groups of parity bits to obtain the first SC-LDPC codeword.

22. A communication device, wherein It includes a module for implementing the method according to any one of claims 1 to 11; or, it includes a module for implementing the method according to any one of claims 12 to 21.

23. A communication device, wherein Comprising a processor for causing the communication device to implement the method according to any one of claims 1 to 11, and / or by means of a logic circuit, or for causing the communication device to implement the method according to any one of claims 12 to 21.

24. The device according to claim 23, wherein Further comprising a memory for storing a computer program, and / or a configuration file of the logic circuit.

25. The device according to claim 23 or 24, wherein Further comprising a communication interface for inputting and / or outputting signals.

26. A computer-readable storage medium, having a computer program stored thereon, wherein When the computer program is executed by the processor, the method according to any one of claims 1 to 11 is executed, or the method according to any one of claims 12 to 21 is executed.

27. A computer program product, whereinComprising a computer program which, when run, executes the method according to any one of claims 1 to 11, or the method according to any one of claims 12 to 21.

28. A communication system, characterized in that, Comprising a first communication device and a second communication device, wherein the first communication device is for implementing the method according to any one of claims 1 to 11, and the second communication device is for implementing the method according to any one of claims 12 to 21.

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