System and method for block-kronecker-based low density parity check (LDPC) codes with 3 / 4 code rates

Abstract

The invention relates to a system and a method for a block Kronecker-based low density parity check (LDPC) code with a 3 / 4 code rate. An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic low density parity check (QC-LDPC) code according to a 3 / 4 code rate, a second parity check matrix corresponding to a first exponential matrix including 576 values of a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of priority of each of U.S. Provisional Patent Application No. 63 / 610,859, filed Dec. 15, 2023; U.S. Provisional Patent Application No. 63 / 610,566, filed Dec. 15, 2023; U.S. Provisional Patent Application No. 63 / 610,762, filed Dec. 15, 2023; and U.S. Provisional Patent Application No. 63 / 610,928, filed Dec. 15, 2023, all of which are hereby incorporated by reference in their entirety for all purposes. Technical Field

[0003] The present disclosure generally relates to systems and methods for improving the encoding process and / or decoding process of a communication system using quasi-cyclic low-density parity-check (QC-LDPC) codes. Background Art

[0004] Error correction codes enable information data to be exchanged reliably between a transmitter communication system and a receiver communication system. The transmitter communication system encodes the information data to obtain a codeword. A codeword is the encoded information data. The transmitter communication system transmits the codeword to the receiver communication system. Due to noise in the communication channel, the transmission received by the receiver communication system may be different from the transmitted codeword. Encoding the information data allows the receiver communication system to recover the information data from the received transmission with an appropriate decoding process despite this noise. For example, the transmitter communication system transmits parity bits to the receiver communication system. The parity bits allow the receiver communication system to verify whether the received transmission is a valid codeword and, if the received transmission is not a valid codeword, correct errors in the transmission. In one method, generating the parity bits involves a complex process. Summary of the Invention

[0005] In one aspect, the present disclosure relates to a method that includes: identifying, by one or more processors of a first device, a second parity-check matrix corresponding to a first exponent matrix including 576 values of a second quasi-cyclic low-density parity-check (QC-LDPC) code based on a first parity-check matrix of a first QC-LDPC code according to a 3 / 4 code rate, wherein the second QC-LDPC code has a code block size that is twice the code block size of the first QC-LDPC code; encoding, by the one or more processors of the first device, data using the second parity-check matrix; and transmitting, by the one or more processors of the first device, the encoded data.

[0006] On the other hand, the present disclosure relates to an apparatus comprising: a transmitter and one or more processors, wherein the one or more processors are configured to: identify a second parity check matrix corresponding to a first exponent matrix including 576 values of a second quasi-cyclic low-density parity-check (QC-LDPC) code based on a first parity check matrix of a first QC-LDPC code according to a 3 / 4 code rate, wherein the second QC-LDPC code has a code block size that is twice the code block size of the first QC-LDPC code; and encode data using the second parity check matrix, and the transmitter is configured to transmit the encoded data.

[0007] On the other hand, the present disclosure relates to an apparatus comprising: a receiver configured to receive encoded data; and one or more processors configured to: identify a second parity check matrix corresponding to a first exponent matrix including 576 values of a second quasi-cyclic low-density parity-check (QC-LDPC) code based on a first parity check matrix of a first QC-LDPC code according to a 3 / 4 code rate, wherein the second QC-LDPC code has a code block size that is twice the code block size of the first QC-LDPC code; and decode the received encoded data using the second binary parity check matrix. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various objects, aspects, features, and advantages of the present disclosure will become more apparent and better understood by referring to the detailed description taken in conjunction with the accompanying drawings, in which like reference symbols identify corresponding elements throughout. In the drawings, like reference symbols generally indicate identical, functionally similar, and / or structurally similar elements.

[0009] Figure 1 is a diagram depicting an exemplary communication environment having a communication system according to one or more embodiments.

[0010] Figure 2 is a schematic block diagram of an operating system according to an embodiment.

[0011] Figure 3 is a diagram depicting an exemplary exponent matrix according to one or more embodiments.

[0012] Figure 4 is a diagram depicting an exemplary shift identity matrix for generating a parity check matrix according to one or more embodiments.

[0013] Figure 5 is a diagram depicting an exemplary parity check matrix according to one or more embodiments.

[0014] Figure 6 is a diagram depicting an exemplary exponent matrix according to one or more embodiments.

[0015] Figure 7A and Figure 7B are diagrams each depicting an exemplary binary matrix Γ (also referred to as a “gamma matrix” or “Γ matrix”) according to one or more embodiments.

[0016] Figures 8A - 8D is a diagram depicting an exemplary exponent matrix and parity-check matrix according to one or more embodiments.

[0017] Figure 9 is a diagram depicting an exemplary implementation (source code) of using the binary matrix Γ to generate a parity-check matrix according to one or more embodiments.

[0018] Figure 10 is a flowchart showing a process for determining one or more binary matrices Γ according to one or more embodiments.

[0019] Figures 11A - 11F is a diagram depicting a graphical representation of a binary parity-check matrix according to one or more embodiments.

[0020] Figure 12 is a flowchart showing a process for encoding data using an LDPC code according to an embodiment.

[0021] Figure 13 is a flowchart showing a process for encoding data and / or decoding data using an LDPC code according to an embodiment.

[0022] Details of various embodiments of the methods and systems are set forth in the figures and the description below. Detailed Description

[0023] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature communicating with or communicatively coupled to a second feature may include embodiments in which the first feature communicates directly with or is directly coupled to the second feature and may also include embodiments in which additional features may intervene between the first and second features such that the first feature communicates indirectly with or is indirectly coupled to the second feature. Additionally, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0024] On the one hand, a parity check matrix defines a set of equations satisfied by any valid codeword. The parity check matrix can be used to encode low-density parity-check ("LDPC") codes, described by Richardson and Urbanke in IEEE Transactions on Information Theory, Vol. 47, No. 2 (February 2001). Generally, many wireless and wired communication systems use LDPC as a forward error correction coding scheme. However, the longest block length (in bits) of the coded data supported by the 802.11 standards (such as 802.11n to 802.11be) is 1944. There may be limited gains achievable with the 1944 block length in a wireless communication channel (such as a 2×2 multiple-input and multiple-output channel).

[0025] To address this issue, according to some aspects, embodiments in the present disclosure relate to techniques for supporting or providing LDPC codes with a block length of 3888 and a code rate of 3 / 4. The 3888 block length is twice the block length of the longest code (such as the 1944 block length) supported by the 802.11n to 802.11be standards. In some embodiments, the LDPC code has a quasi-cyclic (QC) structure that aids in efficient encoding and decoding. In some embodiments, the QC-LDPC code can be a class of structured LDPC codes that can be used in many practical applications including the IEEE 802.11n, 802.11ac, 802.11ax, 802.11be standards. In a QC-LDPC code, the parity check matrix has a cyclic structure that repeats itself in a quasi-cyclic manner, which can simplify the encoding and decoding processes to make the QC-LDPC code more efficient. The code block size (denoted by n) refers to the total number of encoded or transmitted bits resulting from encoding data using an error correction code (such as LDPC). The number of information bits (denoted by k) refers to the number of bits carrying data that is to be encoded using the error correction code. The code rate (denoted by R) refers to the ratio of the number of information bits to the code block size (R = k / n). In some embodiments, the LDPC encoder can take a block of k bits from the information bits (such as k = 2916) and produce n encoded bits with a code rate R = k / n (such as R = 3 / 4, n = 3888). The LDPC decoder can operate on the n received bits (the noisy versions) and (ideally) recover the k information bits. In some embodiments, the LDPC encoder can take a block of k bits from the information bits as input, encode the block of k bits to produce a block of n encoded bits with a code rate of 3 / 4 (R = k / n) (such as n = 3888).

[0026] In some embodiments, a device may include a transmitter and one or more processors. The one or more processors may be configured to determine a first parity-check matrix of a first QC-LDPC code having a first code block size and a 3 / 4 code rate. A parity-check matrix refers to a matrix that can define the relationship (e.g., parity-check equations or constraints) between information bits and parity-check bits. A binary parity-check matrix refers to a parity-check matrix in which all elements are 0 or 1. The one or more processors may be configured to determine a binary matrix (also referred to as a "gamma matrix" or "Γ matrix") having the same size as the exponent matrix of the first parity-check matrix. For example, the exponent matrix of the first parity-check matrix may have a dimension of 6×24 (6 rows and 24 columns) that is the same as the dimension of the binary matrix. The one or more processors may be configured to generate a second parity-check matrix of a second QC-LDPC code having a second code block size and a 3 / 4 code rate based on the first parity-check matrix and the binary matrix. The one or more processors may be configured to encode data using the generated second parity-check matrix. The one or more processors may be configured to transmit the encoded data to another device via the transmitter of the device.

[0027] In some embodiments, the first code block size may be 1944 bits, and the second code block size may be 3888 bits. In some embodiments, each of the first parity-check matrix and the second parity-check matrix may have an exponent matrix including a plurality of integers, the number of the plurality of integers being equal to the number of elements of the parity-check matrix divided by z, where z is an integer representing the lifting coefficient of the QC-LDPC. Each element of the exponent matrix may correspond to a cyclic shift value of an identity matrix. The size of the identity matrix is z×z, and the cyclic shift value d is an integer such that -1≤d<z, where z is an integer representing the lifting coefficient of the QC-LDPC. The cyclic shift value d may represent a shifted identity matrix obtained by shifting the identity matrix to the right by d. The cyclic shift value -1 may represent the zero matrix of the identity matrix.

[0028] In some embodiments, when determining the binary matrix, the one or more processors may be configured to determine a plurality of sub-matrices of the binary matrix, each sub-matrix being a power of a 2nd-order permutation matrix. The one or more processors may be configured to randomize the non-zero values of the binary matrix such that the binary matrix maintains full rank.

[0029] In some embodiments, the binary matrix may comprise the following group of values: [0 1 0 0 0 0 1 1 1 0 0 1 1 11 0 1 1 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 00 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 1 0 11 0 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 10 1 1 0 1 1 1 0 1 1 1 1 0]; and the second exponent matrix corresponding to the second parity-check matrix of the binary matrix may comprise the following group of values: [48 -1 -1 29 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -145 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 -1 32 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 29 -1 -1 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 32 -1 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 49-1 -1 42 -1 48 11 -1 -1 30 -1 -1 -1 -1 -1 -1 49 -1 -1 17 41 -1 37 -1 -1 15 -1-1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 49 42 -1 48 -1-1 11 30 -1 -1 -1 -1 -1 -1 -1 -1 49 17 -1 -1 41 -1 37 15 -1 -1 -1 -1 54 -1 -1-1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 35 -1 76 78 -1 51 -1 37 -1 35 -121 -1 -1 -1 -1 17 64 -1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1-1 -1 32 -1 -1-1 -1 0 -1 0 -1 -1 -1 -1 -1 35 -1 76 -1 -1 78 -1 51 -1 37 -1 35 -1 21 -1 -117 -1 -1 64 -1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 9 -1 -1 65 44 -1 9 -1 -1 54 -1 56 73 -1 -1 34 42 -1 -1 -1 -1-1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 -1 39 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1-1 9 65 -1 -1 44 -1 9 54 -1 56 -1 -1 73 34 -1 -1 42 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7-1 80 -1 68 -1 26 -1 -1 -1 80 55 -1 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1-1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -1 80 -1 68 -1 26-1 -1 -1 80 -1 -1 55 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -1 72 -1 -1 -1 -1-1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 26 -1 75 33 -1 21 -1 69 -1 59 -1 3 -1 -1 38-1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 62 36 -1 -1 26 -1 -1 -1 -1 1 -1 -1 -1 -1 -1-1 -1 -1 -1 0 -1 26 -1 75 -1 -1 33 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 62 -1 -1 36 26 -1 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1-1 -1 -1 0]。

[0030] In some embodiments, when generating a second parity check matrix based on a first parity check matrix and a binary matrix, one or more processors may be configured to determine a first exponent matrix of the first parity check matrix, determine the Khatri-Rao product of the first exponent matrix and the binary matrix, and determine a second exponent matrix of the second parity check matrix based on the result of the Khatri-Rao product. When generating a second parity check matrix based on the first parity check matrix and the binary matrix, one or more processors may be configured to generate a shifted identity matrix of the identity matrix for each element of the second exponent matrix based on the value of each element of the second exponent matrix. One or more processors may be configured to generate the second parity check matrix such that the second parity check matrix includes the generated shifted identity matrix as an element corresponding to each element of the second exponent matrix.

[0031] In some embodiments, the binary matrix may comprise the following set of values: [0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0]; and the second exponent matrix corresponding to the second parity-check matrix of the binary matrix may comprise the following set of values: [48 -1 29 -1 -1 28 -1 39 9 -1 -1 61 -1 -1 -1 -1 -1 -1 -1 -1 63 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 32 -1 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 -1 29 28 -1 39 -1 -1 9 61 -1 -1 -1 -1 -1 -1 -1 63 -1 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 -1 32 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 49 -1 42 48 -1 -1 11 -1 30 -1 -1 -1 -1 -1 -1 -1 49 17 -1 41 -1 37 -1 15 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 49 -1 42 -1 -1 48 11 -1 30 -1 -1 -1 -1 -1 -1 -1 49 -1 -1 17 -1 41 -1 37 -1 15 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 35 -1 76 -1 78 -1 51 -1 37 -1 35 21 -1 -1 -1 17 -1 64 -1 -1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1-1 -1 32 -1 -1-1 -1 0 -1 0 -1 -1 -1 -1 -1 35 -1 76 -1 78 -1 51 -1 37 -1 35 -1 -1 21 -1 -1 -1 17 -1 64 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 -1 0 -10 -1 -1 -1 -1 -1 9 -1 65 -1 44 -1 9 54 -1 56 -1 -1 73 -1 34 -1 42 -1 -1 -1 -1-1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46 -1 39 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 9-1 65 -1 44 -1 9 -1 -1 54 -1 56 73 -1 34 -1 42 -1 -1 -1 -1 -1 -1 -1 -1 35 -1-1 -1 -1 -1 -1 46 -1 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7 -1 80 68 -1 -1 26 -1 -1 80 -1 -1 55 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -172 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -1 80 -1 -1 68 26-1 -1 -1 80 55 -1 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -1 -1 72 -1 -1 -1 -1-1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 26 -1 75 33 -1 -1 21 -1 69 -1 59 -1 3 38 -1 -1-1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 36 -1 26 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1-1 -1 -1 0 -1 26 -1 75 -1 -1 33 21 -1 69 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 -1 -1 36 -1 26 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1-1 -10].

[0032] Generally, the parity - check matrix representation of a code determines equations for whether an error has occurred during transmission. More formally, for all valid codewords (i.e., bits produced error - free by the encoder), the following equation can be true:

[0033] Hc = 0................(Equation 1)

[0034] In Equation 1, "H" is the parity - check matrix, "c" is the codeword vector, and "0" is the all - zero vector. The parity - check matrix H is a way of describing the code.

[0035] The generator matrix G of the code satisfies the following equation:

[0036] sG = c................(Equation 2)

[0037] In Equation 2, "s" is the information - bit vector, "G" is the generator matrix and "c" is the codeword corresponding to "s". In some embodiments, a system (a communication system 108 including Figure 1 the decoder 160 therein) can use Equation 2 to decode the codeword c to obtain the decoded data s.

[0038] The parity - check and generator matrices of a code are related according to the above matrix equations. Generally, if the parity - check matrix is low - density, then the corresponding generator matrix will be high - density, and vice versa. Thus, LCPC codes are characterized by a low - density parity - check matrix and a high - density generator matrix. The density of a matrix is related to the number of operations that must be performed to implement one of the above equations. Although it was recognized in 1995 that LDPC codes can be used to transmit data with very few errors (i.e., having an error rate as good as or better than turbo codes), one disadvantage of LDPC codes is that their generator matrices are high - density and make the encoding operations intensive, making the codes unsuitable for many applications.

[0039] In some embodiments, the parity - check matrix can have a quasi - cyclic structure, such as the parity - check matrix for a QC - LDPC code (n = 3888, k = 2916, R = 3 / 4). For example, given a lifting factor z, the parity - check matrix can have multiple sub - matrices such that each sub - matrix is a cyclic - shifted version of the identity matrix of size (z×z), where z = 162. The parity - check matrix can be represented in two equivalent forms: (1) the parity - check matrix H and (2) the block matrix or exponent matrix P = E(H).

[0040] In some embodiments, the parity check matrix H can be a binary matrix of size m×n, where each of m and n is an integer. The elements of the parity check matrix are binary values. Given the block length n and the code rate R, the LDPC code (or QC-LDPC code) LDPC(n,R) satisfies the following equations:

[0041] k = nR................(Equation 3)

[0042] m = n(1 - R)................(Equation 4)

[0043] In some embodiments, a block matrix or an exponent matrix (QC-LDPC exponent matrix) can be obtained. Given the lifting coefficient z, the exponent matrix P = E(H) can have a size of m / z×n / z. If n = 24z (e.g., n = 3888, z = 162), then the size of P = E(H) is 24(1 - R)×24(= n(1 - R) / z×n / z). The elements of the exponent matrix can be integer values corresponding to the cyclic shift values of the identity matrix of size z×z. The parity check matrix H can be a sparse binary matrix that can be derived from the exponent matrix P = E(H). The generator matrix G can have a size of n×k in binary form (e.g., the elements of the generator matrix G are binary values). The exponent matrix P = E(H) can have a structure that includes multiple sub-matrices (e.g., A, B, C, D, E, T).

[0044] In some embodiments, the binary QC-LDPC code LDPC(n,R) can be characterized by the null space of an n(1 - R)×n parity check matrix H. The parity check matrix H can be a binary sparse matrix that includes a set of circulant matrices of size z×z. The parity check matrix H of the QC-LDPC code can be equivalently represented by the exponent matrix P = E(H). This representation can help to illustrate the graphical structure of the underlying code along with the shift coefficients as a base graph.

[0045] In some embodiments, the parity check matrix H can be generated from the exponent matrix P = E(H). The exponent matrix P = E(H) can include shift values d (as elements) in the range 0 <= d < z and d = -1. For example, if z = 7, then the shift values d can include -1, 0, 1, 2, 3, 4, 5, 6. The shift value d = 0 can correspond to (or map to) the identity matrix of size z×z, denoted by I(z). The shift value d = -1 can correspond to (or map to) the zero matrix of size z×z (all elements are zero), denoted by 0*I(z). Any other integer value d in [1,z - 1] can correspond to (or map to) a matrix that is cyclically shifted right from I(z). The parity check matrix H can be obtained from the exponent matrix P = E(H) by expanding the exponent matrix P such that each element (as the shift value d) of the exponent matrix P is replaced by the matrix corresponding to the shift value.

[0046] In some embodiments, the exponent matrix P = E(H) may include a plurality of elements P1,1, P1,2, P1,3, ..., P2,1, P2,2, P2,3, …, …, P1,1, P1,2, P1,3, …, which corresponds to values, where and satisfy the following equations:

[0047]

[0048] The exponent matrix (or permutation matrix) P = E(H) can be represented as follows:

[0049]

[0050] The corresponding parity check matrix H can be obtained by replacing each element of the matrix (as the shift value d) with the matrix C(d) corresponding to the shift value as follows:

[0051]

[0052] For example, the matrix C(1) can be represented as follows:

[0053]

[0054] In some embodiments, the encoder may use a generator matrix (e.g., using Equation 2) to generate a codeword. In some embodiments, the encoder may use a parity check matrix (instead of a generator matrix) to generate a codeword from an information bit vector. After obtaining the parity check matrix H, the parity check matrix H may have submatrices A, B, C, D, T, E. The upper region O of the submatrix T may correspond to the region where the matrix contains all 0s, and the other regions may represent positions where 1s may be contained.

[0055] In some embodiments, the codeword c can be obtained by the following expression:

[0056] c = [s p1 p2]............(Equation 10)

[0057] where "s" is the vector of information bits to be encoded, "p1" is the vector of the first g parity check bits, and "p2" is the vector of the remaining m to g parity check bits.

[0058] The vectors p1 and p2 can be obtained by the following equations:

[0059] Φ = -ET -1 B + D............(Equation 11);

[0060] p1 T = -Φ -1 (-ET -1 A + C)s T ............(Equation 12); and

[0061] p2 T = -T -1 (As T + Bp1 T )............(Equation 13).

[0062] Although the various embodiments disclosed herein are described for encoding data for wireless communication (e.g., a wireless local area network (WLAN) conforming to any IEEE 802.11 standard), the principles disclosed herein can be applied to other types of communication (e.g., wired communication) or any process for performing encoding on LDPC codes.

[0063] In some embodiments, the system and / or method may use Khatri-Rao lifting (e.g., using the Khatri-Rao product) to generate an LDPC code with a 3 / 4 code rate. For example, the system may use a base LDPC code (as a mother code) to recursively construct an LDPC code with a block length that is twice the block length of the base LDPC code. Similar to QC-LDPC codes, the mother code may be defined by a parity check matrix H or an exponent matrix P = E(H). Each element in P may be an integer value corresponding to a cyclic shift value of an identity matrix of size z×z.

[0064] In some embodiments, the system may determine (e.g., calculate, operate, obtain) a binary matrix Γ that has the same size (or dimension) as P = E(H). The binary matrix Γ may internally contain sub-matrices that are powers of permutation matrices (e.g., permutation matrices of order 2). The non-zero values (1) of the matrix Γ may be randomized such that the rank of the binary matrix remains full rank while the binary matrix conforms to good LDPC code performance (e.g., achieves a low packet error rate). The system may perform a computer search (e.g., search using one or more processors) to identify the best Γ that can produce the minimum packet error performance (e.g., packet error rate (PER)). For example, for a Wi-Fi code with a code rate R, the matrix Γ may maintain a full rank equal to 24 / (1 - R). For example, for an R = 3 / 4 code rate, the binary matrix Γ may have a dimension of 6×24 (6 rows, 24 columns) and have a full rank of 6 (= 24 / (1 - 3 / 4)). The rank of a matrix refers to the maximum number of linearly independent columns of the matrix or the dimension of the vector space spanned by the columns of the matrix.

[0065] In some embodiments, LDPC codes generated (eg, constructed, created) using the Katri-Rao lifting scheme may be used to design a Wi-Fi LDPC code with block length = 3888 bits from an existing LDPC code with block length = 1944 bits.

[0066] The Cattery-Rao product is an extension of the block-wise Kronecker product operation when the matrices involved are appropriately partitioned. The Cattery-Rao product can be defined as follows. Consider two matrices A and B of order (dimension or size) u×v and p×q, respectively. In partitioned form, A = (a i,j ) and B=(b k,l ). In addition, let A=(A i,j ) with order u i ×v j A i,j Divide into (i, j)th sub-matrix blocks and make B = (B i,j ) with order p k ×q l B i,j is divided into the (k,1)th sub-matrix block, where ∑ i u i =u,∑ j v j =v,∑ k p k =p,∑ l q l =q. The Cattell-Rao product operation of two matrices A and B can be defined as follows:

[0067]

[0068] in is the Catterelli-Rao product operation, is of order u i p i ×v j q j The Kronecker product and total output With order ∑ i u i p i ×∑ j v j q j When the matrix involved can be well partitioned, the block-wise Kronecker product is extended. An example of computing the Katli-Rao product is shown below.

[0069]

[0070] Then, when u i =1,v i =1,1≤i≤2,1≤j≤4 and pk = q l = 2, when 1 ≤ k ≤ 2 and 1 ≤ l ≤ 4, the Khatri - Rao product of A and B is given by the following

[0071]

[0072] In some embodiments, the system can perform (e.g., compute, operate on) Khatri - Rao lifting as follows. Let P ≡ E(H) be the exponent matrix corresponding to the parity - check matrix H of a QC - LDPC code. The exponent matrix can contain integer values between - 1, 0, …, z - 1, where z is a design parameter of the code. For a block length of 1944, the system can use z = 81 for Wi - Fi error - correction codes. By cyclically shifting the components of the identity matrix the parity - check matrix H can be obtained from the P matrix. The system can use Equation 15 below to determine (e.g., compute, operate on, obtain) a new code matrix

[0073]

[0074] where is the Khatri - Rao product operation, Γ is a binary matrix, is a matrix of all - ones whose order (dimension or size) is the same as that of the Γ matrix (e.g., u×v), and is called a swap matrix of order 2. ⊙ is an operation involving matrix exponentiation defined as follows:

[0075]

[0076] where B has dimension (u×v).

[0077] In some embodiments, the system can generate (e.g., compute, operate on, obtain) a (new) parity - check code by computing the Khatri - Rao product (using Equation 16) of the parity - check matrix (of size m×n) of the base code and a binary (random) matrix Γ. In some embodiments, the system can determine the binary matrix Γ by iteratively changing the elements of the matrix and finding one or more optimal matrices based on the number of shortest loops and / or block - error performance (see Figure 10 ).

[0078] In some embodiments, as with QC-LDPC codes, the system may define (e.g., compute, operate on, obtain, generate) a base code as a parity-check matrix H or an exponent matrix E(H). The system may compute (e.g., generate, operate on, obtain, determine) a binary matrix Γ that has the same size as E(H). In some embodiments, if H is chosen as the representation of the parity-check matrix, then matrix Γ may have the same size as H. Matrix Γ may internally contain submatrices that are powers of a permutation matrix J(2). The non-zero values (e.g., value “1”) of the binary matrix Γ may be randomized such that the resulting matrix conforms to good LDPC code performance (e.g., block error performance). For example, for a Wi-Fi error-correction code with an R code rate, the system may randomize the non-zero values of the binary matrix Γ (which has dimensions (u×v)) such that matrix Γ may maintain a full rank equal to min(u,v) = 24 / (1 - R). An example of the binary matrix Γ is shown in FIG. 7, but the present disclosure is not limited thereto and any suitable binary matrix Γ may be used to generate a QC-LDPC code. Examples of the exponent matrix E(H) and the parity-check matrix H are shown in Figure 8A and Figure 8B respectively, but the present disclosure is not limited thereto (e.g., not limited to Wi-Fi error-correction codes) and the techniques according to some embodiments may be applied to any general parity-check matrix or its equivalent cyclic representation. In some embodiments, the system may verify the binary Γ matrix from a given parity-check matrix and a base matrix. For example, the system may verify the binary Γ matrix based on the performance of the given parity-check matrix and the base matrix. In some embodiments, the binary Γ matrix may be any binary matrix Γ that is full rank. A matrix A is full rank if the rank of the matrix (i.e., matrix A) is the highest possible for a matrix of the same size as matrix A.

[0079] Embodiments in the present disclosure have at least the following advantages and benefits.

[0080] First, embodiments in the present disclosure may provide useful techniques for providing significant gains in all modulation schemes. For example, the block length of a QC-LDPC code according to some embodiments (e.g., 3888 bits) is at least twice the block length of the longest code supported by the 802.11n to 802.11be standards (e.g., 1994 bits). This QC-LDPC code may provide a gain of about 2 dB in a 2×2 MIMO (multiple-input multiple-output) channel and the gain is consistent in all modulation schemes with or without beamforming.

[0081] Second, embodiments in the present disclosure may provide useful techniques for providing significant gains (e.g., a gain of 0.5 dB to 1.2 dB compared to the SNR (signal-to-noise ratio) of existing codes) in all modulation schemes. For example, the block length of the QC-LDPC code according to some embodiments (e.g., 3888 bits) is at least twice the block length of the longest code supported by the 802.11n to 802.11be standards (e.g., 1994 bits). This QC-LDPC code can provide a gain of approximately 2 dB in a 2×2 MIMO channel and the gain is consistent across all modulation schemes with or without beamforming.

[0082] Third, the codes generated using the systems and / or methods according to embodiments in the present disclosure can facilitate parallel decoding and reusing several blocks of the mother code.

[0083] Referring Figure 1 , FIG. depicts an exemplary communication environment 100 including communication systems (communication devices) 105, 108 according to one or more embodiments. In one embodiment, communication system 105 includes baseband circuitry 110 and transmitter circuitry 120, and communication system 108 includes baseband circuitry 150 and receiver circuitry 140. On the one hand, communication system 105 is regarded as a transmitter communication system, and communication system 108 is regarded as a receiver communication system. These components operate together to exchange data (e.g., messages or frames) over a wireless medium. In one or more embodiments, these components are embodied as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof. In some embodiments, communication systems 105, 108 include more, fewer, or different components than Figure 1 shown in. For example, each of communication systems 105, 108 includes transceiver circuitry for allowing two-way communication between communication systems 105, 108 or with other communication systems. In some embodiments, each of communication systems 105, 108 may have a configuration similar to the configuration of computing system 2000 shown in Figure 2 .

[0084] The baseband circuitry 110 of the communication system 105 is circuitry that generates baseband data 115 for transmission. The baseband data 115 contains information data (such as signals) at baseband frequencies for transmission. In one method, the baseband circuitry 110 includes an encoder 130 that encodes data and generates or outputs parity bits. In one aspect, the baseband circuitry 110 (or the encoder 130) obtains a generator matrix or a parity-check matrix, or uses a previously generated generator matrix or a previously generated parity-check matrix, and encodes the information data by applying the information data to the generator matrix or the parity-check matrix to obtain a codeword. In some embodiments, the baseband circuitry 110 stores one or more generator matrices or one or more parity-check matrices that conform to any IEEE 802.11 standard for WLAN communication. The baseband circuitry 110 retrieves the stored generator matrix or the stored parity-check matrix in response to detecting information data to be transmitted or in response to receiving an instruction to encode the information data. In one method, the baseband circuitry 110 generates parity bits based on a portion of the generator matrix or using the parity-check matrix, and appends the parity bits to the information bits to form a codeword. The baseband circuitry 110 generates baseband data 115 that contains the codeword for the communication system 108 and provides the baseband data 115 to the transmitter circuitry 120.

[0085] The transmitter circuitry 120 of the communication system 105 includes or corresponds to circuitry that receives baseband data 115 from the baseband circuitry 110 and transmits a wireless signal 125 based on the baseband data 115. In one configuration, the transmitter circuitry 120 is coupled between the baseband circuitry 110 and an antenna (not shown). In this configuration, the transmitter circuitry 120 upconverts the baseband data 115 from the baseband circuitry 110 onto a carrier signal to generate a wireless signal 125 at an RF frequency (such as 10 MHz to 60 GHz) and transmits the wireless signal 125 through the antenna.

[0086] The receiver circuitry 140 of the communication system 108 is circuitry that receives the wireless signal 125 from the communication system 105 and obtains baseband data 145 from the received wireless signal 125. In one configuration, the receiver circuitry 140 is coupled between the baseband circuitry 150 and an antenna (not shown). In this configuration, the receiver circuitry 140 receives the wireless signal 125 through the antenna and downconverts the wireless signal 125 at an RF frequency based on the carrier signal to obtain baseband data 145 from the wireless signal 125. The receiver circuitry 140 then provides the baseband data 145 to the baseband circuitry 150.

[0087] The baseband circuitry 150 of the communication system 108 includes or corresponds to circuitry that receives baseband data 145 from the receiver circuitry 140 and obtains information data from the received baseband data 145. In one embodiment, the baseband circuitry 150 includes a decoder 160 that extracts information and parity bits from the baseband data 145. The decoder 160 decodes the baseband data 145 to obtain the information data generated by the baseband circuitry 110 of the communication system 105.

[0088] In some embodiments, each of the baseband circuitry 110 (including the encoder 130), the transmitter circuitry 120, the receiver circuitry 140, and the baseband circuitry 150 (including the decoder 160) may be one or more processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any combination thereof.

[0089] Figure 2 is a schematic block diagram of an operating system according to an embodiment. The illustrated exemplary operating system 2000 includes one or more processors 2010 that communicate directly or indirectly via a communication system 2040 (such as a bus) with a memory 2060, at least one network interface controller 2030 having a network interface port for connecting to a network (not shown), and other components (such as input / output (“I / O”) components 2050). Generally, the processor 2010 will execute instructions (or computer programs) received from the memory. The illustrated processor 2010 incorporates or is connected to a cache 2020. In some examples, instructions are read from the memory 2060 into the cache 2020 and executed by the processor 2010 from the cache 2020. The operating system 2000 does not necessarily contain Figure 2 all of these components shown in Figure 2 and may contain

[0090] More specifically, the processor 2010 can be any logic circuitry that processes instructions (such as instructions fetched from the memory 2060 or the cache 2020). In many implementations, the processor 2010 is a microprocessor unit or a dedicated processor. The computing device 2050 can be based on any processor or group of processors capable of operating as described herein. The processor 2010 can be a single-core or multi-core processor. The processor 2010 can be multiple different processors.

[0091] The memory 2060 can be any device suitable for storing computer-readable data. The memory 2060 can be a device with fixed storage or a device for reading removable storage media. Examples include all forms of volatile memory (e.g., RAM), non-volatile memory, media and memory devices, semiconductor memory devices (e.g., EPROM, EEPROM, SDRAM, and flash memory devices), magnetic disks, magneto-optical disks, and optical disks (e.g., CD ROM, DVD-ROM, or optical disk). The computing system 2000 can have any number of memory devices 2060.

[0092] The cache 2020 is generally in the form of computer memory placed closely adjacent to the processor 2010 to achieve fast read times. In some embodiments, the cache 2020 is part of the processor 2010 or on the same chip as the processor. In some embodiments, there are multiple levels of cache 2020, such as L2 and L3 cache layers.

[0093] The network interface controller 2030 manages data exchange via a network interface (sometimes referred to as a network interface port). The network interface controller 2030 handles the physical and data link layers of the OSI model for network communication. In some embodiments, some tasks of the network interface controller are handled by one or more of the processors 2010. In some embodiments, the network interface controller 2030 is part of the processor 2010. In some embodiments, the computing system 2000 has multiple network interfaces controlled by a single controller 2030. In some embodiments, the computing system 2000 has multiple network interface controllers 2030. In some embodiments, each network interface is a connection point for a physical network link (e.g., a cat-5 Ethernet link). In some embodiments, the network interface controller 2030 supports wireless network connections and the interface port is wireless (e.g., radio) receiver or transmitter (e.g., for IEEE 802.11 protocol, near field communication "NFC", Bluetooth, ANT, or any other wireless protocol). In some embodiments, the network interface controller 2030 implements one or more network protocols, such as Ethernet. Generally, the computing device 2050 exchanges data with other computing devices via a network interface over a physical or wireless link. The network interface can be directly linked to another device or linked to another device via an intermediate device (e.g., a network device such as a hub, bridge, switch, or router) of a data network that connects the computing device 2000 to, for example, the Internet.

[0094] The computing system 2000 may include one or more input or output ("I / O") devices or provide an interface for one or more input or output ("I / O") devices. Input devices include (but are not limited to) keyboards, microphones, touchscreens, foot pedals, sensors, MIDI devices, and pointing devices such as mice or trackballs. Output devices include (but are not limited to) video displays, speakers, refreshable braille terminals, lights, MIDI devices, and 2D or 3D printers.

[0095] Other components may include an I / O interface, an external serial device port, and any additional coprocessors. For example, the computing system 2000 may include an interface (such as a Universal Serial Bus (USB) interface) for connecting input devices, output devices, or additional memory devices (such as a portable flash drive or an external media drive). In some embodiments, the computing device 2000 includes additional devices such as a coprocessor. For example, a math coprocessor may assist the processor 2010 with high-precision or complex calculations.

[0096] The component 2090 may be configured to connect to external media, the display 2070, the input device 2080, or any other component in the computing system 2000 or a combination thereof. The display 2070 may be a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a flat panel display, a solid state display, a cathode ray tube (CRT) display, a projector, a printer, or any other currently known or later developed display device for outputting determined information. The display 2070 may act as an interface for a user to view the functions of the processor 2010 or, specifically, as an interface for software stored in the memory 2060.

[0097] The input device 2080 may be configured to allow a user to interact with any of the components of the computing system 2000. The input device 2080 may be a plurality of boards, a keyboard, a cursor control device such as a mouse, or a joystick. Additionally, the input device 2080 may be a remote control, a touchscreen display (which may be a combination of the display 2070 and the input device 2080), or any other device operable to interact with the computing system 2000 (such as any device operable to act as an interface between the user and the computing system 2000).

[0098] Figure 3 is a diagram depicting an exemplary exponent matrix (QC-LDPC exponent matrix) 300 according to one or more embodiments. Given the lifting coefficient z, the exponent matrix 300 may have a size of m / z × n / z. If n = 24z (e.g., n = 3888, z = 162), then the size of P = E(H) is 24(1 - R) × 24 (= n(1 - R) / z × n / z). The elements of the exponent matrix may be integer values corresponding to cyclic shift values of an identity matrix of size z × z. The parity check matrix H (seeFigure 5 ) can be a sparse binary matrix derivable from the exponent matrix P = E(H). The generator matrix G can have a size of n×k in binary form (e.g., the elements of the generator matrix G are binary values). Refer to Figure 3 , the exponent matrix P = E(H) can have a structure that includes multiple sub-matrices (e.g., A 310, B 312, C 316, D 318, E 320, T 314).

[0099] Figure 4 FIG. 400 depicts exemplary shift identity matrices 409, 410, 411, 412, 413, 414, 415, 416 for generating a parity check matrix according to one or more embodiments. The parity check matrix H can be generated from the exponent matrix P = E(H) (e.g., exponent matrix 300) or can be identified using a codebook. As shown in Equation 7, the exponent matrix P = E(H) can include shift values d (as elements) in the range 0 <= d < z and d = -1. For example, see the equation, if z = 7, then the shift values d can include -1, 0, 1, 2, 3, 4, 5, 6 (see Figure 4 ). The shift value d = 0 can correspond to (or map to) an identity matrix of size z×z represented by I(z) (e.g., matrix 410). The shift value d = -1 can correspond to (or map to) a zero matrix of size z×z represented by 0*I(z) (all elements are zero) (e.g., matrix 409). Any other integer value d in [1, z - 1] can correspond to (or map to) a matrix that is circularly shifted right from I(z) (e.g., matrices 411, 412, 413, 414, 415, 416). As shown in Equation 8, the parity check matrix H can be obtained from the exponent matrix P = E(H) by expanding the exponent matrix P such that each element (as the shift value d) of the exponent matrix P is replaced by a matrix corresponding to the shift value.

[0100] Figure 5 FIG. depicts an exemplary parity check matrix 500 according to one or more embodiments. In some embodiments, an encoder (e.g., encoder 130) can use a generator matrix (e.g., using Equation 2) to generate a codeword. In some embodiments, an encoder (e.g., encoder 130) can use a parity check matrix (instead of a generator matrix) to generate a codeword from an information bit vector. After obtaining the parity check matrix H (e.g., using a codebook), the parity check matrix H (e.g., parity check matrix 500) can have sub-matrices A 510, B 512, C 516, D 518, T 514, E 520. The upper region O 515 of the sub-matrix T 514 (e.g., Figure 5 the white region in ) can correspond to the region where the matrix contains all 0s, and the other regions (e.g., Figure 5The gray area (in ) can represent positions that may contain 1. The size of the parity-check matrix 500 can be m×n, where the size of the submatrix D 518 is g×g and the size of the submatrix T is (m - g)×(m - g). In some embodiments, given the information-bit vector s to be encoded, the encoder can use Equation 10, Equation 11, Equation 12, and Equation 13 to obtain the codeword c.

[0101] In some embodiments, the codebook of an R = 3 / 4 LDPC code with a block length of 3888 bits can provide high-performance error correction and / or provide a gain of up to 1.2 dB compared to existing LDPC codes specified in the Wi-Fi standard. In some embodiments, the set of LDPC codes with a block length of 3888 bits (2×1944) supports all code rates in the Wi-Fi standard (e.g., 802.11be). The code (e.g., an R = 3 / 4 LDPC code with a block length of 3888 bits) can be directly used in existing modulations in IEEE 802.11be for 64-QAM and may be combined with more combinations of QAM sizes in IEEE 802.11bn.

[0102] In some embodiments, the codebook of an R = 3 / 4 LDPC code with a block length of 3888 bits can be directly used in existing modulations, just like existing modulation schemes such as binary phase shift keying (BPSK), quadrature phase shift keying (BPSK), 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, as seen in standards such as IEEE 802.11be or IEEE 802.11bn. Additionally, the codebook of an R = 3 / 4 LDPC code with a block length of 3888 bits has the potential to be employed in combination with one or more combinations of QAM sizes (whether similar or different), across orthogonal frequency division multiple access (OFDMA) resource units (RUs), distributed RUs (DRUs), punctured RUs (MRUs), within a single stream, and / or across multiple spatial streams, as provided in a multiple-input multiple-output (MIMO) configuration.

[0103] A set of LDPC codes with a block length of 3888 bits (2×1944) can achieve a significant performance improvement with ultra-high reliability (UHR) in various communication scenarios while maintaining manageable complexity. A performance comparison is made between these codes and the LDPC codes specified in the IEEE 802.11be standard as well as recently proposed codes with a block length of 4×1944. The results of the performance comparison show significant gains across the board (e.g., channel, PHY bandwidth, MIMO, modulation and coding scheme (MCS), transmit beamforming). For example, depending on the channel conditions, the LDPC codes with a block length of 3888 bits according to some embodiments can provide a 0.5 to 1.0 dB gain compared to the current 802.11 LDPC codes. Depending on the channel conditions, the LDPC codes with a block length of 4×1944 bits can provide an additional 0.0 to 0.5 dB gain.

[0104] The longest LDPC code specified in the 802.11be standard has a block length = 1944 bits. In terms of performance, the LDPC codes specified in the 802.11be standard differ from the best random codes by approximately 2.7 dB (e.g., bit-interleaved coded modulation (BICM)-additive white Gaussian noise (AWGN)-QAM (quadrature amplitude modulation) R = 3 / 4 limit). According to the finite-length scaling law, longer block length random codes (e.g., the Shannon limit addresses the asymptotic case when the block length grows infinitely large) can lead to enhanced coding gain. Sub-optimal deterministic codes can exhibit a scaling gain significantly larger than that of the best random codes. For example, in AWGN, the doubling effect is known to be true.

[0105] In some embodiments, there are LDPC codes with a block length = 2×1944 = 3888 bits (which is twice the size of the maximum supported block length in the current 802.11be standard). In some embodiments, the LDPC codes with a block length of 3888 bits can support all existing code rates (e.g., R = 1 / 2, 2 / 3, 3 / 4, and 5 / 6). In some embodiments, in addition to the matrix size expansion, the LDPC codes with a block length of 3888 bits can keep the structure of the 802.11be codes (specifically, QC-LDPC) unchanged. This adaptation can facilitate the reuse of existing embodiments and allow for simultaneous encoding and decoding functionality.

[0106] Figure 6 is a diagram depicting an exemplary exponent matrix (QC-LDPC exponent matrix) 600 according to one or more embodiments. Given the lifting factor z, the exponent matrix 600 can have a size of m / z × n / z. If n = 48z (e.g., n = 3888, z = 81), then for n = 3888 The size of the matrix is 48(1 - R)×48(= n(1 - R) / z×n / z). The elements of the exponent matrix can be integer values corresponding to the cyclic shift values of the identity matrix of size z×z. The parity check matrix H can be a sparse binary matrix derivable from the exponent matrix The generator matrix G can have a size of n×k in binary form (e.g., the elements of the generator matrix G are binary values). Refer to Figure 6 , the exponent matrix can have a structure that includes multiple sub - matrices (e.g 610,[[]] 612,[[]] 616,[[]] 618,[[]] 620,[[]] 614).

[0107] Figures 7A - 7B and Figures 8A - 8D show a new Wi - Fi LDPC code with a block length = 3888 constructed using a Wi - Fi LDPC code with a block length = 1944 as the base matrix (or base / mother code). Figure 7A FIG. 700 depicts an exemplary binary matrix Γ1 of size (6×24) (dimension) according to one or more embodiments. In some embodiments, using Equation 8, a system or method can calculate (obtain, operate on, generate) a base parity check matrix H using a base exponent (or permutation) matrix P = E(H) corresponding to a code block size n = 1994 and a code rate R = 3 / 4. The size (dimension) of the exponent matrix P can be the same as the size (6×24) of the exemplary binary matrix Γ1, and the size (dimension) of the base parity check matrix H can be (6*z, 24*z), where z is a lifting coefficient, e.g., z = 81. Using Figure 7A the binary matrix Γ1 shown in, a system according to some embodiments can determine (e.g., calculate, operate on, obtain) a new parity check matrix Figure 7B FIG. 720 depicts an exemplary binary matrix Γ2 of the same size (dimension) as the binary matrix Γ1 but with elements different from the binary matrix Γ1 according to one or more embodiments.

[0108] Figure 8A FIG. 800 depicts an exemplary new code matrix (e.g., exponent matrix) Figure 7A constructed due to performing Khatri - Rao lifting using the base parity check matrix H and the binary matrix Γ1 shown in The exemplary new exponent matrix It may have a size (dimension) of (12×48) and correspond to a code block size n = 3888 (which is twice the code block size of the basic matrix P) and a code rate R = 3 / 4 (which is the same as the code rate of the basic matrix P). Figure 8B FIG. 820 depicts an exemplary exponent matrix constructed by performing Khatri-Rao lifting using a basic parity check matrix H and a binary matrix Γ2.

[0109] Figure 8C depicts, according to one or more embodiments, a corresponding Figure 8A exponent matrix shown in and Figure 7A a novel parity check matrix of the binary matrix Γ1 shown in FIG. 860. Corresponding to the Figure 8A exponent matrix shown in and Figure 7A a novel parity check matrix of the binary matrix Γ1 shown in It may have a size (dimension) of (12*z, 48*z) (where z is a lifting coefficient, e.g., z = 81) and correspond to a code block size n = 3888 (which is twice the code block size of the basic parity check matrix H) and a code rate R = 3 / 4 (which is the same as the code rate of the basic parity check matrix H). The novel parity check matrix may be a sparse matrix. Referring to Figure 8C , each black dot / line may represent a value of 1 and each blank space may represent a value of 0. Figure 8D depicts, according to one or more embodiments, a corresponding Figure 8B exponent matrix shown in and Figure 7B a novel parity check matrix of the binary matrix Γ2 shown in FIG. 880.

[0110] Figure 9 FIG. 900 depicts an exemplary implementation (source code of a programming language) of generating a novel parity check matrix using a binary matrix Γ according to one or more embodiments. Figure 9 The source code in Figure 9 contains lines 1 to 12. For example, the source code shown in (e.g., variable "EH3888"). In this manner, a system according to some embodiments may use a Wi-Fi LDPC code with a block length = 1944 as a base code (e.g., variable "EH1944") to generate a new Wi-Fi LDPC code with a block length = 3888 (e.g., variable "EH3888").

[0111] In some embodiments, the system may use multi-level optimization to derive one or more matrices Γ by leveraging graph theory constraints (e.g., the number of shortest loops / cycles in a protograph) and simulations. In some embodiments, the system may calculate the number of shortest loops in the protograph corresponding to a novel parity check matrix based on the Γ matrix and then perform simulations (e.g., block error rate) on the novel parity check matrix to evaluate the performance / quality of the Γ matrix. A "protograph" may refer to a bipartite graph having two disjoint and independent vertex sets representing a matrix (e.g., a parity check matrix) (e.g., a set of left vertices indicated by circles and a set of right vertices indicated by rectangles in protograph 1100 shown in Figure 11A . For example, the system may apply some graph theory constraints to select a better Γ matrix, which may eliminate or reduce short cycles in the protograph or remove problem nodes (e.g., trap sets) that cause iterative decoding performance to get stuck (congested, trapped). In some embodiments, the cycles in the protograph generated using the Γ matrix may be weighted in descending order of the degree of the cycle to evaluate the matrix Γ. In some embodiments, the system may shortlist multiple candidate Γ matrices, perform simulations (e.g., PER simulation or codeword simulation) on the corresponding parity check matrices generated using the multiple candidate Γ matrices, and select (identify, pick, determine) one or more "best" Γ matrices from the shortlisted (candidate) Γ matrices (e.g., best in terms of satisfying graph theory constraints and / or simulation constraints (e.g., above a threshold)).

[0112] Figure 10 is a flowchart showing a process 1000 for determining one or more binary matrices Γ according to one or more embodiments. The system may execute process 1000 to derive (generate, determine, obtain) one or more (best) binary matrices Γ for use in generating a novel parity check matrix (using Katti-Rao lifting) using the derived matrices. In some embodiments, process 1000 is executed by one or more processors of a device (e.g., encoder 130 or processor 2010 of communication system 105 or decoder 160 or processor 2010 of communication system 108). In other embodiments, process 1000 is executed by other entities (e.g., an operating system other than system 105 or system 108). In some embodiments, process 1000 includes more, fewer, or different steps than those shown in Figure 10 .

[0113] In step 1002, one or more processors may initialize a Γ matrix corresponding to a code rate (such as 1 / 2, 2 / 3, 3 / 4, 5 / 6) with any random binary matrix. For example, if z = 5, u = 3, v = 4, then a system (such as communication system 105 or 108) may initialize the Γ matrix with the following matrix (referred to as "Γ1") having a size (dimension) of (3×4):

[0114]

[0115] The system may identify (receive, obtain, calculate) a basic parity-check matrix H1 corresponding to an exponent (or permutation) matrix E(H1) as follows:

[0116]

[0117] Reference Figure 11A and Figure 11B , the H1 matrix may correspond to the protograph 1100 and different graphical representations 1110 of the protograph 1100. Since the H1 matrix can be obtained by cyclically shifting the values of a 5×5 identity matrix by E(H1), the protograph 1100 (and the graph 1110) may include 3*5 check nodes 1 to 15 (indicated by rectangles) and 4*5 variable nodes 16 to 35 (indicated by circles). As shown in Figure 11B , the H1 matrix (and the corresponding graph 1110) may contain 20 shortest cycles with length = 8 (one of the shortest cycles is indicated by the reference sign 1111).

[0118] In step 1004, the system may perform (apply, operate, calculate) Katti-Rao lifting on the basic parity-check matrix H1 using the Γ1 matrix initialized in step 1002 to generate (obtain, calculate, operate) a new parity-check matrix H2 as a new QC-LDPC code. The exponent (or permutation) matrix E(H2) may be generated as follows:

[0119]

[0120] Reference Figure 11C and Figure 11D , the H2 matrix may correspond to the protograph 1120 and different graphical representations 1130 of the protograph 1100. Since the H2 matrix can be obtained by cyclically shifting the values of a 5×5 identity matrix by E(H2), the protograph 1120 (and the graph 1130) may include 6*5 check nodes 1 to 30 (indicated by rectangles) and 8*5 variable nodes 31 to 70 (indicated by circles). As shown in Figure 11DAs shown, the H2 matrix (and corresponding graph 1130) may contain 20 shortest cycles with length = 8 (one of the shortest cycles is indicated by reference numeral 1131). That is, when using the Γ1 matrix (see Equation 17), the H2 matrix may contain the same number (20) of short cycles with the same length (8) as the H1 matrix.

[0121] In step 1006, the system may identify and enumerate all the shortest loops corresponding to the new graph of the H2 matrix (e.g., Figure 11D graph 1130 in ). For example, the system may identify 20 shortest cycles with length = 8 from graph 1130 and enumerate each cycle (e.g., cycle 1131 may be enumerated as

[0122] In step 1008, the system may determine (verify) whether the size (length) of the shortest cycle (loop) in the graph corresponding to the H2 matrix is < 6. In step 1010, in response to determining that the size (length) of the shortest cycle (loop) is < the threshold (e.g., 6), the system may discard the Γ matrix. In step 1012, in response to determining that the size (length) of the shortest cycle (loop) is ≥ the threshold (e.g., 6), the system may add the current Γ matrix (e.g., Γ1) to the shortlist of candidate gamma matrices.

[0123] In step 1014, the system may change one element in the current Γ matrix (e.g., Γ1). For example, in response to determining that the length of the shortest cycle (8) ≥ 6, the system may change one element in the Γ1 matrix to obtain a new Γ matrix (referred to as "Γ2") as follows:

[0124]

[0125] Then, the system may proceed to step 1004 and perform (apply, operate, calculate) the Katti-Rao lift on the base parity-check matrix H1 using the Γ2 matrix updated / changed in step 1014 to generate (obtain, calculate, operate) a new parity-check matrix H2' as a new QC-LDPC code. The exponent (or permutation) matrix E(H2') may be generated as follows:

[0126]

[0127] Referring to Figure 11E and Figure 11F , the H2' matrix may correspond to the original protograph 1140 and different graphical representations 1150 of the original protograph 1140. Since the H2' matrix may be obtained by cyclically shifting the values of the 5×5 identity matrix by E(H2'), the protograph 1140 (and graph 1150) may contain 6*5 check nodes 1 to 30 (indicated by rectangles) and 8*5 variable nodes 31 to 70 (indicated by circles). AsFigure 11F As shown, the H2' matrix (and corresponding figure 1130) may contain 10 shortest cycles with length = 8 (one of the shortest cycles is indicated by reference numeral 1151). That is, when using the Γ2 matrix (see Equation 20), the H2' matrix may contain a smaller number of short cycles (10) than the number of short cycles (20) of the H2 matrix generated when using the Γ1 matrix (see Equation 17).

[0128] In step 1006, the system may identify and enumerate all shortest loops corresponding to the new figure (e.g., figure 1150 in Figure 11F ) of the H2' matrix. For example, the system may identify 10 shortest cycles with length = 8 from figure 1150 and enumerate each cycle (e.g., cycle 1151 may be enumerated as ). In step 1012, in response to determining that the size (length) of the shortest cycle (loop) ≥ a threshold (e.g., 6), the system may add the current Γ matrix (e.g., Γ2) to the shortlist of candidate gamma matrices.

[0129] In step 1016, the system may perform one or more simulations (e.g., PER simulation or codeword simulation) on the candidate Γ matrices in the shortlist. In some embodiments, the system may determine that the number of candidate Γ matrices in the shortlist reaches a threshold (e.g., 10) and perform the simulation. In some embodiments, the system may determine that the number of iterations (e.g., iterating through steps 1004 to 1014) reaches a threshold (e.g., 100) and perform the simulation.

[0130] In step 1018, the system may select (determine, pick) one or more Γ matrices from the shortlist as the "best" Γ matrices based on the results of the simulation. In some embodiments, the system may select one or more Γ matrices that satisfy the simulation constraints (e.g., the average PER is less than the threshold).

[0131] Figure 12 is a flowchart showing a process 1200 for encoding data using an LDPC code according to an embodiment. In some embodiments, the process 1200 is executed by one or more processors of a device (e.g., communication system 105, encoder 130, or processor 2010). In other embodiments, the process 1200 is executed by other entities. In some embodiments, the process 1200 includes more, fewer, or different steps than those shown in Figure 12 .

[0132] In step 1202, one or more processors may determine a first parity-check matrix (e.g., basic parity-check matrix H) of a first quasi-cyclic low-density parity-check (QC-LDPC) code having a first code block size (e.g., n = 1944) and a code rate of 3 / 4.

[0133] In step 1204, one or more processors may determine a binary matrix (e.g., binary matrix Γ or Γ matrix) having the same size as the exponent matrix E(H) of the first parity check matrix. In some embodiments, when determining the binary matrix, one or more processors may be configured to determine a plurality of sub-matrices of the binary matrix (e.g., using Equation 16), each sub-matrix being a power of a 2nd order permutation matrix (e.g., matrix J(2)). One or more processors may be configured to randomize the non-zero values of the binary matrix such that the binary matrix maintains full rank. For example, for a Wi-Fi code with a code rate R, a matrix Γ of size (u×v) (dimension) may maintain full rank, which is equal to min(u,v)=24 / (1 - R).

[0134] In step 1206, one or more processors may generate a second parity check matrix (e.g., a new parity check matrix ) of a second QC-LDPC code having a second code block size (e.g., n = 3888) and a 3 / 4 code rate based on the first parity check matrix and the binary matrix.

[0135] In some embodiments, each of the first parity check matrix and the second parity check matrix may have an exponent matrix that includes a plurality of integers (e.g., P1,1, P1,2, P1,3, …, P2,1, P2,2, P2,3, …, …, P1,1, P1,2, P1,3, …, as shown in Equation 7), the number of the plurality of integers being equal to the number of elements of the parity check matrix divided by z, where z is an integer representing the lifting coefficient of the QC-LDPC code (e.g., z = 81). See Equation 5 and Equation 6. Each element of the exponent matrix may correspond to a cyclic shift value of the identity matrix. The size of the identity matrix is z×z, and the cyclic shift value d is an integer such that -1 ≤ d < z, where z is an integer representing the lifting coefficient of the QC-LDPC code. The cyclic shift value d may represent a shifted identity matrix obtained by shifting the identity matrix to the right by d (see Figure 4 , when z = 7). The cyclic shift value -1 may represent the zero matrix of the identity matrix (see Figure 4 matrix 412 in).

[0136] In some embodiments, when generating a second parity check matrix based on a first parity check matrix and a binary matrix, one or more processors may be configured to determine a first exponent matrix of the first parity check matrix, determine the Khatri-Rao product of the first exponent matrix and the binary matrix (e.g., using Equation 16), and determine a second exponent matrix of the second parity check matrix based on the result of the Khatri-Rao product (e.g., using Equation 14).

[0137] In some embodiments, when generating a second parity check matrix based on a first parity check matrix and a binary matrix, one or more processors may be configured to generate a shifted identity matrix of the identity matrix (e.g., matrices 410, 411, 412, 413, 414, 415, 416) for each element of the second exponent matrix based on the value of each element of the second exponent matrix (e.g., d = 0, 1, 2, 3, 4, 5, 6). One or more processors may be configured to generate the second parity check matrix such that the second parity check matrix includes the generated shifted identity matrix (see Equation 8) as an element corresponding to each element of the second exponent matrix.

[0138] In step 1208, one or more processors may use the generated second parity check matrix to encode data (e.g., using Equation 10, Equation 11, Equation 12, and Equation 13). In step 1210, one or more processors may transmit the encoded data to another device (e.g., the transmitter circuit system 120 of the communication system 108) via a transmitter of the device (e.g., the communication system 105).

[0139] In one method, a device (e.g., the encoder 130 or the processor 2010 of the communication system 105) may include a transmitter (e.g., the transmitter circuit system 120) and one or more processors (e.g., the processor 2010 or the baseband circuit system 110). One or more processors may be configured to identify a second parity check matrix (e.g., a novel parity check matrix ) corresponding to a first exponent matrix (e.g., ) that includes 576 values of a second QC-LDPC code based on a first parity check matrix (e.g., a basic parity check matrix H) of a first quasi-cyclic low-density parity-check (QC-LDPC) code with a 3 / 4 code rate. The second QC-LDPC code may have a code block size (e.g., n = 3888) that is twice the code block size of the first QC-LDPC code (e.g., n = 1944). One or more processors may be configured to use the second parity check matrix to encode data. The transmitter may be configured to transmit the encoded data to another device (e.g., the decoder 160 or the processor 2010 of the communication system 108).

[0140] In some embodiments, one or more processors may be configured to identify, e.g., from a codebook, a first parity-check matrix of a first QC-LDPC code having a 3 / 4 code rate. One or more processors may be configured to determine a first binary matrix (e.g., a Γ1 matrix) having a dimension (e.g., m / Z × n / Z if the first parity-check matrix has a (m × n) dimension) that is the same as the dimension of the exponent matrix (e.g., E(H)) of the first parity-check matrix. One or more processors may be configured to determine the Khatri-Rao product of the first parity-check matrix and the first binary matrix (e.g., using Equation 15). One or more processors may be configured to determine a second parity-check matrix (e.g., a novel parity-check matrix) based on the result of the Khatri-Rao product. )

[0141] In some embodiments, when determining the first binary matrix, one or more processors may be configured to determine a second binary matrix having the same dimension as the first binary matrix. One or more processors may be configured to determine a first binary matrix that includes at least (1) one or more rows of the second binary matrix or (2) one or more columns of the second binary matrix.

[0142] In some embodiments, when determining the second parity-check matrix, one or more processors may be configured to determine a second exponent matrix having the same dimension as the dimension of the first exponent matrix based on the result of the Khatri-Rao product. One or more processors may be configured to determine the first exponent matrix based on the second exponent matrix. For example, the first exponent matrix may have the same elements as the second exponent matrix except for one or two elements. One or more processors may be configured to determine the second parity-check matrix based on the first exponent matrix (e.g., using Equation 8).

[0143] In some embodiments, the second binary matrix may comprise the following group of values: [0 1 0 0 0 0 1 1 1 0 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 0]. The second exponent matrix may comprise the following group of values: [48 -1 -1 29 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 -1 63 -1 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 -1 32 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 29 -1 -1 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 32 -1 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 49 -1 -1 42 -1 48 11 -1 -1 30 -1 -1 -1 -1 -1 -1 49 -1 -1 17 41 -1 37 -1 -1 15 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 4 -1 49 42 -1 48 -1 -1 11 30 -1 -1 -1 -1 -1 -1 -1 -1 49 17 -1 -1 41 -1 37 15 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 35 -1 76 78 -1 51 -1 37 -1 35 -1 21 -1 -1 -1 -1 17 64 -1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 -1 -1 32 -1 -1 -1-1 0 -1 0 -1 -1 -1 -1 -1 35 -176 -1 -1 78 -1 51 -1 37 -1 35 -1 21 -1 -1 17 -1 -1 64 -1 -1 -1 -1 -1 -1 -1 59-1 7 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 9 -1 -1 65 44 -1 9 -1 -1 54 -1 56 73 -1 -1 34 42 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46-1 -1 39 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 9 65 -1 -1 44 -1 9 54 -1 56 -1 -1 73 34 -1 -1 42 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7 -1 80 -1 68 -1 26 -1 -1 -1 80 55 -1 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -1 80 -1 68 -1 26 -1 -1 -1 80 -1 -1 55 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -126 -1 75 33 -1 21 -1 69 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -162 36 -1 -1 26 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -133 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 62 -1 -1 36 26-1 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0]。

[0144] In some embodiments, when determining the first exponent matrix, one or more processors may be configured to select at least 574 values from the values of the second exponent matrix as the values of the first exponent matrix. One or more processors may be configured to shift one or two values of the first exponent matrix by -1 or +1 from one or more corresponding positive values of the second exponent matrix. One or more corresponding positive values of the second exponent matrix may not be selected as at least 574 values. The first exponent matrix (e.g., permutation matrix ) It can be generated by perturbing one or two values from the second exponential matrix. For example, based on the second exponential matrix, the first matrix can be generated as [47 -1 -1 28 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 -1 32 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 29 -1 -1 28 -139 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 32-1 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 49 -1 -1 42 -1 48 11 -1 -1 30-1 -1 -1 -1 -1 -1 49 -1 -1 17 41 -1 37 -1 -1 15 -1 -1 54 -1 -1 -1 -1 -1 -1 -10 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 49 42 -1 48 -1 -1 11 30 -1 -1 -1 -1 -1 -1-1 -1 49 17 -1 -1 41 -1 37 15 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 35 -1 76 78 -1 51 -1 37 -1 35 -1 21 -1 -1 -1 -1 17 64 -1 -1-1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 -1 -1 32 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -135 -1 76 -1 -1 78 -1 51 -1 37 -1 35 -1 21 -1 -1 17 -1 -1 64 -1 -1 -1 -1 -1 -1-1 59 -1 7 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 9 -1 -1 65 44-1 9 -1 -1 54 -1 56 73 -1 -1 34 42 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1-1 46 -1 -1 39 0 -1 -1 -1 -1-1 0 -1 0 -1 -1 -1 -1 9 65 -1 -1 44 -1 9 54 -156 -1 -1 73 34 -1 -1 42 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46 39 -1-1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7 -1 80 -1 68 -1 26 -1 -1 -180 55 -1 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1-1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -1 80 -1 68 -1 26 -1 -1 -1 80 -1 -1 55 -1 -1-1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 26 -1 75 33 -1 21 -1 69 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1-1 -1 62 36 -1 -1 26 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -1 33 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 62 -1 -136 26 -1 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0], where the first value 47 and the fourth value 28 are shifted from 48 and 29 respectively. One or more processors may be configured to determine the resulting matrix of the shift as the first exponent matrix.

[0145] In some embodiments, the second binary matrix may comprise the following set of values: [0 0 1 1 0 1 1 1 1 1 01 1 1 1 0 0 1 0 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 11 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 11 0 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 01 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0]. The second exponent matrix may comprise the following set of values: [48 -1 29 -1 -128 -1 39 9 -1 -1 61 -1 -1 -1 -1 -1 -1 -1 63 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37-1 32 -1 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 -1 29 28 -1 39 -1 -1 961 -1 -1 -1 -1 -1 -1 -1 63 -1 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 -1 32 22 -1-1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 49 -1 42 48 -1 -1 11 -1 30 -1 -1 -1-1 -1 -1 -1 49 17 -1 41 -1 37 -1 15 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 49 -1 42 -1 -1 48 11 -1 30 -1 -1 -1 -1 -1 -1 -1 49 -1 -1 17 -1 41 -1 37 -1 15 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1-1 -1 -1 35 -1 76 -1 78 -1 51 -1 37 -1 35 21 -1 -1 -1 17 -1 64 -1 -1 -1 -1 -1-1 -1 -1 59 -1 7 -1 -1 -1 -1 -1 32 -1 -1 -1-1 0 -1 0 -1 -1 -1 -1 -1 35 -1 76-1 78 -1 51 -1 37 -1 35 -1 -1 21 -1 -1 -1 17 -1 64 -1 -1 -1 -1 -1 -1 59 -1 7-1 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 9 -1 65 -1 44 -1 954 -1 56 -1 -1 73 -1 34 -1 42 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46-1 39 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 9 -1 65 -1 44 -1 9 -1 -1 54 -1 56 73 -1 34 -1 42 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7 -1 80 68 -1 -1 26 -1 -1 80 -1 -1 55 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0-1 0 -1 3 -1 -1 62 7 -1 80 -1 -1 68 26 -1 -1 -1 80 55 -1 -1 -1 -1 36 -1 -1 26-1 -1 -1 -1 9 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 26 -1 7533 -1 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 36 -126 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -1 33 21 -169 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 -1 -1 36 -1 26 -1 -1-1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0]。

[0146] In some embodiments, when determining the first binary matrix, one or more processors may be configured to permute (1) two or more rows in the second binary matrix or (2) two or more columns in the second binary matrix. For example, the first binary matrix may correspond to a binary matrix in which the first row and the second row of the second binary matrix are permuted. One or more processors may be configured to determine the resulting permuted binary matrix as the first binary matrix. The first binary matrix may be determined such that the first binary matrix maintains full rank.

[0147] In some embodiments, one or more processors may be further configured to use (1) the matrix product of the second binary parity-check matrix and the first exponent matrix (e.g., ) or (2) the matrix product of the first exponent matrix and the second binary parity-check matrix (e.g., ) to generate a second binary parity-check matrix corresponding to (e.g., matrix). For example, matrix may be generated by multiplying the matrix product (right) by the inverse matrix of the first exponent matrix (e.g., ).

[0148] In one method, a device (e.g., decoder 160 or processor 2010 of communication system 108) may include a receiver (e.g., receiver circuitry 140) configured to receive encoded data (e.g., from another device such as communication system 105) and one or more processors (e.g., processor 2010). The one or more processors may be configured to identify a second parity-check matrix (e.g., novel parity-check matrix ) corresponding to a first exponent matrix of 576 values that includes a second QC-LDPC code based on a first parity-check matrix (e.g., base parity-check matrix H) of a first quasi-cyclic low-density parity-check (QC-LDPC) code according to a 3 / 4 code rate (e.g., from a codebook). The second QC-LDPC code may have a code block size (e.g., n = 3888) that is twice the code block size of the first QC-LDPC code (e.g., n = 1944). The one or more processors may be configured to decode the received encoded data using the second binary parity-check matrix (e.g., novel parity-check matrix ). For example, the encoded data (e.g., codeword c) may be decoded using Equations 1 and 10 through 13 to obtain the information bits s.

[0149] In some embodiments, the first exponent matrix may include at least 574 values selected from a second exponent matrix having the same dimensions as the dimensions of the first exponent matrix (e.g., m / Z × n / Z, if the first parity check matrix has (m × n) dimensions). In some embodiments, the second exponent matrix may include the following set of values: [48 -1 -1 29 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 -1 32 -122 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 29 -1 -1 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 63 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 32 -1 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 49 -1 -1 42 -1 48 11 -1 -1 30 -1 -1 -1 -1 -1 -1 49 -1 -1 17 41 -1 37 -1 -1 15 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 4 -1 49 42 -1 48 -1 -1 11 30 -1 -1 -1 -1 -1 -1 -1 -1 49 17 -1 -1 41 -1 37 15 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 35 -1 76 78 -1 51 -1 37 -1 35 -1 21 -1 -1 -1 -1 17 64 -1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 -1 -1 32 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 35 -1 76 -1 -1 78 -1 51 -1 37 -1 35 -1 21 -1 -1 17 -1 -1 64 -1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 9 -1 -1 65 44 -1 9 -1 -1 54 -156 73 -1 -1 34 42 -1 -1-1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 -1 39 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 9 65 -1 -1 44 -1 9 54 -1 56 -1 -1 73 34 -1 -1 42 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7 -1 80 -1 68 -1 26 -1 -1 -1 80 55 -1 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -1 80 -1 68 -1 26 -1 -1 -1 80 -1 -1 55 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 26 -1 75 33 -1 21 -1 69 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 62 36 -1 -1 26 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -1 33 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 62 -1 -1 36 26 -1 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0]。

[0150] The first exponent matrix may include one or two values that are shifted -1 or +1 from one or more corresponding positive values of the second exponent matrix. One or more corresponding positive values of the second exponent matrix may not be selected as at least 382 values. The first exponent matrix (e.g., a permutation matrix ) It can be generated by perturbing one or two values from the second exponential matrix. For example, based on the second exponential matrix, the first matrix can be generated as [47 -1 -1 28 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 -1 32 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -148 29 -1 -1 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 80 -1 -1 -1 -1-1 -1 -1 -1 37 32 -1 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 49 -1 -1 42-1 48 11 -1 -1 30 -1 -1 -1 -1 -1 -1 49 -1 -1 17 41 -1 37 -1 -1 15 -1 -1 54 -1-1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 49 42 -1 48 -1 -1 11 30-1 -1 -1 -1 -1 -1 -1 -1 49 17 -1 -1 41 -1 37 15 -1 -1 -1 -1 54 -1 -1 -1 -1 -1-1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 35 -1 76 78 -1 51 -1 37 -1 35 -1 21 -1 -1 -1 -1 17 64 -1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 -1 -1 32 -1 -1 -1 -1 0 -10 -1 -1 -1 -1 -1 35 -1 76 -1 -1 78 -1 51 -1 37 -1 35 -1 21 -1 -1 17 -1 -1 64-1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1-1 9 -1 -1 65 44 -1 9 -1 -1 54 -1 56 73 -1 -1 34 42 -1 -1 -1 -1 -1 -1 -1 -135 -1 -1 -1 -1 -1 -1 46 -1 -1 39 0 -1 -1 -1 -1-1 0 -1 0 -1 -1 -1 -1 9 65 -1 -1 44 -1 9 54 -1 56 -1 -1 73 34 -1 -1 42 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7 -1 80 -1 68 -1 26 -1 -1 -1 80 55 -1 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -1 80 -1 68 -1 26 -1 -1 -1 80 -1 -1 55 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 26 -1 75 33 -1 21 -1 69 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 62 36 -1 -1 26 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -1 33 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 62 -1 -1 36 26 -1 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0], where the first value 47 and the fourth value 28 are shifted from 48 and 29 respectively.

[0151] In some embodiments, the second exponent matrix may include the following set of values: [48 -1 29 -1 -1 28 -1 399 -1 -1 61 -1 -1 -1 -1 -1 -1 -1 63 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 32 -1 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 -1 29 28 -1 39 -1 -1 9 61 -1 -1 -1 -1 -1 -1 63 -1 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 -1 32 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 49 -1 42 48 -1 -1 11 -1 30 -1 -1 -1 -1 -1 -1 -1 49 17 -1 41 -1 37 -1 15 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 4 49 -1 42 -1 -1 48 11 -1 30 -1 -1 -1 -1 -1 -1 -1 49 -1 -1 17 -1 41 -1 37 -1 15 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 35 -1 76 -1 78 -1 51 -1 37 -1 35 21 -1 -1 -1 17 -1 64 -1 -1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 -1 32 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 35 -1 76 -1 78 -1 51 -1 37 -1 35 -1 -1 21 -1 -1 -1 17 -1 64 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 9 -1 65 -1 44 -1 9 54 -1 56 -1 -1 73 -1 34 -1 42 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46 -1 390 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 9-1 65 -1 44 -1 9 -1 -1 54 -1 56 73 -1 34 -1 42 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7 -1 80 68 -1 -1 26 -1 -1 80 -1 -1 55 -1 -136 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0-1 3 -1 -1 62 7 -1 80 -1 -1 68 26 -1 -1 -1 80 55 -1 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 26 -1 75 33-1 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 36 -1 26-1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -1 33 21 -1 69 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 -1 -1 36 -1 26 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0]。

[0152] In some embodiments, one or more processors may be configured to identify (e.g., from a codebook) a third binary parity-check matrix that permutes one or more rows or one or more columns of a second binary parity-check matrix, the third binary parity-check matrix having the same dimensions as the first binary parity-check matrix. For example, the third binary parity-check matrix may correspond to a binary parity-check matrix that permutes the first row and the second row of the second binary parity-check matrix. One or more processors may be further configured to use the third binary parity-check matrix to decode the received encoded data.

[0153] In some embodiments, one or more processors may be configured to identify a fourth binary parity-check matrix corresponding to a third exponent matrix in which one or more rows or one or more columns of a first exponent matrix are permuted. For example, the third exponent matrix may correspond to an exponent matrix in which the first row and the second row of the first exponent matrix are permuted. The third exponent matrix may have the same dimensions as the first exponent matrix. One or more processors may be configured to use the fourth binary parity-check matrix to decode received encoded data.

[0154] Figure 13 is a flowchart showing a process for encoding data and / or decoding data using an LDPC code according to an embodiment. Figure 13 is a flowchart showing a process 1300 for encoding data using an LDPC code according to an embodiment. In some embodiments, process 1300 is performed by one or more processors of a first device (e.g., encoder 130 or processor 2010 of communication system 105) or by one or more processors of a second device (e.g., decoder 160 or processor 2010 of communication system 108). In other embodiments, process 1300 is performed by other entities (e.g., computing systems other than communication systems 105 or 108). In some embodiments, process 1300 includes more, fewer, or different steps than those Figure 13 shown therein.

[0155] In step 1302, the first device may identify a second parity-check matrix (e.g., novel parity-check matrix ) corresponding to a first exponent matrix (e.g., ) that includes 576 values of a second QC-LDPC code based on a first parity-check matrix (e.g., base parity-check matrix H) of a first quasi-cyclic low-density parity-check (QC-LDPC) code having a 3 / 4 code rate. The second QC-LDPC code may have a code block size (e.g., n = 3888) that is twice the code block size (e.g., n = 1944) of the first QC-LDPC code.

[0156] In some embodiments, the first parity-check matrix of the first QC-LDPC code having a 3 / 4 code rate may be identified by the first device or another device other than the first device (e.g., from a codebook). If a device other than the first device identifies the first parity-check matrix, then the device may transmit the first parity-check matrix to the first device. A first binary matrix having the same dimensions as the dimensions of the exponent matrix of the first parity-check matrix (e.g., m / Z × n / Z, if the first parity-check matrix has (m × n) dimensions) may be determined. The Khatri-Rao product of the first parity-check matrix and the first binary matrix may be determined (e.g., using Equation 15). The second parity-check matrix (e.g., novel parity-check matrix )。

[0157] In some embodiments, the first binary matrix can be determined by the following steps: (i) determining a second binary matrix having the same dimensions as the first binary matrix; and (ii) determining the first binary matrix that at least includes (1) one or more rows of the second binary matrix or (2) one or more columns of the second binary matrix. The second parity-check matrix can be determined by the following steps: (i) determining a second exponent matrix having the same dimensions as the first exponent matrix based on the result of the Khatri-Rao product; (ii) determining the first exponent matrix based on the second exponent matrix; and (iii) determining the second parity-check matrix based on the first exponent matrix (e.g., using Equation 8).

[0158] In some embodiments, the second binary matrix may comprise the following set of values: [0 1 0 0 0 0 1 1 1 0 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 0]. The second exponent matrix may comprise the following set of values: [48 -1 -1 29 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 -1 63 -1 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 -1 32 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 29 -1 -1 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 32 -1 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 49 -1 -1 42 -1 48 11 -1 -1 30 -1 -1 -1 -1 -1 -1 49 -1 -1 17 41 -1 37 -1 -1 15 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 4 -1 49 42 -1 48 -1 -1 11 30 -1 -1 -1 -1 -1 -1 -1 -1 49 17 -1 -1 41 -1 37 15 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 35 -1 76 78 -1 51 -1 37 -1 35 -1 21 -1 -1 -1 -1 17 64 -1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 -1 -1 32 -1 -1 -1-1 0 -1 0 -1 -1 -1 -1 -1 35 -176 -1 -1 78 -1 51 -1 37 -1 35 -1 21 -1 -1 17 -1 -1 64 -1 -1 -1 -1 -1 -1 -1 59-1 7 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 9 -1 -1 65 44 -1 9 -1 -1 54 -1 56 73 -1 -1 34 42 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46-1 -1 39 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 9 65 -1 -1 44 -1 9 54 -1 56 -1 -1 73 34 -1 -1 42 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7 -1 80 -1 68 -1 26 -1 -1 -1 80 55 -1 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -1 80 -1 68 -1 26 -1 -1 -1 80 -1 -1 55 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -126 -1 75 33 -1 21 -1 69 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -162 36 -1 -1 26 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -133 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 62 -1 -1 36 26-1 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0]。

[0159] In some embodiments, the first exponential matrix can be determined by the following steps: (i) selecting at least 574 values from the second exponential matrix as the values of the first exponential matrix; and (ii) shifting one or two values of the first exponential matrix by -1 or +1 from one or more corresponding positive values of the second exponential matrix; (iii) determining the resulting shifted matrix as the first exponential matrix. One or more corresponding positive values of the second exponential matrix may not be selected as the at least 574 values. The first exponential matrix (e.g., a permutation matrix ) It can be generated by perturbing one or two values from the second exponential matrix. For example, based on the second exponential matrix, the first matrix can be generated as [47 -1 -1 28 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 -1 -1 80 -1 -1 -1 -1 -1 37 -1 -1 32 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 29 -1 -1 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 32 -1 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 49 -1 -1 42 -1 48 11 -1 -1 30 -1 -1 -1 -1 -1 -1 49 -1 -1 17 41 -1 37 -1 -1 15 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 4 -1 49 42 -1 48 -1 -1 11 30 -1 -1 -1 -1 -1 -1 -1 -1 -1 49 17 -1 -1 41 -1 37 15 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 35 -1 76 78 -1 51 -1 37 -1 35 -1 21 -1 -1 -1 -1 1764 -1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 -1 -1 32 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 35 -1 76 -1 -1 78 -1 51 -1 37 -1 35 -1 21 -1 -1 17 -1 -1 64 -1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 9 -1 -1 65 44 -1 9 -1 -1 54 -1 56 73 -1 -1 34 42 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 -1 39 0 -1 -1 -1 -1-1 0 -1 0 -1 -1 -1 -1 9 65 -1 -1 44 -19 54 -1 56 -1 -1 73 34 -1 -1 42 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -146 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7 -1 80 -1 68 -1 26 -1 -1 -1 80 55 -1 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -1 80 -1 68 -1 26 -1 -1 -1 80 -1 -155 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1-1 -1 0 -1 0 -1 26 -1 75 33 -1 21 -1 69 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -135 -1 -1 -1 -1 62 36 -1 -1 26 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -126 -1 75 -1 -1 33 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -162 -1 -1 36 26 -1 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0], where the first value 47 and the fourth value 28 are shifted from 48 and 29 respectively. One or more processors may be configured to determine the resulting matrix of the shifts as the first exponent matrix.

[0160] In some embodiments, the second binary matrix may include the following set of values: [0 0 1 1 0 1 1 1 1 1 01 1 1 1 0 0 1 0 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 11 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 11 0 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 01 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0]. The second exponential matrix may include the following set of values: [48 -1 29 -1 -128 -1 39 9 -1 -1 61 -1 -1 -1 -1 -1 -1 -1 63 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37-1 32 -1 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 -1 29 28 -1 39 -1 -1 961 -1 -1 -1 -1 -1 -1 -1 63 -1 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 -1 32 22 -1-1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 49 -1 42 48 -1 -1 11 -1 30 -1 -1 -1-1 -1 -1 -1 49 17 -1 41 -1 37 -1 15 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 49 -1 42 -1 -1 48 11 -1 30 -1 -1 -1 -1 -1 -1 -1 49 -1 -1 17 -1 41 -1 37 -1 15 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1-1 -1 -1 35 -1 76 -1 78 -1 51 -1 37 -1 35 21 -1 -1 -1 17 -1 64 -1 -1 -1 -1 -1-1 -1 -1 59 -1 7 -1 -1 -1 -1 -1 32 -1 -1 -1 -10 -1 0 -1 -1 -1 -1 -1 35 -1 76-1 78 -1 51 -1 37 -1 35 -1 -1 21 -1 -1 -1 17 -1 64 -1 -1 -1 -1 -1 -1 59 -1 7-1 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 9 -1 65 -1 44 -1 954 -1 56 -1 -1 73 -1 34 -1 42 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46-1 39 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 9 -1 65 -1 44 -1 9 -1 -1 54 -1 56 73 -1 34 -1 42 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7 -1 80 68 -1 -1 26 -1 -1 80 -1 -1 55 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0-1 0 -1 3 -1 -1 62 7 -1 80 -1 -1 68 26 -1 -1 -1 80 55 -1 -1 -1 -1 36 -1 -1 26-1 -1 -1 -1 9 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 26 -1 7533 -1 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 36 -126 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -1 33 21 -169 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 -1 -1 36 -1 26 -1 -1-1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0]。

[0161] In some embodiments, the first binary matrix can be determined by the following steps: (i) permuting (1) two or more rows of the second binary matrix or (2) two or more columns of the second binary matrix; and (ii) determining the resulting permuted binary matrix as the first binary matrix. For example, the first binary matrix can correspond to the binary matrix in which the first row and the second row of the second binary matrix are permuted. The first binary matrix can be determined such that the first binary matrix maintains full rank.

[0162] In step 1304, the first device can encode data using the second parity check matrix. In step 1306, the first device can transmit the encoded data to another device (e.g., communication system 108).

[0163] In step 1308, the second device (e.g., decoder 160 or processor 2010 of communication system 108) can identify the second binary parity check matrix (e.g., the novel parity check matrix ) (e.g., from a codebook). In step 1310, the second device can receive the encoded data from the first device (e.g., communication system 105). In step 1312, the second device can decode the encoded data using the second binary parity check matrix.

[0164] In some embodiments, the second device can identify a third binary parity check matrix in which one or more rows or one or more columns of the second binary parity check matrix are permuted, the third binary parity check matrix having the same dimensions as the first binary parity check matrix. For example, the third binary parity check matrix can correspond to the binary parity check matrix in which the first row and the second row of the second binary parity check matrix are permuted. The second device can use the third binary parity check matrix to decode the received encoded data.

[0165] In some embodiments, the second device can be configured to identify a fourth binary parity check matrix corresponding to a third exponent matrix in which one or more rows or one or more columns of the first exponent matrix are permuted. For example, the third exponent matrix can correspond to the exponent matrix in which the first row and the second row of the first exponent matrix are permuted. The third exponent matrix can have the same dimensions as the first exponent matrix. The second device can use the fourth binary parity check matrix to decode the received encoded data.

[0166] The reference “or” may be interpreted inclusively such that any item described using “or” may indicate any of a single, more than one, and all of the described items. The reference to at least one of a list of conjunctive items may be interpreted as an inclusive “or” to indicate any of a single, more than one, and all of the described items. For example, the reference “at least one of ‘A’ and ‘B’” may include only ‘A’, only ‘B’, and both ‘A’ and ‘B’. Such references used in conjunction with “comprising” or other open terms may include additional items.

[0167] It should be noted that certain paragraphs of this disclosure may refer to terms such as “first” and “second” for the purpose of relating to each other or to other identification or differentiation, e.g., in relation to transmission spatial streams, sounding frames, responses, and subsets of devices. These terms are not intended to relate entities (such as a first device and a second device) only in terms of time or according to a sequence, but in some cases, these entities may include such a relationship. These terms also do not limit the number of possible entities (such as STAs, APs, beamformers, and / or beamforming receivers) that may operate within a system or environment. It should be understood that the above system may provide multiple of any or each of these components and these components may be provided on a single machine or, in some embodiments, on multiple machines in a distributed system. Additionally, bit field positions may be varied and multi-bit words may be used. Further, the above system and method may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture (such as floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or magnetic tapes). The program may be implemented in any programming language (such as LISP, PERL, C, C++, C#) or in any bytecode language (such as JAVA). The software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0168] Although the foregoing written description of the method and system enables one of ordinary skill in the art to make and use its embodiments, one of ordinary skill in the art should understand and appreciate that there are variations, combinations, and equivalents to the specific embodiments, methods, and examples herein. Accordingly, the method and system of the present invention should not be limited to the above embodiments, methods, and examples, but rather to all embodiments and methods within the scope and spirit of this disclosure.

Claims

1. A method comprising: identifying, by the one or more processors of the first device, a second parity check matrix corresponding to a first exponential matrix including 576 values ​​of a second QC-LDPC code based on a first parity check matrix of a first quasi-cyclic low density parity check (QC-LDPC) code according to a code rate of 3 / 4, wherein the second QC-LDPC code has a code block size that is twice the code block size of the first QC-LDPC code; encoding data using the second parity-check matrix by the one or more processors of the first device; and The encoded data is transmitted by the one or more processors of the first device.

2. The method according to claim 1, further comprising: identifying the first parity check matrix of the first QC-LDPC code having the 3 / 4 code rate; determining a first binary matrix having the same dimension as the dimension of an exponential matrix of the first parity-check matrix; determining a Katri-Rao product of the first parity-check matrix and the first binary matrix; and The second parity check matrix is ​​determined based on a result of the Catelli-Rao product.

3. The method according to claim 2, wherein Determining the first binary matrix includes: determining a second binary matrix having the same dimensions as the first binary matrix; and determining the first binary matrix including at least (1) one or more rows of a second binary matrix or (2) one or more columns of the second binary matrix, and Determining the second parity check matrix includes: determining a second exponential matrix having the same dimension as the first exponential matrix based on a result of the Catterelli-Rao product; determining the first exponential matrix based on the second exponential matrix; and The second parity check matrix is ​​determined based on the first exponential matrix.

4. The method according to claim 3, wherein The second binary matrix comprises the following set of values: [0 1 0 0 0 0 1 1 1 0 0 1 1 1 1 0 1 1 0 0 11 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 0 1 11 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 10 1 1 1 1 0], and The second exponential matrix includes the following value set: [48 -1 -1 29 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 -1 32 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 29 -1 -1 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 32 -1 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 49 -1 -1 42 -1 48 11 -1 7 -1 37 15 -1-1 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4-1 49 42 -1 48 -1 -1 11 30 -1 -1 -1 -1 -1 -1 -1 -1 49 17 -1 -1 41 -1 37 15 -1-1 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0-1 -1 -1 -1 -1 -1 -1 35 -1 76 78 -1 51-1 37 -1 35 -1 21 -1 -1 -1 -1 17 64 -1 -1 -1 -1 4 -1 9 -1 -1 54 -1 56 73 -1 -1 34 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 -1 39 0 -1 -1 -1 -1 -10 -1 0 -1 -1 -1 -1 9 65 -1-1 44 -1 9 54 -1 56 -1 -1 73 34 -1 -1 42 -1 -1 -1-1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1-1 3 62 -1 -1 7 -1 80 -1 68 -1 26 -1 -1 -1 80 55 -1 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -180 -1 68 -1 26 -1 -1 -1 80 -1 -1 55 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -172 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 26 -1 75 33 -1 21 -1 69 -159 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 62 36 -1 -1 26 -1 -1 -1 -11 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -1 33 -1 21 -1 69 -1 59 -1 3 38-1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 62 -1 -1 36 26 -1 -1 -1 -1 -1 -1 1 -1 -1 -1-1 -1 -1 -1 -1 -1 0]。 5. The method according to claim 3, wherein The second binary matrix comprises the following set of values: [0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 0 11 1 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 11 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 11 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 0 1 10 1 1 1 1 0], and The second exponential matrix includes the following value set: [48 -1 29 -1 -1 28 -1 39 9 -1 -1 61 -1 -1 -1-1 -1 -1 -1 63 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 32 -1 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 -1 29 28 -1 39 -1 -1 9 61 -1 -1 -1 -1 -1 -1 -1 63 -1 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 -1 32 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 49 -1 42 48 -1 -1 11 -1 30 -1 -1 -1 -1 -1 -1 -1 49 17 -1 41 -1 37 -1 15 -1-1 54 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 49-1 42 -1 -1 48 11 -1 30 -1 -1 -1 -1 -1 -1 -1 49 -1 -1 17 -1 41 -1 37 -1 15 -1-1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 76 -1 78 -1 51 -1 37 -1 35 21 -1 -1 -1 17 -1 64 -1 -1 -1 -1 4 -1 9 54 -1 56 -1 -1 73 -1 34 -1 42 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 39 0 -1 -1 -1 -1 -1 0-1 0 -1 -1 -1 9 -1 65-1 44 -1 9 -1 -1 54 -1 56 73 -1 34 -1 42 -1 -1 -1 -1 -1-1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -13 62 -1 -1 7 -1 80 68 -1 -1 26 -1 -1 80 -1 -1 55 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -1 80-1 -1 68 26 -1 -1 -1 80 55 -1 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -1 -1 72-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 26 -1 75 33 -1 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 36 -1 26 -1 -1 -1 -1 -1 1 -1 -1-1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -1 33 21 -1 69 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 -1 -1 36 -1 26 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0]。 6. The method of claim 3, wherein determining the first exponential matrix comprises: selecting at least 574 values ​​from the values ​​of the second index matrix as values ​​of the first index matrix; shifting one or two values ​​of the first index matrix by -1 or +1 from one or more corresponding positive values ​​of the second index matrix, wherein the one or more corresponding positive values ​​of the second index matrix are not selected as the at least 574 values; and The shifted resulting matrix is ​​determined as the first exponential matrix.

7. The method according to claim 1, further comprising: identifying, by a second device, the second binary parity check matrix; receiving, by the second device, the encoded data from the first device; and The encoded data is decoded by the second device using the second binary parity check matrix.

8. A device comprising: A transmitter and one or more processors, wherein The one or more processors are configured to: identifying a second parity check matrix corresponding to a first exponential matrix including 576 values ​​of a second QC-LDPC code based on a first parity check matrix of a first quasi-cyclic low density parity check (QC-LDPC) code according to a 3 / 4 code rate, wherein the second QC-LDPC code has a code block size that is twice that of the first QC-LDPC code; and The data is encoded using the second parity check matrix, and The transmitter is configured to transmit the encoded data.

9. The apparatus of claim 8, wherein the one or more processors are configured to: identifying the first parity check matrix of the first QC-LDPC code having the 3 / 4 code rate; determining a first binary matrix having the same dimension as the dimension of an exponential matrix of the first parity-check matrix; determining a Katri-Rao product of the first parity-check matrix and the first binary matrix; and The second parity check matrix is ​​determined based on a result of the Catelli-Rao product.

10. The device according to claim 9, wherein In determining the first binary matrix, the one or more processors are configured to: determining a second binary matrix having the same dimensions as the first binary matrix; and determining the first binary matrix including at least (1) one or more rows of a second binary matrix or (2) one or more columns of the second binary matrix, and In determining the second parity-check matrix, the one or more processors are configured to: determining, based on the result of the Catterelli-Rao product, a second exponential matrix having the same dimension as the first exponential matrix; determining the first exponential matrix based on the second exponential matrix; and The second parity check matrix is ​​determined based on the first exponential matrix.

11. The device according to claim 10, wherein The second binary matrix comprises the following set of values: [0 1 0 0 0 0 1 1 1 0 0 1 1 1 1 0 1 1 0 0 11 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 0 1 11 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 0 1 0 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 10 1 1 1 1 0], and The second exponential matrix includes the following value set: [48 -1 -1 29 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 -1 32 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 29 -1 -1 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 32 -1 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 49 -1 -1 42 -1 48 11 -1 7 -1 37 15 -1-1 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4-1 49 42 -1 48 -1 -1 11 30 -1 -1 -1 -1 -1 -1 -1 -1 49 17 -1 -1 41 -1 37 15 -1-1 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0-1 0 -1 -1 -1 -1 -1 -1 -1 35 -1 76 78 -1 51-1 37 -1 35 -1 21 -1 -1 -1 -1 17 64 -1 -1 -1 -1 4 -1 9 -1 -1 54 -1 56 73 -1 -1 34 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 -1 39 0 -1 -1 -1 -1 -10 -1 0 -1 -1 -1 -1 9 65 -1-1 44 -1 9 54 -1 56 -1 -1 73 34 -1 -1 42 -1 -1 -1-1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1-1 3 62 -1 -1 7 -1 80 -1 68 -1 26 -1 -1 -1 80 55 -1 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -180 -1 68 -1 26 -1 -1 -1 80 -1 -1 55 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -172 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 26 -1 75 33 -1 21 -1 69 -159 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 62 36 -1 -1 26 -1 -1 -1 -11 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -1 33 -1 21 -1 69 -1 59 -1 3 38-1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 62 -1 -1 36 26 -1 -1 -1 -1 -1 -1 1 -1 -1 -1-1 -1 -1 -1 -1 -1 0]。 12. The device according to claim 10, wherein The second binary matrix comprises the following set of values: [0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 0 11 1 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 11 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 11 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 0 1 10 1 1 1 1 0], and The second exponential matrix includes the following value set: [48 -1 29 -1 -1 28 -1 39 9 -1 -1 61 -1 -1 -1-1 -1 -1 -1 63 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 32 -1 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 -1 29 28 -1 39 -1 -1 9 61 -1 -1 -1 -1 -1 -1 -1 63 -1 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 -1 32 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 49 -1 42 48 -1 -1 11 -1 30 -1 -1 -1 -1 -1 -1 -1 49 17 -1 41 -1 37 -1 15 -1-1 54 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 49-1 42 -1 -1 48 11 -1 30 -1 -1 -1 -1 -1 -1 -1 49 -1 -1 17 -1 41 -1 37 -1 15 -1-1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 76 -1 78 -1 51 -1 37 -1 35 21 -1 -1 -1 17 -1 64 -1 -1 -1 -1 4 -1 9 54 -1 56 -1 -1 73 -1 34 -1 42 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 39 0 -1 -1 -1 -1 -1 0-1 0 -1 -1 -1 9 -1 65-1 44 -1 9 -1 -1 54 -1 56 73 -1 34 -1 42 -1 -1 -1 -1 -1-1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 39 -1 -1 0 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -13 62 -1 -1 7 -1 80 68 -1 -1 26 -1 -1 80 -1 -1 55 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -1 80-1 -1 68 26 -1 -1 -1 80 55 -1 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -1 -1 72-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 26 -1 75 33 -1 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 36 -1 26 -1 -1 -1 -1 -1 1 -1 -1-1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -1 33 21 -1 69 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 -1 -1 36 -1 26 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0]。 13. The apparatus of claim 10, wherein in determining the first exponential matrix, the one or more processors are configured to: selecting at least 574 values ​​from the values ​​of the second index matrix as values ​​of the first index matrix; shifting one or two values ​​of the first index matrix by -1 or +1 from one or more corresponding positive values ​​of the second index matrix, wherein the one or more corresponding positive values ​​of the second index matrix are not selected as the at least 574 values; and The shifted resulting matrix is ​​determined as the first exponential matrix.

14. The apparatus of claim 10, wherein in determining the first exponential matrix, the one or more processors are configured to: permuting (1) two or more rows of the second binary matrix or (2) two or more columns of the binary matrix; and determining the permuted binary matrix as the first binary matrix, Wherein the first binary matrix is ​​determined such that the first binary matrix maintains full rank.

15. The apparatus of claim 14, wherein the one or more processors are further configured to: identifying a third binary parity check matrix in which one or more rows or one or more columns of the second binary parity check matrix are permuted, the third binary parity check matrix having the same dimensions as the first binary parity check matrix; and The received encoded data is decoded using the third binary parity-check matrix.

16. An apparatus comprising: a receiver configured to receive the encoded data; and One or more processors configured to: identifying a second parity check matrix corresponding to a first exponential matrix including 576 values ​​of a second QC-LDPC code based on a first parity check matrix of a first quasi-cyclic low density parity check (QC-LDPC) code according to a 3 / 4 code rate, wherein the second QC-LDPC code has a code block size that is twice that of the first QC-LDPC code; and The received encoded data is decoded using the second binary parity-check matrix.

17. The apparatus of claim 16, wherein the first exponential matrix comprises at least 574 values ​​selected from a second exponential matrix having the same dimension as the first exponential matrix.

18. The apparatus of claim 17, wherein the first exponential matrix comprises one or two values ​​shifted by -1 or +1 from one or more corresponding positive values ​​of the second exponential matrix, Wherein the one or more corresponding positive values ​​of the second exponential matrix are not selected as the at least 574 values.

19. The apparatus of claim 17, wherein the second exponential matrix comprises the following set of values: [48 -1 -1 29 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 -1 32 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 29 -1 -1 28 -1 39 -1 9 -1 61 -1 -1 -1 -1 -1 -1 -1 63 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 32 -1 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 49 -1 -1 42 -1 48 11 -1 -1 30 -1-1 -1 -1 -1 -1 49 -1 -1 17 41 -1 37 -1 -1 15 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0-1 0 -1 -1 -1 -1 -1 -1 -1 4 -1 49 42 -1 48 -1 -1 11 30 -1 -1 -1 -1 -1 -1 -1 -1 49 17 -1 -1 41 -1 37 15 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1-1 -1 -1 -1 -1 35 -1 76 78 -1 51 -1 37 -1 35 -1 21 -1 -1 -1 -1 17 64 4 -1 56 73 -1 -1 34 42 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 -1 39 0 -1 -1 -1 -1 -1 0 -1 0-1 -1 -1 -1 9 65 -1 -1 44 -1 9 54 -1 56 -1 -1 73 34 -1 -1 42 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 -1 46 39 -1 -10 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7 -1 80 -1 68 -1 26 -1 -1 -1 8055 -1 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1-1 -1 0 -1 0 -1 3 -1 -1 62 7 -1 80 -1 68 -1 26 -1 -1 -1 80 -1 -1 55 -1 -1 -136 -1 -1 26 -1 -1 -1 -1 9 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0-1 26 -1 75 33 -1 21 -1 69 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1-1 62 36 -1 -1 26 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -1 33 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 62 -1 -1 3626 -1 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0]。 20. The apparatus of claim 17, wherein the second exponential matrix comprises the following set of values: [48 -1 29 -1-1 28 -1 39 9 -1 -1 61 -1 -1 -1 -1 -1 -1 -1 63 45 -1 -1 80 -1 -1 -1 -1 -1 -1 37 -1 32 -1 -1 22 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 -1 29 28 -1 39 -1 -1 9 61 -1 -1 -1 -1 -1 -1 -1 63 -1 -1 45 80 -1 -1 -1 -1 -1 -1 -1 -1 37 -1 32 22 -1 -1 1 -1 0 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 49 -1 42 49 -1 42 -1 -1 48 11 -1 30 -1 -1 -1 -1 -1 -1 -1 49 -1 -1 17 -1 41 -1 37 -1 15 -1 -1 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1-1 -1 -1 -1 -1 4 49 -1 42 -1 -1 48 11 -1 30 -1-1 -1 -1 -1 -1 -1 49 -1 17 -1 41 -1 37 -1 15 -1 -1 54 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1-1 -1 -1 -1 -1 35 -1 76 -1 78 -1 64 -1 -1 -1 -1 -1 -1 -1 59 -1 7 -1 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 35-1 76 -1 78 -1 51 -1 37 -1 35 -1 -1 21 -1 -1 -1 17 -1 64 -1 -1 -1 -1 -1 59-1 7 -1 -1 -1 -1 -1 32 -1 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 -1 -1 9 -1 65 -1 44-1 9 54 -1 56 -1 -1 73 -1 34 -1 42 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 -1 46 -1 39 0 -1 -1 -1 -1 -1 0 -1 0-1 -1 -1 9 -1 65 -1 44 -1 9 -1 -1 54 -156 73 -1 34 -1 42 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 -1 -1 -1 46 -1 39 -1 -10 -1 -1 -1 -1 -1 0 -1 0 -1 -1 -1 3 62 -1 -1 7 -1 80 68 -1 -1 26 -1 -1 80 -1 -1 55 -1 -1 36 -1 -1 -1 -1 26 -1 -1 9 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -1 3 -1 -1 62 7 -1 80 -1 -1 68 26 -1 -1 -1 80 55 -1 -1 -1 -1 36 -1 -1 26 -1 -1 -1 -1 9 -1 -1 -1 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 0 -126 -1 75 33 -1 -1 21 -1 69 -1 59 -1 3 38 -1 -1 -1 -1 -1 -1 -1 -1 35 -1 -1 -162 36 -1 26 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 26 -1 75 -1 -133 21 -1 69 -1 59 -1 3 -1 -1 38 -1 -1 -1 -1 -1 -1 35 -1 -1 -1 62 -1 -1 36 -126 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0]。

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