LDPC (Low Density Parity Check) code construction method and device of flash memory, terminal equipment and storage medium

Abstract

The invention relates to the technical field of flash memory control, in particular to an LDPC (Low Density Parity Check) code construction method and device of a flash memory, terminal equipment and a storage medium. The method comprises the following steps: determining construction parameters of the LDPC code, wherein the construction parameters are used for constructing a mother matrix of the LDPC code; constructing a prototype matrix of each sub-matrix, and simplifying the structure of each sub-matrix to obtain each simplified sub-matrix; combining the simplified sub-matrixes to obtain sub code rate matrixes of the mother matrix, and combining the sub code rate matrixes to obtain a mother code prototype matrix; assigning a cyclic shift value to the mother code prototype matrix in an arithmetic progression mode; and detecting whether each sub-matrix in the mother code prototype matrix contains four rings or not under the current shift value, if so, re-executing the step of assigning the cyclic shift value to the mother code prototype matrix through the arithmetic progression method, and if not, ending the construction. The construction of the LDPC code is simplified by simplifying the sub-matrix, and the calculation difficulty during error correction application is also simplified.

Description

Technical Field

[0001] This application relates to the field of flash memory control technologies, and in particular, to a method, apparatus, terminal device, and storage medium for constructing LDPC codes for flash memory. Background Art

[0002] QC-LDPC code is a low-density parity-check code with specific structural characteristics, generally described by a base matrix and a lifting factor (Lifting Size, LS) Z. Each element in the base matrix corresponds to a cyclic right shift value of a Z×Z identity matrix, that is, the element "0" represents a Z×Z identity matrix. The element "-1" is defined to represent a Z×Z zero matrix. Other cyclic shift values are all between 1 and (Z - 1).

[0003] However, the diversity of different NAND flash page sizes (Page Size, PS) poses challenges to the construction of LDPC matrices. For example, in MLC flash memory, the size of a single page may be relatively small, while in QLC flash memory, the size of a single page may be much larger, and the Spare Size of QLC pages from different die manufacturers is also different. This requires that the error correction code design be compatible with flash memories of different page sizes, while existing LDPC matrix construction methods are usually optimized for specific page sizes, which makes it necessary to construct different LDPC matrices for different types of NAND flash memories during the design process, increasing the design complexity and possibly affecting the efficiency of hardware implementation. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method, apparatus, terminal device, and storage medium for constructing LDPC codes for flash memory, which can effectively solve problems such as affecting the efficiency of hardware implementation and complex design.

[0005] In a first aspect, embodiments of this application provide a method for constructing an LDPC code for flash memory, including: Determine the construction parameters of the LDPC code, where the construction parameters are used to construct the mother matrix of the LDPC code; Construct the prototype matrices of each submatrix, and simplify the structures of each submatrix to obtain each simplified submatrix; Merge the simplified submatrices to obtain the sub-code rate matrix of the mother matrix, and merge each sub-code rate matrix to obtain the mother code prototype matrix; Assign cyclic shift values to the mother code prototype matrix by an arithmetic progression method; Detect whether each submatrix in the mother code prototype matrix contains a 4-cycle under the current shift value. If it contains a 4-cycle, re-execute the step of assigning cyclic shift values to the mother code prototype matrix by the arithmetic progression method. If it does not contain a 4-cycle, the construction ends.

[0006] In some embodiments, determining the construction parameters of the LDPC code, where the construction parameters are used to construct the mother matrix of the LDPC code, includes: Calculating a lifting factor according to the hardware parameters of the target flash memory, and calculating the number of columns of the user data matrix according to the lifting factor; Determining the highest code rate and the lowest code rate of the target flash memory, and calculating the number of rows of the mother matrix and the number of rows of each sub-matrix according to the number of columns of the user data matrix, the highest code rate, and the lowest code rate.

[0007] In some embodiments, the sub-matrices include a user data matrix, a rate-compatible matrix, an all-1 matrix, a dense matrix, and a specific structure sub-matrix; Constructing the prototype matrices of each sub-matrix and simplifying the structures of each sub-matrix includes: Setting all the data in the first row of the user data matrix to 0, and setting all the diagonal data of the rate-compatible matrix to 0; Setting the dense matrix to a full matrix, and setting the column weight of each sub-matrix to a value within a preset interval based on a preset column weight; the column weight is the number of 1s in a column of data in the matrix.

[0008] In some embodiments, setting the column weight of each sub-matrix to a value within a preset interval based on a preset column weight further includes: The maximum column weight of the mother matrix is not greater than the preset column weight + 1; The maximum column weight of the user data matrix is not greater than the preset column weight - 1; The maximum column weight of the rate-compatible matrix is not greater than the preset column weight - 1; In some embodiments, combining each of the simplified sub-matrices to obtain the sub-code rate matrix of the mother matrix includes: Performing prototype matrix construction on each sub-matrix through the progressive edge-growth algorithm, and combining each of the simplified sub-matrices at preset positions; Determining the number of rows and columns to be deleted, continuously deleting the rows to be deleted starting from the second row, and continuously deleting the columns to be deleted starting from the second column of the rate-compatible matrix to obtain the sub-code rate matrix of the mother matrix.

[0009] In some embodiments, combining each of the sub-code rate matrices to obtain the mother code prototype matrix includes: Performing a logical OR operation on the positions of 1 in each sub-code rate matrix and the cumulative OR temporary matrix respectively to obtain the mother code prototype matrix.

[0010] In some embodiments, assigning cyclic shift values to the mother code prototype matrix in an arithmetic progression manner includes; Select any prime number between 0 and the lifting factor as the equal difference value for each row of the mother code prototype matrix; the equal difference values for each row are different; Set the initial value for each row of the first column of the mother code prototype matrix; Generate the cyclic shift value for each row according to the initial value of each row and the equal difference value of each row.

[0011] In some embodiments, the hardware parameters include the length of firmware filling, the length of cyclic redundancy check, the minimum page capacity, the maximum page capacity, the throughput rate, and the operating frequency; Calculating the lifting factor according to the hardware parameters of the target flash memory, and calculating the number of columns of the user data field according to the lifting factor includes: Calculate the maximum codeword length according to the maximum page capacity and the number of codewords; Calculate the size of the user data field of each codeword according to the length of firmware filling and the cyclic redundancy check; Calculate the lifting factor according to the maximum codeword length, the throughput rate, the operating frequency, the size of the user data field of each codeword, and the hardware parameters of the target flash memory controller; Calculate the number of columns of the user data field according to the lifting factor and the size of the user data field of each codeword.

[0012] In some embodiments, determining the highest compatible code rate and the lowest code rate, and calculating the number of rows of the mother matrix and the number of rows of each sub-matrix according to the highest code rate and the lowest code rate includes: Calculate the number of rows of the mother matrix and the number of rows of each sub-matrix according to a preset inequality; The expression of the inequality is; ; ; In the formula, R is the lowest code rate, R1 is the highest code rate, K is the number of columns of the user data field, M is the number of rows of the mother matrix, and M1 is the number of rows of the sub-matrix corresponding to the highest code rate.

[0013] In a second aspect, the present application also provides an LDPC code construction device for a flash memory, including: A first construction module for determining the construction parameters of the LDPC code, where the construction parameters are used to construct the mother matrix of the LDPC code; A second construction module for constructing the prototype matrix of each sub-matrix and simplifying the structure of each sub-matrix to obtain each simplified sub-matrix; A merging module for merging the simplified sub-matrices to obtain the sub-code rate matrix of the mother matrix, and merging the sub-code rate matrices to obtain the mother code prototype matrix; An assignment module, configured to assign cyclic shift values to the prototype matrix of the mother code in an arithmetic progression manner; A detection module, configured to detect whether each sub-matrix in the prototype matrix of the mother code contains a 4-cycle under the current shift value. If it contains a 4-cycle, the step of assigning cyclic shift values to the prototype matrix of the mother code by the arithmetic progression method is re-executed. If it does not contain a 4-cycle, the construction ends.

[0014] In a third aspect, the present application further provides a terminal device, which includes a processor and a memory. The memory stores a computer program, and the processor is configured to execute the computer program to implement the LDPC code construction method for flash memory described above.

[0015] In a fourth aspect, the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed on a processor, the LDPC code construction method for flash memory described above is implemented.

[0016] The embodiments of the present application have the following beneficial effects: In the LDPC code construction method for flash memory of the present application, by simplifying the structure of each sub-matrix, the shift calculation amount can be reduced in subsequent error correction applications of the LDPC code, and the design structure is also simplified. By assigning cyclic shift values to the prototype matrix by the arithmetic progression method, random shifts are reduced to fixed shifts, simplifying the hardware implementation complexity and the storage overhead of cyclic shift values. Then, through the detection of shift values, it is ensured that the finally generated LDPC code does not contain a 4-cycle, guaranteeing the error correction performance of the LDPC code. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 Shows a schematic flowchart of an LDPC code construction method for flash memory according to an embodiment of the present application; Figure 2 Shows a schematic diagram of an LDPC code structure according to an embodiment of the present application; Figure 3 Shows a schematic diagram of a sub-matrix of an LDPC code construction according to an embodiment of the present application; Figure 4 Shows a schematic diagram of a constructed LDPC code according to an embodiment of the present application; Figure 5Shows a schematic diagram of the sum-product performance analysis of different half-port codes of each sub-matrix in an additive Gaussian noise channel according to an embodiment of the present application; Figure 6 Shows a schematic diagram of the structure of an LDPC code construction device for a flash memory according to an embodiment of the present application. Detailed implementation manners

[0019] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0020] Generally, the components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0021] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are only intended to represent specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be construed as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and cannot be understood as indicating or implying relative importance.

[0022] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the various embodiments of the present application belong. The terms (such as those defined in a general-use dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or being overly formal, unless clearly defined in the various embodiments of the present application.

[0023] QC-LDPC code is a type of low-density parity-check code with specific structural characteristics. The diversity of different NAND flash page sizes (Page Size, PS) poses challenges to the construction of the LDPC matrix. This application provides a method for constructing the LDPC code of a flash memory. After constructing and simplifying sub-matrices, each sub-matrix is obtained, and then each sub-matrix is spliced to obtain a mother matrix. Then, corresponding inspection operations are performed to remove the loops in the mother matrix, and finally, the required QC-LDPC code matrix is obtained.

[0024] The following will illustrate the method for constructing the LDPC code of the flash memory in combination with some specific embodiments.

[0025] Figure 1 A flowchart showing the method for constructing the LDPC code of the flash memory according to an embodiment of the present application is presented. Exemplarily, the method for constructing the LDPC code of the flash memory includes the following steps: Step S100, determine the construction parameters of the LDPC code, where the construction parameters are used to construct the mother matrix of the LDPC code.

[0026] The LDPC code is a QC-LDPC code matrix, which is used for error correction and data protection in the flash memory. The LDPC code includes multiple sub-matrices, and its specific form is as Figure 2 shown, including a total of seven parts: A, B, C, D, E, F, and G. Part A corresponds to the user data matrix, part B corresponds to the code rate compatibility matrix, part C is a full '-1' matrix, corresponding to the full 0 matrix after expansion, parts D, F, and G correspond to the dense matrix, and part E has diagonal elements of "0", corresponding to the identity matrix after expansion.

[0027] Among them, the construction of the LDPC code is related to the flash memory in which it operates. The LDPC code needs to be designed according to the hardware parameters of the flash memory. Otherwise, the generated LDPC code cannot work properly in the flash memory.

[0028] For the convenience of description, in this embodiment, the hardware parameters of the target flash memory that the QC-LDPC code needs to be compatible with are preset. Among them, the hardware parameters include the minimum page capacity, the maximum page capacity, the throughput rate, and the operating frequency. For the convenience of description and calculation, exemplary data of each operating parameter are given here: the minimum page capacity is denoted as MLC: 16384 + 1536 Bytes, corresponding to the highest code rate of the matrix; the maximum page capacity size is QLC: 16384 + 2608 Bytes, corresponding to the lowest code rate of the matrix. The number of codewords stored in each logical page, T, is 4. The designed throughput rate φ >= 4 GBps, and the designed operating frequency f is 500 MHz.

[0029] First, calculate the maximum codeword length L according to the maximum page capacity. The specific calculation formula is: L = (16384 + 2608) / T = 4748 Bytes.

[0030] In the formula, T as the denominator is 4, and substituting it can obtain the above result.

[0031] Calculate the size of the user data field of each codeword according to the length of the firmware padding and the cyclic redundancy check.

[0032] The length of the firmware padding is a known value, preferably 12 in this embodiment, denoted as OOB (Out-of-Band field), and the cyclic redundancy check is a known value, preferably 4 in this embodiment, denoted as CRC (Cyclic Redundancy Check).

[0033] The size of the user data field of each codeword Lu = (16384 / T) + OOB + CRC = 4748 Bytes.

[0034] Calculate the boosting factor according to the maximum codeword length and the size of the user data field of each codeword.

[0035] The boosting factor needs to satisfy the following inequality: .

[0036] In the formula, i is the number of convergence iterations, preferably 3 in this embodiment. Then, substituting it and calculating, we can get: .

[0037] For the convenience of data transmission and conversion, generally, the size of Z is taken as a power of 2. Then, the boosting factor Z is preferably 256 here.

[0038] Calculate the number of columns of the user data field according to the boosting factor and the size of the user data field of each codeword.

[0039] The calculation formula for the user field K is: K = ceil(Lu / Z), where ceil represents rounding up. Then, here K = ceil(4112 / 32) = 129, that is, the number of columns corresponding to the user field is 129 columns, and 16 Bytes need to be filled at the end of the user data during encoding to meet the requirement of alignment with the Z size of the QC-LDPC code.

[0040] Next, it is necessary to calculate the number of rows M of the mother matrix and the number of rows M1 of the sub-matrix corresponding to the highest code rate, which have the following expressions: ; ; For example, the highest code rates to be compatible are R1 = 0.9214 and R2 = 0.8694. Substituting these values into the above expression, we can calculate M = 19 and M1 = 11, thus obtaining the construction parameters of the LDPC code.

[0041] According to the above construction parameters, a mother matrix of the LDPC code can be constructed as Figure 2 shown, that is, the size of the largest matrix. At this time, each element in the mother matrix has no initial value, and it can be all 0 or default values such as null.

[0042] Among them, N in the figure is the number of columns of the mother matrix. This number of columns is based on the number of columns of the sub - matrices, so it is not calculated separately here. In the subsequent steps, after constructing the mother matrix from the sub - matrices, the number of columns N is the number of columns of the constructed mother matrix.

[0043] Step S200: Construct the prototype matrices of each sub - matrix and simplify the structures of each sub - matrix.

[0044] Among them, the two matrices of all - 1 and all - 0 do not need special processing, so mainly process the user data matrix, the code rate compatible matrix, and the dense matrix.

[0045] Set all the data in the first row of the user data matrix to 0, and set all the diagonal data of the code rate compatible matrix to 0. This can simplify the encoding complexity because the all - 0 row does not require cyclic shift operations, directly reducing the cyclic shift operations of the first row and enabling direct XOR calculations.

[0046] To ensure the reversibility of the parity - check part, set the dense matrix G as a full matrix, and based on a preset column weight, set the column weights of each sub - matrix to values within a preset range.

[0047] Thus, it is determined that the maximum column weight of the mother matrix is g + 1. To ensure the power consumption balance of the hardware, keep the column weights relatively concentrated and facilitate the solution in subsequent steps, define the column weights of matrix A and matrix B as g - 1, and the column weights of the D + F part as g.

[0048] The column weight refers to the number of 1s in a column of data in the matrix. Since the decoding operation is calculated column by column, the size of the column determines the power consumption of the processor when processing the column. By distributing the column weights in the above - mentioned way, the column weights of each column are within the range around the preset column weight g, so that the processor will not have large power consumption fluctuations during processing and can work in a stable state, which is a very friendly and stable state for both the processor and the power supply. In this way, the construction of each sub - matrix is completed.

[0049] Step S300: Combine the simplified sub - matrices to obtain the sub - code rate matrix of the mother matrix, and combine the sub - code rate matrices to obtain the mother - code prototype matrix.

[0050] To ensure the maximum local girth and minimize the number of loops in the prototype matrix as much as possible, in this embodiment, the Progressive Edge Growth (PEG) algorithm can be used to construct the prototype matrix for each sub - matrix.

[0051] After splicing each sub - matrix according to the Figure 2 shown construction, a prototype matrix is obtained, and this prototype matrix conforms to the construction parameters in step S100.

[0052] Among them, if the adaptation length of the current flash memory logical page size is N - 2 columns, it means that the current N columns are larger than the flash memory logical page size. To adapt to the flash memory logical page size, 2 rows and 2 columns need to be deleted.

[0053] At the same time, to ensure the maximum local girth and minimize the number of loops in the prototype matrix as much as possible, since a loop is a structure in the matrix and there should be no 4 - loops in the QC - LDPC code matrix, and loops are composed of 1s, rows and columns with 1s need to be deleted. Therefore, in this embodiment, rows and columns will be deleted based on the flash memory logical page size.

[0054] A loop refers to a closed loop formed by variable nodes, check nodes, and edges connected end - to - end. A 4 - loop is a loop with a side length of 4. For QC - LDPC codes, after reasonable assignment, the 4 - loops in the matrix can be eliminated.

[0055] For rows, since the first row is set to all 0s, there will definitely be no 1s. Therefore, when rows need to be deleted, the first row does not need to be deleted. So, deletion can start from the second row. The first row can obtain the first check block through the exclusive - OR operation on the information block and serves as the first row of all sub - matrices at the same time.

[0056] When deleting columns, deletion needs to start from the second column of the rate - compatible matrix. Since each element in the rate - compatible matrix can be calculated from its first element, as long as the first element is retained, deleting subsequent elements will have no impact. So, deletion can start from the second column of the rate - compatible matrix.

[0057] Therefore, reflected in the entire mother matrix, for a flash memory particle with a compatible page capacity of 16384 + 2432 Bytes, the corresponding sub - matrix is 18×147, corresponding to removing the 2nd row and the 131st column from the mother matrix. An example of the final prototype matrix is Figure 4 shown.

[0058] It should be noted that the sub-code rate matrix obtained by the above method is a corresponding sub-code rate matrix among the sub-code rates supported by the device. Through the above method, a corresponding sub-code rate matrix can be obtained for each sub-code rate. In this embodiment, the sub-code rate matrices will also be combined to obtain the mother code prototype matrix.

[0059] Among them, in this embodiment, combining the sub-code rate matrices into the mother code prototype matrix can be to perform an OR logic on the positions of 1 in the sub-code rate matrix and the positions of 1 in the corresponding mother matrix, and traversing all the sub-matrices that need to be supported can obtain the mother code prototype matrix. The combination when the sub-matrix size is (M - 1)×(N - 1) is as Figure 3 shown. The cumulative OR temporary matrix 1 is the matrix before performing the bitwise OR operation with the sub-matrix (M - 1)×(N - 1), and the cumulative OR temporary matrix 2 is the matrix after performing the bitwise OR operation with the sub-matrix (M - 1)×(N - 1). When all the sub-matrices have completed the bitwise OR operation, the cumulative OR temporary matrix is the mother code prototype matrix.

[0060] Among them, the cumulative OR temporary matrix is a matrix that is all 0 initially. For example, if there are 5 sub-code rate matrices, then these five sub-code rate matrices will perform OR operations with this cumulative OR temporary matrix in sequence. After 5 OR operations are completed, the final cumulative OR temporary matrix is the mother code prototype matrix, and this mother code prototype matrix is the LDPC matrix used for verification.

[0061] Step S400, assign cyclic shift values to the mother code prototype matrix in an arithmetic progression manner.

[0062] The arithmetic progression method is to assign an equal difference value to each row of the mother code prototype matrix, set an initial value for the first column, and then calculate the values of each element in each row based on this equal difference value and the initial value.

[0063] Among them, according to the theory of no 4-cycle of QC-LDPC codes, the equal difference values of each row need to be different. The equal difference value can preferably select prime numbers in the range of 0 to Z as the equal difference value.

[0064] Exemplarily, in this embodiment, Z is taken as 256 for illustration. Therefore, for the first few rows, to meet the requirement that the last valid element is "0", the initial value of the first column needs to be obtained according to the row weight of that row. In this embodiment, the equal difference values of the 1st row to the 19th row are 0, 5, 7, 2, 3, 1, 23, 6, 10, 110, 214, 27, 167, 163, 149, 17, 223, 151, and 4 in sequence. The initial values of the 1st row to the 19th row in this embodiment are 0, 175, 150, 138, 246, 97, 206, 154, 106, 256, 126, 47, 61, 174, 197, 94, 62, 70, and 229 in sequence.

[0065] In this way, the shift values at various positions in the matrix can be calculated.

[0066] Step S500: Detect whether each sub-matrix in the mother code prototype matrix contains a 4-cycle under the current shift value. If it contains a 4-cycle, re-execute the step of assigning cyclic shift values to the mother code prototype matrix by the arithmetic progression method; if it does not contain a 4-cycle, the construction ends.

[0067] After the calculation is completed, it is necessary to check whether each sub-matrix contains a 4-cycle. A 4-cycle is a cycle composed of four 1s. If it does not contain a 4-cycle, the construction ends; if it contains a 4-cycle, it is necessary to re-execute the above step S400 until there is no 4-cycle in each sub-matrix.

[0068] As Figure 5 shown, it is the sum-product performance analysis of different half-port codes of each sub-matrix under an additive Gaussian noise channel after removing the 4-cycle through the above method. The decoding algorithm is the ideal sum-product decoding algorithm. The size in the figure is the sub-matrix size, the abscissa is the original bit error rate, and the ordinate is the uncorrected bit error rate. It can be seen that as the original bit error rate increases, the uncorrected bit error rates of each sub-matrix show a convergent state, indicating that the uncorrected bit error rates of each sub-matrix are effectively controlled after removing the 4-cycle.

[0069] The method for constructing an LDPC code of a flash memory according to this embodiment simplifies the structure of each sub-matrix, so that the LDPC code can reduce the shift calculation amount in subsequent error correction applications, and also simplifies the design structure. By assigning cyclic shift values to the prototype matrix by the arithmetic progression method, the random shift is reduced to a fixed shift, simplifying the hardware implementation complexity; simplifying the storage overhead of the cyclic shift value, only the initial value and the difference need to be stored. Then, through the detection of the shift value, it is ensured that the finally generated LDPC code will not have a cycle, increasing the stability of constructing the LDPC code, making the construction process of the finally constructed LDPC code simple. When actually calculating and using, it can ensure stable power consumption, reduce calculation operations, thereby reducing the burden on the hardware, and further increasing the work efficiency.

[0070] Figure 6 Fig. shows a device for constructing an LDPC code of a flash memory according to an embodiment of the present application, including: The first construction module 10 is used to determine the construction parameters of the LDPC code, and the construction parameters are used to construct the mother matrix of the LDPC code; The second construction module 20 is used to construct the prototype matrix of each sub-matrix, simplify the structure of each sub-matrix, and obtain each simplified sub-matrix; The merging module 30 is used to merge the simplified sub-matrices to obtain the sub-code rate matrix of the mother matrix, and merge each sub-code rate matrix to obtain the mother code prototype matrix; An assignment module 40 is configured to assign cyclic shift values to the prototype mother code matrix in an arithmetic progression manner. A detection module 50 is configured to detect whether each sub-matrix in the prototype mother code matrix contains a 4-cycle under the current shift value. If a 4-cycle is contained, the step of assigning cyclic shift values to the prototype mother code matrix by the arithmetic progression method is re-executed. If no 4-cycle is contained, the construction is completed.

[0071] This application also provides a terminal device, which includes a processor and a memory. The memory stores a computer program, and the processor is configured to execute the computer program to implement the method for constructing the LDPC code of the flash memory.

[0072] The terminal device in this embodiment may be an electronic device such as a computer, a mobile phone, or a tablet equipped with a flash memory. The LDPC code in the flash memory is constructed based on the method for constructing the LDPC code in the above embodiment.

[0073] This application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed on a processor, the method for constructing the LDPC code of the flash memory is implemented.

[0074] It can be understood that the device in this embodiment corresponds to the method in the above embodiment. The optional items in the above embodiment also apply to this embodiment, so they will not be described repeatedly here.

[0075] Among them, the processor may be an integrated circuit chip with signal processing capabilities. The processor may be a general-purpose processor, including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc., which can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0076] The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electric Erasable Programmable Read-Only Memory (EEPROM), etc. Among them, the memory is used to store computer programs, and after receiving the execution instruction, the processor can execute the computer program accordingly.

[0077] The computer-readable storage medium of the present application is used to store the computer program used in the above terminal device. For example, the computer-readable storage medium may include, but is not limited to: various media that can store program codes such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs.

[0078] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions, and operations of the devices, methods, and computer program products according to multiple embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the block may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the structure diagram and / or flowchart, as well as the combination of blocks in the structure diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0079] In addition, each functional module or unit in various embodiments of the present application can be integrated together to form an independent part, or each module can exist separately, or two or more modules can be integrated to form an independent part.

[0080] When the above-described functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application.

[0081] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application.

Claims

1. A method for constructing an LDPC code for a flash memory, characterized in that: include: Determining construction parameters of an LDPC code, wherein the construction parameters are used to construct a mother matrix of the LDPC code; Constructing prototype matrices of each submatrix, and simplifying the structure of each submatrix to obtain each simplified submatrix; Combining the simplified sub-matrices to obtain a sub-rate matrix of the mother matrix, and combining the sub-rate matrices to obtain a mother code prototype matrix; Assigning cyclic shift values ​​to the mother code prototype matrix by means of an arithmetic progression; Under the current shift value, it is detected whether each sub-matrix in the mother code prototype matrix contains 4 rings. If it contains 4 rings, the step of assigning a cyclic shift value to the mother code prototype matrix by the arithmetic progression method is re-executed. If it does not contain 4 rings, the construction is completed.

2. The method for constructing an LDPC code of a flash memory according to claim 1, wherein: The step of determining construction parameters of an LDPC code, wherein the construction parameters are used to construct a mother matrix of the LDPC code, includes: Calculate a boost factor according to hardware parameters of the target flash memory, and calculate the number of columns of the user data matrix according to the boost factor; The maximum code rate and the minimum code rate of the target flash memory are determined, and the number of rows of the mother matrix and the number of rows of each sub-matrix are calculated according to the number of columns of the user data matrix, the maximum code rate and the minimum code rate.

3. The method for constructing an LDPC code of a flash memory according to claim 1, wherein: The sub-matrices include a user data matrix, a rate compatibility matrix, an all-1 matrix, a dense matrix and a specific structure sub-matrix; The step of constructing a prototype matrix of each sub-matrix and simplifying the structure of each sub-matrix includes: The first row of the user data matrix is ​​set to 0, and the diagonal data of the rate compatible matrix is ​​set to 0; The dense matrix is ​​set to a full matrix, and based on a preset column weight, the column weight of each sub-matrix is ​​set to a value within a preset interval; the column weight is the number of 1s in a column of matrix data.

4. The method for constructing an LDPC code of a flash memory according to claim 3, characterized in that: The step of setting the column weight of each submatrix to a value within a preset interval based on the preset column weight further includes: The maximum column weight of the mother matrix is ​​not greater than the preset column weight+1; The maximum column weight of the user data matrix is ​​not greater than the preset column weight - 1; The maximum column weight of the rate compatibility matrix is ​​no greater than the preset column weight-1.

5. The method for constructing an LDPC code of a flash memory according to claim 3, wherein: Combining the simplified sub-matrices to obtain a sub-rate matrix of the mother matrix includes: Constructing a prototype matrix for each sub-matrix by a progressive edge algorithm, and merging each simplified sub-matrix according to a preset position; The number of rows and columns to be deleted is determined, the rows to be deleted are continuously deleted starting from the second row, and the columns to be deleted are continuously deleted starting from the second column of the rate compatibility matrix to obtain a sub-rate matrix of the mother matrix.

6. The method for constructing an LDPC code of a flash memory according to claim 1, wherein: The combining of the sub-rate matrices to obtain a mother code prototype matrix includes: The positions of the sub-coding rate matrices 1 are respectively logically ORed with the cumulative or temporary matrix to obtain the mother code prototype matrix.

7. The method for constructing an LDPC code of a flash memory according to claim 2, wherein: The assigning a cyclic shift value to the mother code prototype matrix by an arithmetic progression method includes: Select any prime number between 0 and the lifting factor as the arithmetic difference value of each row of the mother code prototype matrix; the arithmetic difference value of each row is different; Setting initial values ​​of each row for the first column of the mother code prototype matrix; According to the initial value of each row and the arithmetic difference value of each row, the cyclic shift value of each row is generated.

8. The method for constructing an LDPC code of a flash memory according to claim 2, wherein: The hardware parameters include firmware padding length, cyclic redundancy check length, minimum page capacity, maximum page capacity, throughput rate and operating frequency; The step of calculating the boost factor according to the hardware parameters of the target flash memory, and calculating the number of columns of the user data field according to the boost factor, comprises: Calculate the maximum codeword length according to the maximum page capacity and the number of codewords; Calculate the size of the user data field of each codeword according to the length of the firmware padding and the cyclic redundancy check; Calculating a boost factor according to the maximum codeword length, the throughput rate, the operating frequency, the size of the user data field of each codeword, and the target flash memory controller hardware parameters; The number of columns of the user data field is calculated according to the lifting factor and the size of the user data field of each codeword.

9. The method for constructing an LDPC code of a flash memory according to claim 8, characterized in that: The determining of the compatible maximum code rate and minimum code rate, and calculating the number of rows of the mother matrix and the number of rows of each sub-matrix according to the maximum code rate and the minimum code rate, comprises: According to a preset inequality, the number of rows of the mother matrix and the number of rows of each sub-matrix are calculated; The expression of the inequality is: ； ； In the formula, R is the minimum code rate, R1 is the maximum code rate, K is the number of columns of the user data field, M is the number of rows of the mother matrix, and M1 is the number of sub-matrix rows corresponding to the maximum code rate.

10. A flash memory LDPC code construction device, characterized in that: include: A first construction module, used to determine construction parameters of an LDPC code, wherein the construction parameters are used to construct a mother matrix of the LDPC code; The second construction module is used to construct a prototype matrix of each sub-matrix and simplify the structure of each sub-matrix to obtain each simplified sub-matrix; A merging module, configured to merge the simplified sub-matrices to obtain a sub-rate matrix of the mother matrix, and merge the sub-rate matrices to obtain a mother code prototype matrix; An assignment module, used to assign a cyclic shift value to the mother code prototype matrix by an arithmetic progression; A detection module is used to detect whether each sub-matrix in the mother code prototype matrix contains 4 rings under the current shift value. If it contains 4 rings, the step of assigning a cyclic shift value to the mother code prototype matrix by an arithmetic progression method is re-executed; if it does not contain 4 rings, the construction is terminated.

11. A terminal device, characterized in that: The terminal device comprises a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement the LDPC code construction method for a flash memory according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that: The computer program stores a computer program, which, when executed on a processor, implements the LDPC code construction method for a flash memory according to any one of claims 1 to 9.

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