Run-time antenna matching for near field communication wireless power transfer

Abstract

The invention relates to runtime antenna matching for near field communication wireless power transfer. Systems and methods for runtime antenna matching of wireless power devices are presented. The integrated circuit may include a controller. The integrated circuit may also include circuitry configured to sense a voltage in the switching converter. The circuit may be further configured to determine the presence or absence of a negative voltage spike in the sensed voltage. The controller may be configured to tune a capacitance of the antenna interface circuit between the switching converter and the antenna to perform impedance matching based on the presence or absence of a negative voltage spike in the sensed voltage.

Description

Technical Field

[0001] The present disclosure generally relates to apparatus and methods for antenna matching in a wireless power device. Specifically, runtime antenna matching that may be performed by a near field communication (NFC) wireless charging device is described. Background Art

[0002] Wireless power transfer using a near field communication (NFC) protocol (e.g., an NFC wireless power system) may occur between two devices including a near field communication (NFC) interface. Such an NFC wireless power system may include a poller having a transmit coil and a listener having a receive coil. In one aspect, the poller may be connected to a structure including a wireless charging area. In response to a device including the listener being placed near the device including the poller, the transmit coil and the receive coil may be inductively coupled to each other to establish an NFC communication link between the poller and the listener, and inductive transfer of alternating current (AC) power may occur using the established NFC communication link. Transfer of AC power from the poller to the listener may facilitate charging of the battery of the device including the listener. Summary of the Invention

[0003] In one embodiment, an integrated circuit for performing runtime antenna matching of a wireless power device is generally described. The integrated circuit may include a controller. The integrated circuit may further include circuitry configured to sense a voltage in a switched converter. The circuitry may be further configured to determine the presence or absence of a negative voltage spike in the sensed voltage. The controller may be configured to tune a capacitance of an antenna interface circuit between the switched converter and an antenna based on the presence or absence of a negative voltage spike in the sensed voltage to perform impedance matching.

[0004] In one embodiment, a device for performing runtime antenna matching of a wireless power device is generally described. The device may include an antenna. The device may further include an antenna interface circuit. The device may further include a transmitter configured to sense a voltage in a switched converter of the transmitter. The transmitter may be further configured to determine the presence or absence of a negative voltage spike in the sensed voltage. The transmitter may be further configured to tune a capacitance of an antenna interface circuit between the switched converter and the antenna based on the presence or absence of a negative voltage spike in the sensed voltage to perform impedance matching.

[0005] In one embodiment, a method for operating a wireless power device to perform matching during antenna operation is described generally. The method may include sensing a voltage in a switching converter. The method may also include determining the presence or absence of a negative voltage spike in the sensed voltage. The method may further include tuning a capacitance of an antenna interface circuit between the switching converter and the antenna based on the presence or absence of the negative voltage spike in the sensed voltage to perform impedance matching.

[0006] The following describes in detail other features, as well as structures and operations, of various embodiments with reference to the accompanying drawings. In the drawings, the same reference numerals indicate the same or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram illustrating an example system in which runtime antenna matching can be implemented for near - field communication wireless power transfer in one embodiment.

[0008] Figure 2 is a diagram illustrating an example embodiment in which runtime antenna matching can be implemented for near - field communication wireless power transfer in one embodiment.

[0009] Figure 3 is a diagram illustrating another example embodiment in which runtime antenna matching can be implemented for near - field communication wireless power transfer in one embodiment.

[0010] Figure 4 is a diagram illustrating one or more circuits in which runtime antenna matching can be implemented for near - field communication wireless power transfer in one embodiment.

[0011] Figure 5 is a diagram illustrating one or more circuits in which runtime antenna matching can be implemented for near - field communication wireless power transfer in one embodiment.

[0012] Figure 6 is a diagram illustrating a process for updating a count that can be used during runtime antenna matching for near - field communication wireless power transfer in one embodiment.

[0013] Figure 7 is a diagram illustrating a process for determining capacitance adjustment during runtime antenna matching for near - field communication wireless power transfer in one embodiment.

[0014] Figure 8 is a diagram illustrating waveforms of an example implementation of runtime antenna matching for near - field communication wireless power transfer in one embodiment.

[0015] Figure 9 is a flowchart illustrating a process for implementing runtime antenna matching for near - field communication wireless power transfer in one embodiment. Detailed implementation manners

[0016] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of the various embodiments of the present application. However, those of ordinary skill in the art can understand that the various embodiments of the present application can be practiced without these specific details. In other instances, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0017] The NFC wireless power system can provide charging in a static mode or a negotiation mode. The static mode can use a standard radio frequency (RF) field strength and provide a consistent power level, and the negotiation mode can use a relatively high RF field to support different power transfer classes, such as 250, 500, 750, and 1000 milliwatts (mW). In the NFC wireless power system, the poller and the listener can communicate with each other using the NFC communication protocol. In one aspect, the NFC wireless power system can use a specific base frequency (e.g., 13.56 megahertz (MHz)) and utilize the NFC communication link between two devices to control power transfer. To perform NFC communication, one device can apply or transmit a modulated signal (e.g., an amplitude-shift keying (ASK) signal) to another device, and the other device can demodulate the modulated signal.

[0018] Figure 1 FIG. is a diagram showing an example system in which current-mode demodulation can be implemented in NFC in one embodiment. System 100 may include an antenna interface circuit 102 and power devices, such as a transmitter 110 and a receiver 120, which are configured to wirelessly transfer power and data between them via inductive coupling. Although the transmitter 110 and the receiver 120 are described herein, each of the transmitter 110 and the receiver 120 can be configured to transmit and receive power or data between them via inductive coupling. The transmitter 110 may be referred to as a wireless power transmitter, and the receiver 120 may be referred to as a wireless power receiver. In an embodiment where the system 100 is configured as an NFC wireless power system, the transmitter 110 can be configured as a poller, and the receiver 120 can be configured as a listener.

[0019] The transmitter 110 can be configured to receive power from one or more power sources and wirelessly transmit AC power to the receiver 120. For example, the transmitter 110 can be configured to connect to a power source 122, such as an adapter or a direct current (DC) power source. The transmitter 110 can be a semiconductor device including a controller 104, a switching converter 106, a circuit 107, and a circuit 108. The transmitter 110 can be connected to an antenna 124. The switching converter 106 can be an integrated circuit (IC), which can be part of a power driver and is configured to convert one type of current to another type of current. As an example, the switching converter 106 can be configured as an inverter for converting a DC signal to an AC signal. As will be described in more detail below, the circuit 107 can be configured to sense a voltage signal in the switching converter 106 and transmit the voltage signal to the circuit 108. The circuit 108 can be configured to detect negative voltage spikes at two low-side metal oxide semiconductor field effect transistors (MOSFETs) labeled LS1 and LS2. In one embodiment, the circuit 107 and the circuit 108 can be mounted on the same circuit board and implemented as one circuit.

[0020] The controller 104 can be configured to control and operate the switching converter 106, the circuit 107, and other components of the transmitter 110. The controller 104 can include, for example, a processor, a central processing unit (CPU), a field programmable gate array (FPGA), or any other circuitry configured to control and operate the switching converter 106. Although described as a CPU in the illustrative embodiments, the controller 104 is not limited to a CPU in these embodiments and can include any other circuitry configured to control and operate the switching converter 106. In an example embodiment, the controller 104 can be configured to control the switching converter 106 to switch a switching device, such as a transistor, in the switching converter 106 by using a drive signal. The device switching in the switching converter 106 can drive the antenna 124 at a frequency and configuration range defined by a wireless power standard, such as the Wireless Charging (WLC) specification of the NFC Forum. The antenna 124 can include a resonant circuit, which includes one or more capacitors, inductors, resistors, and the one or more capacitors, inductors, resistors can form circuitry for outputting a communication signal 132 and transmitting AC power 134 to the receiver 120. The antenna interface circuit 102 can be connected to the transmitter 110 and includes one or more capacitors, inductors, resistors forming a filter, a matching network, or other circuitry for interfacing the transmitter 110 with the antenna 124.

[0021] The receiver 120 can be configured to receive the AC power 134 transmitted from the transmitter 110 and supply power to one or more loads 118 or other components of the target device including the receiver 120. The load 118 can include, for example, a battery charger configured to charge the battery of the target device 140, a DC-DC converter configured to supply DC power 136 to the processor, display, or other electronic components of the target device 140, or any other load of the target device 140. The target device can include an antenna interface circuit 112 and the receiver 120. The target device 140 can be, for example, a computing device, a smart device, a wearable device, or any other electronic device configured to wirelessly receive power. In other embodiments, the receiver 120 can be separated from the target device and connected to the target device via a wire or other components configured to supply power to the target device 140.

[0022] The receiver 120 can be a semiconductor device including a controller 114 and a switch converter 116. The receiver 120 can be connected to the antenna 126. The controller 114 can be an integrated circuit including, for example, a digital controller such as a microcontroller, a processor, a CPU, an FPGA, or any other circuitry configured to control and operate the switch converter 116. The antenna 126 can be connected to the antenna interface circuit 112, which includes one or more capacitors, inductors, resistors, and one or more capacitors, inductors, resistors can form a circuitry for outputting the communication signal 132 and transmitting the AC power 134 received by the antenna 126 from the transmitter 110. The antenna interface circuit 112 can include one or more capacitors, inductors, resistors forming a filter, a matching network, or other circuitry for interfacing the receiver 120 with the antenna 126. The switch converter 116 can be an IC configured to convert one type of current to another type of current. As an example, the switch converter 116 can be configured as a power rectifier for converting an AC signal to a DC signal. When configured as a power rectifier, the switch converter 116 can include a rectifier circuit such as a half-bridge rectifier, a full-bridge rectifier, or other types of rectifier circuits configured to rectify the power received via the antenna 126 into the power type required by the load 118. The controller 114 can be configured to execute application-specific programs and / or firmware to control and operate various components such as the antenna interface circuit 112 and the switch converter 116 of the receiver 120.

[0023] As an example, when the receiver 120 is placed near the transmitter 110, the magnetic field generated by the antenna 124 can induce a current in the antenna 126. The induced current causes the AC power 134 to be inductively transferred to the switch converter 116 via the antenna 126. The switch converter 116 can receive the AC power 134 and convert the AC power 134 into DC power 136. The DC power 136 is then provided to the load 118.

[0024] The transmitter 110 and the receiver 120 are also configured to exchange information or data, such as messages, via inductive coupling of the antenna 124 and the antenna 126. For example, before the transmitter 110 starts to transfer power to the receiver 120, a power contract can be agreed upon and created between the receiver 120 and the transmitter 110. For example, the receiver 120 can send a communication signal 132 or other data to the transmitter 110, the communication signal 132 or other data indicating power transfer information, such as, for example, the amount of power to be transferred to the receiver 120; a command 134 to increase, decrease, or maintain the power level of the AC power 134; a command to stop power transfer; or other power transfer information. In another example, in response to the receiver 120 being placed in a position near the transmitter 110, for example, close enough such that a transformer can be formed by the antenna 124 and the antenna 126 to allow power transfer, the receiver 120 can be configured to initiate communication by sending a signal requesting power transfer to the transmitter 110. In such a case, the transmitter 110 can respond to the request by establishing a power contract or starting to transfer power to the receiver 120 (e.g., if a power contract already exists). The transmitter 110 and the receiver 120 can transmit and receive the communication signal 132, data, or other information via inductive coupling of the antenna 124 and the antenna 126.

[0025] NFC is a short-range wireless communication technology that enables standardized communication between two devices, such as smartphones or smart tags. Traditionally, NFC can be used for data exchange, and NFC can be extended to allow wireless power transfer from a poller to a listener in a power level range of approximately 1 watt (W) to 5 W. A key challenge for NFC systems is antenna design and impedance matching for achieving optimal power transfer efficiency. The equivalent impedance seen by the receiver can vary widely, especially in wireless power applications.

[0026] As will be described in more detail below, the transmitter 110 of system 100 may perform runtime antenna matching techniques to continuously optimize the antenna impedance as the operating conditions change, using a reduced number of external components. To perform runtime antenna matching without additional external components, the circuit 107 in the transmitter 110 may be configured to sense the voltage in the switched-mode converter 106 and transmit a voltage signal to the circuit 108. The circuit 108 may be configured to detect negative voltage spikes. The controller 104 may be configured to use the detected voltage spikes to determine how to continuously match the antenna impedance to the output impedance of the transmitter 110.

[0027] Figure 2 FIG. [FIG. NUMBER] is a diagram illustrating an example circuit that may be implemented in a poller for performing runtime antenna matching for near-field communication wireless power transfer. Figure 2 The description of [COMPONENT NAME] may refer to Figure 1 the components shown in Figure 2 the embodiment shown in Figure 1 The antenna interface circuit 102 shown in [[FIGURE REFERENCE]] may be formed by a plurality of circuit components, such as resistors, inductors, and capacitors, which may be continuously tuned to match the input impedance of the antenna 124 to the output impedance of the transmitter 110. The antenna interface circuit 102 may include an electromagnetic compatibility (EMC) filter 202, a matching network 204, and a damping circuit 206. Additionally, the EMC filter 202 may include two inductors L1 and L2, and two variable capacitors VC1 and VC2. The matching network 204 may include four capacitors C1, C2, C3, and C4. The damping circuit 206 may include two resistors R1 and R2. The equivalent antenna circuit may include a resistor R3, an inductor L3, and a capacitor C7. The antenna interface circuit 102 may be connected to two nodes TX1, TX2 of the switched-mode converter 106 in the transmitter 110.

[0028] The switching converter 106 can send one or more drive signals 130 to the EMC filter 202 of the antenna interface circuit 102, and the one or more drive signals 130 can be square waves. The EMC filter 202 can convert the drive signal 130 into a sine signal 230 to reduce electromagnetic interference (EMI). Due to the high impedance inherent in an antenna (such as antenna 124 or antenna 126), the impedance needs to be matched between the output of the transmitter 110 and the input of the antenna 124. The sine signal 230 output by the EMC filter 202 can be transmitted through the matching network 204, where the arrangement of the capacitors C1, C2, C3, and C4 in the matching network 204 can allow the impedance in the antenna 124 to match the output impedance of the transmitter 110. In one embodiment, the damping circuit 206 can include optional components configured to reduce the quality (Q) factor of the antenna 124. The resistors R1 and R2 in the damping circuit 206 can increase the bandwidth of the system by reducing the Q factor of the antenna. Similarly as Figure 2 shown, the antenna 124 can be modeled by at least the resistor R3, the inductor L3, and the capacitor C5. The antenna 124 can be configured to transmit a communication signal from the transmitter 110 to the receiver 120 by generating a magnetic field.

[0029] Referring Figure 1 to the embodiment shown, the circuit 107 can measure the voltage in the switching converter 116 (e.g., the voltage across LS1 and LS2). The circuit 108 can detect the presence or absence of voltage spikes, such as negative voltage spikes, in the voltage measured by the circuit 107. The controller 104 can tune one or more components in the antenna interface circuit 102 based on the presence or absence of the voltage spikes, and the presence or absence of the voltage spikes can be indicated by the output of the circuit 108. In one embodiment, the controller 104 can tune the variable capacitors VC1 and VC2 by changing their voltages. The tuning of the variable capacitors VC1 and VC2 can cause the antenna 124 to be tuned to match the output impedance of the transmitter 110. By tuning VC1 and VC2, the resonant frequency of the antenna interface circuit 102 can be adjusted to correspond to the switching frequency of the switching converter 106. The correspondence between the resonant frequency of the antenna interface circuit 102 and the switching frequency of the switching converter 106 can make the load impedance of the transmitter 110 a pure resistance, thereby avoiding reactive losses, and the impedance of the antenna 124 can be matched to the output impedance of the transmitter 110.

[0030] Figure 3 is a diagram showing another example circuit that can be implemented in a poller. The another example circuit can perform runtime antenna matching for near-field communication wireless power transfer. In Figure 3In another exemplary embodiment shown, the antenna interface circuit 102 may be configured to series capacitors and switches C1a, C2a, ..., Cna and C1b, C2b, ..., Cnb in the EMC filter 202. As an alternative method of tuning the antenna 124 using variable capacitors VC1 and VC2 (as Figure 2 shown), the capacitors C1a, C2a, ..., Cna and C1b, C2b, ..., Cnb may be switched into or out of the EMC filter 202 to tune the antenna 124. Each capacitor in the EMC filter 202 may be serially connected to a switch, and each connected switch may be controlled by the controller 104 to switch the connected capacitor into or out of the EMC filter 202. Some capacitors in the EMC filter 202 may be serially connected to each other, and some capacitors in the EMC filter 202 may be connected in parallel to each other. The series and parallel connections, along with having corresponding switches for each capacitor, may allow the controller 104 to perform different degrees of tuning on the antenna 124. The controller 104 may control the switches to enable or disable the corresponding capacitors to change the impedance of the antenna 124. For example, switching two serially connected capacitors into or out of the EMC filter 202 may have a smaller impact on the impedance of the antenna 124 compared to switching two capacitors connected in parallel. By selectively switching the capacitors in the EMC filter 202, the resonant frequency of the antenna interface circuit 102 may be adjusted to correspond to the switching frequency of the switch converter 106. The correspondence between the resonant frequency of the antenna interface circuit 102 and the switching frequency of the switch converter 106 may cause the load impedance of the transmitter 110 to be a pure resistance, thereby avoiding reactive losses, and the impedance of the antenna 124 may be matched to the output impedance of the transmitter 110.

[0031] Figure 4 FIG. is a diagram showing one or more circuits that may be implemented for runtime antenna matching for near field communication wireless power transfer in one embodiment. In Figure 4In the illustrated embodiment, the switching converter 106 can be an inverter configured to drive the antenna 124. The switching converter 106 can be formed by two half-bridge circuits, the two half-bridge circuits including two high-side metal oxide semiconductor field effect transistors (MOSFETs) HS1, HS2 and two low-side MOSFETs LS1, LS2. Two nodes TX1 and TX2 are driven by the switches HS1, HS2, LS1, LS2 of the switching converter 106 and can generate two square waves with a duty cycle of 50% and a relative phase shift of 180 degrees. The circuit 107 can include a circuit 152 and a circuit 154. The circuit 152 can be configured to sense the voltage on LS1 by measuring the voltage between the TX1 node and the power supply ground (PVSS). The circuit 154 can be configured to sense the voltage on LS2 by measuring the voltage between the TX2 node and the PVSS.

[0032] As an example, the circuit 152 includes a clamping circuit 501, and the clamping circuit 501 can be connected between the TX1 node and the comparator 402. The clamping circuit 501 can be a MOSFET or a circuit configured to limit the output voltage to shield any high voltage at TX1. The comparator 402 can be configured to generate a voltage signal CO1. The circuit 154 includes a clamping circuit 502, and the clamping circuit 502 can be connected between the TX2 node and the comparator 404. The clamping circuit 502 can be a MOSFET or a circuit configured to limit the output voltage to shield any high voltage at TX2. The comparator 404 can be configured to generate a voltage signal CO2.

[0033] In one embodiment, the switch converter 106 may operate in a three-state mode, in which the switches HS1, HS2, LS1, and LS2 are turned off. When the switches HS1, HS2, LS1, and LS2 are turned off, their body diodes may still have the ability to conduct. Therefore, the circuits 152, 154 may still sense low voltage signals (e.g., zero, near zero, or a relatively low voltage representing logic low). The sensed low voltage signals may be provided to the comparators 402, 404 in the circuits 152, 154, respectively. The comparator 402 may output a voltage signal CO1 and the comparator 404 may output a voltage signal CO2. In one embodiment, the circuit 108 may be configured to use the voltage signals CO1, CO2 to detect negative spikes in the voltages measured from the nodes TX1 and TX2 at the end of a switching cycle. In one embodiment, if there are glitches or negative voltage spikes in the voltages measured from LS1, LS2 at the end of a switching cycle, the voltage signals CO1, CO2 may be high voltage signals (e.g., "1" or a relatively high voltage representing logic high). In one embodiment, the circuit 108 may be configured to use the voltage signals CO1, CO2 to detect negative spikes in the voltages measured from the nodes TX1 and TX2 at the start of a switching cycle. In another embodiment, the circuit 108 may be configured to use the voltage signals CO1, CO2 to detect positive spikes in the voltages measured from HS1 and HS2 at the end of a switching cycle.

[0034] Figure 5 is a diagram showing one or more circuits that may be implemented for runtime antenna matching for near field communication wireless power transfer. In Figure 5In the illustrated embodiment, circuit 152 and circuit 154 are respectively connected to circuits 156 and 158 in circuit 108. Circuit 156 includes an inverter 506, an AND gate 508, a rising edge filter 510, and a C element 512. Circuit 155 can receive the voltage signal CO1 from circuit 107. Circuit 155 can also receive the gate-source voltage of LS1, labeled VGS_LS1, from the switching converter 106. The inverter 506 can invert VGS_LS1, and the inverted VGS_LS1 and the voltage signal CO1 can be provided as inputs to the AND gate 508. When LS1 is turned off, VGS_LS1 can gradually drop to zero, and the inverter 506 can output a voltage representing logic high (or "1"), which causes the AND gate 508 to pass CO1 to the rising edge filter 510 regardless of the state or value of CO1. The rising edge filter 510 can be a circuit configured to filter the voltage signal CO1 to reduce any high-frequency bouncing caused by the comparator 402. The C element 512 can be a logic circuit that maintains its current state unless both inputs are the same. If CO1 remains at a high voltage for a predefined amount of time dT, the C element 512 can latch a high voltage at its output 514 within dT. The output 514 of the C element 512 remaining high within dT can indicate that the voltage at node TX1 has a glitch, i.e., a negative voltage spike.

[0035] Circuit 158 includes an inverter 516, an AND gate 518, a rising edge filter 520, and a C element 522. Circuit 158 can receive the voltage signal CO2 from circuit 107. Circuit 158 can also receive the gate-source voltage of LS2, labeled VGS_LS2, from the switching converter 106. The inverter 516 can invert VGS_LS2, and the inverted VGS_LS2 and the voltage signal CO2 can be provided as inputs to the AND gate 518. When LS2 is turned off, VGS_LS2 can gradually drop to zero, and the inverter 516 can output a voltage representing logic high (or "1"), which causes the AND gate 518 to pass CO2 to the rising edge filter 520 regardless of the state or value of CO2. The rising edge filter 520 can be a circuit configured to filter the voltage signal CO2 to reduce any high-frequency bouncing caused by the comparator 404. The C element 522 can be a logic circuit that maintains its current state unless both inputs are the same. If CO2 remains at a high voltage for a predefined time dT, the C element 522 can latch a high voltage at its output 524 within dT. The output 524 of the C element 522 remaining high within dT can indicate that the voltage at node TX2 has a glitch, i.e., a negative voltage spike.

[0036] Figure 6FIG. is a flowchart showing a process for updating a count in one embodiment, where the count can be used in a runtime antenna match for near field communication wireless power transfer. Figure 6 The illustrated process 600 may include one or more operations, actions, or functions as shown in one or more of the blocks such as blocks S601, S602, S603, S604, S605, S606, S607, S608, S609, S610, S611, S612, S613, S614, and / or S615. Although illustrated as discrete blocks, depending on the desired implementation, the various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, executed in a different order, or executed in parallel. Figure 6 The description may refer to Figures 1 to 5 the components shown in

[0037] In one aspect, to achieve an exact match between the output impedance of the transmitter 110 and the input impedance of the matching network 204, the input impedance of the matching network 204 needs to be purely resistive. To make the input impedance of the matching network 204 purely resistive, the voltages at nodes TX1, TX2 need to be in phase with the currents flowing through TX1, TX2. When the voltages and currents at nodes TX1, TX2 are in phase, the zero current event is also in phase with the zero voltage event. In one aspect, the voltages at nodes TX1, TX2 are known because the voltages are provided by the transmitter 110. To measure the currents at nodes TX1, TX2, the controller 104 may execute Figure 6 the process 600 shown to insert the tri - state mode of the switch converter 106 at a time close to the zero voltage event. During the tri - state mode, the controller 104 may detect the presence or absence of a negative voltage spike in the voltages at nodes TX1, TX2. The presence or absence of a negative voltage spike may indicate the direction of the current flowing through nodes TX1, TX2 (e.g., positive or negative). The direction of the current may indicate the relative phase between the voltage and the current and can be used to determine how to adjust Figure 2 VC1, VC2 in Figure 3 or which switch in

[0038] The process 600 starts at block S601, where the controller 104 sets the count C to an initial value, such as C = 32. The count C may represent the number of consecutive negative voltage spike presences or absences counted by the controller 104. The maximum value of the count C may be programmable, and the minimum value of the count C may be set to zero. In one embodiment, the initial value of C may be the median between the maximum and minimum values of C (e.g., rounded to the nearest integer). For example, if the maximum value of C is 63 and the minimum value is zero, the initial value of C may be set to 32 in block S601.

[0039] At block S603, the controller 104 can drive the switch converter 106 acting as an inverter by alternately switching pairs of HS1, LS2 and HS2, LS1. At block S603, HS1 and LS2 are turned on, and HS2 and LS1 are turned off. At block S605, the clock of the controller 104 can transition from a low state to a high state, i.e., a rising edge event occurs. In response to the rising edge event, process 600 can proceed to block S607 where the controller 104 can start a tri-state mode by turning off HS1, HS2, LS1, and LS2. In one aspect, since HS1 and LS2 are turned on at block S603, when the controller 104 turns off HS1 and LS2 for the tri-state mode, the voltage at LS2 may take some time to drop to zero. Inserting the tri-state mode in response to the rising edge event can allow sufficient voltage to be fed into the comparator 404 of the circuit 154 to measure the voltage across LS2 from nodes TX2 and PVSS. Thus, at block S607, the controller 104 inserts the tri-state mode close to the zero voltage event (e.g., before the voltage at LS2 becomes zero).

[0040] During the tri-state time or tri-state mode, the controller 104 can execute blocks S609, S611, S613, and S615. At block S609, the controller 104 can use circuits 107, 108 to detect the presence or absence of voltage spikes in the voltages measured from nodes TX1 and TX2. In response to the controller 104 detecting the absence of voltage spikes at block S609, process 600 can proceed to block S611 to update the value of count C. The absence of negative voltage spikes at block S609 can indicate that the resonant frequency Fres needs to be increased. In response to the controller 104 detecting the presence of voltage spikes at block S609, process 600 can proceed to block S613 to update the value of count C. The presence of negative voltage spikes at block S609 can indicate that the resonant frequency Fres needs to be decreased. At block S611, the absence of voltage spikes can indicate that the resonant frequency (“Fres”) is less than or equal to the switching frequency (“Fsw”) of the switch converter 106. Thus, the controller 104 can determine at block S611 that Fres ≤ Fsw. Additionally, at block S611, the count C can be set to the larger of 0 and C – 1. For example, if C = 32, then at block S613, the count C will be set to 31 since 32 - 1 is greater than zero. Thus, the count C will not be less than zero. At block S615, the tri-state time can elapse, and the controller 104 can return to operating the switch converter 106 by switching HS1, HS2, LS1, LS2 by proceeding to block S602.

[0041] At block S613, the presence of a voltage spike can indicate that the resonant frequency Fres is greater than or equal to the switching frequency Fsw of the switch converter 106. Thus, the controller 104 can determine in block S613 that Fres > Fsw. Additionally, at block S613, the count C can be set to the smaller value between the maximum C (such as 63) and C + 1. For example, if C = 32, then at block S611, the count C will be set to 33 because 32 + 1 is less than the maximum value of C, which is 63.

[0042] In Figure 6 the example shown, since at block S603, HS1 and LS2 are turned on and HS2 and LS1 are turned off, the controller 104 can turn off HS1 and LS2 and turn on HS2 and LS1 in block S602. At block S604, the clock of the controller 104 can transition from a high state to a low state, i.e., a falling edge event occurs. In response to the falling edge event, process 600 can proceed to block S606, where the controller 104 can start a tri-state mode by turning off HS1, HS2, LS1, and LS2. In one aspect, since HS2 and LS1 are turned on in block S602, when the controller 104 turns off HS2 and LS1 to enter the tri-state mode, the voltage at LS1 may take some time to drop to zero. Inserting the tri-state mode in response to the falling edge event can allow sufficient voltage to be fed into the comparator 402 of the circuit 152 to measure the voltage across LS1 from nodes TX1 and PVSS. Thus, at block S606, the controller 104 inserts a tri-state mode close to the zero voltage event (e.g., before the voltage at LS1 becomes zero). Blocks S608, S610, S612, and S614 can be the same as blocks S609, S611, S613, and S615, respectively. At the end of the tri-state time at block S614, process 600 can return to block S603.

[0043] According to process 600, the controller 104 can perform negative voltage spike detection to update the count C at each transition of the clock of the transmitter 110, each transition including a rising edge and a falling edge. Thus, the count C can be updated for each clock cycle of the transmitter 110. As Figure 7 described, the count C can be used to determine whether to increase Figure 2 the capacitances of VC1 and VC2 shown, or selectively switch Figure 3 the capacitors shown to tune the antenna 124 of the transmitter 110.

[0044] Figure 7 is a diagram showing a process for determining capacitance adjustment in runtime antenna matching for near-field communication wireless power transfer in one embodiment. Figure 7The process 700 shown may include one or more operations, actions, or functions as shown in one or more of the blocks S701, S703, S705, S707, S709, and / or S711. Although illustrated as discrete blocks, depending on the desired implementation, the various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, performed in a different order, or performed in parallel. Figure 7 The description of Figures 1 to 6 may refer to the components shown in

[0045] The process 700 may be executed by the controller 104 to determine whether to increase or decrease the capacitance of the EMC filter as shown in Figure 2 and Figure 3 based on the accumulation of the count C. The process 700 may start at block S701, where the controller 104 may begin to execute the process 700. At block S703, the controller 104 may determine whether the polling timer has expired. In one embodiment, the polling timer may be configured to track the number of clock cycles of the transmitter 110. As an example, the polling timer may track the clock cycles of the transmitter 110 and assert an expiration time for every five clock cycles, or some other programmable number of cycles less than the maximum value of C.

[0046] In response to the polling timer expiring at block S703, the controller 104 may determine at block S705 whether the count C has reached the maximum value of 63. If the count C has reached the maximum value of 63, then at block S709, the controller 104 may increase the capacitance in the EMC filter 202 as shown in Figure 2 or Figure 3 . For example, the controller 104 may increase the capacitance of the EMC filter 202 by increasing the capacitance of VC1 and VC2 in Figure 2 , or by switching an additional capacitor into the EMC filter 202 as shown in Figure 3 . If the count C has not reached the maximum value of 63, the process 700 may proceed to block S707 to check whether the value of the count C has reached the minimum value of zero.

[0047] If the count C has reached zero, then at block S711, the controller 104 may decrease the capacitance in the EMC filter 202 as shown in Figure 2 or Figure 3 . For example, the controller 104 may decrease the capacitance of the EMC filter 202 by decreasing the capacitance of VC1 and VC2 in Figure 2 , or by removing from Figure 3Capacitors are switched out in the EMC filter 202 shown to reduce the capacitance of the EMC filter 202. After increasing the capacitance in block S709 or reducing the capacitance at block S711, the process 700 may return to block S701 to wait for the next expiration of the polling timer at block S703.

[0048] Figure 8 FIG. is a diagram showing waveforms of an example implementation of runtime antenna matching for near - field communication wireless power transfer in one embodiment. Figure 8 The description of may refer to Figures 1 to 7 the components shown in. The waveform 802 depicts the voltages at nodes TX1 and TX2 of the switch converter 106 within a half - cycle. The waveform 804 depicts the voltages of VC1 and VC2 applied to the antenna interface circuit 102 as shown in Figure 2 FIG.. The waveform 806 is a plot of the actual values of the variable capacitors (e.g., VC1 and VC2 of the antenna interface circuit 102 shown in Figure 2 FIG.). In the first time period 812, due to the presence of negative voltage spikes in the voltages measured from nodes TX1, TX2, the resonant frequency Fres can be significantly greater than the switching frequency Fsw. According to Figure 6 the process 600 in, when Fres is greater than Fsw, the count C can be incremented. Then according to Figure 7 the process 700 in, when the count C reaches its maximum value, the controller 104 can increase the capacitance of VC1, VC2. Note that in the waveform 804, the voltages applied to VC1, VC2 are similar to a step function because the controller 104 adjusts the capacitance of VC1, VC2 based on Figure 7 the expiration of the polling time in and based on whether the count C has reached its maximum value. In other words, to maintain processing power, it may not be necessary to adjust the voltages applied to VC1, VC2 in each cycle. In the second time period 814, the resonant frequency Fres is still greater than the switching frequency Fsw because of the presence of negative voltage spikes in the voltages measured from nodes TX1, TX2 at the start of the switching cycle. Thus, the controller 104 can continue to increase the capacitance of VC1, VC2 during the time period 814.

[0049] In the third time period 816, the resonant frequency Fres is equal to the switching frequency Fsw because there are no negative voltage spikes in the voltages measured from nodes TX1, TX2 at the start of the switching cycle. Thus, the capacitance of VC1, VC2 can be considered the optimal capacitance that makes the impedance of the antenna 124 match the output impedance of the transmitter 110. In one embodiment, according to Figure 6 the process 600 in, when Fres is equal to Fsw, the count C can be decremented. Then according to Figure 7In process 700, when the count C reaches its minimum value or zero, the controller 104 may reduce the capacitance of VC1 and VC2.

[0050] In the fourth time period 818, the resonant frequency Fres becomes less than the switching frequency Fsw because there is no negative voltage spike in the voltages measured from nodes TX1 and TX2 at the start of the switching cycle. According to Figure 6 In process 600, when Fres is less than Fsw, the count C may be decreased. Then according to Figure 7 In process 700, when the count C reaches its minimum value or zero, the controller 104 may reduce the capacitance of VC1 and VC2. In the fifth time period 820, the resonant frequency Fres remains less than the switching frequency Fsw because there is no negative voltage spike in the voltages measured from nodes TX1 and TX2 at the start of the switching cycle. Accordingly, the controller 104 may continue to reduce the capacitance of VC1 and VC2 during the time period 820.

[0051] Figure 9 is a flowchart illustrating a process for implementing runtime antenna matching for near - field communication wireless power transfer in one embodiment. Process 900 may include one or more operations, actions, or functions as shown in one or more of blocks 901, 903, and / or 905. Although illustrated as discrete blocks, depending on the desired implementation, the various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, executed in a different order, or executed in parallel.

[0052] Process 900 may be implemented by a wireless power transfer device (e.g., a transmitter, a receiver, or a transceiver). Process 900 may begin at block 901, where circuitry in the wireless power transfer device may sense a voltage in a switched - mode converter. In one embodiment, the circuitry may detect a clock event of a clock signal. The circuitry may operate the switched - mode converter in a tri - state mode in response to detecting the clock event. The circuitry may sense the voltage in the switched - mode converter during the tri - state mode.

[0053] Process 900 can continue from block 901 to block 903. At block 903, the circuit can determine the presence or absence of a negative voltage spike in the sensed voltage. Process 900 can continue from block 903 to block 905. At block 905, the circuit can tune the capacitance of the antenna interface circuit between the switch converter and the antenna based on the presence or absence of a negative voltage spike in the sensed voltage to perform impedance matching. In one embodiment, the circuit can tune the capacitance of the antenna interface circuit by determining the presence of a negative voltage spike in the sensed voltage. The circuit can increase the capacitance of the antenna interface circuit in response to determining the presence of a negative voltage spike in the sensed voltage. The circuit can further determine the absence of a negative voltage spike in the sensed voltage. The circuit can decrease the capacitance of the antenna interface circuit in response to determining the absence of a negative voltage spike in the sensed voltage.

[0054] In one embodiment, the circuit can determine that the number of consecutive negative voltage spikes present in the sensed voltage has reached a first predefined value, and increase the capacitance of the antenna interface circuit in response to determining that the number of consecutive negative voltage spikes present has reached the first predefined value. In one embodiment, the circuit can determine that the number of consecutive negative voltage spikes absent in the sensed voltage has reached a second predefined value, and decrease the capacitance of the antenna interface circuit in response to determining that the number of consecutive negative voltage spikes absent has reached the second predefined value.

[0055] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified (multiple) logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. Note that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by special purpose hardware systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

[0056] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to limit the invention. Unless the context clearly dictates otherwise, as used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms. It will be further understood that the terms "comprises", "comprising", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0057] All structural, material, acts, and equivalents of the means or step plus function elements in the appended claims, if any, are intended to include any structure, material, or act for performing the function in combination with other elements specifically claimed. The description of the invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. An integrated circuit, comprising: Controller; A circuit, the circuit being configured as: sensing voltage in a switching converter; and determining the presence or absence of a negative voltage spike in the sensed voltage; as well as A controller is configured to tune a capacitance of an antenna interface circuit between the switching converter and an antenna to perform impedance matching based on the presence or absence of the negative voltage spike in the sensed voltage.

2. The integrated circuit of claim 1, wherein the controller, the switching converter, and the circuit are part of a poller of a near field communication (NFC) wireless power transfer system. 3 . The integrated circuit of claim 1 , wherein the circuit is configured to sense the voltage from a low-side switch in the switching converter. 4 . The integrated circuit of claim 1 , wherein the circuit is configured to sense the voltage in the switching converter during a tri-state mode of the switching converter.

5. The integrated circuit of claim 1 , wherein the controller is configured to: determining the presence of the negative voltage spike in the sensed voltage; In response to determining that the negative voltage spike is present in the sensed voltage, increasing the capacitance of the antenna interface circuit; determining that the negative voltage spike is absent in the sensed voltage; and In response to determining that the negative voltage spike is absent in the sensed voltage, the capacitance of the antenna interface circuit is reduced. 6 . The integrated circuit of claim 1 , wherein the controller is configured to tune the capacitance of the antenna interface circuit by tuning a capacitance of an electromagnetic compatibility (EMC) filter in the antenna interface.

7. The integrated circuit of claim 1 , wherein the controller is configured to: determining that a number of consecutive negative voltage spikes in the sensed voltage has reached a first predefined value; responsive to determining that the number of consecutive negative voltage spikes present reaches the first predefined value, increasing the capacitance of the antenna interface circuit; determining that the number of consecutive absences of negative voltage spikes in the sensed voltage has reached a second predefined value; and In response to determining that the number of consecutive negative voltage spikes are absent reaches the second predefined value, the capacitance of the antenna interface circuit is reduced.

8. The integrated circuit of claim 1, wherein: The controller is configured to: detecting a clock event of a clock signal; and responsive to detection of the clock event, operating the switching converter in a tri-state mode; and The circuit is configured to sense the voltage in the switching converter during the tri-state mode.

9. A device comprising: antenna; Antenna interface circuit; as well as A transmitter, the transmitter being configured to: sensing a voltage in a switching converter of the transmitter; determining the presence or absence of a negative voltage spike in the sensed voltage; as well as Based on the presence or absence of the negative voltage spike in the sensed voltage, a capacitance of the antenna interface circuit between the switching converter and the antenna is tuned to perform impedance matching. 10 . The device of claim 9 , wherein the transmitter is a poller of a Near Field Communication (NFC) wireless power transfer system.

11. The device of claim 9, wherein the transmitter is configured to sense the voltage from a low-side switch in the switching converter. 12 . The device of claim 9 , wherein the transmitter is configured to sense the voltage in the switching converter during a tri-state mode of the switching converter.

13. The apparatus of claim 9, wherein the transmitter is configured to: determining the presence of the negative voltage spike in the sensed voltage; In response to determining that the negative voltage spike is present in the sensed voltage, increasing the capacitance of the antenna interface circuit; determining that the negative voltage spike is absent in the sensed voltage; and In response to determining that the negative voltage spike is absent in the sensed voltage, the capacitance of the antenna interface circuit is reduced.

14. The device of claim 9, wherein the transmitter is configured to tune the capacitance of the antenna interface circuit by tuning a capacitance of an electromagnetic compatibility (EMC) filter in the antenna interface.

15. The apparatus of claim 9, wherein the transmitter is configured to: determining that a number of consecutive negative voltage spikes in the sensed voltage has reached a first predefined value; responsive to determining that the number of consecutive negative voltage spikes present reaches the first predefined value, increasing the capacitance of the antenna interface circuit; determining that the number of consecutive absences of negative voltage spikes in the sensed voltage has reached a second predefined value; and In response to determining that the number of consecutive negative voltage spikes are absent reaches the second predefined value, the capacitance of the antenna interface circuit is reduced.

16. The apparatus of claim 9, wherein: The transmitter is configured as: Detecting clock events of clock signals; responsive to detection of the clock event, operating the switching converter in a tri-state mode; and The voltage in the switching converter is sensed during the tri-state mode.

17. A method for operating a wireless power device, the method comprising: sensing voltage in a switching converter; determining the presence or absence of a negative voltage spike in the sensed voltage; as well as Based on the presence or absence of the negative voltage spike in the sensed voltage, a capacitance of an antenna interface circuit between the switching converter and an antenna is tuned to perform impedance matching.

18. The method of claim 17, wherein tuning the capacitance of the antenna interface circuit comprises: determining the presence of the negative voltage spike in the sensed voltage; In response to determining that the negative voltage spike is present in the sensed voltage, increasing the capacitance of the antenna interface circuit; determining that the negative voltage spike is absent in the sensed voltage; and In response to determining that the negative voltage spike is absent in the sensed voltage, the capacitance of the antenna interface circuit is reduced.

19. The method according to claim 17, further comprising: determining that a number of consecutive negative voltage spikes in the sensed voltage has reached a first predefined value; responsive to determining that the number of consecutive negative voltage spikes present reaches the first predefined value, increasing the capacitance of the antenna interface circuit; determining that the number of consecutive absences of negative voltage spikes in the sensed voltage has reached a second predefined value; and In response to determining that the number of consecutive negative voltage spikes are absent reaches the second predefined value, the capacitance of the antenna interface circuit is reduced.

20. The method of claim 17, further comprising: Detecting clock events of clock signals; responsive to detection of the clock event, operating the switching converter in a tri-state mode; as well as The voltage in the switching converter is sensed during the tri-state mode.

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