Data transmission method, device, equipment and medium
By optimizing the FPGA, reducing the number of general input and output ports, and configuring a preset conversion protocol to convert data format and bit width, the problem of limited number of FPGA chip interfaces is solved, efficient data transmission is achieved and circuit board complexity is reduced.
Patent Information
- Application Number
- CN202510360610.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2025-06-17
AI Technical Summary
When using the FPGA prototype verification platform to conduct prototype verification on BMC chips, due to the limited number of interfaces of FPGA chips, it is difficult to support the numerous interfaces of BMC chips, especially USB interfaces, which requires at least two FPGA chips to be interconnected to achieve prototype verification. In addition, the transmission of low-speed signals requires a large number of GPIO ports, which increases the wiring complexity of the circuit board.
By optimizing the original FPGA, the number of general-purpose input and output ports is reduced, and a preset conversion protocol is configured for the optimized FPGA, format and bit-width conversion of the data to be transferred in each clock cycle, reorganize it into one data packet, and then transfer the packet to another FPGA through one universal input and output port.
It reduces the number of universal input and output ports required for data transmission, reduces the circuit board's trace complexity, and avoids the problem of insufficient universal input and output ports when high data volumes.
Smart Images
Figure CN120166150A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication technologies, and in particular, to a data transmission method, apparatus, device, and medium. Background Art
[0002] FPGA (Field Programmable Gate Array) prototype verification is a relatively mainstream and mature verification method in current SoC (System on Chip) chip design. When the SoC chip is a BMC (Baseboard Management Controller) chip, due to the numerous interfaces of the BMC chip, including not only high-speed interfaces for communicating with servers, such as PCIe (Peripheral Component Interconnect express) interfaces, Ethernet interfaces, etc., but also low-speed interfaces, such as I2C (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver / Transmitter), PECI (Platform Environment Control Interface) interfaces, etc., and also including peripheral interfaces of the BMC chip, such as USB (Universal Serial Bus) interfaces, etc. Based on this, when using an FPGA prototype verification platform to perform prototype verification on a BMC chip, since the number of interfaces of a single FPGA chip is limited, it is difficult to support the numerous interfaces of the BMC chip, especially the USB interface. A single USB interface requires hundreds of IO (Input / Output) interfaces. Therefore, generally, at least two FPGA chips need to be interconnected to achieve prototype verification of the BMC chip. And for the low-speed signals between the interconnected FPGA chips, they generally need to be transmitted through a large number of GPIO (General-purpose input / output) ports between the FPGA chips. This not only increases the routing complexity of the circuit board, but also when there are many low-speed signals, it may not be achievable due to insufficient GPIO ports.
[0003] It can be seen that how to achieve data transmission between FPGA chips with fewer GPIO ports is a problem that needs to be solved by those skilled in the art. Summary of the Invention
[0004] An object of an embodiment of the present invention is to provide a data transmission method, apparatus, device, and medium, which can solve the problem of realizing data transmission between FPGA chips with fewer general input / output ports. The specific solution is as follows:
[0005] In a first aspect, the present invention provides a data transmission method applied to a first optimized FPGA, including:
[0006] Obtaining, in each clock cycle, each piece of data to be transmitted that needs to be transmitted to a second optimized FPGA through a general input / output port; wherein, the optimized FPGA is an FPGA obtained by optimizing an original FPGA; the number of general input / output ports in the optimized FPGA is less than that of the original FPGA;
[0007] Converting the format of the data to be transmitted according to a preset conversion protocol, determining the number of clock cycles required for the data to be transmitted to be transmitted to the second optimized FPGA based on a preset transmission bit width, and performing bit width conversion on the data to be transmitted, and determining a reorganized data packet according to the data to be transmitted after bit width conversion and their respective corresponding clock cycle numbers;
[0008] Transmitting the reorganized data packet to the second optimized FPGA through a first general input / output port for data transmission locally; the preset transmission bit width is the transmission bit width of the first general input / output port in the first optimized FPGA, and the preset transmission bit width is determined based on the port information of the first general input / output port in the first optimized FPGA and the original FPGA.
[0009] Optionally, the process of determining the preset transmission bit width includes:
[0010] Determining a first data transmission amount based on the transmission bit width and data transmission mode of the first general input / output port in the original FPGA;
[0011] Counting the number of the first general input / output ports in the original FPGA to obtain a first port number, and determining a first total data amount according to the first data transmission amount and the first port number;
[0012] Counting the number of the first general input / output ports in the first optimized FPGA to obtain a second port number, and determining a second data transmission amount based on the ratio between the first total data amount and the second port number;
[0013] Determining the preset transmission bit width based on the second data transmission amount and the data transmission mode of the first general input / output port in the first optimized FPGA;
[0014] Wherein, the amount of transmitted data is the amount of data that can be transmitted by the general-purpose input / output port within one clock cycle; the data transmission mode includes a single-edge data transmission mode and a double-edge data transmission mode. When the data transmission mode is the single-edge data transmission mode, the amount of transmitted data is the transmission bit width of the general-purpose input / output port. When the data transmission mode is the double-edge data transmission mode, the amount of transmitted data is twice the transmission bit width of the general-purpose input / output port.
[0015] Optionally, based on a preset transmission bit width, determining the number of clock cycles required for transmitting the data to be transmitted to the second optimized FPGA includes:
[0016] Determining a second amount of transmitted data based on the preset transmission bit width and the data transmission mode of the first general-purpose input / output port in the first optimized FPGA;
[0017] Determining the number of clock cycles required for transmitting the data to be transmitted to the second optimized FPGA according to the number of bits of the data to be transmitted and the second amount of transmitted data.
[0018] Optionally, performing bit width conversion on the data to be transmitted includes:
[0019] Determining whether to expand the data to be transmitted by judging whether the number of bits of the data to be transmitted is a multiple of the second amount of transmitted data;
[0020] If the data to be transmitted is expanded, performing bit width conversion on the expanded data to be transmitted by using the second amount of transmitted data; wherein, the expanded data to be transmitted is a multiple of the second amount of transmitted data;
[0021] If the data to be transmitted is not expanded, directly performing bit width conversion on the data to be transmitted by using the second amount of transmitted data.
[0022] Optionally, determining a reorganized data packet according to each data to be transmitted after bit width conversion and their respective corresponding number of clock cycles includes:
[0023] Determining a data block according to each data to be transmitted after bit width conversion and their respective corresponding number of clock cycles;
[0024] Determining a reorganized data packet based on a preset start character, data type character, data block, and check code; the data type character is a binary number determined based on the number of data to be transmitted; the check code is a check value obtained by checking the data block.
[0025] Optionally, after transmitting the reorganized data packet to the second optimized FPGA through the first general-purpose input / output port used for transmitting data locally, it further includes:
[0026] If an error retransmission signal returned by the second optimized FPGA is obtained through the local second general-purpose input / output port, the reorganized data packet is re-transmitted to the second optimized FPGA through the local first general-purpose input / output port;
[0027] The error retransmission signal is a signal generated by the second optimized FPGA when the check code parsed from the received data packet fails to verify the parsed data block, and the error retransmission signal is used to instruct the first optimized FPGA to re-transmit the reorganized data packet to the second optimized FPGA.
[0028] Optionally, in the process of transmitting the reorganized data packet to the second optimized FPGA through the local first general-purpose input / output port for data transmission, it further includes:
[0029] Transmit a data valid indication signal to the second optimized FPGA through the local third general-purpose input / output port, so that the second optimized FPGA triggers the parsing operation of the received data packet when it determines that the received data packet is a valid data packet based on the data valid indication signal.
[0030] In a second aspect, the present invention provides a data transmission device, which is applied to the first optimized FPGA and includes:
[0031] A data acquisition module, configured to acquire each piece of data to be transmitted to the second optimized FPGA through the general-purpose input / output port in each clock cycle; wherein, the optimized FPGA is an FPGA obtained by optimizing the original FPGA; the number of general-purpose input / output ports in the optimized FPGA is less than that of the original FPGA;
[0032] A data conversion module, configured to perform format conversion on the data to be transmitted according to a preset conversion protocol, to determine the number of clock cycles required for the data to be transmitted to the second optimized FPGA based on the preset transmission bit width, and perform bit width conversion on the data to be transmitted, and determine a reorganized data packet according to the data to be transmitted after bit width conversion and their respective corresponding clock cycles;
[0033] A data transmission module, configured to transmit the reorganized data packet to the second optimized FPGA through the local first general-purpose input / output port for data transmission; the preset transmission bit width is the transmission bit width of the first general-purpose input / output port in the first optimized FPGA, and the preset transmission bit width is determined based on the port information of the first general-purpose input / output ports in the first optimized FPGA and the original FPGA.
[0034] In a third aspect, the present invention provides an electronic device, including:
[0035] A memory, configured to store a computer program;
[0036] A processor for executing a computer program to implement the steps of the foregoing data transmission method.
[0037] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the foregoing data transmission method are implemented.
[0038] In the present invention, the first optimized FPGA obtains each piece of data to be transmitted that needs to be transmitted to the second optimized FPGA through a general-purpose input / output port in each clock cycle; wherein, the optimized FPGA is an FPGA obtained by optimizing the original FPGA; the number of general-purpose input / output ports in the optimized FPGA is less than that of the original FPGA; the data to be transmitted is format-converted according to a preset conversion protocol to determine the number of clock cycles required for the data to be transmitted to the second optimized FPGA based on a preset transmission bit width, and the bit width of the data to be transmitted is converted, and a reorganized data packet is determined according to the data to be transmitted after bit width conversion and their respective corresponding clock cycle numbers; the reorganized data packet is transmitted to the second optimized FPGA through a first general-purpose input / output port for data transmission locally; the preset transmission bit width is the transmission bit width of the first general-purpose input / output port in the first optimized FPGA, and the preset transmission bit width is determined based on the port information of the first general-purpose input / output ports in the first optimized FPGA and the original FPGA.
[0039] Beneficial effects: By optimizing the original FPGA, the present invention obtains an optimized FPGA with a smaller number of general-purpose input / output ports than the original FPGA, and configures a preset conversion protocol for the optimized FPGA to format-convert each piece of data to be transmitted that needs to be transmitted to another optimized FPGA through a general-purpose input / output port in each clock cycle, and reorganizes the format-converted data to be transmitted into a data packet, and then the reorganized data packet can be transmitted to another optimized FPGA through one general-purpose input / output port. Compared with transmitting each piece of data to be transmitted in each clock cycle to another FPGA through multiple general-purpose input / output ports, the number of general-purpose input / output ports required for data transmission is significantly reduced, and when there are a relatively large number of data to be transmitted in one clock cycle, there is no need to worry about the problem that the general-purpose input / output ports may not be sufficient. Based on this, the number of general-purpose input / output ports in the design of the FPGA can also be greatly reduced, thereby reducing the routing complexity of the circuit board. Description of the Drawings
[0040] To more clearly illustrate the embodiments of the present invention, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.
[0041] Figure 1 A flowchart of a data transmission method provided by an embodiment of the present invention;
[0042] Figure 2 A data transmission flowchart provided by an embodiment of the present invention;
[0043] Figure 3 A schematic structural diagram of a data transmission device provided by an embodiment of the present invention;
[0044] Figure 4 A structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners
[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
[0046] Since low-speed signals between interconnected FPGA chips generally need to be transmitted through a large number of GPIO ports between FPGA chips, this will not only increase the routing complexity of the circuit board, but also when there are many low-speed signals, it may not be possible to implement due to insufficient GPIO ports. For this reason, the present invention provides a data transmission method. By performing format conversion and recombination on each data to be transmitted within each clock cycle, the reorganized data packet can be transmitted to another FPGA through a single general-purpose input / output port, reducing the number of general-purpose input / output ports required for data transmission. And when there are more data to be transmitted within one clock cycle, there is no need to worry about the problem that the general-purpose input / output ports may not be sufficient. Correspondingly, the routing complexity of the circuit board can also be reduced in the design of the FPGA.
[0047] See Figure 1 As shown, an embodiment of the present invention discloses a data transmission method, which is applied to the first optimized FPGA and includes:
[0048] Step S11: Obtain each data to be transmitted to the second optimized FPGA through the general-purpose input / output port in each clock cycle; wherein, the optimized FPGA is the FPGA obtained by optimizing the original FPGA; the number of general-purpose input / output ports in the optimized FPGA is less than that in the original FPGA.
[0049] In the embodiment of the present invention, the first optimized FPGA reads each data generation module according to its own clock to obtain the data to be transmitted from each data generation module in each clock cycle; wherein, the data to be transmitted is the data that needs to be transmitted to the second optimized FPGA through the general-purpose input / output port. Generally, the data that needs to be transmitted between FPGAs through the general-purpose input / output port is low-speed data.
[0050] It should be noted that the optimized FPGA is the FPGA obtained by optimizing the original FPGA; and, the number of general-purpose input / output ports in the optimized FPGA is less than that in the original FPGA, and the architectures of the first optimized FPGA and the second optimized FPGA are basically the same.
[0051] Step S12: Perform format conversion on the data to be transmitted according to a preset conversion protocol, to determine the number of clock cycles required for the data to be transmitted to the second optimized FPGA based on a preset transmission bit width, and perform bit width conversion on the data to be transmitted, and determine a reorganized data packet according to the data to be transmitted after bit width conversion and their respective corresponding clock cycles.
[0052] In the embodiment of the present invention, after the first optimized FPGA obtains each data to be transmitted, it performs format conversion on the data to be transmitted according to a preset conversion protocol, to determine the number of clock cycles required for the data to be transmitted to the second optimized FPGA based on the preset transmission bit width and the number of bits of the data to be transmitted, and performs bit width conversion on the data to be transmitted using the preset transmission bit width, and then reorganizes the data to be transmitted after bit width conversion and their respective corresponding clock cycles to obtain a reorganized data packet.
[0053] Specifically, after obtaining the data to be transmitted after bit width conversion and their respective corresponding clock cycles, first determine a data block according to the data to be transmitted after bit width conversion and their respective corresponding clock cycles; then determine a reorganized data packet based on a preset start character, data type character, data block, and check code. Wherein, the data type character is a binary number determined based on the number of data to be transmitted; the check code is a check value obtained by checking the data block.
[0054] It should be noted that the purpose of the preset start character is to separate the data block from the previous data, indicating that the real valid data is about to start. The preset start character is set at the start position of a data packet and can be set to one or more. Exemplarily, the preset start character can be defined as 8’hAA, representing the eight-bit binary number 10101010 corresponding to hexadecimal AA; the preset start character can also be defined as 8’b10101010, representing the eight-bit binary number 10101010.
[0055] The data type character is a binary number determined based on the quantity of the data to be transmitted, defining how many sources or types of data are included in the data packet. And the data type character can be an eight-bit binary number. In this case, the eight-bit binary number can support up to 256 sources or types of data to be transmitted. Exemplarily, if the quantity of the data to be transmitted is 2, that is, the first optimized FPGA obtains the data to be transmitted from two data generation modules respectively. At this time, the data type character can be 00000010.
[0056] The checksum is the check value obtained after checking the data block, aiming to ensure the integrity and correctness of data transmission. The position of the checksum in the data packet is after the data block and can generally also be used as the end character of a data packet. And the checksum can be a 32-bit binary number. The checksum can be calculated through CRC (Cyclical Redundancy Check), parity check, ECC (Error Checking and Correction), etc., which is not limited here.
[0057] Based on this, the data structure of the reorganized data packet is: preset start character, data type character, the number of clock cycles corresponding to the first data to be transmitted, the first data to be transmitted after bit width conversion, the number of clock cycles corresponding to the second data to be transmitted, the second data to be transmitted after bit width conversion,..., the number of clock cycles corresponding to the last data to be transmitted, the last data to be transmitted after bit width conversion, checksum.
[0058] For the reorganized data packet, in addition to the above characters, a specific type character can also be added for each data to be transmitted in the reorganized data packet to represent what specific type of data the data to be transmitted is, that is, based on the specific type character corresponding to each data to be transmitted, the data type corresponding to each data to be transmitted can be determined. Of course, these characters can also be adaptively adjusted or some other characters can be added according to actual needs, which is not limited here.
[0059] Step S13: Transmit the reorganized data packet to the second optimized FPGA through the first general-purpose input / output port for data transmission locally; the preset transmission bit width is the transmission bit width of the first general-purpose input / output port in the first optimized FPGA, and the preset transmission bit width is determined based on the port information of the first general-purpose input / output ports in the first optimized FPGA and the original FPGA.
[0060] In the embodiment of the present invention, after determining the reorganized data packet according to the data to be transmitted after bit width conversion and their respective corresponding number of clock cycles, the first optimized FPGA transmits the reorganized data packet to the second optimized FPGA through the first general-purpose input / output port for data transmission locally.
[0061] Among them, the preset transmission bit width for determining the number of clock cycles corresponding to the data to be transmitted and for performing bit width conversion on the data to be transmitted is the transmission bit width of the first general-purpose input / output port in the first optimized FPGA, and moreover, the preset transmission bit width is the transmission bit width determined based on the port information of the first general-purpose input / output ports in the first optimized FPGA and the original FPGA.
[0062] For the determination of the preset transmission bit width, it specifically includes: determining the first data transmission amount based on the transmission bit width of the first general-purpose input / output port in the original FPGA and the data transmission mode; counting the number of the first general-purpose input / output ports in the original FPGA to obtain the first port number, and determining the first total data amount according to the first data transmission amount and the first port number; counting the number of the first general-purpose input / output ports in the first optimized FPGA to obtain the second port number, and determining the second data transmission amount based on the ratio between the first total data amount and the second port number; determining the preset transmission bit width based on the second data transmission amount and the data transmission mode of the first general-purpose input / output port in the first optimized FPGA.
[0063] It should be noted that the data transmission amount is the amount of data that the general-purpose input / output port can transmit within one clock cycle; the data transmission mode includes single-edge data transmission mode and double-edge data transmission mode. When the data transmission mode is the single-edge data transmission mode, the data transmission amount is the transmission bit width of the general-purpose input / output port, and when the data transmission mode is the double-edge data transmission mode, the data transmission amount is twice the transmission bit width of the general-purpose input / output port.
[0064] Among them, the single-edge data transmission mode refers to triggering data transmission at the rising edge or falling edge of the clock cycle, and the double-edge data transmission mode refers to triggering data transmission at both the rising edge and falling edge of the clock cycle. The transmission bit width refers to the amount of data that the general-purpose input / output port can transmit in one data transmission.
[0065] Taking the transmission bit width of the first general-purpose input / output port in the original FPGA as 1 bit and the data transmission mode as the single-edge data transmission mode, while the data transmission mode of the first general-purpose input / output port in the first optimized FPGA is the double-edge data transmission mode as an example, based on the transmission bit width and the single-edge data transmission mode of the first general-purpose input / output port in the original FPGA, the first transmission data volume is determined. At this time, the first transmission data volume is 1×1 = 1 bit; the number of the first general-purpose input / output ports in the original FPGA is counted to obtain the first port number, such as 16, and then based on the product of the first transmission data volume and the first port number, the first total data volume is determined. At this time, the first total data volume is 1×16 = 16 bits. Further, the number of the first general-purpose input / output ports in the first optimized FPGA is counted to obtain the second port number, such as 4, and then based on the ratio between the first total data volume and the second port number, the second transmission data volume is determined. At this time, the second transmission data volume is 16 / 4 = 4 bits; based on the second transmission data volume and the double-edge data transmission mode of the first general-purpose input / output port in the first optimized FPGA, the preset transmission bit width is determined. At this time, the preset transmission bit width is 4 / 2 = 2 bits.
[0066] Correspondingly, in the process of determining the number of clock cycles required for the data to be transmitted to the second optimized FPGA based on the preset transmission bit width, first, based on the preset transmission bit width and the data transmission mode of the first general-purpose input / output port in the first optimized FPGA, the second transmission data volume is determined; then, based on the number of bits of the data to be transmitted and the second transmission data volume, the number of clock cycles required for the data to be transmitted to the second optimized FPGA is determined.
[0067] Specifically, when the data transmission mode of the first general-purpose input / output port in the first optimized FPGA is the single-edge data transmission mode, the second transmission data volume is equal to the preset transmission bit width; when the data transmission mode of the first general-purpose input / output port in the first optimized FPGA is the double-edge data transmission mode, the second transmission data volume is equal to twice the preset transmission bit width. Further, after determining the second transmission data volume, based on the ratio between the number of bits of the data to be transmitted and the second transmission data volume, the number of clock cycles required for the data to be transmitted to the second optimized FPGA is determined.
[0068] It should be noted that the number of clock cycles can be represented by an eight-bit binary number, and if the ratio between the number of bits of the data to be transmitted and the second transmission data volume is not an integer, the ratio needs to be rounded up to obtain the number of clock cycles.
[0069] Further, in the process of performing bit-width conversion on the data to be transmitted based on a preset transmission bit-width, it is determined whether to expand the data to be transmitted by judging whether the number of bits of the data to be transmitted is a multiple of the second transmission data volume. If the data to be transmitted is to be expanded, the second transmission data volume is used to perform bit-width conversion on the expanded data to be transmitted; wherein, the expanded data to be transmitted is a multiple of the second transmission data volume; if the data to be transmitted is not to be expanded, the second transmission data volume is directly used to perform bit-width conversion on the data to be transmitted.
[0070] Specifically, if the number of bits of the data to be transmitted is not a multiple of the second transmission data volume, the second total data volume is determined based on the product of the number of clock cycles and the second transmission data volume, and the number of bits to be expanded is determined based on the difference between the second total data volume and the number of bits of the data to be transmitted. Then, the corresponding number of 0s is added to the high bits of the data to be transmitted to obtain the expanded data to be transmitted. At this time, the expanded data to be transmitted is a multiple of the second transmission data volume. In this way, by adding the corresponding number of 0s to the high bits of the data to be transmitted, the data to be transmitted is not changed, that is, the data to be transmitted remains unchanged, and it can also help to achieve the subsequent bit-width conversion of the data to be transmitted.
[0071] After that, the bit-width conversion is performed on the data to be transmitted by using the second transmission data volume to obtain the data to be transmitted after bit-width conversion. Exemplarily, if the number of bits of the data to be transmitted is 16 bits and the second transmission data volume is 4 bits, the 16-bit data to be transmitted can be converted into 4-bit data in 4 clock cycles by performing bit-width conversion on the data to be transmitted by using the second transmission data volume, where the number of clock cycles is 4.
[0072] In the embodiment of the present invention, after the first optimized FPGA transmits the reorganized data packet to the second optimized FPGA through the first general input / output port for data transmission locally, if an error retransmission signal returned by the second optimized FPGA is obtained through the second general input / output port locally, it indicates that the second optimized FPGA has an error in receiving data. At this time, the first optimized FPGA needs to retransmit the reorganized data packet to the second optimized FPGA through the first general input / output port locally.
[0073] Wherein, the error retransmission signal is a signal generated by the second optimized FPGA when the data block verification fails by using the check code parsed from the received data packet, and the error retransmission signal is used to instruct the first optimized FPGA to retransmit the reorganized data packet to the second optimized FPGA.
[0074] Specifically, after the first optimized FPGA transmits the reorganized data packet to the second optimized FPGA through the first general input / output port used for data transmission locally, the second optimized FPGA uses a preset conversion protocol to parse the received data packet to parse out the check code and the data block, and uses the parsed check code to check the parsed data block; if the check passes, it indicates that the received data packet is correct, and the received data packet is stored and forwarded to the corresponding module for processing and execution, etc.; if the check fails, it indicates that the received data packet is incorrect. At this time, the error retransmission signal is pulled high, and the error retransmission signal is transmitted to the first optimized FPGA through the second general input / output port locally. Correspondingly, when the first optimized FPGA obtains the error retransmission signal returned by the second optimized FPGA through the second general input / output port locally, it needs to retransmit the reorganized data packet to the second optimized FPGA through the first general input / output port locally.
[0075] It should be noted that during the process of the first optimized FPGA transmitting the reorganized data packet to the second optimized FPGA through the first general input / output port used for data transmission locally, the first optimized FPGA also needs to transmit the data valid indication signal to the second optimized FPGA through the third general input / output port locally, so that the second optimized FPGA can receive the data valid indication signal through the third general input / output port locally, and when it is determined that the received data packet is a valid data packet based on the data valid indication signal, trigger the parsing operation of the received data packet.
[0076] It should also be noted that during the process of the first optimized FPGA transmitting the reorganized data packet to the second optimized FPGA through the first general input / output port used for data transmission locally, the first optimized FPGA also needs to transmit the clock synchronization signal to the second optimized FPGA through the fourth general input / output port locally, so that the second optimized FPGA can receive the clock synchronization signal through the fourth general input / output port locally, thereby realizing the clock synchronization between the first optimized FPGA and the second optimized FPGA.
[0077] In addition, when the reset signal is triggered by the reset button on the circuit board, the first optimized FPGA and the second optimized FPGA respectively obtain the reset signal through the fifth general input / output port locally to reset themselves. Among them, the reset button can reset multiple FPGAs at the same time.
[0078] It can be found that the architectures of the first optimized FPGA and the second optimized FPGA are basically the same, both including a first general-purpose input / output port for transmitting data, a second general-purpose input / output port for transmitting error retransmission signals, a third general-purpose input / output port for transmitting data valid indication signals, a fourth general-purpose input / output port for transmitting clock synchronization signals, and a fifth general-purpose input / output port for transmitting reset signals.
[0079] Moreover, the above solutions are described with the first optimized FPGA as the data sender and the second optimized FPGA as the data receiver. By analogy, it can also be described with the second optimized FPGA as the data sender and the first optimized FPGA as the data receiver, and no more examples will be given here.
[0080] Beneficial effects: By optimizing the original FPGA, the present invention obtains an optimized FPGA with a smaller number of general-purpose input / output ports than the original FPGA, and configures a preset conversion protocol for the optimized FPGA to perform format conversion on each piece of data to be transmitted that needs to be transmitted to another optimized FPGA through the general-purpose input / output port within each clock cycle, and reorganizes the data to be transmitted after format conversion into a data packet. Then, the reorganized data packet can be transmitted to another optimized FPGA through one general-purpose input / output port. Compared with transmitting each piece of data to be transmitted within each clock cycle to another FPGA through multiple general-purpose input / output ports, the number of general-purpose input / output ports required for data transmission is significantly reduced, and when there are a relatively large number of data to be transmitted within one clock cycle, there is no need to worry about the problem that the general-purpose input / output ports may not be sufficient. Based on this, the number of general-purpose input / output ports can also be greatly reduced in the design of the FPGA, thereby reducing the routing complexity of the circuit board.
[0081] See Figure 2 As shown, an embodiment of the present invention discloses a data transmission method, including:
[0082] The first optimized FPGA includes an internal module for generating user status data, a data storage module for storing the user status data generated by the internal module, a key debounce module for debouncing the key signal, a key detection module for detecting the debounced key signal, a sending state machine module for performing format conversion and packetizing on the data to be transmitted, a first general-purpose input / output port for transmitting the reorganized data packet to the second optimized FPGA according to the double-edge data transmission mode, and a second general-purpose input / output port for receiving error retransmission signals. The second optimized FPGA includes a first general-purpose input / output port for receiving data packets, a receiving state machine module for parsing the data packets, and a second general-purpose input / output port for transmitting error retransmission signals to the first optimized FPGA.
[0083] Specifically, the internal module in the first optimized FPGA generates the data to be transmitted and the corresponding enable signal that need to be transmitted to the second optimized FPGA through the general-purpose input / output ports, and writes the data to be transmitted into the data storage module in the first optimized FPGA according to its own clock when the enable signal is valid; among them, the data storage module can adopt an asynchronous FIFO (First Input First Output) queue. The key debounce module in the first optimized FPGA debounces the externally input key signal and transmits the debounced key signal to the key detection module in the first optimized FPGA; the key detection module needs to compare the currently sampled key signal with the previously sampled key signal for consistency. If they are inconsistent, it indicates that a new key value needs to be transmitted. At this time, the key value corresponding to the currently sampled key signal needs to be stored. If they are consistent, the key value corresponding to the currently sampled key signal is not stored.
[0084] The transmission state machine module in the first optimized FPGA regularly obtains the data to be transmitted from the data storage module and the key detection module respectively according to its own clock cycle, and performs format conversion on the data to be transmitted according to the preset conversion protocol to determine the number of clock cycles required for the data to be transmitted to the second optimized FPGA based on the preset transmission bit width, and performs bit width conversion on the data to be transmitted. Then, it determines the data block according to the data to be transmitted after bit width conversion and their respective corresponding clock cycle numbers, and inserts a preset start character and data type character at the head of the data block, and inserts a check code at the tail of the data block to obtain the reorganized data packet. Further, the transmission state machine module in the first optimized FPGA sends the reorganized data packet to the first general-purpose input / output port in the first optimized FPGA, so as to transmit the reorganized data packet to the first general-purpose input / output port in the second optimized FPGA according to the double-edge data transmission mode through the first general-purpose input / output port in the first optimized FPGA.
[0085] The first general input / output port in the second optimized FPGA receives the data packet sent by the first optimized FPGA and transmits the data packet to the receive state machine module in the second optimized FPGA. The receive state machine module in the second optimized FPGA parses the received data packet according to a preset conversion protocol to parse out the check code and the data block from it, and uses the parsed check code to check the parsed data block; if the check fails, it indicates that the received data packet is incorrect. At this time, the error retransmission signal is pulled high, and the error retransmission signal is transmitted to the first optimized FPGA through the local second general input / output port. Correspondingly, when the first optimized FPGA obtains the error retransmission signal returned by the second optimized FPGA through the local second general input / output port, it re-transmits the reorganized data packet to the second optimized FPGA through the local first general input / output port, thus completing the data transmission between the first optimized FPGA and the second optimized FPGA.
[0086] Advantageous effects: By optimizing the original FPGA, the present invention obtains an optimized FPGA with a smaller number of general input / output ports than the original FPGA, and configures a preset conversion protocol for the optimized FPGA to perform format conversion on each piece of data to be transmitted that needs to be transmitted to another optimized FPGA through the general input / output port within each clock cycle, and reorganizes the formatted data to be transmitted into a data packet, and then the reorganized data packet can be transmitted to another optimized FPGA through one general input / output port. Compared with transmitting each piece of data to be transmitted within each clock cycle to another FPGA through multiple general input / output ports, the number of general input / output ports required for data transmission is significantly reduced, and when there are a relatively large number of data to be transmitted within one clock cycle, there is no need to worry about the problem that the general input / output ports may not be enough. Based on this, the number of general input / output ports in the FPGA design can also be greatly reduced, thereby reducing the routing complexity of the circuit board.
[0087] See Figure 3 As shown, an embodiment of the present invention discloses a data transmission device, which is applied to the first optimized FPGA and includes:
[0088] A data acquisition module 11, configured to acquire each piece of data to be transmitted that needs to be transmitted to the second optimized FPGA through the general input / output port in each clock cycle; wherein, the optimized FPGA is an FPGA obtained by optimizing the original FPGA; the number of general input / output ports in the optimized FPGA is less than that of the original FPGA;
[0089] The data conversion module 12 is configured to perform format conversion on the data to be transmitted according to a preset conversion protocol, determine the number of clock cycles required for the data to be transmitted to the second optimized FPGA based on a preset transmission bit width, perform bit width conversion on the data to be transmitted, and determine a reorganized data packet according to each data to be transmitted after bit width conversion and their respective corresponding clock cycles.
[0090] The data transmission module 13 is configured to transmit the reorganized data packet to the second optimized FPGA through a first general-purpose input / output port for data transmission locally; the preset transmission bit width is the transmission bit width of the first general-purpose input / output port in the first optimized FPGA, and the preset transmission bit width is determined based on the port information of the first general-purpose input / output ports in the first optimized FPGA and the original FPGA.
[0091] Since the embodiments of the device part correspond to the above embodiments, the embodiments of the device part are described with reference to the embodiments of the above method part and will not be elaborated here.
[0092] Beneficial effects: The present invention optimizes the original FPGA to obtain an optimized FPGA with a smaller number of general-purpose input / output ports than the original FPGA, and configures a preset conversion protocol for the optimized FPGA to perform format conversion on each data to be transmitted that needs to be transmitted to another optimized FPGA through the general-purpose input / output port within each clock cycle, and reorganize each data to be transmitted after format conversion into a data packet, and then the reorganized data packet can be transmitted to another optimized FPGA through one general-purpose input / output port. Compared with transmitting each data to be transmitted within each clock cycle to another FPGA through multiple general-purpose input / output ports, the number of general-purpose input / output ports required for data transmission is significantly reduced, and when there are a relatively large number of data to be transmitted within one clock cycle, there is no need to worry about the problem that the general-purpose input / output ports may not be sufficient. Based on this, the number of general-purpose input / output ports in the FPGA design can also be greatly reduced, thereby reducing the wiring complexity of the circuit board.
[0093] Furthermore, an embodiment of the present application also discloses an electronic device. Figure 4 It is a structural diagram of an electronic device shown according to an exemplary embodiment. The content in the figure cannot be regarded as any limitation on the scope of use of the present application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the data transmission method disclosed in any of the foregoing embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.
[0094] In this embodiment, the power supply 23 is used to provide operating voltages for the various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and no specific limitation is imposed on it here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application requirements, and no specific limitation is imposed here.
[0095] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, a random access memory, a magnetic disk, an optical disc, etc., and the resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.
[0096] Among them, the operating system 221 is used to manage and control the various hardware devices and the computer program 222 on the electronic device, and it can be Windows Server, Netware, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of implementing the data transmission method executed by the electronic device disclosed in any of the foregoing embodiments, may further include a computer program capable of performing other specific tasks.
[0097] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the data transmission method disclosed above is implemented. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details are not described herein again.
[0098] Furthermore, this application also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, the data transmission method disclosed above is implemented. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details are not described herein again.
[0099] In this specification, the various embodiments are described in a progressive manner, and the key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.
[0100] Those skilled in the art may further realize that the units and algorithm steps of each example described in connection with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.
[0101] The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0102] Finally, it should also be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.
[0103] The technical solutions provided in this application have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation manners of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.
Claims
1. A data transmission method, characterized in that: Applied to the first optimized FPGA, including: Acquire each data to be transmitted that needs to be transmitted to the second optimized FPGA through the universal input and output ports in each clock cycle; wherein the optimized FPGA is an FPGA obtained by optimizing the original FPGA; and the number of universal input and output ports in the optimized FPGA is less than that of the original FPGA; Performing format conversion on the data to be transmitted according to a preset conversion protocol, determining the number of clock cycles required for transmitting the data to be transmitted to the second optimized FPGA based on a preset transmission bit width, performing bit width conversion on the data to be transmitted, and determining a reassembled data packet according to each of the data to be transmitted after the bit width conversion and the corresponding number of clock cycles; The reassembled data packet is transmitted to the second optimized FPGA through a first general purpose input / output port locally used for transmitting data; the preset transmission bit width is the transmission bit width of the first general purpose input / output port in the first optimized FPGA, and the preset transmission bit width is determined based on the port information of the first general purpose input / output port in the first optimized FPGA and the original FPGA.
2. The data transmission method according to claim 1, characterized in that: The process of determining the preset transmission bit width includes: Determine a first transmission data amount based on a transmission bit width and a data transmission mode of a first general purpose input / output port in the original FPGA; Counting the number of first general-purpose input / output ports in the original FPGA to obtain a first port number, and determining a first total data volume according to the first transmission data volume and the first port number; Counting the number of first general-purpose input / output ports in the first optimized FPGA to obtain a second port number, and determining a second transmission data amount based on a ratio between the first total data amount and the second port number; Determine the preset transmission bit width based on the second transmission data amount and the data transmission mode of the first general input and output port in the first optimized FPGA; Among them, the transmission data volume is the amount of data that the general input and output port can transmit in one clock cycle; the data transmission mode includes a single-edge data transmission mode and a dual-edge data transmission mode. When the data transmission mode is the single-edge data transmission mode, the transmission data volume is the transmission bit width of the general input and output port; when the data transmission mode is the dual-edge data transmission mode, the transmission data volume is twice the transmission bit width of the general input and output port.
3. The data transmission method according to claim 2, characterized in that: The step of determining the number of clock cycles required for transmitting the to-be-transmitted data to the second optimized FPGA based on the preset transmission bit width includes: Determine the second transmission data amount based on the preset transmission bit width and the data transmission mode of the first general input and output port in the first optimized FPGA; The number of clock cycles required for transmitting the data to be transmitted to the second optimized FPGA is determined according to the number of bits of the data to be transmitted and the second transmission data amount.
4. The data transmission method according to claim 3, characterized in that: The bit width conversion of the data to be transmitted includes: Determining whether to expand the data to be transmitted by judging whether the number of bits of the data to be transmitted is a multiple of the amount of the second transmission data; If the data to be transmitted is expanded, the second transmission data amount is used to perform bit width conversion on the expanded data to be transmitted; wherein the expanded data to be transmitted is in a multiple relationship with the second transmission data amount; If the data to be transmitted is not expanded, the second transmission data amount is directly used to perform bit width conversion on the data to be transmitted.
5. The data transmission method according to any one of claims 1 to 4, characterized in that: The step of determining the reassembled data packet according to each of the to-be-transmitted data after bit width conversion and the respective corresponding clock cycle numbers comprises: Determine a data block according to each of the to-be-transmitted data after bit width conversion and the respective corresponding numbers of clock cycles; The reassembled data packet is determined based on a preset starting character, a data type character, the data block and a check code; the data type character is a binary number determined based on the amount of data to be transmitted; and the check code is a check value obtained after checking the data block.
6. The data transmission method according to claim 5, characterized in that: After transmitting the reassembled data packet to the second optimized FPGA via the first general purpose input / output port for transmitting data locally, the method further includes: If an error retransmission signal returned by the second optimized FPGA is obtained through the local second general purpose input / output port, the reassembled data packet is retransmitted to the second optimized FPGA through the local first general purpose input / output port; The error retransmission signal is a signal generated by the second optimized FPGA when an error occurs in checking a parsed data block using a check code parsed from a received data packet, and the error retransmission signal is used to instruct the first optimized FPGA to retransmit the reassembled data packet to the second optimized FPGA.
7. The data transmission method according to claim 6, characterized in that: The process of transmitting the reassembled data packet to the second optimized FPGA through the first general purpose input and output port for transmitting data locally also includes: The data valid indication signal is transmitted to the second optimized FPGA through the local third general input and output port, so that the second optimized FPGA triggers the parsing operation of the received data packet when it is determined that the received data packet is a valid data packet based on the data valid indication signal.
8. A data transmission device, characterized in that: Applied to the first optimized FPGA, including: A data acquisition module, used for acquiring each data to be transmitted through the universal input and output ports to the second optimized FPGA in each clock cycle; wherein the optimized FPGA is an FPGA obtained by optimizing the original FPGA; and the number of universal input and output ports in the optimized FPGA is less than that of the original FPGA; A data conversion module, configured to perform format conversion on the data to be transmitted according to a preset conversion protocol, determine the number of clock cycles required for transmitting the data to be transmitted to the second optimized FPGA based on a preset transmission bit width, perform bit width conversion on the data to be transmitted, and determine a reassembled data packet according to each of the data to be transmitted after the bit width conversion and the number of clock cycles corresponding to each of the data; A data transmission module, used to transmit the reassembled data packet to the second optimized FPGA through a first general input / output port locally used for transmitting data; the preset transmission bit width is the transmission bit width of the first general input / output port in the first optimized FPGA, and the preset transmission bit width is determined based on the port information of the first general input / output port in the first optimized FPGA and the original FPGA.
9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the data transmission method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data transmission method according to any one of claims 1 to 7 are implemented.