Structure and method for regulating performance of semiconductor device
By setting the position of the PN metal gate interface in the semiconductor device layout and adjusting the performance of NMOS and PMOS tubes using the metal gate interface effect, the problem of difficulty in regulating the read and write performance of SRAM in the prior art is solved, and a simple and easy performance regulation effect is achieved.
Patent Information
- Application Number
- CN202510214439.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-06-17
AI Technical Summary
The prior art is difficult to regulate the performance of semiconductor devices without changing the process flow, especially in the adjustment of read and write performance of SRAM.
By setting the position of the PN metal gate interface in the layout of the semiconductor device, the threshold voltage and saturation current of the N-type metal gate structure and the P-type metal gate structure are used to adjust the threshold voltage and saturation current of the NMOS tube and the PMOS tube, thereby controlling the read and write performance of the SRAM.
It is achieved to regulate the performance of semiconductor devices, especially the read and write performance of SRAM without changing the process flow and device area, which is simple and effective.
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Figure CN120166686A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a structure for regulating the performance of semiconductor devices. The present invention also relates to a method for regulating the performance of semiconductor devices. Background Art
[0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously reducing the device size to increase its speed. Currently, since the nanotechnology process node has been entered, the preparation and performance of semiconductor devices are restricted by various physical limits.
[0003] For the SRAM we studied, the performance regulation of SRAM is achieved by adjusting the proportional relationship between MOSFETs. Especially for small-size nodes, the read and write performance of SRAM is basically adjusted by changing the size of the active area (AA) of each transistor.
[0004] As Figure 1 shown, it is the circuit diagram of the cell structure of the existing SRAM; the storage cell of the SRAM includes: a first pull-down transistor 101, a second pull-down transistor 102, a first select transistor 103, and a second select transistor 104 composed of NMOS transistors, and a first pull-up transistor 105 and a second pull-up transistor 106 composed of PMOS transistors. Figure 1 In, the first pull-down transistor 101 is also represented by PDL, the second pull-down transistor 102 is also represented by PDR, the first select transistor 103 is also represented by PGL, the second select transistor 104 is also represented by PGR, the first pull-up transistor 105 is also represented by PUL, and the second pull-up transistor 106 is also represented by PUR.
[0005] The source regions of the first pull-down transistor 101 and the second pull-down transistor 102 are connected to the ground Vss.
[0006] The source regions of the first pull-up transistor 105 and the second pull-up transistor 106 are connected to the power supply Vdd.
[0007] The drain region of the first pull-down transistor 101, the drain region of the first pull-up transistor 105, the drain region of the first select transistor 103, and the gates of the second pull-down transistor 102 and the second pull-up transistor 106 are all connected to the storage node N1.
[0008] The drain region of the second pull-down transistor 102, the drain region of the second pull-up transistor 106, the drain region of the second select transistor 104, and the gates of the first pull-down transistor 101 and the first pull-up transistor 105 are all connected to the inverted storage node N2. The information stored in the storage node N1 and the inverted storage node N2 are complementary to each other.
[0009] The gates of the first selection transistor 103 and the second selection transistor 104 are both connected to the word line WL.
[0010] The source region of the first selection transistor 103 is connected to the bit line BL.
[0011] The source region of the second selection transistor 104 is connected to the bit line BLB. The bit lines BL and BLB form a pair of bit line groups.
[0012] The proportional relationships of MOSFETs in SRAM generally include:
[0013] α_ratio, β_ratio, and γ_ratio.
[0014] Among them, α_ratio = I_(ON,PU) / I_(ON,PD);
[0015] β_ratio = I_(ON,PD) / I_(ON,PG);
[0016] γ_ratio = I_(ON,PG) / I_(ON,PU).
[0017] The three parameters restrict each other and their product is 1.
[0018] Among them, I_(ON,PU) represents the on-current of the pull-up transistor, i.e., the first pull-up transistor 105 or the second pull-up transistor 106, I_(ON,PD) represents the on-current of the pull-down transistor, i.e., the first pull-down transistor 101 or the second pull-down transistor 102, and I_(ON,PG) represents the on-current of the selection transistor, i.e., the first selection transistor 103 or the second selection transistor 104.
[0019] A decrease in α_ratio and β_ratio will lead to a decrease in SNM and a decline in read performance; a decrease in γ_ratio will lead to a decrease in WM and a decline in write performance. Especially for the fin-shaped transistor node, the SRAM performance is basically improved through the following structural settings:
[0020] (1). Adjust the SRAM read and write performance by changing the number of fin-shaped active regions of each transistor. For example, the read and write performance of the "111" SRAM is not excellent, but the density is high; "111" means that the number of fin-shaped active regions of the pull-up transistor, the selection transistor, and the pull-down transistor in the SRAM is all 1.
[0021] The "112" SRAM improves the read stability by enhancing the pull-down transistor (NPD), but the write ability still needs to be improved; "112" means that the number of fin-shaped active regions of the pull-up transistor, the selection transistor, and the pull-down transistor in the SRAM is 1, 1, and 2 respectively.
[0022] The "122" SRAM improves both read and write capabilities by means of a transfer transistor (NPG) and a pull-down transistor (NPD), but its SNM is not significantly improved and the area increases accordingly. "122" indicates that the numbers of raised-bar active regions of the pull-up transistor, the select transistor, and the pull-down transistor in the SRAM are 1, 2, and 2 respectively.
[0023] (2) An external auxiliary circuit can also improve the read and write performance of the SRAM, but it also sacrifices the chip area. Summary of the Invention
[0024] The technical problem to be solved by the present invention is to provide a structure for regulating the performance of semiconductor devices, which can regulate the performance of semiconductor devices including threshold voltage, saturation current, etc. without changing the process flow, and is particularly suitable for adjusting the performance of SRAMs, such as controlling the read and write performance of SRAMs, and is simple and easy to implement. For this purpose, the present invention also provides a method for regulating the performance of semiconductor devices.
[0025] To solve the above technical problem, the structure for regulating the performance of semiconductor devices provided by the present invention includes:
[0026] A first active region and a second active region arranged in parallel, with field oxides provided on the periphery of the first active region and on the periphery of the second active region.
[0027] The first active region is used to form an NMOS transistor, and the second active region is used to form a PMOS transistor.
[0028] A first metal gate bar spanning the first active region and the second active region, the first metal gate bar being perpendicular to the first active region.
[0029] The first metal gate bar has a PN metal gate interface, and the PN metal gate interface is located at the top of the field oxide between the first active region and the second active region.
[0030] The PN metal gate interface divides the first metal gate bar into an N-type metal gate structure spanning the first active region and a P-type metal gate structure spanning the second active region. The position of the PN metal gate interface serves as a regulation structure for the performance of semiconductor devices. The position of the PN metal gate interface is set according to the requirements of the performance of the semiconductor device and is defined by layout. The closer the PN metal gate interface is to the first active region and the farther it is from the second active region, the larger the threshold voltage of the NMOS transistor and the smaller the threshold voltage of the PMOS transistor. Conversely, the farther the PN metal gate interface is from the first active region and the closer it is to the second active region, the smaller the threshold voltage of the NMOS transistor and the larger the threshold voltage of the PMOS transistor.
[0031] A further improvement is that the semiconductor device includes an SRAM, and the memory cell of the SRAM includes: a first pull-down transistor, a second pull-down transistor, a first selection transistor, and a second selection transistor composed of the NMOS transistors, and a first pull-up transistor and a second pull-up transistor composed of the PMOS transistors.
[0032] The first pull-down transistor, the second pull-down transistor, the first selection transistor, and the second selection transistor are all formed in the first active region.
[0033] The first pull-up transistor and the second pull-up transistor are both formed in the second active region.
[0034] The first pull-down transistor and the first pull-up transistor share a first metal gate bar.
[0035] The second pull-down transistor and the second pull-down transistor share another first metal gate bar.
[0036] The first pull-down transistor and the second pull-down transistor share a first N+ source region.
[0037] The first pull-up transistor and the second pull-up transistor share a first P+ source region.
[0038] The first pull-down transistor and the first selection transistor share a first N+ drain region.
[0039] The second pull-down transistor and the second selection transistor share a second N+ drain region.
[0040] A second metal gate bar is disposed on the top of the first selection transistor.
[0041] Another second metal gate bar is disposed on the top of the second selection transistor.
[0042] Each of the second metal gate bars is an N-type metal gate structure.
[0043] A further improvement is that the SRAM is formed by arranging a plurality of the memory cells.
[0044] The layout structure of the SRAM includes:
[0045] The first active regions of the memory cells in the same row are connected together, and the second active regions are spaced apart from each other.
[0046] In the column structure, the second active regions of the memory cells in two adjacent columns are staggered from each other, and each of the first metal gate bars and the corresponding second metal gate bars are aligned and have a gap.
[0047] A further improvement is that the N-type metal gate structure includes: a gate dielectric layer, a bottom barrier layer, an N-type work function layer, and a metal gate conductive material layer.
[0048] The P-type metal gate structure includes: the gate dielectric layer, the bottom barrier layer, the P-type work function layer, and the metal gate conductive material layer.
[0049] A further improvement is that the P-type metal gate structure further includes a top barrier layer located between the P-type work function layer and the metal gate conductive material layer.
[0050] A further improvement is that the material of the gate dielectric layer is a high-k dielectric material.
[0051] An interface layer is formed between the gate dielectric layer and the semiconductor substrate at the bottom.
[0052] A further improvement is that the material of the semiconductor substrate includes silicon.
[0053] The interface layer includes silicon dioxide.
[0054] The high-k dielectric material includes hafnium oxide.
[0055] The bottom barrier layer includes a stacked layer of TiN and TaN.
[0056] The material of the top barrier layer includes TaN.
[0057] The material of the N-type work function layer includes TiAl.
[0058] The material of the P-type work function layer includes TiN.
[0059] To solve the above technical problems, the method for regulating the performance of a semiconductor device provided by the present invention includes:
[0060] Step 1: Set the position of the metal gate interface in the layout of the semiconductor device according to the requirements of the performance of the semiconductor device.
[0061] The metal gate interface is the interface between the N-type metal gate structure spanning the first active region and the P-type metal gate structure spanning the second active region in the first metal gate bar.
[0062] The first active region and the second active region are arranged in parallel, and field oxides are provided on the periphery of the first active region and the periphery of the second active region.
[0063] The first active region is used to form an NMOS transistor, and the second active region is used to form a PMOS transistor.
[0064] The semiconductor device has the first metal gate bar spanning the first active region and the second active region, and the first metal gate bar is perpendicular to the first active region.
[0065] The PN metal gate interface is located at the top of the field oxide between the first active region and the second active region.
[0066] Step 2: Fabricate the semiconductor device on the product wafer according to the layout of the semiconductor device;
[0067] The position of the PN metal gate interface serves as a control structure for the performance of the semiconductor device. The closer the PN metal gate interface is to the first active region and the farther it is from the second active region, the larger the threshold voltage of the NMOS transistor and the smaller the threshold voltage of the PMOS transistor. Conversely, the farther the PN metal gate interface is from the first active region and the closer it is to the second active region, the smaller the threshold voltage of the NMOS transistor and the larger the threshold voltage of the PMOS transistor.
[0068] A further improvement is that before Step 1, there is also a step:
[0069] Step 01: Modify the layout of the semiconductor device to obtain multiple different position structures of the metal gate interface.
[0070] Step 02: Fabricate the semiconductor devices corresponding to the metal gate interfaces with different positions on the test wafer.
[0071] Step 03: Test the test wafer, extract the electrical parameters of the semiconductor device, and obtain the relationship between the electrical parameters of the semiconductor device and the position of the metal gate interface; the electrical parameters include the threshold voltage and saturation current of the NMOS transistor and the threshold voltage and saturation current of the PMOS transistor.
[0072] In Step 1, according to the relationship between the electrical parameters of the semiconductor device and the position of the metal gate interface, set the layout of the semiconductor device on the product wafer.
[0073] A further improvement is that the semiconductor device includes an SRAM, and the storage unit of the SRAM includes: a first pull-down transistor, a second pull-down transistor, a first selection transistor, and a second selection transistor composed of the NMOS transistors, and a first pull-up transistor and a second pull-up transistor composed of the PMOS transistors.
[0074] The first pull-down transistor, the second pull-down transistor, the first selection transistor, and the second selection transistor are all formed in the first active region.
[0075] The first pull-up transistor and the second pull-up transistor are both formed in the second active region.
[0076] The first pull-down transistor and the first pull-up transistor share a first metal gate bar.
[0077] The second pull-down tube and the second pull-down tube share another one of the first metal gate bars.
[0078] The first pull-down tube and the second pull-down tube share a first N+ source region.
[0079] The first pull-up tube and the second pull-up tube share a first P+ source region.
[0080] The first pull-down tube and the first selection tube share a first N+ drain region.
[0081] The second pull-down tube and the second selection tube share a second N+ drain region.
[0082] A second metal gate bar is provided on the top of the first selection tube.
[0083] Another second metal gate bar is provided on the top of the second selection tube.
[0084] Each of the second metal gate bars is an N-type metal gate structure.
[0085] A further improvement is that the SRAM is formed by arranging a plurality of the storage units.
[0086] The layout structure of the SRAM includes:
[0087] The first active regions of the storage units in the same row are connected together, and the second active regions are spaced apart from each other.
[0088] In the column structure, the second active regions of the storage units in two adjacent columns are staggered from each other, and each of the first metal gate bars and the corresponding second metal gate bars are aligned and have a gap.
[0089] A further improvement is that the N-type metal gate structure includes: a gate dielectric layer, a bottom barrier layer, an N-type work function layer, and a metal gate conductive material layer.
[0090] The P-type metal gate structure includes: the gate dielectric layer, the bottom barrier layer, a P-type work function layer, and the metal gate conductive material layer.
[0091] A further improvement is that the P-type metal gate structure further includes: a top barrier layer located between the P-type work function layer and the metal gate conductive material layer.
[0092] A further improvement is that the material of the gate dielectric layer is a high-k material.
[0093] An interface layer is formed between the gate dielectric layer and the semiconductor substrate at the bottom.
[0094] A further improvement is that the material of the semiconductor substrate includes silicon.
[0095] The interface layer adopted includes silicon dioxide.
[0096] The high-k dielectric material includes hafnium oxide.
[0097] The bottom barrier layer includes a stacked layer of TiN and TaN.
[0098] The material of the top edge barrier layer includes TaN.
[0099] The material of the N-type work function layer includes TiAl.
[0100] The material of the P-type work function layer includes TiN.
[0101] Different from the prior art where the device performance is changed by changing the size of the active region of the transistor, the present invention utilizes the effect of the PN metal gate interface between the N-type metal gate structure and the P-type metal gate structure on the NMOS transistor and the PMOS transistor when adjacent active regions corresponding to transistors of different conduction types share the same metal gate strip, so as to realize adjusting the performance of the NMOS transistor and the PMOS transistor by changing the position of the PN metal gate interface, and finally changing the performance of the semiconductor device composed of the NMOS transistor and the PMOS transistor such as SRAM. Changing the PN metal gate interface can be achieved only by changing the layout of the semiconductor device, without changing other structures of the semiconductor device, such as not changing the size of the active region of each transistor and not changing the process flow. Therefore, the process is simple and feasible and will not affect the area of the device. So, the present invention can regulate the performance of the semiconductor device including the threshold voltage, saturation current, etc. without changing the process flow, is particularly suitable for adjusting the performance of SRAM such as controlling the read / write performance of SRAM and is simple and feasible, and will not affect the area of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0102] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments:
[0103] Figure 1 is the circuit diagram of the storage unit of the existing SRAM;
[0104] Figure 2 is the layout of the storage unit of SRAM in the structure for regulating the performance of the semiconductor device according to the embodiment of the present invention;
[0105] Figure 3 is the layout of multiple storage units of SRAM in the structure for regulating the performance of the semiconductor device according to the embodiment of the present invention;
[0106] Figure 4 is along Figure 3Cross-sectional view of line BB in Detailed implementation mode
[0107] As Figure 2 shown, it is the layout of the storage unit of SRAM in the structure for regulating the performance of semiconductor devices in the embodiment of the present invention; in the embodiment of the present invention, for the circuit diagram of the storage unit of SRAM, please also refer to the figure shown. The structure for regulating the performance of semiconductor devices in the embodiment of the present invention includes:
[0108] The first active region 202a and the second active region 202b arranged in parallel, and field oxides 203 are provided on the periphery of the first active region 202a and the periphery of the second active region 202b.
[0109] The first active region 202a is used to form an NMOS transistor, and the second active region 202b is used to form a PMOS transistor.
[0110] The first metal gate strip 204 straddles the first active region 202a and the second active region 202b, and the first metal gate strip 204 is perpendicular to the first active region 202a.
[0111] The first metal gate strip 204 has a PN metal gate interface AA, and the PN metal gate interface AA is located at the top of the field oxide 203 between the first active region 202a and the second active region 202b.
[0112] The PN metal gate interface AA divides the first metal gate strip 204 into an N-type metal gate structure straddling the first active region 202a and a P-type metal gate structure straddling the second active region 202b. The position of the PN metal gate interface AA is used as a control structure for the performance of semiconductor devices. The position of the PN metal gate interface AA is set according to the requirements of the performance of semiconductor devices and is defined by layout. The closer the PN metal gate interface AA is to the first active region 202a and the farther it is from the second active region 202b, the greater the threshold voltage of the NMOS transistor and the smaller the threshold voltage of the PMOS transistor. On the contrary, the farther the PN metal gate interface AA is from the first active region 202a and the closer it is to the second active region 202b, the smaller the threshold voltage of the NMOS transistor and the greater the threshold voltage of the PMOS transistor.
[0113] In an embodiment of the present invention, since there is a corresponding relationship between the position of the PN metal gate interface AA and the performance of the semiconductor device, the position of the PN metal gate interface AA is obtained in advance according to the required performance of the semiconductor device, and then the position of the PN metal gate interface AA is defined through a layout. The required position of the PN metal gate interface AA can be achieved through a manufacturing process such as a CMOS process. Among them, the corresponding relationship between the position of the PN metal gate interface AA and the performance of the semiconductor device can be obtained in advance by forming multiple different positions of the PN metal gate interface AA on a test chip and then testing the performance parameters of the corresponding semiconductor device.
[0114] In an embodiment of the present invention, the semiconductor device includes an SRAM, and the storage unit 201 of the SRAM includes: a first pull-down transistor 101, a second pull-down transistor 102, a first selection transistor 103, and a second selection transistor 104 composed of NMOS transistors, and a first pull-up transistor 105 and a second pull-up transistor 106 composed of PMOS transistors. Figure 1 Among them, the first pull-down transistor 101 is also represented by PDL, the second pull-down transistor 102 is also represented by PDR, the first selection transistor 103 is also represented by PGL, the second selection transistor 104 is also represented by PGR, the first pull-up transistor 105 is also represented by PUL, and the second pull-up transistor 106 is also represented by PUR.
[0115] The first pull-down transistor 101, the second pull-down transistor 102, the first selection transistor 103, and the second selection transistor 104 are all formed in the first active region 202a.
[0116] The first pull-up transistor 105 and the second pull-up transistor 106 are both formed in the second active region 202b.
[0117] The first pull-down transistor 101 and the first pull-up transistor 105 share a first metal gate strip 204.
[0118] The second pull-down transistor 102 and the second pull-down transistor 102 share another first metal gate strip 204.
[0119] The first pull-down transistor 101 and the second pull-down transistor 102 share a first N+ source region, and the first N+ source region is grounded to Vss through a contact hole and one or more top front metal layers.
[0120] The first pull-up transistor 105 and the second pull-up transistor 106 share a first P+ source region. The first P+ source region is connected to the power supply Vdd through a contact hole and one or more top front metal layers.
[0121] The first pull-down tube 101 and the first selection tube 103 share a first N+ drain region, and the first N+ drain region is connected to the first P+ drain region of the first pull-up tube 105 through a contact hole and one or more top front metal layers and serves as a storage node N1. The storage node N1 is also connected to the first metal gate strip 204 on top of the second pull-down tube 102 through a contact hole or a front metal layer.
[0122] The second pull-down tube 102 and the second selection tube 104 share a second N+ drain region, and the second N+ drain region is connected to the second P+ drain region of the second pull-up tube 106 through a contact hole and one or more top front metal layers and serves as an inverted storage node N2. The inverted storage node N2 is also connected to the first metal gate strip 204 on top of the first pull-down tube 101 through a contact hole or a front metal layer.
[0123] A second metal gate strip 205 is provided on top of the first selection tube 103.
[0124] Another second metal gate strip 205 is provided on top of the second selection tube 104. The second metal gate strips 205 on top of the first selection tube 103 and the second selection tube 104 are both connected to the same word line WL composed of front metal layers.
[0125] Each of the second metal gate strips 205 has an N-type metal gate structure.
[0126] The N+ source region of the first selection tube 103 is connected to a bit line BL composed of front metal layers.
[0127] The N+ source region of the second selection tube 104 is connected to a bit line BLB composed of front metal layers. The bit lines BL and BLB form a pair of bit line groups.
[0128] As Figure 3 shown, it is the layout of the cell structure of the SRAM according to an embodiment of the present invention; the SRAM is formed by arranging a plurality of the storage cells 201. Figure 3 Two rows of the storage cells 201 are shown,
[0129] The layout structure of the SRAM includes:
[0130] The first active regions 202a of the storage cells 201 in the same row are connected together, and the second active regions 202b are spaced apart from each other.
[0131] In the column structure, the second active regions 202b of the storage cells 201 in two adjacent columns are staggered from each other, and by Figure 3As can be seen, the second active regions 202b of the storage cells 201 in adjacent columns are close to each other, without any intervening first active region 202a. Each of the first metal gate strips 204 and the corresponding second metal gate strips 205 are aligned and have a gap. Since the second active regions 202b of the storage cells 201 in adjacent columns are staggered from each other, the first metal gate strips 204 in adjacent columns are also staggered from each other, and the second metal gate strips 205 are also staggered from each other. Moreover, the staggered first metal gate strips 204 will be aligned with the corresponding second metal gate strips 205, but there is a gap directly between the aligned first metal gate strips 204 and the corresponding second metal gate strips 205 in the same column. The gap is achieved through a polysilicon cutoff (POC) layer 207, that is, the first metal gate strips 204 and the corresponding second metal gate strips 205 are defined by truncating the same polysilicon strip.
[0132] As can be seen from Figure 3 As can be seen, the PN metal gate interfaces AA of the storage cells 201 in each row are aligned. The region 206 between the PN metal gate interfaces AA of the storage cells 201 in adjacent rows is the formation region of the P-type metal gate structure in the first metal gate strip 204. The region 206 is defined by layout. If it is necessary to change the position of the corresponding PN metal gate interface AA, the layout of the region 206 can be modified.
[0133] As Figure 4 shown, is a cross-sectional view along Figure 3 line BB in
[0134] The N-type metal gate structure includes: a gate dielectric layer 303, a bottom barrier layer, an N-type work function layer 306, and a metal gate conductive material layer 309.
[0135] The P-type metal gate structure includes: the gate dielectric layer 303, the bottom barrier layer, a P-type work function layer 307, and the metal gate conductive material layer 309.
[0136] In an embodiment of the present invention, the material of the gate dielectric layer 303 is a high-k dielectric material.
[0137] An interface layer 302 is formed between the gate dielectric layer 303 and the semiconductor substrate at the bottom. The first active region 202a and the second active region 202b are both composed of the semiconductor substrate within the region surrounded by the field oxide 203. A P-well is formed in the first active region 202a, and an N-well is formed in the second active region 202b. Figure 4In [the figure], on the left side of the PN metal gate interface AA is the formation region of the PMOS transistor, and on the right side is the formation region of the NMOS transistor.
[0138] In some embodiments, the material of the semiconductor substrate includes silicon.
[0139] The interface layer 302 is made of silicon dioxide.
[0140] The high-k dielectric material includes hafnium oxide.
[0141] The bottom barrier layer includes a stacked layer of TiN and TaN, such as Figure 4 the TiN layer 304 and TaN layer 305 shown in [the figure].
[0142] The material of the top-edge barrier layer includes TaN.
[0143] The material of the N-type work function layer 306 includes TiAl.
[0144] The material of the P-type work function layer 307 includes TiN.
[0145] Different from the prior art where the device performance is changed by changing the size of the active region of the transistor, the embodiments of the present invention utilize the effect of the PN metal gate interface AA between the N-type metal gate structure and the P-type metal gate structure when adjacent active regions corresponding to transistors of different conductivity types share the same metal gate strip on the performance of the NMOS transistor and the PMOS transistor. Thus, by changing the position of the PN metal gate interface AA, the performance of the NMOS transistor and the PMOS transistor can be adjusted, and finally the performance of the semiconductor device composed of the NMOS transistor and the PMOS transistor, such as SRAM, can be changed. Changing the PN metal gate interface AA can be achieved only by changing the layout of the semiconductor device, without changing other structures of the semiconductor device, such as not changing the size of the active region of each transistor and not changing the process flow. Therefore, the process is simple and easy to implement and will not affect the area of the device. So, the embodiments of the present invention can regulate the performance of the semiconductor device, including the threshold voltage, saturation current, etc., without changing the process flow, and are particularly suitable for adjusting the performance of SRAM, such as controlling the read / write performance of SRAM, which is simple and easy to implement and will not affect the area of the device.
[0146] The method for regulating the performance of the semiconductor device in the embodiments of the present invention includes:
[0147] Step 1: Set the position of the metal gate interface in the layout of the semiconductor device according to the requirements of the semiconductor device performance.
[0148] The metal gate interface is the interface between the N-type metal gate structure that crosses the first active region 202a in the first metal gate strip 204 and the P-type metal gate structure that crosses the second active region 202b.
[0149] The first active region 202a and the second active region 202b are arranged in parallel, and field oxides 203 are provided on the periphery of the first active region 202a and on the periphery of the second active region 202b.
[0150] The first active region 202a is used to form an NMOS transistor, and the second active region 202b is used to form a PMOS transistor.
[0151] The semiconductor device has a first metal gate strip 204 that straddles the first active region 202a and the second active region 202b, and the first metal gate strip 204 is perpendicular to the first active region 202a.
[0152] The PN metal gate interface AA is located at the top of the field oxide 203 between the first active region 202a and the second active region 202b.
[0153] In the method of the embodiment of the present invention, before step one, the following steps are further included:
[0154] Step 01: Change the layout of the semiconductor device to obtain the position structures of a plurality of different metal gate interfaces.
[0155] Step 02: Fabricate the semiconductor devices corresponding to the metal gate interfaces with different positions on a test chip.
[0156] Step 03: Test the test chip, extract the electrical parameters of the semiconductor device, and obtain the relationship between the electrical parameters of the semiconductor device and the position of the metal gate interface; the electrical parameters include the threshold voltage and saturation current of the NMOS transistor and the threshold voltage and saturation current of the PMOS transistor.
[0157] In step one, according to the relationship between the electrical parameters of the semiconductor device and the position of the metal gate interface, set the layout of the semiconductor device on the product chip.
[0158] Step two: Fabricate the semiconductor device on the product chip according to the layout of the semiconductor device.
[0159] The position of the PN metal gate interface AA serves as a regulation structure for the performance of the semiconductor device. The closer the PN metal gate interface AA is to the first active region 202a and the farther it is from the second active region 202b, the greater the threshold voltage of the NMOS transistor and the smaller the threshold voltage of the PMOS transistor. On the contrary, the farther the PN metal gate interface AA is from the first active region 202a and the closer it is to the second active region 202b, the smaller the threshold voltage of the NMOS transistor and the greater the threshold voltage of the PMOS transistor.
[0160] In the method of the embodiment of the present invention, the semiconductor device includes an SRAM, and the memory cell 201 of the SRAM includes: a first pull-down transistor 101, a second pull-down transistor 102, a first selection transistor 103, and a second selection transistor 104 composed of NMOS transistors, and a first pull-up transistor 105 and a second pull-up transistor 106 composed of PMOS transistors. Figure 1 Among them, the first pull-down transistor 101 is also represented by PDL, the second pull-down transistor 102 is also represented by PDR, the first selection transistor 103 is also represented by PGL, the second selection transistor 104 is also represented by PGR, the first pull-up transistor 105 is also represented by PUL, and the second pull-up transistor 106 is also represented by PUR.
[0161] The first pull-down transistor 101, the second pull-down transistor 102, the first selection transistor 103, and the second selection transistor 104 are all formed in the first active region 202a.
[0162] The first pull-up transistor 105 and the second pull-up transistor 106 are both formed in the second active region 202b.
[0163] The first pull-down transistor 101 and the first pull-up transistor 105 share a first metal gate strip 204.
[0164] The second pull-down transistor 102 and the second pull-down transistor 102 share another first metal gate strip 204.
[0165] The first pull-down transistor 101 and the second pull-down transistor 102 share a first N+ source region, and the first N+ source region is grounded to Vss through a contact hole and one or more top front metal layers.
[0166] The first pull-up transistor 105 and the second pull-up transistor 106 share a first P+ source region. The first P+ source region is connected to the power supply Vdd through a contact hole and one or more top front metal layers.
[0167] The first pull-down transistor 101 and the first selection transistor 103 share a first N+ drain region, and the first N+ drain region is connected to the first P+ drain region of the first pull-up transistor 105 through a contact hole and one or more top front metal layers and serves as a storage node N1. The storage node N1 is also connected to the first metal gate strip 204 on top of the second pull-down transistor 102 through a contact hole or a front metal layer.
[0168] The second pull-down tube 102 and the second selection tube 104 share a second N+ drain region, and the second N+ drain region is connected to the second P+ drain region of the second pull-up tube 106 through a contact hole and one or more top positive metal layers and serves as an inverting storage node N2. The inverting storage node N2 is also connected to the first metal gate strip 204 at the top of the first pull-down tube 101 through a contact hole or a positive metal layer.
[0169] A second metal gate strip 205 is provided at the top of the first selection tube 103.
[0170] Another second metal gate strip 205 is provided at the top of the second selection tube 104. The second metal gate strips 205 at the tops of the first selection tube 103 and the second selection tube 104 are both connected to the same word line WL composed of positive metal layers.
[0171] Each of the second metal gate strips 205 has an N-type metal gate structure.
[0172] The N+ source region of the first selection tube 103 is connected to a bit line BL composed of positive metal layers.
[0173] The N+ source region of the second selection tube 104 is connected to a bit line BLB composed of positive metal layers. The bit lines BL and BLB form a pair of bit line groups.
[0174] As Figure 3 shown, it is the layout of the cell structure of the SRAM according to an embodiment of the present invention; the SRAM is formed by arranging a plurality of the storage cells 201. Figure 3 Two rows of the storage cells 201 are shown,
[0175] The layout structure of the SRAM includes:
[0176] The first active regions 202a of the storage cells 201 in the same row are connected together, and the second active regions 202b are spaced apart from each other.
[0177] In the column structure, the second active regions 202b of the storage cells 201 in two adjacent columns are staggered from each other, by Figure 3As can be seen, the second active regions 202b of the storage cells 201 in adjacent columns are close to each other, and there is no first active region 202a in between. Each of the first metal gate strips 204 and the corresponding second metal gate strips 205 are aligned and have a gap. Since the second active regions 202b of the storage cells 201 in adjacent columns are staggered from each other, the first metal gate strips 204 in adjacent columns are also staggered from each other, and the second metal gate strips 205 are also staggered from each other. Moreover, the staggered first metal gate strips 204 will be aligned with the corresponding second metal gate strips 205, but there is a gap directly between the aligned first metal gate strips 204 and the corresponding second metal gate strips 205 in the same column. The gap is achieved through a polysilicon cutoff (POC) layer 207, that is, the first metal gate strips 204 and the corresponding second metal gate strips 205 are defined by truncating the same polysilicon strip.
[0178] As can be seen from Figure 3 shown, the PN metal gate interfaces AA of the storage cells 201 in each row are aligned. The region 206 between the PN metal gate interfaces AA of the storage cells 201 in adjacent rows is the formation region of the P-type metal gate structure in the first metal gate strip 204. The region 206 is defined by layout. If the position of the corresponding PN metal gate interface AA needs to be changed, the layout of the region 206 can be modified.
[0179] As Figure 4 shown, it is a cross-sectional view along Figure 3 line BB in; the N-type metal gate structure includes: a gate dielectric layer 303, a bottom barrier layer, an N-type work function layer 306, and a metal gate conductive material layer 309.
[0180] The P-type metal gate structure includes: the gate dielectric layer 303, the bottom barrier layer, a P-type work function layer 307, and the metal gate conductive material layer 309.
[0181] The P-type metal gate structure further includes: a top barrier layer 308 located between the P-type work function layer 307 and the metal gate conductive material layer 309.
[0182] In the method of the embodiment of the present invention, the material of the gate dielectric layer 303 is a high-k material.
[0183] An interface layer 302 is formed between the gate dielectric layer 303 and the semiconductor substrate at the bottom. The first active region 202a and the second active region 202b are both composed of the semiconductor substrate within the region surrounded by field oxide 203. A P-well is formed in the first active region 202a, and an N-well is formed in the second active region 202b. Figure 4In it, to the left of the PN metal gate interface AA is the formation region of the PMOS transistor, and to the right is the formation region of the NMOS transistor.
[0184] In some embodiments of the method, the material of the semiconductor substrate includes silicon.
[0185] The interface layer 302 is made of silicon dioxide.
[0186] The high-k dielectric material includes hafnium oxide.
[0187] The bottom barrier layer includes a stacked layer of TiN and TaN, such as Figure 4 the TiN layer 304 and TaN layer 305 shown in
[0188] The material of the top edge barrier layer includes TaN.
[0189] The material of the N-type work function layer 306 includes TiAl.
[0190] The material of the P-type work function layer 307 includes TiN.
[0191] In the embodiments of the present invention, as Figure 3 shown, due to circuit requirements, the pull-down transistor (PD) and the pull-up transistor (PU) share a common PO for metal gate striping. However, due to their different Vt settings, the filling films of their work functions (WF) are different, which inevitably leads to a junction between the N-type metal gate structure (NMG) and the P-type metal gate structure (PMG), namely the PN metal gate interface AA. Due to the mutual diffusion of metal atoms between the NMG and the PMG, such as the Al diffusion shown by the arrow line 301, thus, the threshold voltages (|VT|) of the PD and the PU change with the position of the N / P metal boundary, i.e., the PN metal gate interface AA. The closer the boundary is to the PD or the PU, the higher its Vt will be; while the PG is not affected by the MBE effect, thereby achieving the purpose of adjusting the performance of different MOSFET devices.
[0192] In this application, however, due to the difference in the work functions of PD and PU, an NP metal gate boundary will appear, causing the work functions of the two to influence each other, thereby changing the threshold voltages of PD and PU. This effect is called the metal boundary effect, also known as the MBE effect. The embodiments of the present invention aim to regulate the performance of MOSFET devices by changing the layout to control the magnitude of MBE, altering the proportional relationship between transistors, and thereby achieving the purpose of controlling the read and write performance of SRAM. The embodiments of the present invention can independently regulate the performance of each device, including the threshold voltage, saturation current, etc., without changing the process flow, and thus can control the performance of SRAM, which is simple and easy to implement.
[0193] In the method of the embodiments of the present invention, first, the size of the PMG CD is changed through the layout to adjust the distance between it and the active region AA; then: the device manufacturing is completed according to the standard CMOS process.
[0194] Then, the following steps are carried out: a WAT test is performed to extract the electrical parameters such as the threshold voltage and saturation current of the NPG (N-type select transistor), NPD (N-type pull-down transistor), and PPU (P-type pull-up transistor), as well as the SRAM electrical parameters. Then, through the analysis of the electrical properties, it can be seen that the purpose of regulating the read and write performance of SRAM is achieved by controlling the effect of the metal gate boundary.
[0195] For the PG (select transistor), its poly will be cut off by POC, and there is no N and P metal gate boundary effect. Due to circuit requirements, PD and PU share a PO. However, due to the different Vt settings, the filling films of their work functions are different, which inevitably leads to a boundary between NMG and PMG. Due to the mutual diffusion of metal atoms between N-MG and P-MG, the threshold voltages (|VT|) of PD and PU change with the different positions of the N / P metal boundary. The closer the boundary is to PD or PU, its Vt will increase. As the distance of the MBE interface AA changes, the performance of each individual transistor is different. PD and PU have different responses with different MBE positions. If the MBE is close to PU and far from PD, the Vt of PU will increase, and the corresponding Vt of PD will decrease, and the ratios of SRAM will change. Conversely, if the MBE is close to PD, the opposite effect will occur. The PG does not have the MBE effect, and its Vt changes little with the change of distance, unless the distance changes too much and a boundary is generated across POC; therefore, by changing the MBE position, the purpose of regulating the ratio of the SRAM cell is achieved, and the read and write performance of SRAM can be controllably adjusted.
[0196] The present invention has been described in detail through specific embodiments, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.
Claims
1. A structure for regulating the performance of a semiconductor device, characterized in that: include: A first active region and a second active region are arranged in parallel, and field oxide is disposed on the periphery of the first active region and the periphery of the second active region; The first active region is used to form an NMOS transistor, and the second active region is used to form a PMOS transistor; A first metal gate strip spanning the first active region and the second active region, wherein the first metal gate strip is perpendicular to the first active region; The first metal gate strip has a PN metal gate interface, and the PN metal gate interface is located on the top of the field oxide between the first active area and the second active area; The PN metal gate interface divides the first metal gate strip into an N-type metal gate structure across the first active area and a P-type metal gate structure across the second active area. The position of the PN metal gate interface serves as a control structure for the performance of the semiconductor device. The position of the PN metal gate interface is set according to the performance requirements of the semiconductor device and is defined through a layout. The closer the PN metal gate interface is to the first active area and the farther it is from the second active area, the greater the threshold voltage of the NMOS tube and the smaller the threshold voltage of the PMOS tube. Conversely, the farther the PN metal gate interface is from the first active area and the closer it is to the second active area, the smaller the threshold voltage of the NMOS tube and the greater the threshold voltage of the PMOS tube.
2. The structure for regulating semiconductor device performance according to claim 1, characterized in that: The semiconductor device includes an SRAM, and the storage unit of the SRAM includes: a first pull-down tube, a second pull-down tube, a first selection tube and a second selection tube composed of the NMOS tube, and a first pull-up tube and a second pull-up tube composed of the PMOS tube; The first pull-down tube, the second pull-down tube, the first selection tube and the second selection tube are all formed in the first active area; The first pull-up tube and the second pull-up tube are both formed in the second active area; The first pull-down tube and the first pull-up tube share the first metal grid strip; The second pull-down tube and the second pull-down tube share another first metal grid strip; The first pull-down tube and the second pull-down tube share a first N+ source region; The first pull-up tube and the second pull-up tube share a first P+ source region; The first pull-down tube and the first selection tube share a first N+ drain region; The second pull-down tube and the second selection tube share a second N+ drain region; A second metal grid bar is arranged on the top of the first selection tube; Another second metal grid bar is arranged on the top of the second selection tube; Each of the second metal gate strips is an N-type metal gate structure.
3. The structure for regulating semiconductor device performance according to claim 2, characterized in that: The SRAM is formed by arranging a plurality of the memory cells; The layout structure of the SRAM includes: The first active regions of the memory cells in the same row are connected together, and the second active regions are spaced apart from each other; In the column structure, the second active regions of the memory cells in two adjacent columns are staggered, and each of the first metal gate strips is aligned with the corresponding second metal gate strip and has a gap therebetween.
4. The structure for regulating semiconductor device performance according to claim 1, characterized in that: The N-type metal gate structure comprises: a gate dielectric layer, a bottom barrier layer, an N-type work function layer and a metal gate conductive material layer; The P-type metal gate structure includes: the gate dielectric layer, the bottom barrier layer, a P-type work function layer and the metal gate conductive material layer.
5. The structure for regulating semiconductor device performance according to claim 4, characterized in that: The P-type metal gate structure also includes: a top barrier layer located between the P-type work function layer and the metal gate conductive material layer.
6. The structure for regulating semiconductor device performance according to claim 5, characterized in that: The gate dielectric layer is made of a high dielectric constant material; An interface layer is formed between the gate dielectric layer and the bottom semiconductor substrate.
7. The structure for regulating semiconductor device performance according to claim 6, characterized in that: The material of the semiconductor substrate includes silicon; The interface layer comprises silicon dioxide; The high dielectric constant material includes hafnium oxide; The bottom barrier layer includes a stacked layer of TiN and TaN; The material of the top edge barrier layer includes TaN; The material of the N-type work function layer includes TiAl; The material of the P-type work function layer includes TiN.
8. A method for regulating the performance of a semiconductor device, characterized in that: include: Step 1: setting the position of the metal gate interface in the layout of the semiconductor device according to the performance requirements of the semiconductor device; The metal gate interface is an interface between an N-type metal gate structure across the first active region and a P-type metal gate structure across the second active region in the first metal gate strip; The first active region and the second active region are arranged in parallel, and field oxygen is disposed on the periphery of the first active region and the periphery of the second active region; The first active region is used to form an NMOS transistor, and the second active region is used to form a PMOS transistor; The semiconductor device has the first metal gate strip crossing the first active area and the second active area, and the first metal gate strip is perpendicular to the first active area; The PN metal gate interface is located on the top of the field oxide between the first active region and the second active region; Step 2: completing the production of the semiconductor device on a product wafer according to the layout of the semiconductor device; The position of the PN metal gate interface serves as a control structure for the performance of the semiconductor device. The closer the PN metal gate interface is to the first active area and the farther it is from the second active area, the greater the threshold voltage of the NMOS tube and the smaller the threshold voltage of the PMOS tube. Conversely, the farther the PN metal gate interface is from the first active area and the closer it is to the second active area, the smaller the threshold voltage of the NMOS tube and the greater the threshold voltage of the PMOS tube.
9. The method for regulating the performance of a semiconductor device according to claim 8, characterized in that: Before step 1, the following steps are also included: Step 01, changing the layout of the semiconductor device to obtain a plurality of different position structures of the metal gate interface; Step 02, completing the fabrication of the semiconductor device corresponding to the metal gate interface at different positions on the test piece; Step 03, testing the test piece, extracting the electrical parameters of the semiconductor device and obtaining the relationship between the electrical parameters of the semiconductor device and the position of the metal gate interface; The electrical parameters include the threshold voltage and saturation current of the NMOS tube and the threshold voltage and saturation current of the PMOS tube; In step one, the layout of the semiconductor device on the product wafer is set according to the relationship between the electrical parameters of the semiconductor device and the position of the metal gate interface.
10. The method for regulating semiconductor device performance according to claim 8, characterized in that: The semiconductor device includes an SRAM, and the storage unit of the SRAM includes: a first pull-down tube, a second pull-down tube, a first selection tube and a second selection tube composed of the NMOS tube, and a first pull-up tube and a second pull-up tube composed of the PMOS tube; The first pull-down tube, the second pull-down tube, the first selection tube and the second selection tube are all formed in the first active area; The first pull-up tube and the second pull-up tube are both formed in the second active area; The first pull-down tube and the first pull-up tube share the first metal grid strip; The second pull-down tube and the second pull-down tube share another first metal grid strip; The first pull-down tube and the second pull-down tube share a first N+ source region; The first pull-up tube and the second pull-up tube share a first P+ source region; The first pull-down tube and the first selection tube share a first N+ drain region; The second pull-down tube and the second selection tube share a second N+ drain region; A second metal grid bar is arranged on the top of the first selection tube; Another second metal grid bar is arranged on the top of the second selection tube; Each of the second metal gate strips is an N-type metal gate structure.
11. The method for regulating semiconductor device performance according to claim 10, characterized in that: The SRAM is formed by arranging a plurality of the memory cells; The layout structure of the SRAM includes: The first active regions of the memory cells in the same row are connected together, and the second active regions are spaced apart from each other; In the column structure, the second active regions of the memory cells in two adjacent columns are staggered, and each of the first metal gate strips is aligned with the corresponding second metal gate strip and has a gap therebetween.
12. The method for regulating semiconductor device performance according to claim 8, characterized in that: The N-type metal gate structure comprises: a gate dielectric layer, a bottom barrier layer, an N-type work function layer and a metal gate conductive material layer; The P-type metal gate structure includes: the gate dielectric layer, the bottom barrier layer, a P-type work function layer and the metal gate conductive material layer.
13. The method for regulating semiconductor device performance according to claim 12, characterized in that: The P-type metal gate structure also includes: a top barrier layer located between the P-type work function layer and the metal gate conductive material layer.
14. The method for regulating semiconductor device performance according to claim 13, characterized in that: The gate dielectric layer is made of a high dielectric constant material; An interface layer is formed between the gate dielectric layer and the bottom semiconductor substrate.
15. The method for regulating semiconductor device performance according to claim 14, characterized in that: The material of the semiconductor substrate includes silicon; The interface layer comprises silicon dioxide; The high dielectric constant material includes hafnium oxide; The bottom barrier layer includes a stacked layer of TiN and TaN; The material of the top edge barrier layer includes TaN; The material of the N-type work function layer includes TiAl; The material of the P-type work function layer includes TiN.