Semiconductor structure, preparation method thereof and storage array structure

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a preparation method thereof, and a memory array structure. The writing transistor and the reading transistor are located on the substrate, the writing transistor comprises a first grid electrode, a first semiconductor layer surrounding the first grid electrode, a writing bit line extending in the first direction and a writing word line extending in the second direction, the writing bit line is in electric contact with the first end of the first semiconductor layer, and the writing word line is in electric contact with the first grid electrode; the reading transistor comprises a second semiconductor layer, a second grid electrode, a reading bit line extending along the second direction and a reading word line extending along the first direction, the second grid electrode is electrically contacted with the second end of the first semiconductor layer, and the reading bit line is electrically contacted with one end of the second semiconductor layer along the first direction; wherein orthographic projections of the reading bit line, the reading word line, the writing word line and the writing bit line on the substrate are not overlapped, and the writing bit line and the reading word line are located on the two sides of the first semiconductor layer in the third direction.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductors, and particularly to a semiconductor structure, a preparation method thereof, and a storage array structure. Background Art

[0002] The DRAM storage unit in a computer is made of a single transistor and a single capacitor, namely the so-called 1T1C design. When writing, the transistor is turned on, and charges are pushed into or removed from the capacitor; when reading, the charges (if any) are extracted and measured. This system is extremely fast, inexpensive, and has low power consumption, but it also has some disadvantages.

[0003] First, the charge in the capacitor is consumed during reading, so reading means writing the bit back to memory. Even without reading, the charge will eventually leak out of the capacitor through the transistor. All cells need to be refreshed regularly to maintain data. In current DRAM chips, this operation is completed every 64 ms. However, there are difficulties in preparing capacitors and manufacturing transistors with ultra-low leakage at present. Therefore, it is difficult to manufacture excellent capacitors in the manufacturing process for logic circuits.

[0004] For the above reasons, the new embedded capacitorless DRAM, abbreviated as 2T0C structure, is applied. The 2T0C embedded DRAM consists of a read transistor and a write transistor to form a unit structure, and uses the gate capacitance to store charges and changes the transistor transconductance to store information. How to reduce the interference between transistors during the preparation of the 2T0C structure is a problem that those skilled in the art need to consider currently. Summary of the Invention

[0005] Embodiments of the present disclosure provide a semiconductor structure, a preparation method thereof, and a storage array structure, which are at least beneficial to reducing the interference between transistors.

[0006] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a substrate; a write transistor located on the substrate, the write transistor including a first gate, a first semiconductor layer surrounding the first gate, a write bit line extending in a first direction, and a write word line extending in a second direction, the first semiconductor layer including a first end and a second end opposite to each other in a third direction, the write bit line being in electrical contact with the first end, and the write word line being in electrical contact with the first gate; a read transistor, the read transistor including a second semiconductor layer, a second gate, a read bit line extending in the second direction, and a read word line extending in the first direction, the second gate being in electrical contact with the second end, the read bit line being in electrical contact with one end of the second semiconductor layer in the first direction, and the read word line being located on one side of the second semiconductor layer in the third direction; wherein, the orthographic projections of the read bit line, the read word line, the write word line, and the write bit line on the substrate do not overlap with each other, and the write bit line and the read word line are located on both sides of the first semiconductor layer in the third direction, and the write bit line and the read word line are located on both sides of the second semiconductor layer in the third direction.

[0007] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a memory array structure, including the semiconductor structure according to any one of the above embodiments, a plurality of semiconductor structures being arranged in an array along the first direction and the second direction, the write word line being electrically connected to a plurality of first gates arranged along the second direction, the write bit line being electrically connected to the first ends of a plurality of first semiconductor layers arranged along the first direction; the read transistor being located on one side of the first semiconductor layer of the corresponding write transistor in the third direction; the read bit line being electrically connected to the third ends of a plurality of second semiconductor layers arranged along the second direction, the read word line being located on one side of a plurality of second semiconductor layers arranged along the first direction; the orthographic projections of at least two write bit lines on the substrate overlap; and / or, the orthographic projections of at least two read word lines on the substrate overlap.

[0008] According to some embodiments of the present disclosure, on yet another hand, an embodiment of the present disclosure further provides a manufacturing method of a semiconductor structure of a memory array structure, including: providing a substrate; forming a write transistor and a read transistor, the write transistor being located on the substrate, the write transistor including a first gate, a first semiconductor layer surrounding the first gate, a write bit line extending in a first direction, and a write word line extending in a second direction, the first semiconductor layer including a first end and a second end opposite to each other in a third direction, the write bit line being in electrical contact with the first end, and the write word line being in electrical contact with the first gate; the read transistor being located on one side of the first semiconductor layer in the third direction; the read transistor including a second semiconductor layer, a second gate, a read bit line extending in the second direction, and a read word line extending in the first direction, the second gate being in electrical contact with the second end, the read bit line being in electrical contact with one end of the second semiconductor layer in the first direction, and the read word line being located on one side of the second semiconductor layer in the third direction; wherein, the orthographic projections of the read bit line, the read word line, the write word line, and the write bit line on the substrate do not overlap with each other.

[0009] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0010] The semiconductor structure, its manufacturing method, and the memory array structure provided by the embodiments of the present disclosure are configured such that the write transistor includes a write bit line extending in a first direction and a write word line extending in a second direction; the read transistor includes a read bit line extending in the second direction and a read word line extending in the first direction. The orthographic projections of the read bit line, the read word line, the write word line, and the write bit line on the substrate do not overlap with each other. Moreover, the write bit line and the read word line are located on both sides of the first semiconductor layer in a third direction, and the write bit line and the read word line are located on both sides of the second semiconductor layer in the third direction. Among them, the write bit line and the read word line can adopt the step structure in the conventional structure to reduce the interference between the write bit line and the write word line and the interference between the read bit line and the read word line. The orthographic projections of the read bit line, the read word line, the write word line, and the write bit line on the substrate do not overlap with each other. Also, the write bit line and the read word line are located on both sides of the first semiconductor layer in a third direction, and the write bit line and the read word line are located on both sides of the second semiconductor layer in the third direction. It can be seen that the read transistor and the write transistor do not affect each other, and the distance between the write bit line and the read word line is relatively far. Thus, the read-write crosstalk between cells can be avoided. Description of the Drawings

[0011] One or more embodiments are illustrated by way of example in the pictures of the corresponding drawings. These exemplary illustrations do not limit the embodiments unless otherwise stated. The figures in the drawings are not drawn to scale. To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the following-described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0012] Figure 1 Schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0013] Figure 2 is Figure 1 the circuit diagram of the corresponding semiconductor structure;

[0014] Figure 3 Schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0015] Figure 4 is Figure 3 the circuit diagram of the corresponding semiconductor structure;

[0016] Figure 5 Schematic diagram of the first structure of a memory array structure provided by another embodiment of the present disclosure;

[0017] Figure 6 is Figure 5Top view of the corresponding memory array structure;

[0018] Figure 7 is Figure 5 Circuit diagram of the corresponding memory array structure;

[0019] Figure 8 Schematic diagram of the second structure of a memory array structure provided by another embodiment of the present disclosure;

[0020] Figure 9 Schematic diagram of the third structure of a memory array structure provided by another embodiment of the present disclosure;

[0021] Figure 10 Schematic diagram of the fourth structure of a memory array structure provided by another embodiment of the present disclosure;

[0022] Figure 11 Schematic diagram of the fifth structure of a memory array structure provided by another embodiment of the present disclosure;

[0023] Figure 12 Schematic diagram of the sixth structure of a memory array structure provided by another embodiment of the present disclosure;

[0024] Figure 13 is Figure 12 Partial structure schematic diagram corresponding to the protruding portion in;

[0025] Figure 14 Schematic diagram of the semiconductor structure corresponding to the preparation of the first film layer and the second film layer in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0026] Figure 15 is Figure 14 Cross-sectional structure schematic diagram along the A1 - A2 section or along the B1 - B2 section;

[0027] Figure 16 Schematic diagram of the semiconductor structure corresponding to the formation of the first groove in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0028] Figure 17 is Figure 16 Cross-sectional structure schematic diagram along the A1 - A2 section;

[0029] Figure 18 is Figure 16 Cross-sectional structure schematic diagram along the B1 - B2 section;

[0030] Figure 19 Cross-sectional structure schematic diagram of a semiconductor structure corresponding to the formation of a write transistor in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0031] Figure 20 Another cross-sectional structure diagram of the semiconductor structure corresponding to the write transistor formed in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0032] Figure 21 A structure diagram of the semiconductor structure corresponding to the write bit line formed in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0033] Figure 22 A structure diagram of the semiconductor structure corresponding to the removal of the second film layer formed in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0034] Figure 23 A cross-sectional structure diagram of the semiconductor structure corresponding to the formation of the second semiconductor layer formed in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0035] Figure 24 Another cross-sectional structure diagram of the semiconductor structure corresponding to the formation of the second semiconductor layer formed in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0036] Figure 25 A cross-sectional structure diagram of the semiconductor structure corresponding to the formation of the second groove formed in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0037] Figure 26 A cross-sectional structure diagram of the semiconductor structure corresponding to the formation of the read bit line formed in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0038] Figure 27 A cross-sectional structure diagram of the semiconductor structure corresponding to the removal of the third film layer formed in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0039] Figure 28 A cross-sectional structure diagram of the semiconductor structure corresponding to the formation of the read word line formed in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure. Detailed implementation manners

[0040] As can be seen from the background art, there is an interference problem between transistors in the current semiconductor structure.

[0041] An embodiment of the present disclosure provides a semiconductor structure, a method for manufacturing the same, and a memory array structure. The write transistor is provided with a write bit line extending in a first direction and a write word line extending in a second direction; the read transistor includes a read bit line extending in the second direction and a read word line extending in the first direction. The orthographic projections of the read bit line, the read word line, the write word line, and the write bit line on the substrate do not overlap with each other, and the write bit line and the read word line are located on both sides of the first semiconductor layer along a third direction, and the write bit line and the read word line are located on both sides of the second semiconductor layer along the third direction. Among them, the write bit line and the read word line can adopt a step structure in a conventional structure to reduce the interference between the write bit line and the write word line and the interference between the read bit line and the read word line; the orthographic projections of the read bit line, the read word line, the write word line, and the write bit line on the substrate do not overlap with each other, and the write bit line and the read word line are located on both sides of the first semiconductor layer along a third direction, and the write bit line and the read word line are located on both sides of the second semiconductor layer along the third direction. It can be seen that the read transistor and the write transistor do not affect each other, and the distance between the write bit line and the read word line is relatively far, thereby avoiding read-write crosstalk between cells.

[0042] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are proposed for the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0043] Figure 1 It is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 2 is Figure 1 the circuit diagram of the corresponding semiconductor structure.

[0044] Refer to Figure 1 According to this application, an embodiment provides a semiconductor structure, including: a substrate.

[0045] In some embodiments, the substrate is a single-layer structure, and the material of the substrate is a semiconductor material, which may include any one of silicon, germanium, silicon carbide, or silicon germanide. The substrate has an N-type doping element or a P-type doping element. The N-type doping element may be a group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), and the P-type doping element may be a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0046] Continue to refer to Figure 1, the semiconductor structure includes: a write transistor 10 located on a substrate, the write transistor 10 includes a first gate, a first semiconductor layer 101 surrounding the first gate, a write bit line 104 extending along a first direction Y, and a write word line 103 extending along a second direction Z. The first semiconductor layer 101 includes a first end 106 and a second end 107 opposite to each other along a third direction X. The write bit line 104 is in electrical contact with the first end 106, and the write word line 103 is in electrical contact with the first gate; a read transistor 11, the read transistor 11 includes a second semiconductor layer 111, a second gate 113, a read bit line 114 extending along the second direction Z, and a read word line 116 extending along the first direction Y. The second gate 113 is in electrical contact with the second end 107, the read bit line 114 is in electrical contact with one end of the second semiconductor layer 111 along the first direction Y, and the read word line 116 is located on one side of the second semiconductor layer 111 along the third direction X; wherein, the orthographic projections of the read bit line 114, the read word line 116, the write word line 103, and the write bit line 104 on the substrate do not overlap with each other, and the write bit line 104 and the read word line 116 are located on both sides of the first semiconductor layer 101 along the third direction X, and the write bit line 104 and the read word line 116 are located on both sides of the second semiconductor layer 111 along the third direction X.

[0047] Reference Figure 1 , the read transistor 11 further includes: a conductive layer 117 extending along the second direction Z and a third gate; the third gate is located on one side of the second semiconductor layer 111 along the third direction X, and the read word line 116 is in electrical contact with the third gate; the second semiconductor layer 111 includes a third end 121 and a fourth end 122 oppositely arranged along the first direction Y, the read bit line 114 is in electrical contact with the third end 121, and the conductive layer 117 is in electrical contact with the fourth end 122.

[0048] In some embodiments, Figure 1 The semiconductor structure shown is a double-gate 2T0C structure, that is, an auxiliary gate (the second gate) is added. The second gate is connected to the source-drain end of the write transistor 10, and the voltage is provided by the source-drain end of the write transistor 10, and the source-drain end of the write transistor 10 is set to store the write voltage of the write transistor 10. Due to the back-gate effect of the transistor gate, as the write transistor 10 writes voltage to the source-drain end of the write transistor 10, the auxiliary gate of the read transistor 11 obtains the corresponding write voltage, and according to the difference in the write voltage of the auxiliary gate (for example, high voltage or low voltage), the gate of the read transistor 11 will exhibit different threshold voltages (V TH ); for an N-type read transistor, when the voltage of the auxiliary gate is a high voltage (for example, the write voltage is "1"), V TH will shift negatively; when the voltage of the auxiliary gate is a low voltage (for example, the write voltage is "0"), V THIt will shift positively. When the read transistor 11 reads the write voltage, it can adjust the input voltage of the third gate according to the voltage on the second gate (i.e., the voltage at the source-drain terminal of the write transistor 10), ensuring the conduction between the source and drain of the read transistor 11, thus avoiding the influence of the back-gate effect on the gate of the read transistor 11 and successfully reading the storage voltage of the write transistor 10.

[0049] In some embodiments, referring to Figure 2 , the write transistor 10 and the read transistor 11 form a 2T0C structure. Among them, the write transistor 10 includes a first pin W1, a second pin W2, and a third pin W3; the first pin W1 is the first source-drain terminal of the write transistor 10, and the first pin W1 is electrically connected to the write bit line WBL. The second pin W2 is the second source-drain terminal of the write transistor 10, and the second pin W2 is electrically connected to the second gate of the write transistor 10; the third pin W3 is the gate terminal of the write transistor 10, and the third pin W3 is electrically connected to the write word line WWL. The read transistor 11 includes a first end point R1, a second end point R2, a third end point R3, and a fourth end point R4. The first end point R1 is the third source-drain terminal of the read transistor 11, and the first end point R1 is electrically connected to the read bit line RBL. The second end point R2 is the fourth source-drain terminal of the read transistor 11, and the second end point R2 is set to input a reference voltage Vref. The third end point R3 is the first gate control terminal of the read transistor 11, and the first gate control terminal is electrically connected to the second pin W2 of the write transistor 10. The fourth end point R4 is the second gate control terminal of the read transistor 11, and the second gate control terminal is electrically connected to the read word line RWL.

[0050] In some embodiments of the present application, compared with the traditional 2T0C structure, the dual-gate 2T0C structure retains the advantages of the traditional 2T0C structure while the read operation is non-destructive, has very low leakage, does not require a large-capacitance capacitor, and indium gallium zinc oxide (IGZO) transistors can be used in this structure. Therefore, the 2T0C structure in some embodiments of the present application solves the problem of the need for a large capacitor, and correspondingly reduces the refresh frequency and power consumption.

[0051] In some embodiments, the material of the first semiconductor layer 101 includes a semiconductor material, such as silicon, germanium, or silicon germanide.

[0052] In some embodiments, the material of the first semiconductor layer 101 is an amorphous material. The amorphous material has gaps inside and has a high carrier mobility, which can reduce the thickness of the first semiconductor layer 101. Within a limited cell area, the line width of the semiconductor structure can be reduced, further improving the storage density of the semiconductor structure. The amorphous material may include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide), or ITO (Indium Tin Oxide).

[0053] In some embodiments, the material of the first semiconductor layer 101 includes IGZO. The carrier mobility of IGZO is 20 to 50 times that of polysilicon, which is beneficial to improving the carrier mobility in the first semiconductor layer 101, thereby facilitating the reduction of leakage current when the semiconductor structure operates, reducing the power consumption of the semiconductor structure, and improving the working efficiency of the semiconductor structure. In addition, the thin film deposition process for preparing IGZO is simple and the deposition temperature is low, which can improve the problems of thermal damage and thermal defects suffered by the substrate and the active layer. Due to the characteristics of IGZO itself, the uniformity of the large-area first semiconductor layer 101 prepared with IGZO is good, which can improve the electrical properties and stability of the first semiconductor layer 101.

[0054] In some embodiments, the first semiconductor layer 101 includes a first source-drain end, a first channel region, and a second source-drain end arranged in sequence. The first source-drain end is in electrical contact with the write bit line 104, the second source-drain end is in electrical contact with the second gate 113, the first gate faces the first channel region, and the first gate is in electrical contact with the write word line 103. Among them, the materials of the first gate and the write word line in the embodiments of the present application are the same and can be prepared in the same manufacturing process, so Figure 1 the reference numeral of the first gate is not shown in the figure.

[0055] In some embodiments, the material of the write bit line 104 includes a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), tungsten (W), or their alloys.

[0056] In some embodiments, the material of the write word line 103 includes a metal material such as copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten, or their alloys.

[0057] In some embodiments, the material of the second semiconductor layer 111 includes a semiconductor material and an amorphous material.

[0058] In some embodiments, the second semiconductor layer 111 includes a third source / drain terminal, a second channel region, and a fourth source / drain terminal arranged in sequence. The third source / drain terminal is in electrical contact with the read bit line 114, the fourth source / drain terminal is in electrical contact with the conductive layer 117, the second channel region includes a first sub-channel region and a second sub-channel region, the first sub-channel region faces the second gate, and the second sub-channel region faces the third gate.

[0059] In some embodiments, the material of the second gate 113 includes a metal material such as doped polysilicon, copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten, or an alloy thereof.

[0060] In some embodiments, the material of the read bit line 114 includes a metal material such as copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten, or an alloy thereof.

[0061] In some embodiments, the material of the conductive layer 117 includes a metal material such as copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten, or an alloy thereof.

[0062] In some embodiments, the material of the read word line 116 includes a metal material such as copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten, or an alloy thereof.

[0063] In some embodiments, the read word line 116 is made of the same material as the third gate. The read word line 116 and the third gate are fabricated in the same manufacturing process. In this way, there is no interface threshold difference between the materials of the read word line 116 and the third gate, and current can cross the interface between the third gate and the read word line 116 without an interface, thereby improving the migration speed of the current and the response speed of the third gate.

[0064] It should be noted that non-overlapping in the orthographic projection includes: the areas and contours of the orthographic projections do not overlap at all, that is, the sides of the orthographic projections do not overlap (refer to Figure 1 ).

[0065] Continuing to refer to Figure 1 , the semiconductor structure further includes: a first gate dielectric layer 102 located between the first semiconductor layer 101 and the first gate; a second gate dielectric layer 112 located between the second gate 113 and the second semiconductor layer 111; and a third gate dielectric layer 115 located between the second semiconductor layer 111 and the third gate.

[0066] In some embodiments, the material of the first gate dielectric layer 102 may include silicon oxide, silicon carbide, silicon nitride, or other high-k materials for suppressing the short-channel effect and thus suppressing tunneling leakage current and the like.

[0067] In some embodiments, the material of the second gate dielectric layer 112 may include silicon oxide, silicon carbide, silicon nitride, or other high-k materials, which are used to suppress the short-channel effect, thereby suppressing tunneling leakage current and the like.

[0068] In some embodiments, the material of the third gate dielectric layer 115 may include silicon oxide, silicon carbide, silicon nitride, or other high-k materials, which are used to suppress the short-channel effect, thereby suppressing tunneling leakage current and the like.

[0069] Continuing to refer to Figure 1 , the semiconductor structure further includes: a first filling layer 105, the first filling layer 105 is located on the surface of the substrate, and the first filling layer 105 is located between the write bit line 104 and the read bit line 114.

[0070] In some embodiments, the write transistor 10 or the read transistor 11 may be an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or may be a P-type MOSFET.

[0071] Embodiments of the present disclosure provide a semiconductor structure. The write transistor 10 is provided with a write bit line 104 extending in the first direction Y and a write word line 103 extending in the second direction Z; the read transistor 11 includes a read bit line 114 extending in the second direction Z and a read word line 116 extending in the first direction Y. The orthographic projections of the read bit line 114, the read word line 116, the write word line 103, and the write bit line 104 on the substrate do not overlap with each other, and the write bit line 104 and the read word line 116 are located on both sides of the first semiconductor layer 101 along the third direction X, and the write bit line 104 and the read word line 116 are located on both sides of the second semiconductor layer 111 along the third direction X. Among them, the write bit line 104 and the read word line 116 may adopt a stepped structure in the conventional structure to reduce the interference between the write bit line 104 and the write word line 103 and the interference between the read bit line 114 and the read word line 116; the orthographic projections of the read bit line 114, the read word line 116, the write word line 103, and the write bit line 104 on the substrate do not overlap with each other, and the write bit line 104 and the read word line 116 are located on both sides of the first semiconductor layer 101 along the third direction X, and the write bit line 104 and the read word line 116 are located on both sides of the second semiconductor layer 111 along the third direction X. It can be seen that the read transistor 11 and the write transistor 10 do not affect each other, and the distance between the write bit line 104 and the read word line 116 is relatively far, thereby avoiding read-write crosstalk between cells.

[0072] Accordingly, according to some embodiments of the present disclosure, on the other hand, the present disclosure further provides a semiconductor structure, which is different from the semiconductor structure described in the above embodiments in that: there is a third gate dielectric layer between the read word line and the second semiconductor layer of the above-mentioned semiconductor structure, and the read word line of the semiconductor structure according to the embodiments of the present disclosure is in direct electrical contact with the second semiconductor layer. The same or corresponding technical features as those in the previous embodiment will not be described herein again.

[0073] Figure 3 FIG. 4 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present disclosure; Figure 4 is Figure 3 the circuit diagram of the corresponding semiconductor structure.

[0074] Referring to Figure 3 , an embodiment of the present application provides a semiconductor structure, including: a substrate; a write transistor 20 located on the substrate, the write transistor 20 includes a first gate, a first semiconductor layer 201 surrounding the first gate, a write bit line 204 extending along a first direction Y, and a write word line 203 extending along a second direction Z. The first semiconductor layer 201 includes a first end 206 and a second end 207 opposite to each other along a third direction X. The write bit line 204 is in electrical contact with the first end 206, and the write word line 203 is in electrical contact with the first gate; a read transistor 21, the read transistor 21 includes a second semiconductor layer 211, a second gate 213, a read bit line 214 extending along the second direction Z, and a read word line 216 extending along the first direction Y. The second gate 213 is in electrical contact with the second end 207, and the read bit line 214 is in electrical contact with one end of the second semiconductor layer 211 along the first direction Y; wherein, the orthographic projections of the read bit line 214, the read word line 216, the write word line 203, and the write bit line 204 on the substrate do not overlap with each other, and the write bit line 204 and the read word line 216 are located on both sides of the first semiconductor layer 201 along the third direction X.

[0075] Referring to Figure 3 , the read word line 216 extends along the second direction Z, and the read word line 216 is in electrical contact with the fourth end 224 of the second semiconductor layer.

[0076] In some embodiments, the read word line is located on one side of the second semiconductor layer 111 along the third direction X; the read word line is in electrical contact with one side of the second semiconductor layer along the third direction X. The third end of the second semiconductor layer has a read bit line, and the fourth end may have another read bit line, that is, the read transistor includes a transistor composed of two channel regions.

[0077] In some embodiments, the material of the read word line 216 includes a metal material such as copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten, or an alloy thereof.

[0078] In some embodiments, referring to Figure 4, the write transistor 20 and the read transistor 21 form a 2T0C structure. Among them, the write transistor 20 includes a first pin W1, a second pin W2, and a third pin W3; the first pin W1 is the first source-drain terminal of the write transistor 20, and the first pin W1 is electrically connected to the write bit line WBL. The second pin W2 is the second source-drain terminal of the write transistor 20, and the second pin W2 is electrically connected to the second gate of the write transistor 20; the third pin W3 is the gate terminal of the write transistor 20, and the third pin W3 is electrically connected to the write word line WWL. The read transistor 21 includes a first end point R1, a second end point R2, and a third end point R3. The first end point R1 is the third source-drain terminal of the read transistor 21, and the first end point R1 is electrically connected to the read bit line RBL. The second end point R2 is the fourth source-drain terminal of the read transistor 21, and the second end point R2 is electrically connected to the read word line RWL. The third end point R3 is the gate control terminal of the read transistor 21, and the first gate control terminal is electrically connected to the second pin W2 of the write transistor 20.

[0079] Reference Figure 4 , the working principle of the read transistor 21 and the write transistor 20 is as follows: A relatively large voltage is applied to the gate of the write transistor 20 through the write word line WWL to turn on the write transistor 20; when it is necessary to write "1", a first voltage is applied to the write bit line WBL; when it is necessary to write "0", a second voltage is applied to the write bit line WBL. Among them, there is a certain voltage difference between the first voltage and the second voltage. Whether the data read is "1" or "0" is judged by determining whether there is current passing between the read bit line RBL and the read word line RWL.

[0080] Figure 3 The write transistor 20, the first semiconductor layer 201, the first gate, the write bit line 204, the write word line 203, the first gate dielectric layer 202, the read transistor 21, the second semiconductor layer 211, the second gate 213, the second gate dielectric layer 212, the read bit line 214, and the first filling layer 205 in the semiconductor structure shown can refer to the write transistor 10, the first semiconductor layer 101, the first gate, the write bit line 104, the write word line 103, the first gate dielectric layer 102, the read transistor 11, the second semiconductor layer 111, the second gate 113, the second gate dielectric layer 112, the read bit line 214, and the first filling layer 105 in the above embodiments, and will not be elaborated here in detail.

[0081] An embodiment of the present disclosure provides a semiconductor structure. The write transistor 20 is provided with a write bit line 204 extending in the first direction Y and a write word line 203 extending in the second direction Z; the read transistor 21 includes a read bit line 214 extending in the second direction Z and a read word line 216 extending in the first direction Y. The orthographic projections of the read bit line 214, the read word line 216, the write word line 203, and the write bit line 204 on the substrate do not overlap with each other. The write bit line 204 and the read word line 216 are located on both sides of the first semiconductor layer 201 along the third direction X, and the write bit line 204 and the read word line 216 are located on both sides of the second semiconductor layer 211 along the third direction X. Among them, the write bit line 204 and the read word line 216 can adopt a stepped structure in the conventional structure to reduce the interference between the write bit line 204 and the write word line 203 and the interference between the read bit line 214 and the read word line 216; the orthographic projections of the read bit line 214, the read word line 216, the write word line 203, and the write bit line 204 on the substrate do not overlap with each other. The write bit line 104 and the read word line 216 are located on both sides of the first semiconductor layer 201 along the third direction X, and the write bit line 204 and the read word line 116 are located on both sides of the second semiconductor layer 211 along the third direction X. It can be seen that the read transistor 21 and the write transistor 20 do not affect each other, and the distance between the write bit line 204 and the read word line 216 is relatively far, so as to avoid read-write crosstalk between cells.

[0082] Correspondingly, according to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a storage array structure, including the semiconductor structure described in any one of the above embodiments. The same or corresponding technical features as those in the previous embodiment will not be described in detail here. This application takes Figure 1 the array storage structure composed of the semiconductor structure shown as an example.

[0083] Figure 5 is the first structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure; Figure 6 is Figure 5 the top view of the corresponding storage array structure; Figure 7 is Figure 5 the circuit diagram of the corresponding storage array structure. Figure 8 is the second structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure; Figure 9 is the third structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure; Figure 10 is the fourth structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure; Figure 11 is the fifth structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure;

[0084] Figure 12 is the sixth structural schematic diagram of a storage array structure provided by another embodiment of the present disclosure.Figure 13 is Figure 12 a schematic diagram of a partial structure corresponding to the protruding part in

[0085] Referring to Figure 5 , the memory array structure includes: a plurality of semiconductor structures arranged in an array along a first direction Y and along a second direction Z, a word line 103 electrically connected to a plurality of first gates arranged along the second direction Z, and a write bit line 104 electrically connected to a first end of a plurality of first semiconductor layers 101 arranged along the first direction Y; a read transistor 11 is located on one side of the first semiconductor layer 101 of the corresponding write transistor 10 along a third direction X; a read bit line 114 is electrically connected to a third end of a plurality of second semiconductor layers 111 arranged along the second direction Z, and a read word line 116 is located on one side of a plurality of second semiconductor layers 111 arranged along the first direction Y; at least two write bit lines 104 overlap in the orthographic projection on the substrate; and / or, at least two read word lines 116 overlap in the orthographic projection on the substrate, which can save the unit configuration size of the read word line 116 and the write bit line 104, that is, there is spatial overlap in the vertical space, so as to save the floor area and footprint in the two-dimensional space and improve the integration degree in the horizontal direction of the semiconductor structure.

[0086] In some embodiments, the orthographic projection overlap includes two aspects of meanings: the first is that the area and contour of the orthographic projection are exactly the same, that is, the orthographic projections completely coincide (refer to Figure 5 ); the second is that the area and contour of the orthographic projection are not exactly the same, there is a size difference in the area, and the large area covers the small area, that is, the orthographic projections cover each other (refer to Figure 12 ).

[0087] In some embodiments, referring to Figure 6 , a plurality of semiconductor structures arranged in an array along the first direction Y and along the second direction Z form an array structure, and the array structure includes a first array structure 13 and a second array structure 14 arranged along the third direction X; the first array structure 13 and the second array structure 14 are axisymmetric about the perpendicular bisector M1-M2 of the read word line 116; and / or, the first array structure 13 and the second array structure 14 are axisymmetric about the perpendicular bisector N1-N2 of the write bit line 104. In this way, the first array structure 13 and the second array structure 14 can share the read word line 116 and the write bit line 104, thereby saving the floor area and footprint in the two-dimensional space and improving the integration degree in the horizontal direction of the semiconductor structure.

[0088] In some embodiments, referring to Figure 7 or Figure 9 , it further includes: a plurality of contact structures 108, and the contact structures 108 are in electrical contact with a connection line, and the connection line is one of the read word line 116 or the write bit line 104.

[0089] In some embodiments, the contact structure 108 is used to connect the read word line 116 or the write bit line 104 in the semiconductor structure to external components, so as to control the read word line 116 or the write bit line 104 in the semiconductor structure by regulating the external components to locate to a specific memory cell, thereby performing related reading and writing.

[0090] In some embodiments, the material of the contact structure 108 includes metallic materials such as copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten, or their alloys.

[0091] Continuing to refer to Figure 7 , the memory array structure further includes: an isolation structure 109, and the isolation structure 109 is located between some of the connection lines and the contact structure 108.

[0092] Refer to Figure 7 or Figure 9 , the other of the read word line 116 or the write bit line 104 includes: a body portion extending along the first direction Y; a connection portion extending along the third direction X, the body portion is located between the first array structure 13 and the second array structure 14, the connection portion is located on one side of the body portion along the first direction Y, and the connection portion is electrically connected to a plurality of body portions; further includes: a selection transistor 33, one side of the selection transistor 33 is electrically connected to the connection portion, and the other side of the selection transistor 33 is electrically connected to the body portion.

[0093] In some embodiments, the selection transistor 33 includes a third semiconductor layer 331, a fourth gate dielectric layer 332, and a gate conductive layer 333.

[0094] In some embodiments, refer to Figure 8 , the read word line 116 includes: a first body portion 1161 extending along the first direction Y; a first connection portion 1162 extending along the third direction X, the first body portion 1161 is located between the first array structure 13 and the second array structure 14, the first connection portion 1162 is located on one side of the first body portion 1161 along the first direction Y, and the first connection portion 1162 is electrically connected to a plurality of first body portions 1161. One side of the selection transistor 33 is electrically connected to the first connection portion 1162, and the other side of the selection transistor 33 is electrically connected to the first body portion 1162.

[0095] In some embodiments, refer to Figure 9, the write bit line 104 includes: a second body portion 1041 extending along the first direction Y; a second connection portion 1042 extending along the third direction X. The second body portion 1041 is electrically connected to the first ends of a plurality of first semiconductor layers 101 arranged along the first direction Y. The first connection portion 1042 is located on one side of the second body portion 1041 along the first direction Y, and the first connection portion 1042 is electrically connected to a plurality of second body portions 1041. One side of the selection transistor 33 is electrically connected to the second connection portion 1042, and the other side of the selection transistor 33 is electrically connected to the second body portion 1041.

[0096] Reference Figure 10 , in some embodiments, it includes: a first contact structure 128 and a second contact structure 118. The first contact structure 128 is electrically connected to the read word line 116, and the second contact structure 118 is electrically connected to the write bit line 104.

[0097] Reference Figure 11 , in some embodiments, the read word line 116 includes: a first body portion 1161 extending along the first direction Y; a first connection portion 1162 extending along the third direction X. The first body portion 1161 is located between the first array structure 13 and the second array structure 14. The first connection portion 1162 is located on one side of the first body portion 1161 along the first direction Y, and the first connection portion 1162 is electrically connected to a plurality of first body portions 1161; it further includes: a first selection transistor 35. One side of the first selection transistor 35 is electrically connected to the first connection portion 1162, and the other side of the first selection transistor 35 is electrically connected to the first body portion 1161; the write bit line 104 includes: a second body portion 1041 extending along the first direction Y; a second connection portion 1042 extending along the third direction X. The second body portion 1041 is electrically connected to the first ends of a plurality of first semiconductor layers 101 arranged along the first direction Y. The first connection portion 1042 is located on one side of the second body portion 1041 along the first direction Y, and the first connection portion 1042 is electrically connected to a plurality of second body portions 1041; it further includes: a second selection transistor 36. One side of the second selection transistor 36 is electrically connected to the second connection portion 1042, and the other side of the second selection transistor 36 is electrically connected to the second body portion 1041.

[0098] Wherein, the first selection transistor 35 includes a first active layer 351, a first gate oxide layer 352, and a first gate conductive layer 353 that are sequentially surrounded. The second selection transistor 36 includes a second active layer 361, a second gate oxide layer 362, and a second gate conductive layer 363 that are sequentially surrounded.

[0099] In some embodiments, the first connection portion 1162 and the second connection portion 1042 are located on both sides of the array structure along the first direction Y.

[0100] Reference Figure 12 and Figure 13, in some embodiments, one end of the connection line along the first direction Y has a protrusion 17. Along the third direction X towards the substrate, the length of the protrusion 17 decreases along the first direction Y, and each contact structure 108 contacts the protrusion 17; the protrusion 17 includes adjacent first protrusion 171, second protrusion 172, and third protrusion 173. The length of the second protrusion 172 is greater than that of the first protrusion 171, and the orthographic projection of the contact structure 108 in electrical contact with the second protrusion 172 on the substrate does not overlap with the orthographic projection of the first protrusion 171 on the substrate.

[0101] Wherein, the contact structure 108 includes a first plug 161 in electrical contact with the first protrusion, a second plug 162 in electrical contact with the second protrusion, and a third plug 163 in electrical contact with the third protrusion.

[0102] Correspondingly, on the other hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The same or corresponding technical features as those in the above embodiments will not be described in detail here. Figures 14 - 28 It is a schematic structural diagram of a semiconductor structure corresponding to each step in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.

[0103] It should be noted that Figures 14 - 28 It is a schematic structural diagram of each step corresponding to a method for manufacturing two memory cells (semiconductor structures) arranged along the second direction Z. Those skilled in the art can, on this basis, reduce the corresponding number of film layers to form a semiconductor structure; or increase the number of film layers to form an array structure.

[0104] Referring to Figure 14 and Figure 15 , the manufacturing method includes: providing a substrate; sequentially forming a first film layer 181 and a second film layer 182 on the surface of the substrate. Among them, in the embodiment of the present disclosure, taking the formation of two memory cells in the second direction Z as an example, therefore, the number of the second film layers 182 is 2.

[0105] In some embodiments, in the same etching process, the etching rates of the first film layer 181 and the second film layer 182 are different. The material of the first film layer 181 includes silicon oxide, and the material of the second film layer 182 includes silicon nitride.

[0106] Referring to Figure 16 , pattern the first film layer 181 and the second film layer 182 to form a first groove 183 exposing the substrate.

[0107] Figure 17 is Figure 16 a schematic cross-sectional structure diagram along the A1-A2 section; Figure 18 is Figure 16 a schematic cross-sectional structure diagram along the B1-B2 section.

[0108] Reference Figure 17 , laterally etch a second film layer 182 with a partial width along the first groove to increase the width of the first groove 183 corresponding to the second film layer 182.

[0109] Figure 19 For a method of manufacturing a semiconductor structure provided by another embodiment of the present disclosure, a schematic diagram of a cross-section along A1-A2 (reference Figure 16 ) of the semiconductor structure corresponding to the write transistor; Figure 20 For a method of manufacturing a semiconductor structure provided by another embodiment of the present disclosure, a schematic diagram of a cross-section along B1-B2 (reference Figure 16 ) of the semiconductor structure corresponding to the write transistor; Figure 21 For a method of manufacturing a semiconductor structure provided by another embodiment of the present disclosure, a schematic diagram of a cross-section along A1-A2 (reference Figure 16 ) of the semiconductor structure corresponding to the write bit line; Figure 22 For a method of manufacturing a semiconductor structure provided by another embodiment of the present disclosure, a schematic diagram of a cross-section along B1-B2 (reference Figure 16 ) of the semiconductor structure corresponding to the removal of the second film layer.

[0110] Reference Figures 19 - 21 , form a write transistor 10, the write transistor 10 is located on a substrate, the write transistor 10 includes a first gate, a first semiconductor layer 101 surrounding the first gate, a write bit line 104 extending along a first direction Y, and a write word line 103 extending along a second direction Z. The first semiconductor layer 101 includes a first end and a second end opposite to each other along a third direction X. The write bit line 104 is in electrical contact with the first end, and the write word line 103 is in electrical contact with the first gate.

[0111] Reference Figure 19 , sequentially form a first semiconductor layer 101, a first gate dielectric layer 102, and a write word line 103. The first semiconductor layer 101 and the first gate dielectric layer 102 are located between the first film layer 181 and the first film layer 181. The write word line 103 fills the first groove 183 (reference Figure 18 ). Among them, the process step of forming the write word line 103 includes forming a first gate. The material of the first gate is the same as that of the write word line 103, and the first gate and the write word line 103 are the same feature.

[0112] Reference Figure 21 , laterally remove a second film layer 182 with a partial width until the side surface of the first semiconductor layer 101 is exposed.

[0113] Continue to refer to Figure 21 , form a write bit line 104, the write bit line 104 is located between the first film layer 181 and the first film layer 181.

[0114] Continue to refer to Figure 21 , remove the second film layer 182 with a partial width (refer to Figure 20 ), but do not expose the side surface of the write bit line 104, that is, there is still a second film layer as the first filling layer 105 between the write bit line 104 and the subsequently formed read bit line 114 (refer to Figure 1 ).

[0115] Refer to Figures 23 - 28 , the preparation method includes: preparing a read transistor 11, the read transistor 11 is located on one side of the first semiconductor layer 101 along the third direction X; the read transistor 11 includes a second semiconductor layer 111, a second gate 113, a read bit line 114 extending along the second direction Z, and a read word line 116 extending along the first direction Y, the second gate 113 is in electrical contact with the second end, the read bit line 114 is in electrical contact with one end of the second semiconductor layer 111 along the first direction Y, and the read word line 116 is located on one side of the second semiconductor layer 111 along the third direction X; wherein, the orthographic projections of the read bit line 114, the read word line 116, the write word line 103, and the write bit line 104 on the substrate do not overlap with each other.

[0116] Figure 23 Schematic diagram of the semiconductor structure corresponding to the formation of the second semiconductor layer along the A1-A2 section in the preparation method of a semiconductor structure provided by another embodiment of the present disclosure (refer to Figure 16 ); Figure 24 Schematic diagram of the semiconductor structure corresponding to the formation of the second semiconductor layer along the B1-B2 section in the preparation method of a semiconductor structure provided by another embodiment of the present disclosure (refer to Figure 16 ).

[0117] Refer to Figure 23 , sequentially form a second gate 113, a second gate dielectric layer 113, and a second semiconductor layer 111 surrounding the first semiconductor layer 101.

[0118] Continue to refer to Figure 23 , form a third film layer 184, the third film layer 184 is located between adjacent first film layers 181, the third film layer 184 surrounds the second semiconductor layer 111, and the third film layer 184 is located on the side surface of the second film layer 182.

[0119] Figure 25 Schematic diagram of the semiconductor structure corresponding to the formation of the second groove along the B1-B2 section in the preparation method of a semiconductor structure provided by another embodiment of the present disclosure (refer to Figure 16 );

[0120] Refer to 25, form a second groove 185, the second groove 185 penetrates through the first film layer 181 and the fourth film layer 184 until the surface of the substrate is exposed, and the second groove 185 exposes the side surface of the second semiconductor layer 111.

[0121] Figure 26 In the method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure, the semiconductor structure corresponding to the formation of the read bit line is along the B1-B2 section (refer to Figure 16 ) schematic diagram of the structure.

[0122] Refer to Figure 26 , the read bit line 114 and the conductive layer 117 are formed. The conductive material filling one of the second grooves 185 serves as the read bit line 114, and the conductive material filling the other second groove 185 serves as the conductive layer 117.

[0123] Figure 27 In the method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure, the semiconductor structure corresponding to the removal of the third film layer is along the A1-A2 section (refer to Figure 16 ) schematic diagram of the structure.

[0124] Refer to Figure 27 , the third film layer 184 exceeding the sides of the read bit line 114 and the conductive layer 117 is removed.

[0125] Figure 28 In the method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure, the semiconductor structure corresponding to the formation of the read word line is along the A1-A2 section (refer to Figure 16 ) schematic diagram of the structure.

[0126] Refer to Figure 28 , the third gate dielectric layer 115 and the read word line 116 are formed. The third gate dielectric layer 115 and the read word line 116 are between the first film layer 181 and the first film layer 181.

[0127] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A write transistor located on the substrate, the write transistor comprising a first gate, a first semiconductor layer surrounding the first gate, a write bit line extending in a first direction, and a write word line extending in a second direction, the first semiconductor layer comprising a first end and a second end opposite to each other in a third direction, the write bit line being in electrical contact with the first end, and the write word line being in electrical contact with the first gate; A read transistor, the read transistor comprising a second semiconductor layer, a second gate, a read bit line extending in the second direction, and a read word line extending in the first direction, the second gate being in electrical contact with the second end, the read bit line being in electrical contact with one end of the second semiconductor layer in the first direction, and the read word line being located on one side of the second semiconductor layer in the third direction; Wherein, the orthographic projections of the read bit line, the read word line, the write word line, and the write bit line on the substrate do not overlap with each other, and the write bit line and the read word line are located on both sides of the first semiconductor layer in the third direction, and the write bit line and the read word line are located on both sides of the second semiconductor layer in the third direction.

2. The semiconductor structure according to claim 1, characterized in that, The read word line is in electrical contact with one side of the second semiconductor layer in the third direction.

3. The semiconductor structure according to claim 1, characterized in that, The read transistor further comprises: a conductive layer extending in the second direction and a third gate; the third gate is located on one side of the second semiconductor layer in the third direction, the read word line is in electrical contact with the third gate; the second semiconductor layer comprises a third end and a fourth end opposite to each other in the first direction, the read bit line is in electrical contact with the third end, and the conductive layer is in electrical contact with the fourth end.

4. A storage array structure, comprising the semiconductor structure according to any one of claims 1 to 3, characterized in that, A plurality of the semiconductor structures are arranged in an array along the first direction and along the second direction, the write word line is electrically connected to a plurality of the first gates arranged along the second direction, and the write bit line is electrically connected to the first ends of a plurality of the first semiconductor layers arranged along the first direction; The read transistor is located on one side of the first semiconductor layer of the corresponding write transistor in the third direction; The read bit line is electrically connected to the third ends of a plurality of the second semiconductor layers arranged along the second direction, and the read word line is located on one side of a plurality of the second semiconductor layers arranged along the first direction; The orthographic projections of at least two of the write bit lines on the substrate overlap; And / or, the orthographic projections of at least two of the read word lines on the substrate overlap.

5. The storage array structure according to claim 4, characterized in that, A plurality of the semiconductor structures arranged in an array along the first direction and along the second direction form an array structure, the array structure comprising a first array structure and a second array structure arranged along the third direction; The first array structure and the second array structure are axisymmetric about the perpendicular bisector of the read word line; And / or, the first array structure and the second array structure are axisymmetric about the perpendicular bisector of the write bit line.

6. The storage array structure according to claim 5, characterized in that, Further comprising: A plurality of contact structures, the contact structures being in electrical contact with the connection line, the connection line being one of the read word line or the write bit line.

7. The storage array structure according to claim 6, characterized in that, One end of the connection line along the first direction has a protruding portion. Along the direction of the third direction towards the substrate, the length of the protruding portion along the first direction decreases, and each contact structure contacts the protruding portion; the protruding portion includes an adjacent first protruding portion and a second protruding portion, the length of the second protruding portion is greater than the length of the first protruding portion, and the orthographic projection of the contact structure in electrical contact with the second protruding portion on the substrate does not overlap with the orthographic projection of the first protruding portion on the substrate.

8. The storage array structure according to claim 6, characterized in that, The other of the word line or the bit line includes: a body portion extending along the first direction; a connection portion extending along the third direction, the body portion is located between the first array structure and the second array structure, the connection portion is located on one side of the body portion along the first direction, and the connection portion electrically connects a plurality of the body portions; further including: a selection transistor, one side of the selection transistor is electrically connected to the connection portion, and the other side of the selection transistor is electrically connected to the body portion.

9. The storage array structure according to claim 6 or 7, characterized in that, Including: A first contact structure and a second contact structure, the first contact structure is electrically connected to the word line, and the second contact structure is electrically connected to the bit line.

10. The storage array structure according to claim 5, characterized in that, The word line includes: a first body portion extending along the first direction; a first connection portion extending along the third direction, the first body portion is located between the first array structure and the second array structure, the first connection portion is located on one side of the first body portion along the first direction, and the first connection portion electrically connects a plurality of the first body portions; further including: a first selection transistor, one side of the first selection transistor is electrically connected to the first connection portion, and the other side of the first selection transistor is electrically connected to the first body portion; the bit line includes: a second body portion extending along the first direction; a second connection portion extending along the third direction, the second body portion electrically connects the first ends of a plurality of the first semiconductor layers arranged along the first direction, the first connection portion is located on one side of the second body portion along the first direction, and the first connection portion electrically connects a plurality of the second body portions; further including: a second selection transistor, one side of the second selection transistor is electrically connected to the second connection portion, and the other side of the second selection transistor is electrically connected to the second body portion.

11. The storage array structure according to claim 10, characterized in that, The first connection portion and the second connection portion are located on both sides of the array structure along the first direction.

12. A method for manufacturing a semiconductor structure, characterized in that, Including: Providing a substrate; Forming a write transistor and a read transistor, the write transistor is located on the substrate, the write transistor includes a first gate, a first semiconductor layer surrounding the first gate, a bit line extending along the first direction, and a write word line extending along the second direction, the first semiconductor layer includes a first end and a second end opposite to each other along the third direction, the bit line is in electrical contact with the first end, and the write word line is in electrical contact with the first gate; The read transistor is located on one side of the first semiconductor layer along the third direction; the read transistor includes a second semiconductor layer, a second gate, a read bit line extending along the second direction, and a read word line extending along the first direction. The second gate is in electrical contact with the second end, the read bit line is in electrical contact with one end of the second semiconductor layer along the first direction, and the read word line is located on one side of the second semiconductor layer along the third direction; Wherein, the orthographic projections of the read bit line, the read word line, the write word line, and the write bit line on the substrate do not overlap with each other.

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