Semiconductor structure and preparation method thereof, and three-dimensional memory

Abstract

The embodiment of the invention relates to a semiconductor structure and a preparation method thereof, and a three-dimensional memory, and the semiconductor structure comprises a first word line which extends along a first direction; the semiconductor layer surrounds part of the side face of the first word line, the semiconductor layer comprises a channel region and source and drain regions located on the two sides of the channel region, and the channel region and the source and drain regions are circumferentially arranged around the side face of the first word line; the second word line extends in the first direction, is located on the side, away from the first word line, of the semiconductor layer and is opposite to the first word line; the bit line is located on the side, away from the first word line, of the semiconductor layer and extends in the second direction; the capacitor is located on the side, away from the first word line, of the semiconductor layer, and the bit line and the capacitor are located on the two opposite sides of the first word line in the third direction respectively and electrically make contact with the source region and the drain region respectively. According to the semiconductor structure provided by the embodiment of the invention, the overall size of the semiconductor structure can be reduced at least while the stability of the channel region is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same, and a three-dimensional memory. Background Art

[0002] As the integration of semiconductor devices increases, the size of memories such as dynamic random access memory (DRAM) becomes smaller and smaller, and the structure of three-dimensional memory is receiving more and more attention.

[0003] In a three-dimensional memory structure, transistors are usually stacked horizontally in an attempt to increase the integration of the memory. However, as the integration density of dynamic memory develops towards a higher direction, higher requirements are placed on the size of transistors in the dynamic memory array structure. As the size of transistors is further reduced, the performance of the memory device is inevitably degraded. For example, as the size of the channel of the transistor is reduced, the stability of the channel is lower, which impairs the performance of the transistor, and in turn causes a reduction in the electrical performance of the memory.

[0004] Therefore, how to reduce the size of the transistor while ensuring the stability of the channel region has become a problem that needs to be solved urgently. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, and a three-dimensional memory, which can at least solve the above-mentioned problems.

[0006] The embodiment of the present disclosure provides a semiconductor structure, including: a first word line, which extends along a first direction; a semiconductor layer, which surrounds a portion of the side of the first word line, and the semiconductor layer includes: a channel region and source and drain regions located on both sides of the channel region, and the channel region and the source and drain regions are arranged circumferentially around the side of the first word line; a second word line, which extends along the first direction, is located on a side of the semiconductor layer away from the first word line, and is arranged opposite to the first word line; a bit line, which is located on a side of the semiconductor layer away from the first word line and extends along a second direction; and a capacitor, which is located on a side of the semiconductor layer away from the first word line, wherein the bit line and the capacitor are respectively located on opposite sides of the first word line in a third direction, and are respectively electrically contacted with the source and drain regions, and the second direction intersects with the third direction.

[0007] In some embodiments, the semiconductor structure further includes: a first gate dielectric layer located between the semiconductor layer and the first word line; a second gate dielectric layer located between the second word line and the semiconductor layer, the second gate dielectric layer covers the channel region and exposes the source and drain regions.

[0008] In some embodiments, the material of the semiconductor layer includes IGZO.

[0009] In some embodiments, the side surface of the first word line facing the source / drain regions is an arc surface, the first gate dielectric layer conformally covers the side surface of the first word line, and the source / drain regions of the semiconductor layer conformally cover the side surface of the first gate dielectric layer.

[0010] In some embodiments, the semiconductor structure further includes: a support layer extending in a third direction, the support layer having a first side and a second side opposite to each other in a second direction, and two third sides opposite to each other in the third direction. The semiconductor layer and the first word line are embedded in the first side, and the second word line is embedded in the second side, wherein the source / drain regions of the semiconductor layer are exposed on the third sides of the support layer.

[0011] In some embodiments, the maximum width dimension of the first word line in the third direction is greater than the maximum width dimension of the second word line in the third direction.

[0012] Correspondingly, an embodiment of the present disclosure further provides a three-dimensional memory, including a plurality of semiconductor structures as described in any one of the above. A plurality of semiconductor structures arranged in the second direction share a bit line, and a plurality of semiconductor structures arranged in the first direction share the first word line and the second word line.

[0013] Correspondingly, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, including: forming a first word line extending in a first direction; forming a semiconductor layer surrounding a partial side surface of the first word line, the semiconductor layer including: a channel region and source / drain regions located on both sides of the channel region, and the channel region and the source / drain regions are circumferentially arranged around the side surface of the first word line; forming a second word line extending in the first direction, the second word line being located on a side of the semiconductor layer away from the first word line and being disposed opposite to the first word line; forming a bit line located on a side of the semiconductor layer away from the first word line and extending in a second direction; forming a capacitor located on a side of the semiconductor layer away from the first word line, wherein the bit line and the capacitor are respectively located on opposite sides of the first word line in the third direction and are respectively in electrical contact with the source / drain regions, and the second direction intersects with the third direction.

[0014] In some embodiments, before the step of forming the first word line, it further includes: forming a first gate dielectric layer covering a partial side surface of the first word line, and the semiconductor layer covers the surface of the first gate dielectric layer; and forming a second gate dielectric layer located on a side of the semiconductor layer away from the first gate dielectric layer and covering the channel region.

[0015] In some embodiments, the method of forming a semiconductor layer, a first gate dielectric layer, and a second gate dielectric layer includes: forming a support layer that extends along a third direction, the support layer having a first side and a second side that are opposite to each other along a second direction, and two third sides that are opposite to each other along the third direction; etching a part of the support layer from the first side of the support layer to form a first groove that extends from the first side to the second side; forming an initial second gate dielectric layer that conformally covers the first groove; forming a semiconductor layer in the first groove that conformally covers the initial second gate dielectric layer; forming a first gate dielectric layer in the first groove that conformally covers the surface of the semiconductor layer; etching a part of the support layer and a part of the initial second gate dielectric layer from the third side of the support layer until a part of the surface of the semiconductor layer facing away from the first word line is exposed, and the remaining part of the initial second gate dielectric layer serves as the second gate dielectric layer.

[0016] In some embodiments, the method of forming a first word line includes: forming a first word line in the remaining first groove, and the first word line fills the first groove.

[0017] In some embodiments, the method of forming a second word line includes: etching a part of the support layer from the second side of the support layer to form a second groove that extends from the second side to the first side; forming a second word line that fills the second groove.

[0018] In some embodiments, after the step of forming the second word line, a first groove is formed, and the first groove exposes the side surface of the second word line facing the first groove.

[0019] In some embodiments, along the third direction, the opening size of the first groove is larger than the opening size of the second groove.

[0020] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0021] In the semiconductor structure provided by the embodiments of the present disclosure, the semiconductor layer is arranged to surround a part of the side surface of the first word line, and the channel region and the source-drain regions of the semiconductor layer are circumferentially arranged around the side surface of the first word line. That is to say, the channel region and the source-drain regions are both located on the side surface of the word line. Compared with the case where the semiconductor layer extends in the same direction, the entire semiconductor layer surrounds a part of the side surface of the word line, which can reasonably utilize the peripheral space of the word line, greatly reduce the space occupied by the semiconductor layer in the same horizontal direction, reduce the overall size of the transistor formed by the semiconductor layer, and thus enable more transistors to be arranged in the memory, improving the integration density of the memory. In addition, a second word line is also arranged on the side of the semiconductor layer away from the first word line to form a double-gate structure, increasing the gate control ability and improving the stability of the channel region. In this way, while ensuring the stability of the channel region, the size of the transistor is reduced. Description of the Drawings

[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0023] Figure 1 Schematic three-dimensional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0024] Figure 2 Schematic top-view structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0025] Figure 3 Schematic three-dimensional structure diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 4 Schematic top-view structure diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figure 5 Schematic three-dimensional structure diagram of yet another semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figure 6 Schematic top-view structure diagram of yet another semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figure 7 Schematic three-dimensional structure diagram of a three-dimensional memory provided by another embodiment of the present disclosure;

[0030] Figure 8 Schematic three-dimensional structure diagram corresponding to the steps of forming an initial support layer and an isolation layer in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure;

[0031] Figure 9 Schematic top-view structure diagram corresponding to the step of forming a first trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0032] Figure 10 Schematic three-dimensional structure diagram corresponding to the step of forming a first trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0033] Figure 11 Schematic three-dimensional structure diagram corresponding to the step of forming an isolation structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0034] Figure 12 Schematic three-dimensional structure corresponding to the step of forming a second trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0035] Figure 13 Partial structure schematic diagram corresponding to the step of forming a first groove in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0036] Figure 14 Partial structure schematic diagram corresponding to the step of forming a first word line in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0037] Figure 15 Schematic three-dimensional structure corresponding to the step of forming a third trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0038] Figure 16 Partial structure schematic diagram corresponding to the step of forming a second groove in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0039] Figure 17 Top view structure schematic diagram corresponding to the step of forming a second word line in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0040] Figure 18 Schematic three-dimensional structure corresponding to the step of forming a second word line in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0041] Figure 19 Schematic three-dimensional structure corresponding to the step of forming a third trench in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0042] Figure 20 Partial structure schematic diagram corresponding to the step of forming a second groove in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0043] Figure 21 Partial structure schematic diagram corresponding to the step of forming a second word line in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0044] Figure 22 Schematic three-dimensional structure corresponding to the step of forming a second word line in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0045] Figure 23 Partial structure schematic diagram corresponding to the step of forming a first groove in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0046] Figure 24 Schematic three-dimensional structure diagram corresponding to the step of forming a first opening in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0047] Figure 25 Partial structure diagram corresponding to the step of etching an initial second gate dielectric layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0048] Figure 26 Schematic three-dimensional structure diagram corresponding to the step of forming a bit line in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0049] Figure 27 Partial structure diagram corresponding to the step of forming a bit line in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0050] Figure 28 Schematic three-dimensional structure diagram corresponding to the step of forming a second opening in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0051] Figure 29 Partial structure diagram corresponding to the step of forming a second gate dielectric layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0052] Figure 30 Schematic three-dimensional structure diagram corresponding to the step of forming a capacitor in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. Detailed implementation manners

[0053] As can be seen from the background art, how to reduce the size of transistors while ensuring the stability of the channel region has become an urgent problem to be solved at present. One of the reasons for the above problems is that in the current semiconductor structure, the 3D stacked DRAM structure has been widely studied. In the current 3D stacked semiconductor structure, multiple semiconductor layers are located on a substrate, extend in a direction parallel to the substrate surface, and the multiple semiconductor layers are stacked in a direction away from the substrate. The semiconductor layer includes adjacent source and drain regions and a channel region. The word line extends perpendicular to the substrate surface and is in electrical contact with the side surface of the channel region of the semiconductor layer. That is, the word lines and the semiconductor layers are arranged adjacent to each other, and the word line only contacts a part of the side surface of the semiconductor layer. The source and drain regions in the semiconductor layer extend in a direction away from the channel region, occupying the space in the extending direction of the semiconductor layer. This results in a relatively large occupied space of each transistor formed by the semiconductor layer in the extending direction of the semiconductor layer, and as the size of the semiconductor structure decreases, the arrangement density of the transistors in the semiconductor structure cannot be further increased, and the gate control ability of the channels in the semiconductor layer is poor.

[0054] Embodiments of the present disclosure provide a semiconductor structure, where the channel region and the source-drain regions are both located on the sides of the word line. Compared with the case where the semiconductor layer extends in the same direction, the entire semiconductor layer surrounds part of the sides of the word line, which can reasonably utilize the peripheral space of the word line, greatly reduce the space occupied by the semiconductor layer in the same horizontal direction, reduce the overall size of the transistor formed by the semiconductor layer, and thus enable more transistors to be arranged in the memory, improving the integration density of the memory. In addition, a second word line is provided on the side of the semiconductor layer away from the first word line to form a double-gate structure, increasing the gate control ability and improving the stability of the channel region. In this way, while ensuring the stability of the channel region, the size of the transistor is reduced.

[0055] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are provided to help the reader better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0056] Figure 1 is a schematic three-dimensional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 2 is a schematic top view structure diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 3 is a schematic three-dimensional structure diagram of another semiconductor structure provided by an embodiment of the present disclosure; Figure 4 is a schematic top view structure diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0057] Figure 5 is a schematic three-dimensional structure diagram of yet another semiconductor structure provided by an embodiment of the present disclosure; Figure 6 is a schematic top view structure diagram of yet another semiconductor structure provided by an embodiment of the present disclosure.

[0058] Refer to Figures 1 to 2, the semiconductor structure includes: a first word line 101 extending along a first direction X. The semiconductor structure further includes: a semiconductor layer 102 surrounding a partial side surface of the first word line 101, the semiconductor layer 102 including: a channel region 10 and source / drain regions 11 located on both sides of the channel region 10, the channel region 10 and the source / drain regions 11 being circumferentially arranged around the side surface of the first word line 101. The semiconductor structure further includes: a second word line 103 extending along the first direction X, the second word line 103 being located on a side of the semiconductor layer 102 facing away from the first word line 101 and being disposed opposite to the first word line 101. The semiconductor structure further includes: a bit line 104 located on a side of the semiconductor layer 102 facing away from the first word line 101 and extending along a second direction Y. The semiconductor structure further includes: a capacitor 105 located on a side of the semiconductor layer 102 facing away from the first word line 101, wherein the bit line 104 and the capacitor 105 are respectively located on opposite sides of the first word line 101 in a third direction W and are respectively in electrical contact with the source / drain regions 11, and the second direction Y intersects with the third direction W.

[0059] Each semiconductor layer 102 can be used to form a transistor. Among them, the channel region 10 can be used to form the channel of the transistor, and the two source / drain regions 11 can be respectively used to form the source electrode and the drain electrode of the transistor. The bit line 104 can be electrically connected to the source electrode, and the capacitor 105 can be electrically connected to the drain electrode.

[0060] The first word line 101 and the second word line 103 are respectively located on opposite sides of the semiconductor layer 102, and the second word line 103 is disposed opposite to the channel region 10. The first word line 101 and the second word line 103 are respectively used to form two gates of the transistor, forming a double-gate structure, increasing the gate control ability, and improving the stability of the channel region 10.

[0061] The channel region 10 and the source / drain regions 11 are arranged around the side surface of the word line, which can utilize the peripheral space of the word line to arrange the source / drain regions 11. Compared with the source / drain regions 11 and the channel region 10 extending in the same horizontal direction, the space occupied by the source / drain regions 11 in the same horizontal direction can be greatly reduced, and thus the overall size of the transistor formed by the semiconductor layer 102 can be reduced. If multiple transistors need to be integrated in the same memory, the arrangement density of the transistors can be increased, and the integration density of the memory can be improved.

[0062] Specifically, in some embodiments, the semiconductor layer 102, the first word line 101, and the second word line 103 can be located on the same substrate. The first word line 101 and the second word line 103 extend in a direction perpendicular to the surface of the substrate, that is, the first direction X is perpendicular to the surface of the substrate.

[0063] The bit line 104 and the capacitor 105 are located on the substrate. The bit line 104 extends in a direction parallel to the surface of the substrate, that is, the second direction Y is parallel to the surface of the substrate. In a specific example, the first direction X may be perpendicular to the second direction Y.

[0064] The bit line 104 and the capacitor 105 are respectively located on opposite sides of the first word line 101 in the third direction W. In some embodiments, the third direction W may be parallel to the surface of the substrate, and the third direction W is perpendicular to the second direction Y. In the related art, the semiconductor layer 102 is arranged to extend in the third direction W, and the source / drain regions 11 are respectively located on both sides of the channel region 10 in the third direction W, and thus can be electrically connected to the bit line 104 and the capacitor 105 respectively. However, this will cause the semiconductor layer 102 to occupy a relatively large space in the third direction W, so that the number of semiconductor layers 102 arranged at intervals in the third direction W is limited. In the embodiments of the present disclosure, the semiconductor layer 102 is arranged to surround the side surface of the first word line 101, and the source / drain regions 11 are located on the side surface of the word line, which can reduce the space occupied by the source / drain regions 11 in the third direction W, and further make the size of the transistor formed by the semiconductor layer 102 smaller in the third direction W. In this way, the number of transistors arranged at intervals in the third direction W can be increased, greatly increasing the arrangement density of the transistors.

[0065] In some embodiments, the material of the semiconductor layer 102 includes IGZO (indium gallium zinc oxide). IGZO is a new type of semiconductor material with high electron mobility and good stability, which can improve the response rate of the transistor. And using the IGZO material as the semiconductor layer 102 enables the thickness of the semiconductor layer 102 to be relatively small. In a specific example, the thickness of the semiconductor layer 102 can be close to the thickness of the first gate dielectric layer or the second gate dielectric layer, and thus the size of the semiconductor structure can be further reduced.

[0066] In some embodiments, the material of the semiconductor layer 102 can also be other semiconductor materials. For example, the material of the semiconductor layer 102 can also be germanium, germanium silicon, or silicon on insulator.

[0067] In some embodiments, the material of the first word line 101 can be a metal-based material. For example, it can include metal, metal nitride, metal silicide, or a combination thereof. The material of the second word line 103 can be a metal-based material. For example, it can include metal, metal nitride, metal silicide, or a combination thereof. Among them, the metal can be at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or titanium.

[0068] In some embodiments, the doping ion type of the source / drain region 11 may be different from that of the channel region 10. For example, the doping ion type of the source / drain region 11 may be N-type doping ions, and the doping ion type of the channel region 10 may be P-type doping ions, and the formed transistor has an N-type conductivity type.

[0069] In some embodiments, the doping ion type of the source / drain region 11 may also be the same as that of the channel region 10.

[0070] Reference Figure 3 And Figure 4 In some embodiments, the semiconductor structure further includes: a first gate dielectric layer 111 located between the semiconductor layer 102 and the first word line 101; a second gate dielectric layer 112 located between the second word line 103 and the semiconductor layer 102, and the second gate dielectric layer 112 covers the channel region 10 and exposes the source / drain region 11.

[0071] The first gate dielectric layer 111 is used to isolate the charge between the first word line 101 and the channel region 10 after the transistor is turned on, and the second gate dielectric layer 112 is used to isolate the charge between the second word line 103 and the channel region 10 after the transistor is turned on, ensuring the stability of the transistor.

[0072] The first gate dielectric layer 111 surrounds a part of the side surface of the first word line 101 and is in direct contact with the side surface of the first word line 101. The semiconductor layer 102 covers the surface of the first gate dielectric layer 111 away from the first word line 101.

[0073] The second gate dielectric layer 112 is located on the side of the semiconductor layer 102 away from the first gate dielectric layer 111 and is in contact with a part of the semiconductor layer 102. Among them, the second gate dielectric layer 112 at least covers the channel region 10 of the semiconductor layer 102, and then isolates the charge between the second word line 103 and the channel region 10 after the transistor is turned on. The source / drain region 11 of the semiconductor layer 102 is not covered by the second gate dielectric layer 112, and then the surface of the source / drain region 11 can be exposed, so that the bit line 104 and the capacitor can be in electrical contact with the exposed source / drain region 11.

[0074] It is not difficult to find that both the first gate dielectric layer 111 and the second gate dielectric layer 112 surround the side surface of the first word line 101, so that the first gate dielectric layer 111 and the second gate dielectric layer 112 do not occupy too much space in the third direction W, and then the size of the transistor in the third direction W can be made smaller.

[0075] In some embodiments, the material of the first gate dielectric layer 111 may be silicon oxide or a high-k dielectric material. The material of the second gate dielectric layer 112 may be silicon oxide or a high-k dielectric material.

[0076] In some embodiments, the side surface of the first word line 101 opposite to the source / drain region 11 is an arc surface, the first gate dielectric layer 111 conformally covers the side surface of the first word line 101, and the source / drain region 11 of the semiconductor layer 102 conformally covers the side surface of the first gate dielectric layer 111.

[0077] Conformal coverage means that the surface topography of the first gate dielectric layer 111 is consistent with the surface topography of the covered first word line 101, and the surface topography of the semiconductor layer 102 is consistent with the surface topography of the covered first gate dielectric layer 111. That is, the surface topography of the first gate dielectric layer 111 opposite to the source / drain region 11 is an arc surface, and the surface topography of the semiconductor layer 102 of the source / drain region 11 is an arc surface.

[0078] The arc surface has a larger surface area. Setting the surface topography of the semiconductor layer 102 of the source / drain region 11 to be an arc surface makes the exposed area of the source / drain region 11 larger. Furthermore, it can make the contact area between the source / drain region 11 and the bit line 104 and the capacitor 105 larger, ensuring better electrical contact performance between the source / drain region 11 and the bit line 104 and the capacitor 105, and improving the signal transmission rate between the bit line 104 and the capacitor 105 and the source / drain region 11. It is not difficult to find that in the embodiments of the present disclosure, although the occupied area of the semiconductor layer 102 is reduced, the contact area between the semiconductor layer 102 and the first word line 101, the bit line 104, and the capacitor 105 is not reduced. That is to say, while ensuring that the overall size of the semiconductor structure is small, the electrical contact performance between the bit line 104, the capacitor 105, and the semiconductor layer 102 can be taken into account, ensuring better electrical performance of the semiconductor structure.

[0079] Reference Figure 5 And Figure 6 In some embodiments, the semiconductor structure further includes: a support layer 106 extending along the third direction W. The support layer 106 has a first side 1 and a second side 2 opposite to each other along the second direction Y, and two third sides 3 opposite to each other along the third direction W. The semiconductor layer 102 and the first word line 101 are embedded in the first side 1, and the second word line 103 is embedded in the second side 2. Among them, the third side 3 of the support layer 106 exposes the source / drain region 11 of the semiconductor layer 102.

[0080] The support layer 106 can support the semiconductor layer 102. The semiconductor layer 102 and the first word line 101 are embedded into the support layer 106 from the first side 1 of the support layer 106, and the second word line 103 is embedded into the support layer 106 from the second side 2 of the support layer 106.

[0081] The third side 3 of the support layer 106 exposes the source-drain regions 11 of the semiconductor layer 102, that is, the source-drain regions 11 are exposed outside the support layer 106. The bit line 104 contacts the source-drain regions 11 and the third side 3 of the support layer 106, and can be electrically connected to the source-drain regions 11, and the support layer 106 can also provide support for the bit line 104. The capacitor 105 contacts the source-drain regions 11 and the other third side 3 of the support layer 106, and can be electrically connected to the source-drain regions 11, and the support layer 106 can also provide support for the capacitor 105.

[0082] In some embodiments, the material of the support layer 106 is an insulating material, for example, it can be silicon nitride or the like.

[0083] In some embodiments, the first gate dielectric layer 111 and the second gate dielectric layer 112 are embedded into the support layer 106 from the first side 1.

[0084] That is to say, the first word line 101, the second word line 103, the semiconductor layer 102, the first gate dielectric layer 111, and the second gate dielectric layer 112 are all located within the support layer 106, and in the second direction Y, the overall dimensions of the first word line 101, the second word line 103, the semiconductor layer 102, the first gate dielectric layer 111, and the second gate dielectric layer 112 are close to or the same as the width dimension of the support layer 106. In this way, by only adjusting the width dimension of the support layer 106 in the second direction Y, the overall dimensions of the first word line 101, the second word line 103, the semiconductor layer 102, the first gate dielectric layer 111, and the second gate dielectric layer 112 in the second direction Y can be adjusted, so that the overall dimensions of the first word line 101, the second word line 103, the semiconductor layer 102, the first gate dielectric layer 111, and the second gate dielectric layer 112 occupy less space in the second direction Y, and thus more semiconductor structures can be arranged in the second direction Y.

[0085] In some embodiments, the side of the first word line 101 away from the second word line 103 can protrude beyond the first side 1.

[0086] In some embodiments, the side of the first word line 101 away from the second word line 103 can be flush with the first side 1.

[0087] In some embodiments, the side of the second word line 103 away from the first word line 101 can protrude beyond the first side 1.

[0088] In some embodiments, the side of the second word line 103 away from the first word line 101 can be flush with the first side 1.

[0089] In some embodiments, if the number of semiconductor layers 102 is multiple, the multiple semiconductor layers 102 are stacked in the first direction X, then the number of support layers 106 is multiple, and the multiple support layers 106 are stacked in the first direction X. Each support layer 106 corresponds to one semiconductor layer 102. The word lines extend in the first direction X and correspond to all of the multiple semiconductor layers 102 stacked in the first direction X. The number of bit lines 104 can be multiple, the multiple bit lines 104 are stacked in the first direction X, and the bit lines 104 are electrically connected to the semiconductor layers 102 stacked in the first direction X in a one-to-one correspondence. The number of capacitors 105 can be multiple, the multiple capacitors 105 are stacked in the first direction X, and the capacitors 105 are electrically connected to the semiconductor layers 102 stacked in the first direction X in a one-to-one correspondence.

[0090] In some embodiments, the maximum width dimension of the first word line 101 in the third direction W is greater than the maximum width dimension of the second word line 103 in the third direction W.

[0091] Since the first gate dielectric layer 111, the semiconductor layer 102, and the second gate dielectric layer 112 all surround the side surfaces of the first word line 101, therefore, setting the maximum width dimension of the first word line 101 in the third direction W to be larger than the maximum width dimension of the second word line 103 in the third direction W makes the side area of the first word line 101 larger than the side area of the second word line 103. Furthermore, it can make the lengths of the first gate dielectric layer 111, the semiconductor layer 102, and the second gate dielectric layer 112 surrounding the side surface of the first word line 101 longer. In this way, the lengths and areas of the source-drain regions 11 of the semiconductor layer 102 can be increased, and further, the contact areas between the bit lines 104 and the capacitors 105 and the source-drain regions 11 can be improved, ensuring good contact performance between the bit lines 104 and the capacitors 105 and the source-drain regions 11.

[0092] In some embodiments, the maximum width dimension of the first word line 101 in the third direction W can also be equal to the maximum width dimension of the second word line 103 in the third direction W.

[0093] In the semiconductor structure provided by the above embodiments, the channel region 10 and the source-drain regions 11 are both located on the side surfaces of the word lines. Compared with the case where the semiconductor layer 102 extends in the same direction, the entire semiconductor layer 102 surrounds part of the side surfaces of the word lines, which can reasonably utilize the peripheral space of the word lines, greatly reduce the space occupied by the semiconductor layer 102 in the same horizontal direction, reduce the overall size of the transistor formed by the semiconductor layer 102, and further enable more transistors to be arranged in the memory, improving the integration density of the memory. In addition, the second word line 103 is also arranged on the side of the semiconductor layer 102 away from the first word line 101 to form a double-gate structure, increasing the gate control ability and improving the stability of the channel region 10. In this way, while ensuring the stability of the channel region 10, the size of the transistor is reduced.

[0094] Correspondingly, an embodiment of the present disclosure further provides a three-dimensional memory, including a plurality of semiconductor structures provided in the above embodiments. As Figure 7 shown, a plurality of semiconductor structures arranged along the second direction Y share a common bit line 104, and a plurality of semiconductor structures arranged along the first direction X share a first word line 101 and a second word line 103. Each semiconductor structure corresponds to a capacitor 105.

[0095] Referring to Figure 7 , specifically, the plurality of semiconductor structures include a plurality of semiconductor layers 102, and the plurality of semiconductor layers 102 may be located on a substrate and stacked in a direction perpendicular to the surface of the substrate. Each column of semiconductor layers 102 stacked in a direction perpendicular to the surface of the substrate is denoted as a stacked structure. There may be a plurality of stacked structures, and the plurality of stacked structures may be arranged along the second direction Y and the third direction W. Each stacked structure may share the same first word line 101 and the same second word line 103. Among them, the second direction Y and the third direction W are both parallel to the surface of the substrate, and the second direction Y and the third direction W are perpendicular to each other.

[0096] Since the semiconductor layer 102 is disposed around the side surface of the first word line 101, and the source-drain region 11 is located on the side surface of the word line, the space occupied by the source-drain region 11 in the third direction W can be reduced, thereby making the size of the transistor formed by the semiconductor layer 102 smaller in the third direction W. That is, the size of each semiconductor structure in the third direction W is smaller, so that more stacked structures can be arranged in the third direction W, increasing the integration degree of the three-dimensional memory.

[0097] The type of the three-dimensional memory may be DRAM (Dynamic Random Access Memory), SRAM (Static Random-Access Memory), or SDRAM (Synchronous Dynamic Random-Access Memory).

[0098] Correspondingly, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure. The method for manufacturing the semiconductor structure can be used to manufacture the semiconductor structure provided in the above embodiments. Hereinafter, a semiconductor structure provided in an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0099] Referring to Figures 8 to 18 , the method for manufacturing a semiconductor structure includes:

[0100] A first word line 101 is formed, and the first word line 101 extends along a first direction X; a second word line 103 is formed, and the second word line 103 extends along the first direction X. The second word line 103 is located on a side of the semiconductor layer 102 away from the first word line 101 and is disposed opposite to the first word line 101; a semiconductor layer 102 is formed, and the semiconductor layer 102 surrounds a partial side surface of the first word line 101. The semiconductor layer 102 includes: a channel region 10 and source-drain regions 11 located on both sides of the channel region 10. The channel region 10 and the source-drain regions 11 are arranged circumferentially around the side surface of the first word line 101.

[0101] Both the channel region 10 and the source-drain regions 11 are located on the side surface of the word line, which can reasonably utilize the peripheral space of the word line, reduce the overall size of the transistor formed by the semiconductor layer 102, and thus more transistors can be arranged in the memory, improving the integration density of the memory. In addition, a second word line 103 is also disposed on a side of the semiconductor layer 102 away from the first word line 101 to form a double-gate structure, increasing the gate control ability, improving the stability of the channel region 10, and realizing the reduction of the transistor size while ensuring the stability of the channel region 10.

[0102] In some embodiments, the first word line 101, the second word line 103, and the semiconductor layer 102 are formed on a substrate 100.

[0103] In some embodiments, the material of the substrate 100 may be a semiconductor material. In some embodiments, the material of the substrate 100 may be silicon. In some embodiments, the substrate 100 may also be germanium, germanium-silicon, or silicon-on-insulator.

[0104] In some embodiments, before the step of forming the first word line 101, it further includes: forming a first gate dielectric layer 111 covering a partial side surface of the first word line 101, and the semiconductor layer 102 covers the surface of the first gate dielectric layer 111; and forming a second gate dielectric layer 112, where the second gate dielectric layer 112 is located on a side of the semiconductor layer 102 away from the first gate dielectric layer 111 and covers the channel region 10.

[0105] The methods for forming the semiconductor layer 102, the first gate dielectric layer 111, and the second gate dielectric layer 112 will be introduced below.

[0106] In some embodiments, the methods for forming the semiconductor layer 102, the first gate dielectric layer 111, and the second gate dielectric layer 112 include:

[0107] Referring to Figures 8 to 10 , first, a support layer 106 is formed. The support layer 106 extends along a third direction W. The support layer 106 has a first side 1 and a second side 2 opposite to each other along a second direction Y, and two third sides 3 opposite to each other along the third direction W.

[0108] In some embodiments, the method of forming the support layer 106 includes:

[0109] Referring Figure 8 , forming a plurality of layers of initial support layers 20 and a plurality of layers of isolation layers 21 alternately stacked in a direction away from the substrate 100 on the substrate 100, that is, the plurality of layers of initial support layers 20 and the plurality of layers of isolation layers 21 are alternately stacked along the first direction X. Among them, the material of the initial support layer 20 can be silicon nitride, and the material of the isolation layer 21 can be silicon oxide.

[0110] Referring Figure 9 And Figure 10 , etching the plurality of layers of initial support layers 20 and the plurality of layers of isolation layers 21 to form a plurality of first trenches 30 spaced apart along the second direction Y. Each first trench 30 penetrates through the plurality of layers of initial support layers 20 and the plurality of layers of isolation layers 21, and the bottom surface of the substrate 100 is exposed at the bottom of the first trench 30. The initial support layers 20 separated by the first trenches 30 form the support layer 106, and each support layer 106 extends along the third direction W. That is, the stacked support layers 106 are between adjacent first trenches 30, and the support layers 106 are separated by the isolation layer 21.

[0111] Referring Figure 9 And Figure 10 , in some embodiments, the substrate 100 includes a first region 23 and a second region 24 adjacent to each other along the third direction W. Only the plurality of layers of initial support layers 20 and the plurality of layers of isolation layers 21 on the second region 24 are etched to form a plurality of first trenches 30 spaced apart along the second direction Y on the second region 24. The initial support layer 20 and the isolation layer 21 located on the first region 23 are retained and are in contact with the third side 3 of the support layer 106. The initial support layer 20 and the isolation layer 21 located on the first region 23 can be denoted as a sub-stack structure 40.

[0112] In some embodiments, the method of forming the first trench 30 may include: performing a patterning process on the top surface of the isolation layer 21 located on the first region 23 to define the position of the first trench 30. In some embodiments, the patterning process may employ any one of the SADP (Self-aligned Double Patterning) process or the SAQP (Self-Aligned Quadruple Patterning) process.

[0113] After that, an etching process is performed on the patterned isolation layer 21 to etch the isolation layer 21 and the initial support layer 20 to form the first trench 30.

[0114] Referring Figure 11After forming the support layer 106, an isolation structure 107 is formed to fill the first trench 30. The isolation structure 107 covers the support layer 106 and the sidewalls of the isolation layer 21.

[0115] In some embodiments, the isolation structure 107 can be formed by a deposition process.

[0116] In some embodiments, the material of the isolation structure 107 is different from that of the support layer 106. Specifically, the material of the isolation structure 107 can be silicon oxide, and the material of the support layer 106 can be silicon nitride.

[0117] Reference Figure 13 After forming the isolation structure 107, a first groove 51 extending from the first side 1 to the second side 2 of the support layer 106 can be etched to form a first groove 51. The first groove 51 is used to provide space for subsequent formation of the first gate dielectric layer 111, the second gate dielectric layer 112, the semiconductor layer 102, and the first word line 101.

[0118] In some embodiments, the method of forming the first groove 51 may include:

[0119] Reference Figure 12 A second trench 61 is formed in the isolation structure 107. The second trench 61 penetrates the isolation structure 107, and the surface of the substrate 100 is exposed at the bottom of the second trench 61, and the sidewalls of the second trench 61 expose the alternately stacked support layer 106 and the sacrificial layer. The second trench 61 only exposes partial sides of each support layer 106 and each sacrificial layer. Subsequently, etching the support layer 106 exposed by the second trench 61 can form the first groove 51 at this position. That is to say, the formed second trench 61 actually positions the subsequently formed first groove 51.

[0120] In some embodiments, the method of forming the second trench 61 may include: patterning the top surface of the isolation structure 107. For example, the top surface of the isolation structure 107 can be patterned by SADP process or SAQP process to define the position of the second trench 61.

[0121] After that, the patterned isolation structure 107 is etched until the surface of the substrate 100 is exposed to form the second trench 61.

[0122] Reference Figure 13 After forming the second trench 61, the support layer 106 exposed by the second trench 61 is etched along the second trench 61, and a part of the width of the support layer 106 is etched to form the first groove 51.

[0123] Since the material of the isolation structure 107 is different from that of the support layer 106, and the material of the isolation layer 21 is different from that of the support layer 106, the etch selectivity between the isolation structure 107 and the support layer 106, and the etch selectivity between the isolation layer 21 and the support layer 106 can be utilized to etch only the support layer 106 to form the first groove 51.

[0124] In some embodiments, a wet etching process can be employed to etch the support layer 106 to form the first groove 51.

[0125] Reference Figure 14 , after forming the first groove 51, an initial second gate dielectric layer 22 conformally covering the first groove 51 is formed along the second trench 61. That is, the initial second gate dielectric layer 22 covers the sidewalls of the first groove 51 and contacts the support layer 106 exposed on the sidewalls of the first groove 51, such that the contour shape of the initial second gate dielectric layer 22 is the same as the contour shape of the first groove 51.

[0126] Reference Figure 14 , along the second trench 61, a semiconductor layer 102 conformally covering the initial second gate dielectric layer 22 is formed within the first groove 51. That is, the semiconductor layer 102 covers the surface of the initial second gate dielectric layer 22, and the contour shape of the semiconductor layer 102 is the same as the contour shape of the initial second gate dielectric layer 22.

[0127] Reference Figure 14 , along the second trench 61, a first gate dielectric layer 111 conformally covering the surface of the semiconductor layer 102 is formed within the first groove 51. That is, the first gate dielectric layer 111 covers the surface of the semiconductor layer 102, and the contour shape of the first gate dielectric layer 111 is the same as the contour shape of the semiconductor layer 102.

[0128] In some embodiments, a deposition process can be used to form the initial second gate dielectric layer 22, the semiconductor layer 102, and the first gate dielectric layer 111 respectively.

[0129] It can be understood that since the second trench 61 exposes not only the support layer 106 but also the isolation layer 21. In the steps of depositing the initial second gate dielectric layer 22, the semiconductor layer 102, and the first gate dielectric layer 111 into the first groove 51 along the second trench 61, the initial second gate dielectric layer 22, the semiconductor layer 102, and the first gate dielectric layer 111 will also be formed on the sidewalls of the isolation layer 21. In order to separate the initial second gate dielectric layer 22, the semiconductor layer 102, and the first gate dielectric layer 111 located in different first grooves 51, it is also necessary to remove the initial second gate dielectric layer 22, the semiconductor layer 102, and the first gate dielectric layer 111 covering the sidewalls of the isolation layer 21.

[0130] In some embodiments, a dry etching process may be employed in the second trench 61 to remove the initial second gate dielectric layer 22, semiconductor layer 102, and first gate dielectric layer 111 located on the sidewalls of the isolation layer 21. Since the isolation layer 21 protrudes beyond the first groove 51, when using a dry etching process, the etching gas is aligned with the second trench 61. The etching gas in the second trench 61 first contacts the initial second gate dielectric layer 22, semiconductor layer 102, and first gate dielectric layer 111 located on the sidewalls of the isolation layer 21. By controlling the etching time, it is possible to remove only the initial second gate dielectric layer 22, semiconductor layer 102, and first gate dielectric layer 111 on the sidewalls of the isolation layer 21.

[0131] Reference Figure 14 and Figure 15 , after forming the first gate dielectric layer 111, a first word line 101 is formed. In some embodiments, the method of forming the first word line 101 includes: forming the first word line 101 in the remaining first groove 51, and the first word line 101 fills the first groove 51. In this way, the side surfaces of the first word line 101 located in the first groove 51 are all in contact with the semiconductor layer 102, enabling the semiconductor layer 102 to surround a part of the side surfaces of the first word line 101.

[0132] The first word line 101 not only fills the first groove 51 but also fills the second trench 61. In this way, the formed first word line 101 extends along the first direction X, and the first word line 101 is opposite to each semiconductor layer 102 stacked along the first direction X.

[0133] In some embodiments, a deposition process, such as atomic layer deposition, may be used to form the first word line 101.

[0134] In some embodiments, the method of forming the second word line 103 includes:

[0135] Reference Figure 16 , etching a part of the support layer 106 on the second side 2 of the self-supporting layer 106 to form a second groove 52 extending from the second side 2 towards the first side 1, and the second groove 52 exposes the surface of the initial second gate dielectric layer 22.

[0136] In some embodiments, the method of forming the second groove 52 may include:

[0137] Reference Figure 15 , forming a third trench 62 in the isolation structure 107. The third trench 62 penetrates the isolation structure 107, and the bottom of the third trench 62 exposes the surface of the substrate 100. The second trench 61 and the third trench 62 may be located on opposite sides of the support layer 106 along the second direction Y, so that the second trench 61 and the third trench 62 expose the first side 1 and the second side 2 of the support layer 106 respectively.

[0138] The sidewalls of the third trench 62 expose the alternately stacked support layers 106 and sacrificial layers. The third trench 62 only exposes partial sides of each support layer 106 and each sacrificial layer. Subsequently, etching the support layer 106 exposed by the third trench 62 can form the second groove 52 at this position.

[0139] In some embodiments, the method of forming the third trench 62 may include: patterning the top surface of the isolation structure 107. For example, the SADP process or the SAQP process may be used to pattern the top surface of the isolation structure 107 to define the position of the third trench 62.

[0140] After that, etching the patterned isolation structure 107 until the surface of the substrate 100 is exposed to form the third trench 62.

[0141] Reference Figure 16 After forming the third trench 62, etching the support layer 106 exposed by the third trench 62 along the third trench 62, and etching the support layer 106 with a partial width to form the second groove 52.

[0142] Reference Figure 13 and Figure 16 In some embodiments, in the third direction W, the opening size d1 of the first groove 51 is greater than the opening size d2 of the second groove 52.

[0143] It can be understood that since the first groove 51 needs to be filled with the first gate dielectric layer 111, the second gate dielectric layer 112, the semiconductor layer 102, and the first word line 101, while the second groove 52 only needs to be filled with the second word line 103, the first groove 51 requires a larger size.

[0144] In some embodiments, a wet etching process may be used to etch the support layer 106 to form the second groove 52. By controlling the etching time for forming the first groove 51 to be longer than the etching time for forming the second groove 52, a first groove 51 with a larger opening size can be formed.

[0145] Reference Figure 17 and Figure 18 After forming the second groove 52, a second word line 103 that fills the second groove 52 is formed.

[0146] The second word line 103 not only fills the second groove 52 but also fills the third trench 62. In this way, the formed second word line 103 extends along the first direction X, and the second word line 103 is opposite to each semiconductor layer 102 stacked along the first direction X.

[0147] In some embodiments, a deposition process, such as atomic layer deposition, may be used to form the second word line 103.

[0148] In the above steps, the second groove 52 is formed after the step of forming the first word line 101 .

[0149] refer to Figures 19 to 23 In some embodiments, after the step of forming the second word line 103, the first groove 51 may be formed, and the first groove 51 exposes the side of the second word line 103 facing the first groove 51. In other words, the step of forming the second groove 52 may be performed first, and the second word line 103 may be formed in the second groove 52. After that, the first groove 51 is formed, and the first groove 51 exposes the surface of the second word line 103, so that the second gate dielectric layer 112 formed subsequently can contact the second word line 103.

[0150] Specifically, refer to Figure 19 , a third trench is formed in the isolation structure 107 , the third trench 62 penetrates the isolation structure 107 , and the bottom of the third trench 62 is exposed to the surface of the substrate 100 .

[0151] refer to Figure 20 After forming the third trench 62 , the support layer 106 exposed by the third trench 62 is etched along the third trench 62 , and a portion of the width of the support layer 106 is etched to form a second groove 52 .

[0152] refer to Figure 21 After the second groove 52 is formed, a second word line 103 is formed in the second groove 52 .

[0153] refer to Figure 22 After forming the second word line 103, a second trench 61 is formed in the isolation structure 107. The second trench 61 penetrates the isolation structure 107, and the bottom of the second trench 61 exposes the surface of the substrate 100, and the sidewall of the second trench 61 exposes the alternately stacked support layer 106 and the sacrificial layer.

[0154] refer to Figure 23 After forming the second trench 61 , the support layer 106 exposed by the second trench 61 is etched along the second trench 61 , and a portion of the width of the support layer 106 is etched to form a first groove 51 , which exposes the surface of the second word line 103 .

[0155] Afterwards, an initial second gate dielectric layer 22 , a semiconductor layer 102 , and a first gate dielectric layer 111 are sequentially formed in the first groove.

[0156] refer to Figures 24 to 26 After forming the first word line 101 and the second word line 103 , a bit line 104 is formed. The bit line 104 is located on a side of the semiconductor layer 102 away from the first word line 101 and extends along the second direction Y.

[0157] The bit line 104 can be located on the third side 3 of the support layer 106 and contact the semiconductor layer 102 exposed on the third side 3 of the support layer 106.

[0158] It can be understood that since the initial second gate dielectric layer 22 covers the entire surface of the semiconductor layer 102, in order for the subsequently formed bit line 104 and capacitor 105 to form electrical connections with the semiconductor layer 102, a part of the surface of the semiconductor layer 102 needs to be exposed to form the source / drain regions 11.

[0159] Therefore, referring to Figure 24 and Figure 25 , a part of the support layer 106 and a part of the initial second gate dielectric layer 22 are etched from the third side 3 of the support layer 106 until a part of the surface of the semiconductor layer 102 facing away from the first word line 101 is exposed.

[0160] Specifically, in some embodiments, the initial support layer 20 in the sub-stack structure 40 is etched away to form a first opening 71 between adjacent isolation layers 21 in the sub-stack structure 40, and the first opening 71 exposes the third side 3 of the support layer 106. Then, the exposed third side 3 of the support layer 106 can be continuously etched until the initial second gate dielectric layer 22 is exposed, and the initial second gate dielectric layer 22 can be continuously etched until a part of the surface of the semiconductor layer 102 facing away from the first word line 101 is exposed.

[0161] In some embodiments, a wet etching process can be used to etch the exposed third side 3 and the initial second gate dielectric layer 22.

[0162] After a part of the surface of the semiconductor layer 102 facing away from the first word line 101 is exposed, the exposed semiconductor layer 102 can be doped to form the source / drain regions.

[0163] Referring to Figures 26 to 27 , after the source / drain regions are formed and a part of the surface of the semiconductor layer 102 facing away from the first word line 101 is exposed, a bit line 104 filling the first opening 71 is formed so that the bit line 104 can contact the surface of the semiconductor layer 102. In some embodiments, a deposition process can be used to form the bit line 104.

[0164] Referring to Figures 28 to 30 , after the bit line 104 is formed, a capacitor 105 is formed. The capacitor 105 is located on the side of the semiconductor layer 102 facing away from the first word line 101. Among them, the bit line 104 and the capacitor 105 are respectively located on opposite sides of the first word line 101 in the third direction W and are respectively in electrical contact with the source / drain regions 11, and the second direction Y intersects the third direction W.

[0165] In some embodiments, the isolation structure 107 is not only located between adjacent support layers 106, covering the first side 1 and the second side 2 of the support layer 106, but also covers the third side 3 of the support layer 106 away from the bit line 104. Based on this, first, it is necessary to etch the isolation structure 107 covering the third side 3 of the support layer 106 away from the bit line 104. For example, a dry etching process can be used to etch the isolation structure 107 covering the third side 3 of the support layer 106 away from the bit line 104 until the third side 3 of the support layer 106 away from the bit line 104 is exposed.

[0166] After that, referring to Figure 28 , a wet etching process is used to etch the third side 3 of the support layer 106 away from the bit line 104 until the initial second gate dielectric layer 22 is exposed, forming a second opening 72.

[0167] Referring to Figure 28 and Figure 29 , the initial second gate dielectric layer 22 is continuously etched along the second opening 72 until a partial surface of the semiconductor layer 102 facing away from the first word line 101 is exposed, and the remaining part of the initial second gate dielectric layer 22 serves as the second gate dielectric layer 112. After the partial surface of the semiconductor layer 102 facing away from the first word line 101 is exposed, a doping process can be performed on the exposed semiconductor layer 102 to form source-drain regions. In this way, two source-drain regions can be respectively formed on the semiconductor layer 102 exposed by the second gate dielectric layer 112, and the semiconductor layer 102 covered by the remaining part of the second gate dielectric layer 112 forms a channel region.

[0168] Referring to Figure 30 , a capacitor 105 is formed to fill the second opening 72, and the capacitor 105 is in electrical contact with the other source-drain region 11 of the semiconductor layer 102.

[0169] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present disclosure. In practical applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be defined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: a first word line extending along a first direction; A semiconductor layer, the semiconductor layer surrounds a portion of the side surface of the first word line, the semiconductor layer comprises: a channel region and source and drain regions located on both sides of the channel region, the channel region and the source and drain regions are circumferentially arranged around the side surface of the first word line; a second word line, the second word line extending along the first direction, the second word line being located at a side of the semiconductor layer away from the first word line and being arranged opposite to the first word line; A bit line, located at a side of the semiconductor layer away from the first word line and extending along a second direction; The capacitor is located on a side of the semiconductor layer away from the first word line, wherein the bit line and the capacitor are respectively located on opposite sides of the first word line in a third direction and are respectively electrically contacted with the source and drain regions, and the second direction intersects the third direction.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further comprises: A first gate dielectric layer, located between the semiconductor layer and the first word line; The second gate dielectric layer is located between the second word line and the semiconductor layer, and the second gate dielectric layer covers the channel region and exposes the source and drain regions.

3. The semiconductor structure according to claim 2, characterized in that, The material of the semiconductor layer includes IGZO.

4. The semiconductor structure according to claim 2, characterized in that, The side surface of the first word line directly facing the source and drain regions is a curved surface, the first gate dielectric layer conformally covers the side surface of the first word line, and the source and drain regions of the semiconductor layer conformally cover the side surface of the first gate dielectric layer.

5. The semiconductor structure according to any one of claims 1 - 4, characterized in that, Also includes: A support layer extends along the third direction, the support layer having a first side and a second side opposite to each other along the second direction, and two third sides opposite to each other along the third direction, the semiconductor layer and the first word line are embedded in the first side, and the second word line is embedded in the second side, wherein the third side of the support layer exposes the source and drain regions of the semiconductor layer.

6. The semiconductor structure according to claim 5, characterized in that, The maximum width dimension of the first word line in the third direction is greater than the maximum width dimension of the second word line in the third direction.

7. A three - dimensional memory, characterized in that, include: A plurality of semiconductor structures as claimed in any one of claims 1 to 6, a plurality of the semiconductor structures arranged along the second direction share one the bit line, and a plurality of the semiconductor structures arranged along the first direction share the first word line and the second word line.

8. A method for manufacturing a semiconductor structure, characterized in that, include: forming a first word line, wherein the first word line extends along a first direction; forming a semiconductor layer, the semiconductor layer surrounding a portion of the side surface of the first word line, the semiconductor layer comprising: a channel region and source and drain regions located on both sides of the channel region, the channel region and the source and drain regions being arranged circumferentially around the side surface of the first word line; forming a second word line, wherein the second word line extends along the first direction, the second word line is located at a side of the semiconductor layer away from the first word line, and is arranged opposite to the first word line; forming a bit line, which is located on a side of the semiconductor layer away from the first word line and extends along a second direction; A capacitor is formed, the capacitor is located on a side of the semiconductor layer away from the first word line, wherein the bit line and the capacitor are respectively located on opposite sides of the first word line in a third direction and are respectively electrically contacted with the source and drain regions, and the second direction intersects the third direction.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, Before the step of forming the first word line, the method further includes: forming a first gate dielectric layer covering a partial side surface of the first word line, the semiconductor layer covering the surface of the first gate dielectric layer; and forming a second gate dielectric layer on a side of the semiconductor layer away from the first gate dielectric layer, the second gate dielectric layer covering the channel region.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, The method of forming the semiconductor layer, the first gate dielectric layer, and the second gate dielectric layer includes: forming a support layer extending along a third direction, the support layer having a first side and a second side opposite to each other along a second direction, and two third sides opposite to each other along the third direction; etching a part of the support layer from the first side of the support layer to form a first groove extending from the first side to the second side; forming an initial second gate dielectric layer conformally covering the first groove; forming a semiconductor layer conformally covering the initial second gate dielectric layer in the first groove; forming a first gate dielectric layer conformally covering the surface of the semiconductor layer in the first groove; etching a part of the support layer and a part of the initial second gate dielectric layer from the third side of the support layer until a part of the surface of the semiconductor layer facing away from the first word line is exposed, and the remaining part of the initial second gate dielectric layer serves as the second gate dielectric layer.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein, The method of forming the first word line includes: forming a first word line in the remaining first groove, the first word line filling the first groove.

12. The method for manufacturing a semiconductor structure according to claim 10, wherein, The method of forming the second word line includes: etching a part of the support layer from the second side of the support layer to form a second groove extending from the second side to the first side; forming the second word line filling the second groove.

13. The method for manufacturing a semiconductor structure according to claim 12, wherein, After the step of forming the second word line, the first groove is formed, and the first groove exposes a side surface of the second word line facing the first groove.

14. The method for manufacturing a semiconductor structure according to claim 12, wherein, In the third direction, an opening size of the first groove is larger than an opening size of the second groove.

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