Manufacturing method of semiconductor structure

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate which comprises an array region; a plurality of active columns are formed, the active columns are located on the array area, the active columns are arranged in the first direction and the second direction, and the active columns extend in the third direction; word lines are formed, the word lines extend in the first direction, and the word lines cover the side walls of the multiple active columns in the first direction; bit lines are formed, the bit lines extend in the second direction, and in the second direction, the bit lines are connected with the ends, in the third direction, of the multiple active columns; word line plugs are formed, the word line plugs are located on the sides, close to the bit lines, of the word lines in the third direction and make electric contact with the word lines, and orthographic projections of the word line plugs on the substrate are located in the array area; a bit line plug is formed, the bit line plug is located on the side, away from the active column in the third direction, of the bit line and makes electric contact with the bit line, the orthographic projection of the bit line plug on the substrate is located in the array area, and at least improvement of the integration density of the semiconductor structure is facilitated.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor structure. Background Art

[0002] A memory is a memory component used to store programs and various data information. The random access memory (RAM) commonly used in general computer systems can be divided into two types: dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor storage device in a computer and is composed of many repeated memory cells.

[0003] A memory cell generally includes a capacitor and a transistor. One of the source and drain or the drain of the transistor is connected to a bit line structure, and the other of the source and drain or the drain is connected to the capacitor. The capacitor includes a capacitor contact structure and a capacitance. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, and further read the data information stored in the capacitor through the bit line structure, or write the data information into the capacitor through the bit line structure for storage.

[0004] Currently, the integration density of semiconductor structures needs to be improved. Summary of the Invention

[0005] Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which is at least beneficial to improving the integration density of the semiconductor structure.

[0006] According to some embodiments of the present disclosure, on the one hand, a method for manufacturing a semiconductor structure is provided, including: providing a substrate, the substrate including an array region; forming a plurality of active pillars, the active pillars being located on the array region, the active pillars being arranged along a first direction and a second direction, and the active pillars extending along a third direction; forming a word line, the word line extending along the first direction, and in the first direction, the word line covering the sidewalls of the plurality of active pillars; forming a bit line, the bit line extending along the second direction, and in the second direction, the bit line connecting one end of the plurality of active pillars along the third direction; forming a word line plug, the word line plug being located on a side of the word line close to the bit line along the third direction and being in electrical contact with the word line, and the orthographic projection of the word line plug on the substrate being located in the array region; forming a bit line plug, the bit line plug being located on a side of the bit line far from the active pillars along the third direction and being in electrical contact with the bit line, and the orthographic projection of the bit line plug on the substrate being located in the array region.

[0007] In some embodiments, one end of the active pillar close to the substrate in the third direction is the first end, and one end of the active pillar far from the substrate in the third direction is the second end; after forming the active pillar and the word line and before forming the bit line, it includes: a planarization process to expose the end face of the first end of the active pillar; forming the bit line includes: forming the bit line at the first end of the active pillar.

[0008] In some embodiments, before performing the planarization process, it further includes: forming a contact structure located at the end face of the second end of the active pillar; providing a first wafer having a plurality of capacitors therein, and one end of the capacitor is exposed on the surface of the first wafer; placing the first wafer opposite to the substrate so that the capacitor contacts the contact structure; performing a bonding process to electrically connect the capacitor and the contact structure.

[0009] In some embodiments, one end of the active pillar close to the substrate in the third direction is the first end, and one end of the active pillar far from the substrate in the third direction is the second end; forming the bit line includes: forming the bit line at the second end of the active pillar; after forming the word line plug and the bit line plug, it further includes: a planarization process to expose the end face of the first end of the active pillar.

[0010] In some embodiments, after forming the word line plug and the bit line plug and before performing the planarization process, it further includes: providing a second wafer having a plurality of driving transistors therein, and the surface of the second wafer has pads electrically connected to one of the gates, sources or drains of the driving transistors; placing the substrate opposite to the second wafer so that the word line plug or the bit line plug contacts the pad; performing a bonding process to electrically connect the word line plug and the pad and to electrically connect the bit line plug and the pad.

[0011] In some embodiments, forming the bit line includes: forming a metal layer on the end face of one end of the active pillar in the third direction; performing a heat treatment process to react a part of the active pillar with the metal layer to form a metal compound layer, and the metal compound layer serves as the bit line.

[0012] In some embodiments, the heat treatment process includes a rapid thermal annealing process.

[0013] In some embodiments, the material for forming the metal layer includes cobalt, titanium, tungsten or tantalum.

[0014] In some embodiments, in the first direction, the size of the spacing between the word line plug and the adjacent active pillar is 5 nm to 15 nm.

[0015] In some embodiments, after forming the bit line and before forming the word line plug, the method includes: forming a first protective layer that covers two opposite sides of the bit line in the first direction and covers two opposite sides of the active pillar in the first direction; forming a second protective layer that covers the surface of the first protective layer away from the bit line and covers the surface of the first protective layer away from the active pillar, and the material of the second protective layer is different from that of the first protective layer; forming the word line plug includes: forming the word line plug between the second protective layers on the sides of adjacent active pillars.

[0016] In some embodiments, forming the word line plug and the bit line plug includes: forming a filling layer that fills the gap between the active pillars and covers the surface of the bit line away from the active pillars; patterning the filling layer to form a word line plug hole and a bit line plug hole, in the plane of the first direction and the second direction, the orthographic projection of the word line plug hole overlaps with the orthographic projection of the word line, and the orthographic projection of the bit line plug hole overlaps with the bit line; filling the word line plug hole to form the word line plug and filling the bit line plug hole to form the bit line plug.

[0017] In some embodiments, forming the word line plug hole includes: forming a first word line plug hole and a second word line plug hole, the first word line plug hole is located on one side of the bit line away from the active pillar in the third direction, and in the first direction, the size of the first word line plug hole is greater than or equal to the spacing between adjacent active pillars; forming a second word line plug hole that communicates with the first word line plug hole, the second word line plug hole is located between adjacent active pillars, and in the first direction, the size of the second word line plug hole is smaller than the size of the first word line plug hole; filling the first word line plug hole and the second word line plug hole to form the word line plug.

[0018] In some embodiments, providing the substrate and forming the active pillars and the word lines includes: providing an initial substrate; forming a plurality of first trenches extending along the first direction and a plurality of second trenches extending along the second direction in the initial substrate, the remaining initial substrate between the first trenches and the second trenches serving as the active pillars, and the remaining initial substrate at the bottoms of the first trenches and the second trenches serving as the substrate; forming an insulating layer that fills the first trenches and the second trenches; patterning the insulating layer to form a plurality of word line trenches extending along the first direction, the word line trenches exposing sidewalls of a plurality of the active pillars; and filling the word line trenches to form the word lines.

[0019] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0020] In the semiconductor structure manufacturing method provided by the embodiments of the present disclosure, the formed active pillars extend along the third direction and are arranged along the first direction and the second direction. In this way, it is convenient for the formed transistor structures to be arranged along the first direction and the second direction, and the transistor structures extend along the third direction. In the plane where the first direction and the second direction are located, the transistor structures may not occupy too much area, which is beneficial to improving the arrangement density of the transistor structures and the space utilization rate of the semiconductor structure. The formed word lines cover the sidewalls of a plurality of active pillars along the first direction, and the formed bit lines are connected to one ends of a plurality of active pillars along the second direction. In this way, the word lines and the bit lines can control a plurality of transistor structures in the first direction and the second direction respectively. The active pillars are located in the array region of the semiconductor structure, and the corresponding transistor structures are located in the array region. In the plane where the first direction and the second direction are located, the orthographic projections of the word line plugs and the bit line plugs are both located in the array region. That is to say, without changing the division of the array region and the peripheral region in the conventional semiconductor structure, both the word line plugs and the bit line plugs are arranged in the array region. In this way, it is possible to avoid the word line plugs and the bit line plugs occupying the space of the peripheral region, which is beneficial to improving the integration density of the semiconductor structure. Description of the Drawings

[0021] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments unless otherwise stated. The figures in the drawings do not constitute a scale limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the conventional technology, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1Schematic diagram of a partial structure of an array region of a semiconductor structure provided in an embodiment of the present application;

[0023] Figure 2 Schematic diagram of a partial cross-sectional structure of a first semiconductor structure provided in an embodiment of the present disclosure along a direction parallel to the bit line;

[0024] Figure 3 Schematic diagram of a partial cross-sectional structure of a first semiconductor structure provided in an embodiment of the present disclosure along a direction parallel to the word line;

[0025] Figure 4 Schematic diagram of a partial cross-sectional structure of a second semiconductor structure provided in an embodiment of the present disclosure along a direction parallel to the bit line;

[0026] Figures 5 to 9 Schematic diagram of a partial cross-sectional structure of a plurality of semiconductor structures provided in an embodiment of the present disclosure along a direction parallel to the word line;

[0027] Figure 10 Schematic diagram of a partial cross-sectional structure of a seventh semiconductor structure provided in an embodiment of the present disclosure along a direction parallel to the word line;

[0028] Figure 11 For Figure 10 Corresponding partial top view of the semiconductor structure along the third direction;

[0029] Figures 12 to 18 Partial top views of a plurality of semiconductor structures provided in an embodiment of the present disclosure along the third direction;

[0030] Figures 19 to 27 Schematic diagrams corresponding to the respective steps of a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure. Detailed implementation manners

[0031] The embodiments of the present disclosure provide a semiconductor structure, which is at least beneficial to improving the integration density of the semiconductor structure.

[0032] The following will elaborate on the embodiments of the present disclosure in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are proposed to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented. The semiconductor structure provided in this embodiment will be described in detail below in conjunction with the accompanying drawings.

[0033] Figure 1 Schematic diagram of a partial structure of an array region of a semiconductor structure provided in an embodiment of the present application.

[0034] Refer to Figure 1, the semiconductor structure includes: a plurality of active pillars 100, word lines 200, bit lines 300, word line plugs 201, and bit line plugs 301. Among them, the active pillars 100 are arranged along the first direction X and the second direction Y, and the active pillars 100 extend along the third direction Z; the word lines 200 extend along the first direction X, and in the first direction X, the word lines 200 cover the side walls of the plurality of active pillars 100; the bit lines 300 extend along the second direction Y, and in the second direction Y, the bit lines 300 are connected to one end of the plurality of active pillars 100 along the third direction Z; the word line plugs 201 are located on the side of the word lines 200 closer to the bit lines 300 along the third direction Z and are in electrical contact with the word lines 200; the bit line plugs 301 are located on the side of the bit lines 300 away from the active pillars 100 along the third direction Z and are in electrical contact with the bit lines 300.

[0035] The active pillars 100 extend along the third direction Z and are arranged along the first direction X and the second direction Y, which is convenient for forming transistor structures arranged along the first direction X and the second direction Y, and the transistor structures extend along the third direction Z. In the plane where the first direction X and the second direction Y are located, the transistor structures may not occupy too much area, which is beneficial to improving the arrangement density of the transistor structures and the space utilization rate of the semiconductor structure. The word lines 200 cover the side walls of the plurality of active pillars 100 along the first direction X, and the bit lines 300 are connected to one end of the plurality of active pillars 100 along the second direction Y. In this way, the word lines 200 and the bit lines 300 can control the plurality of transistor structures in the first direction X and the second direction Y respectively.

[0036] In some embodiments, the semiconductor structure may have an array region and a peripheral region. The array region is used to form transistor structures arranged in an array, and the peripheral region is used to form circuit structures for controlling the transistor structures. The active pillars 100 are located in the array region of the semiconductor structure, and the corresponding transistor structures are located in the array region. In the plane where the first direction X and the second direction Y are located, the orthographic projections of the word line plugs 201 and the bit line plugs 301 are both located in the array region. That is to say, without changing the division of the array region and the peripheral region in the conventional semiconductor structure, both the word line plugs 201 and the bit line plugs 301 are arranged in the array region. In this way, it is possible to avoid the word line plugs 201 and the bit line plugs 301 occupying the space of the peripheral region, which is beneficial to improving the integration density of the semiconductor structure.

[0037] It should be noted that Figure 1The shapes of the active pillar 100, word line 200, bit line 300, word line plug 201, and bit line plug 301 shown do not constitute limitations on the active pillar 100, word line 200, bit line 300, word line plug 201, and bit line plug 301. The shapes of the active pillar, word line, bit line, word line plug, and bit line plug can be designed according to actual situations. For example, the shape of the active pillar can be a cylinder, an elliptical cylinder, a quadrangular prism, or a polygonal prism; the shape of the word line can be a cylinder, an elliptical cylinder, a quadrangular prism, or a polygonal prism; the shape of the bit line can be a cylinder, an elliptical cylinder, a quadrangular prism, or a polygonal prism; the shape of the word line plug can be a cylinder, an elliptical cylinder, a quadrangular prism, or a polygonal prism; the shape of the bit line plug can be a cylinder, an elliptical cylinder, a quadrangular prism, or a polygonal prism.

[0038] Figure 2 FIG. 4 is a schematic partial cross-sectional structure diagram of a first semiconductor structure provided by an embodiment of the present disclosure along a direction parallel to the bit line; Figure 3 FIG. 6 is a schematic partial cross-sectional structure diagram of a first semiconductor structure provided by an embodiment of the present disclosure along a direction parallel to the word line.

[0039] Referring to Figure 2 and Figure 3 , in some embodiments, the active pillar 100 may include a first doping region 101, a channel region 103, and a second doping region 102 arranged in sequence along the third direction Z. The word line 200 may cover the channel region 103 of the active pillar 100, and the bit line 300 may be in electrical contact with the first doping region 101 of the active pillar 100. In some embodiments, the bit line may also be in electrical contact with the second doping region of the active pillar, and the corresponding bit line plug is located on the side of the bit line away from the second doping region along the third direction, and the word line plug is located on the side of the word line close to the second doping region along the third direction.

[0040] The first doping region 101 and the second doping region 102 may have P-type or N-type doping ions. For example, the N-type ions may specifically be phosphorus ions, arsenic ions, or antimony ions; the P-type ions may specifically be boron ions, indium ions, or gallium ions.

[0041] The material of the active pillar 100 may include semiconductor materials such as silicon, gallium arsenide, silicon carbide, or gallium nitride.

[0042] The material of the active pillar 100 may also include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide), or ITO (Indium Tin Oxide).

[0043] The material of the word line 200 may include at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0044] In some embodiments, a gate dielectric layer may also be included between the word line and the sidewall of the active pillar. The material of the gate dielectric layer may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, antiferroelectric material, or a combination thereof.

[0045] In Figure 1 Taking the example that the word line 200 surrounds the sidewall of the active pillar 100 is used for illustration, which is beneficial to increasing the contact area between the word line 200 and the channel region 103 and improving the control gate control ability of the word line 200. In some embodiments, the word line may also only cover a part of the sidewall of the active pillar on one side in the second direction.

[0046] The material of the bit line 300 may include single metal, metal compound, or alloy. Among them, the single metal may be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum, etc.; the metal compound may be tungsten nitride, tantalum nitride, or titanium nitride; the alloy may be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0047] The material of the word line plug 201 may include one or more of copper, aluminum, nickel, tungsten, silver, gold, etc., of metal or metal alloy.

[0048] In some embodiments, the material of the word line plug 201 may be the same as or different from the material of the word line 200.

[0049] The material of the bit line plug 301 may include one or more of copper, aluminum, nickel, tungsten, silver, gold, etc., of metal or metal alloy.

[0050] In some embodiments, the material of the bit line plug 301 may be the same as or different from the material of the bit line 300.

[0051] Figure 4 FIG. is a schematic partial cross-sectional structure diagram of a second semiconductor structure provided by an embodiment of the present disclosure along a direction parallel to the bit line; Figure 5 FIG. is a schematic partial cross-sectional structure diagram of a second semiconductor structure provided by an embodiment of the present disclosure along a direction parallel to the word line.

[0052] Refer to Figure 4 and Figure 5, in some embodiments, the semiconductor structure may further include: a capacitor 400, which extends along the third direction Z. The capacitor 400 is located on a side of the active pillar 100 away from the bit line 300 along the third direction Z and is in electrical contact with the active pillar 100. In this way, the transistor structure and the corresponding capacitor 400 can form a memory cell, and the word line 200 and the bit line 300 can store or read data from the memory cell. Additionally, the capacitor 400 and the word line plug 201 are respectively located at two ends of the active pillar, and the capacitor 400 and the bit line plug 302 are respectively located at two ends of the active pillar, improving the space utilization rate of the semiconductor structure. At the same time, it can also avoid problems such as parasitic capacitance or leakage caused by the too-close distance between the word line plug 201 or the bit line plug 301 and the capacitor 400, improving the stability of the semiconductor structure.

[0053] In some embodiments, the capacitor may include a top plate, a dielectric layer, and a bottom plate stacked in sequence. Among them, the bottom plate extends along the third direction, and one end is electrically connected to the end of the active pillar away from the bit line; the dielectric layer covers the side surface of the bottom plate and the surface of the bottom plate away from the active pillar along the third direction; the top plate covers the surface of the dielectric layer away from the top plate.

[0054] In some embodiments, the bottom plate can be directly in electrical contact with the active pillar to electrically connect the capacitor to the active pillar. In some embodiments, the capacitor may further include a contact structure located between the bottom plate and the active pillar. The capacitor is electrically connected to the active pillar through the contact structure, which is beneficial to reducing the contact resistance between the bottom plate and the active pillar and improving the signal transmission efficiency.

[0055] The materials of the top plate and the bottom plate may include at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0056] The material of the dielectric layer may include high-k materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0057] The material of the contact structure may include copper, silver, gold, tungsten, tin, or lead, etc.

[0058] In some embodiments, the semiconductor structure may further include: a driving transistor, which is located on a side of the word line plug away from the word line along the third direction and on a side of the bit line plug away from the bit line along the third direction. One of the gate, source, or drain of the driving transistor is electrically connected to the word line plug or the bit line plug. In this way, the driving transistor and the capacitor can be respectively located at two ends of the active pillar, and the memory cell and the driving transistor are arranged in the third direction. In the plane where the first direction and the second direction are located, the driving transistor may not occupy area, which is beneficial to improving the space utilization rate of the semiconductor structure.

[0059] It should be noted that in the accompanying drawings provided in this embodiment, the included angle between the first direction X and the second direction Y is 90°, and the included angle between the plane where the first direction X and the second direction Y are located and the third direction Z is 90° as an example. In some embodiments, the included angle between the first direction and the second direction may be 30°, 45° or 60°, and the included angle between the plane where the first direction and the second direction are located and the third direction may be 30°, 45° or 60°. This embodiment does not constitute a limitation on the included angles between the first direction, the second direction and the third direction.

[0060] Figure 6 FIG. 5 is a schematic partial cross-sectional structure diagram of a third semiconductor structure provided by an embodiment of the present disclosure along a direction parallel to the word line.

[0061] Referring to Figure 6 , in some embodiments, the word line plug 201 may include a first portion 221 and a second portion 211 connected in sequence. The first portion 221 is located between adjacent active pillars 100 and is in electrical contact with the word line 200. The second portion 211 is located on the side of the first portion 221 away from the word line 200 along the third direction Z. In the first direction X, the size of the first portion 221 is smaller than that of the second portion 211. In this way, the end face area of the word line plug 201 away from the word line 200 along the third direction Z is larger than the end face area of the word line plug 201 close to the word line 200 along the third direction Z, which is beneficial to improving the contact window for the electrical connection between the word line plug 201 and other devices, avoiding the problem of disconnection of the word line plug, and improving the stability of the semiconductor structure.

[0062] In some embodiments, in the first direction X, the size of the spacing between the first portion 221 and the adjacent active pillar 100 is 5 nm to 15 nm, for example, it may be 5 nm, 5.4 nm, 6 nm, 6.6 nm, 7 nm, 7.5 nm, 8 nm, 9.3 nm, 10.2 nm, 11.6 nm, 12.8 nm, 13.7 nm, 14.5 nm or 15 nm, etc. Since the first portion 221 is located between the first doping regions 101 of the adjacent active pillars 100, in order to avoid the problem of leakage between the first portion 221 and the first doping region 101 of the active pillar 100, the width of the first portion 221 needs to be within an appropriate range.

[0063] For example, in the first direction X, the width of the first portion 221 may be 20 nm to 30 nm, such as 20 nm, 22 nm, 25 nm, 27 nm, 29 nm or 30 nm.

[0064] The material of the first portion 221 and the material of the second portion 211 may both include one or more of copper, aluminum, nickel, tungsten, silver, gold, etc., metals or metal alloys.

[0065] In some embodiments, the material of the first part 221 may be different from that of the second part 211. In this way, a material with a lower contact resistance to the word line 200 can be selected to fabricate the first part 221, and a material with a higher conductivity can be selected to fabricate the second part 211, which is beneficial to reducing the contact resistance between the via plug 201 and the word line 200 and improving the signal transmission efficiency of the via plug 201.

[0066] In some embodiments, the material of the first part 221 may also be the same as that of the second part 211.

[0067] Figure 7 FIG. is a partial cross-sectional structural schematic diagram of a fourth semiconductor structure provided by an embodiment of the present disclosure along a direction parallel to the word line.

[0068] Reference Figure 7 , in some embodiments, the semiconductor structure may further include: a protective layer 500. Along the second direction Y, the protective layer 500 covers two opposite side surfaces of a plurality of active pillars 100 along the first direction X, and covers two opposite side surfaces of the bit line 300 along the first direction X. The via plug 201 is located between the protective layers 500 on the side surfaces of two adjacent active pillars 100. In this way, the problem of short circuit between the via plug 201 and the bit line 300 can be avoided, which is beneficial to improving the stability of the semiconductor structure.

[0069] Figure 8 FIG. is a partial cross-sectional structural schematic diagram of a fifth semiconductor structure provided by an embodiment of the present disclosure along a direction parallel to the word line.

[0070] Reference Figure 8 , in some embodiments, the protective layer 500 may further include: a first protective layer 501, the first protective layer 501 covers two opposite side surfaces of the bit line 300 along the first direction X, and covers two opposite side surfaces of one end of the active pillar 100 close to the bit line 300 along the first direction X; a second protective layer 502, the second protective layer 502 covers the surface of the first protective layer 501 away from the bit line 300, and covers the surface of the first protective layer 501 away from the active pillar 100. The via plug 201 is located between the second protective layers 502 on the side surfaces of two adjacent active pillars 100; wherein, the material of the first protective layer 501 is different from that of the second protective layer 502. In this way, when forming the via plug 201 between adjacent bit lines 300 and active pillars 100, the second protective layer 502 can be used as an etching stop layer, avoiding etching damage to the side surface of the bit line 300 or the side surface of the active pillar 100 close to the bit line end during the etching process, and the subsequently formed via plug 201 will not contact the active pillar 100 or the bit line 300, avoiding problems of leakage or short circuit and improving the stability of the semiconductor structure.

[0071] The materials of the first protective layer 501 and the second protective layer 502 may both include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0072] Figure 9 FIG. 4 is a schematic partial cross-sectional structure diagram of a sixth semiconductor structure provided by an embodiment of the present disclosure along a direction parallel to the word line.

[0073] In some embodiments, along a direction perpendicular to the second direction Y, the size of the bit line plug 301 may be larger than that of the bit line 300. The bit line plug 301, the bit line 300, and the active column 100 are arranged along the third direction Z. In this way, the size of the bit line plug 301 may not be affected by the size of the active column 100 or the bit line 300. Without affecting the word line plug 201, a larger size of the bit line plug 301 than that of the bit line 300 is beneficial for electrically connecting the bit line plug 301 to other devices, increasing the contact window between the bit line plug 301 and other structures, and thus improving the signal transmission efficiency.

[0074] For example, along a direction perpendicular to the second direction Y, the size of the bit line plug 301 may be 20 nm to 30 nm, such as 20 nm, 22 nm, 25 nm, 27 nm, 29 nm, or 30 nm.

[0075] Along the extension direction of the bit line 300, that is, the second direction Y, the size of the bit line plug 301 may not be affected by the size of the bit line 300. However, the size of the bit line plug 301 still needs to be within an appropriate range to avoid affecting other device structures due to an overly large size of the bit line plug 301. For example, along the second direction Y, the size of the bit line plug 301 may be 60 nm to 65 nm, specifically 60 nm, 61 nm, 62 nm, 62.5 nm, 63 nm, 64 nm, or 65 nm.

[0076] In some embodiments, along a direction perpendicular to the second direction, the size of the bit line plug may also be less than or equal to the size of the bit line.

[0077] In Figure 1 , taking the plane where the first direction X and the second direction Y are located as an example, the bit line plugs 301 are aligned and arranged along the first direction X, and the word line plugs 201 are staggeredly arranged along the second direction Y.

[0078] In some embodiments, along the first direction X, adjacent bit line plugs 301 may also be staggeredly arranged.

[0079] In some embodiments, along the second direction Y, adjacent word line plugs 201 may also be aligned and arranged.

[0080] Figure 10Schematic diagram of a partial cross-sectional structure of a seventh semiconductor structure provided by an embodiment of the present disclosure along a direction parallel to the word line; Figure 11 is Figure 10 Corresponding partial top view of the semiconductor structure along the third direction; Figures 12 to 18 Partial top view of multiple semiconductor structures provided by an embodiment of the present disclosure along the third direction.

[0081] With reference to Figure 10 and Figure 11 , in some embodiments, the semiconductor structure may further include: a dummy bit line 202, the dummy bit line 202 extends along the second direction Y, the dummy bit line 202 is located on the outermost side of a plurality of bit lines 300 arranged along the first direction X, and in the plane where the first direction X and the second direction Y are located, the orthographic projection of the word line plug 201 overlaps with the orthographic projection of the dummy bit line 202. Thus, the size of the word line plug 201 can be not affected by the distance between adjacent active pillars 100, which is beneficial to increasing the size of the word line plug 201 to reduce the contact resistance of the word line plug 201, and the bit line plug 301 can have a relatively long distance from the word line plug 201 to avoid problems of parasitic capacitance or short circuit between the word line plug 201 and the bit line plug 301.

[0082] It should be noted that the dummy bit line 202 and the bit line 300 are fabricated by the same manufacturing process, but in this embodiment, the dummy bit line 202 is not electrically connected to other device structures and only provides a formation area for the word line plug 201.

[0083] In some embodiments, along the first direction X, the width of the dummy bit line 202 is a first width W1, the width of the bit line 300 is a second width W2, the first width W1 is greater than the second width W2 and less than 2 times the second width W2. Thus, in the plane where the first direction X and the second direction Y are located, the word line plug 201 still remains within the array area and does not occupy a large area, avoiding causing a spatial burden on the semiconductor structure, which is beneficial to increasing the integration density of the semiconductor structure.

[0084] In some embodiments, along the first direction X, the width W1 of the dummy bit line 202 may be 50 nm to 100 nm, such as 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm.

[0085] With reference to Figure 11 and Figure 12 , in some embodiments, when the semiconductor structure includes the dummy bit line 202, the word line plug 201 is located at the end of the word line 200, and the word line plugs 201 of multiple word lines 200 can be aligned and arranged along the second direction Y, where the bit line plug 301 can be as Figure 12Aligned and arranged along the first direction X, so that the bit line plug 301 can be arranged at the end of the bit line 300; or the bit line plug 301 can be misaligned along the first direction X as shown in Figure 11 . In Figure 12 , in the plane where the first direction X and the second direction Y are located, the areas occupied by the word line plug 201 and the bit line plug 301 are located at the edge positions of the array region, saving the area of the array region and making it more convenient to fabricate the word line plug 201 and the bit line plug 301. In Figure 11 , the misaligned arrangement of the bit line plugs 301 has a larger spacing between adjacent bit line plugs 301 compared to the aligned arrangement of the bit line plugs 301 in Figure 12 , to avoid leakage or parasitic capacitance problems between adjacent bit line plugs 301.

[0086] Refer to Figure 13 . When the dummy bit line 202 is not provided in the semiconductor structure, the word line plug 201 can be arranged in the array region and aligned along the second direction Y. In this way, the dummy bit line 202 can be not provided, further increasing the space of the array region, and the word line plug 201 and the bit line plug 301 can be arranged more flexibly in the array region without occupying too much area.

[0087] Refer to Figure 14 . When the dummy bit line 202 is not provided in the semiconductor structure, the word line plug 201 can be arranged in the array region and misaligned along the second direction Y. This is beneficial to avoid mutual influence between the word line plugs 201 and further reduce the parasitic capacitance.

[0088] Refer to Figure 15 . When the word line plugs 201 are misaligned along the second direction Y, or, refer to Figure 16 . When the word line plugs 201 are aligned along the second direction Y, for the bit line plugs 301, some of the bit line plugs 301 can be aligned and some can be misaligned. In this way, the bit line plugs 301 make room for the word line plugs 201, which is beneficial to increase the size of the word line plugs 201, reduce the contact resistance of the word line plugs 201, and avoid leakage or parasitic capacitance problems between the word line plugs 201 and the bit line plugs 301. Similarly, refer to Figure 17 . The word line plugs 201 can also be arranged in a way that some are aligned and some are misaligned, so that the distance between the word line plugs 201 and the bit line plugs 301 is relatively large, and their respective sizes can be designed larger, which is beneficial to reduce the contact resistance and delay of the word line plugs 201 and the bit line plugs 301.

[0089] In some embodiments, referring to Figure 18 and Figure 6, when the word line plug 201 includes a first portion 221 and a second portion 211, in the first direction X, the size of the second portion 211 can also be larger than the size of the bit line 300, so as to further increase the top surface area of the word line plug 201 and improve the electrical connection stability between the word line plug 201 and other device structures. In the actual design process of the semiconductor structure, in order to meet the design requirements of the miniaturized semiconductor structure, the word line plug 201 can also be designed smaller as shown in Figures 12 to 17 . In this way, the distance between the word line plugs 201 increases, the parasitic capacitance decreases, thereby reducing the leakage risk between the word line plug 201 and the bit line plug 301 and reducing the delay.

[0090] In some embodiments, the staggered arrangement of the word line plugs in the second direction can also be that every 2, 4, or 5 aligned word line plugs form a word line plug group, and the adjacent word line plug groups are staggered. Similarly, the staggered arrangement of the bit line plugs in the first direction can also be that every 2, 3, or 6 aligned bit line plugs form a bit line plug group, and the adjacent bit line plug groups are staggered.

[0091] It can be understood that the arrangement methods of the word line plugs or the bit line plugs provided in the above embodiments can be arbitrarily combined without conflict to obtain new embodiments. In the actual design process of the semiconductor structure, the arrangement and size of the word line plug 201 and the bit line plug 301 can be comprehensively adjusted in combination with the above embodiments, so that the distance between the word line plug and the bit line plug is as large as possible to avoid problems of leakage or parasitic capacitance between the word line plug and the bit line plug.

[0092] In the semiconductor structure provided by the embodiment of the present disclosure, the active pillar 100 extends along the third direction Z and is arranged along the first direction X and the second direction Y. In this way, it is convenient to form a transistor structure arranged along the first direction X and the second direction Y, and the transistor structure extends along the third direction Z. In the plane where the first direction X and the second direction Y are located, the transistor structure may not occupy too much area, which is beneficial to improving the arrangement density of the transistor structure and the space utilization rate of the semiconductor structure. The word line 200 covers the side walls of a plurality of active pillars 100 along the first direction X, and the bit line 300 is connected to one end of a plurality of active pillars 100 along the second direction Y. In this way, the word line 200 and the bit line 300 can control a plurality of transistor structures in the first direction X and the second direction Y respectively. The semiconductor structure may have an array region and a peripheral region. The array region is used to form an array of transistor structures, and the peripheral region is used to form a circuit structure for controlling the transistor structure. The active pillar 100 is located in the array region of the semiconductor structure, and the corresponding transistor structure is located in the array region. In the plane where the first direction X and the second direction Y are located, the orthographic projections of the word line plug 201 and the bit line plug 301 are both located in the array region. That is to say, without changing the division of the array region and the peripheral region in the conventional semiconductor structure, the word line plug 201 and the bit line plug 301 are both arranged in the array region. In this way, it is possible to avoid the word line plug 201 and the bit line plug 301 occupying the space of the peripheral region, which is beneficial to improving the integration density of the semiconductor structure.

[0093] Another embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, which can be used to form the above semiconductor structure to improve the integration density of the semiconductor structure. It should be noted that the same or corresponding parts as those in the above embodiments can refer to the corresponding descriptions of the foregoing embodiments, and will not be elaborated in detail below. The manufacturing method of the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0094] Figures 19 to 27 Structural schematic diagrams corresponding to the respective steps of a manufacturing method of a semiconductor structure provided in another embodiment of the present disclosure. Among them, Figures 20 to 27 is Figure 19 A cross-sectional structural schematic diagram along the AA1 direction and the BB1 direction.

[0095] Referring to Figures 19 to 27 , the manufacturing method of the semiconductor structure includes:

[0096] Referring to Figure 19, a substrate 110 is provided. The substrate 110 includes an array region and a peripheral region. The array region is used to form transistor structures arranged in an array, and the peripheral region is used to form circuit structures for controlling the transistor structures; A plurality of active pillars 100 are formed on the array region of the substrate 110. The active pillars 100 are arranged along a first direction X and a second direction Y, and the active pillars 100 extend along a third direction Z. The active pillars 100 include a first doped region 101, a channel region 103, and a second doped region 102 arranged in sequence along the third direction Z.

[0097] It should be noted that only the array region of the substrate 110 is shown in Figure 19 . Other structures may also be present on the peripheral region of the substrate 110. The structure of the peripheral region is not limited in this embodiment.

[0098] In some embodiments, the substrate 110 may be a silicon substrate, a silicon-germanium substrate, a gallium arsenide substrate, a silicon carbide substrate, a gallium nitride substrate, or the like.

[0099] The material of the active pillar 100 may include semiconductor materials such as silicon, gallium arsenide, silicon carbide, or gallium nitride.

[0100] The material of the active pillar 100 may also be at least one of IGZO, IWO, or ITO.

[0101] In some embodiments, providing the substrate 110 and forming the active pillar 100 may include: providing an initial substrate 120; forming a plurality of first trenches 111 extending along the first direction X and a plurality of second trenches 112 extending along the second direction Y in the initial substrate 120. The remaining initial substrate 120 between the first trenches 111 and the second trenches 112 serves as the active pillar 100, and the remaining initial substrate 120 at the bottom of the first trenches 111 and the second trenches 112 serves as the substrate 110. In this way, the material of the substrate 110 and the material of the active pillar 100 may be the same.

[0102] In some embodiments, providing the substrate and the active pillar may also include: forming a semiconductor layer on the substrate and patterning the semiconductor layer to form the active pillar. In this way, the material of the active pillar and the material of the substrate may be different.

[0103] In some embodiments, after forming the active pillar, chamfering treatment may be performed on the corners of the active pillar to avoid the problem of tip discharge at the corners of the active pillar.

[0104] After forming the active pillar 100, doping treatment may be performed on the first doped region 101 and the second doped region 102 so that the first doped region 101 and the second doped region 102 contain P-type or N-type doping ions. For example, the N-type ions may specifically be phosphorus ions, arsenic ions, or antimony ions; the P-type ions may specifically be boron ions, indium ions, or gallium ions.

[0105] In some embodiments, the depth of the first trench 111 in the initial substrate 120 may be less than the depth of the second trench 112 in the initial substrate 120. In some embodiments, the depth of the first trench in the initial substrate may also be greater than or equal to the depth of the second trench in the initial substrate.

[0106] Reference Figure 20 , a word line 200 is formed. The word line 200 extends along the first direction X. Along the first direction X, the word line 200 covers the sidewalls of the channel regions 103 of a plurality of active pillars 100, and the insulating layer 130 is filled between adjacent word lines 200 and between adjacent active pillars 100.

[0107] In some embodiments, forming the word line may include: forming an insulating layer, the insulating layer filling the first trench and the second trench; patterning the insulating layer to form a plurality of word line trenches extending along the first direction, the word line trenches exposing the sidewalls of the channel regions of a plurality of active pillars; forming a gate dielectric layer, the gate dielectric layer covering the surface of the channel regions of the active pillars; filling the word line trenches to form the word line; and reforming the insulating layer on the top surface of the word line.

[0108] The material for forming the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0109] The material for forming the gate dielectric layer may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof.

[0110] The material for forming the word line 200 may include at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0111] Reference Figure 21 , a bit line 300 is formed. The bit line 300 extends along the second direction Y. Along the second direction Y, the bit line Y is connected to one end of a plurality of active pillars 100 in the third direction Z.

[0112] Reference Figure 20 , taking the end of the active pillar 100 close to the substrate 110 in the third direction Z as the first end (i.e., the end of the second doped region 102 far from the channel region 103), and the end of the active pillar 100 far from the substrate 110 in the third direction Z as the second end (i.e., the end of the first doped region 101 far from the channel region 103).

[0113] In some embodiments, after forming the active pillar 100 and the word line 200, before forming the bit line 300, it includes: performing a planarization process to remove the substrate 110 to expose the end face of the first end of the active pillar 100, and then forming the bit line 300 at the first end of the active pillar 100, that is, the bit line 300 is located at the end face of the second doped region 102. The planarization process can remove the substrate 110 at the first end of the active pillar 100, and at the same time, can also remove the insulating layer (shallow trench isolation structure) between the bottoms of the active pillars 100, so as to reduce the height when forming the bit line 300 subsequently, and avoid forming air gaps in the bit line 300.

[0114] In some embodiments, the planarization process can adopt a chemical mechanical polishing process.

[0115] In some embodiments, forming the bit line 300 can include: removing a part of the thickness of the active pillar 100 (that is, a part of the second doped region); forming a metal layer, the metal layer is located at the end face of the first end of the active pillar 100; performing a heat treatment process to make a part of the active pillar 100 react with the metal layer to form a metal compound layer, and the metal compound layer serves as the bit line 300. The contact resistance between the bit line 300 and the active pillar 100 can be reduced through the heat treatment process.

[0116] In some embodiments, the heat treatment process includes a rapid thermal annealing process.

[0117] In some embodiments, the material for forming the metal layer can be a single metal, a metal compound or an alloy. Among them, the single metal can be cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum, etc.; the metal compound can be tungsten nitride, tantalum nitride or titanium nitride; the alloy can be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum.

[0118] In some embodiments, the metal layer can also be directly used as the bit line.

[0119] Reference Figure 22 , forming the word line plug 201 and the bit line plug 301, the word line plug 201 is located on the side of the word line 200 close to the bit line 300 along the third direction Z, and the bit line plug 301 is located on the side of the bit line 300 far from the active pillar 100 along the third direction Z, that is, both the word line plug 201 and the bit line plug 301 are close to the first end of the active pillar 100.

[0120] In some embodiments, forming the word line plug 201 and the bit line plug 301 includes: forming a filling layer 140, the filling layer 140 being located on the surface of the bit line 300 away from the active pillar 100 and the surface of the insulating layer 130; patterning the filling layer 140 and the insulating layer 130 to form a word line plug hole 203 and a bit line plug hole 303. In the plane where the first direction X and the second direction Y are located, the orthographic projection of the word line plug hole 203 overlaps with the orthographic projection of the word line 200, and the orthographic projection of the bit line plug hole 303 overlaps with the bit line 300. The word line plug hole 203 exposes the surface of the word line 200 at the first end close to the active pillar 100 along the third direction Z, and the bit line plug hole 303 exposes the surface of the bit line 300 at the first end close to the active pillar 100 along the third direction Z; filling the word line plug hole 203 to form the word line plug 201, and filling the bit line plug hole 303 to form the bit line plug 301.

[0121] The material for forming the filling layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0122] The material for forming the word line plug 201 may include one or more metals or metal alloys such as copper, aluminum, nickel, tungsten, silver, gold, etc.

[0123] The material for forming the bit line plug 301 may include one or more metals or metal alloys such as copper, aluminum, nickel, tungsten, silver, gold, etc.

[0124] In some embodiments, in the first direction X, the size of the spacing between the word line plug 201 and the adjacent active pillar 100 may be 5 nm to 15 nm, for example, it may be 5 nm, 5.4 nm, 6 nm, 6.6 nm, 7 nm, 7.5 nm, 8 nm, 9.3 nm, 10.2 nm, 11.6 nm, 12.8 nm, 13.7 nm, 14.5 nm or 15 nm, etc.

[0125] In some embodiments, refer to Figure 23, after forming the bit line 300 and before forming the word line plug 201, it may further include: removing the partial insulating layers 130 on the two opposite side surfaces of the bit line 300 along the first direction X and the partial insulating layers 130 on the two opposite side surfaces of the active pillar 100 along the first direction X; forming a first protective layer 501, the first protective layer 501 covering the two opposite side surfaces of the bit line 300 along the first direction X and covering the two opposite side surfaces of the active pillar 100 along the first direction X; forming a second protective layer 502, the second protective layer 502 covering the surface of the first protective layer 501 away from the bit line 300 and covering the surface of the first protective layer 501 away from the active pillar 100, and the material of the second protective layer 502 is different from the material of the first protective layer 501. Forming the word line plug 201 includes: forming the word line plug 201 between the second protective layers 502 on the side surfaces of adjacent active pillars 100. In this way, when forming the word line plug hole, the second protective layer 502 can be used as an etching stop layer to avoid etching damage to the side surface of the bit line 300 or the side surface of the active pillar 100 close to the bit line end during the etching process, and the formed word line plug 201 will not contact the active pillar 100 or the bit line 300, avoiding problems such as leakage or short circuit and improving the stability of the semiconductor structure.

[0126] The materials for forming the first protective layer 501 and the second protective layer 502 may both include silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0127] In some embodiments, referring to Figure 24, forming the word line plug hole 203 may include: forming a first word line plug hole 213, the first word line plug hole 213 is located on the side of the bit line 300 away from the active pillar 100 along the third direction Z, and in the first direction X, the size of the first word line plug hole 213 may be greater than or equal to the pitch between adjacent active pillars 100; forming a second word line plug hole 223, the second word line plug hole 223 communicates with the first word line plug hole 213, the second word line plug hole 223 is located between adjacent active pillars 100, and in the first direction X, the size of the second word line plug hole 223 is smaller than the size of the first word line plug hole 213; filling the first word line plug hole 213 and the second word line plug hole 223 to form a word line plug 201. In this way, the word line plug 201 may include a first part 221 and a second part 211 connected in sequence, the first part 221 is located between adjacent active pillars 100 and is in electrical contact with the word line 200, the second part 211 is located on the side of the first part 221 away from the word line 200 along the third direction Z, and in the first direction X, the size of the first part 221 is smaller than the size of the second part 211. The end face area of the word line plug 201 away from the word line 200 along the third direction Z is larger than the end face area of the word line plug 201 close to the word line 200 along the third direction Z, which may be beneficial to improving the contact window for the electrical connection between the word line plug 201 and other devices, avoiding the problem of disconnection of the word line plug 201, and improving the stability of the semiconductor structure.

[0128] In some embodiments, in the first direction X, the size of the pitch between the first part 221 and the adjacent active pillar 100 may be 5 nm to 15 nm, for example, it may be 5 nm, 5.4 nm, 6 nm, 6.6 nm, 7 nm, 7.5 nm, 8 nm, 9.3 nm, 10.2 nm, 11.6 nm, 12.8 nm, 13.7 nm, 14.5 nm or 15 nm, etc.

[0129] Reference Figure 25 , in some embodiments, after forming the word line plug 201 and the bit line plug 301, it may further include: providing a second wafer 150, the second wafer 150 has a plurality of driving transistors (not shown in the figure) therein, the surface of the second wafer 150 has pads 151, and the pads 151 are electrically connected to one of the gates, sources or drains of the driving transistors; placing the second wafer 150 opposite to the word line plug 201 and the bit line plug 301 so that the word line plug 201 or the bit line plug 301 is in contact with the pads 151; performing a bonding process so that the word line plug 201 is in electrical contact with the pads 151 and the bit line plug 301 is in electrical contact with the pads 151.

[0130] The material of the pad 151 may include copper, silver, gold, tungsten, tin, lead, etc. In some embodiments, the material of the pad 151 may be the same as that of the word line plug 201 and / or the bit line plug 301, which is beneficial to the bonding process, beneficial to the electrical contact between the word line plug 201 and the pad 151, and / or beneficial to the electrical contact between the bit line plug 301 and the pad 151.

[0131] In some embodiments, a contact structure 170 may further be formed on the end face of the active pillar 100 on the side away from the bit line 300 along the third direction Z: The contact structure 170 is located on the end face of the second end of the active pillar 100 (i.e., the end face of the first doped region 101); A first wafer 160 is provided, and a plurality of capacitors 400 are provided in the first wafer 160, and one end of the capacitor 400 is exposed on the surface of the first wafer 160; The first wafer 160 is placed opposite to the contact structure 170 so that the capacitor 400 is in contact with the contact structure 170; A bonding process is performed so that the capacitor 400 is in electrical contact with the contact structure 170.

[0132] In this way, the active pillar 100 and the corresponding capacitor 400 form a storage unit. The driving transistor can control the conduction of the word line 200 and the bit line 300 through the word line plug 201 and the bit line plug 301 to read or store data in the storage unit. The storage units and the driving transistors are arranged in the third direction Z. Then, in the plane where the first direction X and the second direction Y are located, the storage units and the corresponding driving transistors may not occupy too much area, which is beneficial to improving the space utilization rate of the semiconductor structure.

[0133] The material for forming the contact structure 170 may include copper, silver, gold, tungsten, tin, lead, etc.

[0134] Reference Figure 26 , in some embodiments, the bit line 300 may also be formed at the second end of the active pillar 100 first, that is, the bit line 300 is located on the end face of the first doped region 101.

[0135] In some embodiments, forming the bit line 300 may include: removing a part of the thickness of the active pillar 101 (i.e., part of the first doped region 101); forming a metal layer on the end face of the second end of the active pillar 100; performing a heat treatment process so that a part of the active pillar 100 reacts with the metal layer to form a metal compound layer, and the metal compound layer serves as the bit line 300.

[0136] Among them, the material of the metal layer may be a single metal, a metal compound or an alloy. Among them, the single metal may be cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum, etc.; the metal compound may be tungsten nitride, tantalum nitride or titanium nitride; the alloy may be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum.

[0137] In some embodiments, a metal layer can also be directly used as a bit line.

[0138] In some embodiments, forming the word line plug 201 and the bit line plug 301 can include: forming a filling layer 140, where the filling layer 140 is located on the surface of the bit line 300 away from the active pillar 100 and on the surface of the insulating layer 130; patterning the filling layer 140 and the insulating layer 130 to form a word line plug hole 203 and a bit line plug hole 303. In the plane of the first direction X and the second direction Y, the orthographic projection of the word line plug hole 203 overlaps with the orthographic projection of the word line 200, and the orthographic projection of the bit line plug hole 303 overlaps with the bit line 300. The word line plug hole 203 exposes the surface of the word line 200 at the first end close to the active pillar 100 along the third direction Z, and the bit line plug hole 303 exposes the surface of the bit line 300 at the first end close to the active pillar 100 along the third direction Z; filling the word line plug hole to form the word line plug 201, and filling the bit line plug hole to form the bit line plug 301.

[0139] Reference Figure 27 , in some embodiments, after forming the word line plug 201 and the bit line plug 301, it can also include: performing a planarization process to remove the substrate 110 to expose the end face of the first end of the active pillar 100; forming a contact structure 170 on the end face of the first end of the active pillar 100; providing a first wafer 160 with a plurality of capacitors 400 therein, and one end of the capacitor 400 is exposed on the surface of the first wafer 160; placing the first wafer 160 opposite to the contact structure 170 so that the capacitor 400 is in contact with the contact structure 170; performing a bonding process to make the capacitor 400 in electrical contact with the contact structure 170.

[0140] In some embodiments, it can also include: providing a second wafer 150 with a plurality of driving transistors therein, and the surface of the second wafer 150 has pads 151, and the pads 151 are electrically connected to one of the gates, sources or drains of the driving transistors; placing the second wafer 150 opposite to the word line plug 201 and the bit line plug 301 so that the word line plug 201 or the bit line plug 301 is in contact with the pads 151; performing a bonding process to make the word line plug 201 in electrical contact with the pads 151 and make the bit line plug 301 in electrical contact with the pads 151. Thus, the active pillar 100 and the corresponding capacitor 400 form a storage unit, and the driving transistor can control the conduction of the word line 200 and the bit line 300 through the word line plug 201 and the bit line plug 301 to read or store data in the storage unit. The storage units and the driving transistors are arranged in the third direction Z, so in the plane of the first direction X and the second direction Y, the storage units and the corresponding driving transistors do not occupy too much area, which is beneficial to improving the space utilization rate of the semiconductor structure.

[0141] The method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure forms active pillars 100 extending along a third direction Z and arranged along a first direction X and a second direction Y. In this way, it is convenient for the formed transistor structures to be arranged along the first direction X and the second direction Y, and the transistor structures extend along the third direction Z. In the plane where the first direction X and the second direction Y are located, the transistor structures may not occupy too much area, which is beneficial to improving the arrangement density of the transistor structures and the space utilization rate of the semiconductor structure. The formed word lines 200 cover the side walls of a plurality of active pillars 100 along the first direction X, and the formed bit lines 300 are connected to one ends of a plurality of active pillars 100 along the second direction Y. In this way, the word lines 200 and the bit lines 300 can control a plurality of transistor structures in the first direction X and the second direction Y respectively. The active pillars 100 are located in the array region of the semiconductor structure, and the corresponding transistor structures are located in the array region. In the plane where the first direction X and the second direction Y are located, the orthographic projections of the word line plugs 201 and the bit line plugs 301 are both located in the array region. That is to say, without changing the division of the array region and the peripheral region in the conventional semiconductor structure, the word line plugs 201 and the bit line plugs 301 are both arranged in the array region. In this way, it is possible to avoid the word line plugs 201 and the bit line plugs 301 occupying the space of the peripheral region, which is beneficial to improving the integration density of the semiconductor structure.

[0142] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including an array region; Forming a plurality of active columns, the active columns being located on the array region, the active columns being arranged along a first direction and a second direction, and the active columns extending along a third direction; Forming word lines, the word lines extending along the first direction, and in the first direction, the word lines covering sidewalls of a plurality of the active columns; Forming bit lines, the bit lines extending along the second direction, and in the second direction, the bit lines connecting one ends of a plurality of the active columns along the third direction; Forming word line plugs, the word line plugs being located on a side of the word lines close to the bit lines along the third direction and being in electrical contact with the word lines, and a positive projection of the word line plugs on the substrate being located in the array region; Forming bit line plugs, the bit line plugs being located on a side of the bit lines far from the active columns along the third direction and being in electrical contact with the bit lines, and a positive projection of the bit line plugs on the substrate being located in the array region.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, One end of the active column close to the substrate along the third direction is a first end, and one end of the active column far from the substrate along the third direction is a second end; After forming the active columns and the word lines and before forming the bit lines, including: a planarization process to expose an end face of the first end of the active columns; Forming the bit lines includes: forming the bit lines at the first ends of the active columns.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Forming the bit lines includes: Forming a metal layer, the metal layer being located on an end face of one end of the active column along the third direction; Performing a heat treatment process to cause a part of the active columns to react with the metal layer to form a metal compound layer, the metal compound layer serving as the bit lines.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, The heat treatment process includes a rapid thermal annealing process.

5. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, Materials for forming the metal layer include cobalt, titanium, tungsten, or tantalum.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, In the first direction, a dimension of a spacing between the word line plugs and adjacent active columns is 5 nm to 15 nm.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After forming the bit lines and before forming the word line plugs, including: Forming a first protective layer, the first protective layer covering two opposite side faces of the bit lines in the first direction and covering two opposite side faces of the active columns in the first direction; Forming a second protective layer, the second protective layer covering a surface of the first protective layer far from the bit lines and covering a surface of the first protective layer far from the active columns, and materials of the second protective layer and the first protective layer being different; Forming the word line plugs includes: forming the word line plugs between the second protective layers on side faces of adjacent active columns.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Forming the word line plugs and the bit line plugs includes: Forming a filling layer, the filling layer filling a gap between the active columns and covering a surface of the bit lines far from the active columns; Patterning the filling layer to form word line plug holes and bit line plug holes, and in a plane where the first direction and the second direction are located, a positive projection of the word line plug holes overlapping a positive projection of the word lines, and a positive projection of the bit line plug holes overlapping a positive projection of the bit lines; Fill the word line plug holes to form the word line plugs, and fill the bit line plug holes to form the bit line plugs.

9. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, The word line plug holes include: A first word line plug hole and a second word line plug hole. The first word line plug hole is located on a side of the bit line away from the active pillar along the third direction; the second word line plug hole communicates with the first word line plug hole, and the second word line plug hole is located between adjacent active pillars. In the first direction, the size of the second word line plug hole is smaller than that of the first word line plug hole.

10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Providing the substrate and forming the active pillars and the word lines includes: Providing an initial substrate; Forming a plurality of first trenches extending in the first direction and a plurality of second trenches extending in the second direction in the initial substrate. The remaining initial substrate between the first trenches and the second trenches serves as the active pillars, and the remaining initial substrate at the bottoms of the first trenches and the second trenches serves as the substrate; Forming an insulating layer that fills the first trenches and the second trenches; Patterning the insulating layer to form a plurality of word line trenches extending in the first direction, and the word line trenches expose the sidewalls of a plurality of the active pillars; Filling the word line trenches to form the word lines.

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