Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises a substrate and a plurality of active columns located on the substrate, and the plurality of active columns are arranged into a plurality of active column rows extending along a first direction and a plurality of active column columns extending along a second direction; wherein the plurality of active column columns comprise a plurality of active column groups which are arranged at intervals along the first direction, and each active column group comprises two active column columns which are adjacently arranged along the first direction; the first direction and the second direction intersect and are parallel to the surface of the substrate; the plurality of embedded bit lines are located between two adjacent active column columns in the active column groups and are electrically connected with each active column in the two adjacent active column columns, and two adjacent embedded bit lines are separated by two adjacent active column columns belonging to different active column groups in the two adjacent active column groups.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] DRAM devices with vertical channel transistors generally include active pillars arranged in an array, and a plurality of bit lines buried under the lower part of the active pillars. As semiconductor structures continue to develop towards miniaturization and high integration, the density of bit lines increases and the size decreases, thus causing a series of problems. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor structure, including: a substrate, and a plurality of active pillars located on the substrate, the plurality of active pillars being arranged into a plurality of rows of active pillars extending in a first direction and a plurality of columns of active pillars extending in a second direction; wherein, the plurality of columns of active pillars include a plurality of groups of active pillars spaced apart in the first direction, and each group of active pillars includes two columns of active pillars adjacent to each other in the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate; a plurality of buried bit lines, located between two adjacent columns of active pillars in the group of active pillars, and electrically connected to each of the two adjacent columns of active pillars in the two adjacent columns of active pillars adjacent thereto, and two adjacent buried bit lines are separated by two adjacent columns of active pillars belonging to different groups of active pillars in two adjacent groups of active pillars.

[0004] In some embodiments, the semiconductor structure further includes: a plurality of bit line contact portions, respectively disposed on two sides of the buried bit line in the first direction and electrically connected to the buried bit line, and the bit line contact portions are at least partially laterally embedded in the active pillars located on two sides of the buried bit line in the first direction.

[0005] In some embodiments, the plurality of active pillars in each column of active pillars are spaced apart in the second direction, and the plurality of bit line contact portions are spaced apart in the second direction and correspondingly disposed in the plurality of active pillars in the column of active pillars.

[0006] In some embodiments, the orthographic projection of the active pillar on the surface of the substrate is symmetrically arranged in the first direction and the second direction; or, the size of one end of the active pillar close to the buried bit line in the second direction is greater than the size of one end of the active pillar far from the buried bit line in the second direction in the first direction.

[0007] In some embodiments, the semiconductor structure further includes: a plurality of connection portions, located between the lower portions of two adjacent active pillars arranged in the second direction, and the lower portions of the plurality of active pillars arranged in the second direction are sequentially connected through the connection portions; The bit line contact portions are located in the plurality of active pillars and the plurality of connection portions and continuously extend in the second direction.

[0008] In some embodiments, the semiconductor structure further includes: a doped layer, at least partially located within the active pillar and at least surrounding the contact surface between the bit line contact portion and the active pillar.

[0009] In some embodiments, the semiconductor structure further includes: a first isolation structure, located below the embedded bit line and extending along a second direction, and the embedded bit line covers the first isolation structure; a second isolation structure, located between two adjacent active pillar groups and extending along the second direction, and the upper surface of the second isolation structure is higher than the upper surface of the embedded bit line.

[0010] In some embodiments, a plurality of active pillar rows are arranged along the second direction; the semiconductor structure further includes: a plurality of word lines located above the embedded bit line, the plurality of word lines are arranged along the second direction, and each word line extends along a first direction, and each word line covers a part of the sidewalls of each active pillar in an active pillar row.

[0011] Embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure, including: providing a substrate; forming a plurality of active pillars on the substrate; forming a plurality of embedded bit lines; wherein, the plurality of active pillars are arranged into a plurality of active pillar rows extending along a first direction and a plurality of active pillar columns extending along a second direction; the plurality of active pillar columns include a plurality of active pillar groups arranged at intervals along the first direction, and each active pillar group includes two adjacent active pillar columns arranged adjacent to each other along the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate; the embedded bit lines are located between two adjacent active pillar columns in the active pillar group, and are electrically connected to each active pillar in the two adjacent active pillar columns, and two adjacent embedded bit lines are separated by two adjacent active pillar columns belonging to different active pillar groups in the two adjacent active pillar groups.

[0012] In some embodiments, forming a plurality of active pillars on the substrate includes: etching the substrate to form a plurality of first trenches extending along the second direction on the substrate, the first trenches defining the substrate into a plurality of wall-like structures extending along the second direction; the plurality of first trenches include first sub-trenches and second sub-trenches arranged alternately in sequence along the first direction; etching at least the wall-like structures to form a plurality of second trenches extending along the first direction in the substrate, and the first trenches and the second trenches intersect with each other to define a plurality of discrete active pillars in the substrate; forming a plurality of embedded bit lines includes: After forming the first trench, before or after forming the second trench, an embedded bit line is formed in the first sub-trench, and the second sub-trench is located between two adjacent embedded bit lines.

[0013] In some embodiments, before forming the embedded bit line in the first sub-trench, the method further includes: Forming bit line contact portions on both sides of the first sub-trench along a first direction, and the bit line contact portions are at least partially laterally embedded in active pillars or wall-like structures located on both sides of the first sub-trench.

[0014] In some embodiments, forming the bit line contact portions includes: Forming a first dielectric layer covering the inner walls of the first sub-trench and the second sub-trench, and a first filling layer covering the first dielectric layer and filling the first sub-trench and the second sub-trench; Removing a part of the first filling layer in the first sub-trench to a first position to expose the first dielectric layer above the first position; Forming a second dielectric layer, the second dielectric layer covering the side walls of the exposed first dielectric layer and the upper surface of the remaining first filling layer; Removing the second dielectric layer covering the upper surface of the first filling layer and retaining the second dielectric layer covering the side walls of the first dielectric layer; Removing a part of the first filling layer in the first sub-trench to a second position to expose the first dielectric layer between the first position and the second position; Removing the first dielectric layer between the first position and the second position to expose a part of the active pillar or a part of the wall-like structure, and retaining at least a part of the first dielectric layer, the retained first dielectric layer covering the side wall of the first sub-trench above the first position; Performing a lateral etching process on the first sub-trench between the first position and the second position to form first grooves on both sides of the first sub-trench, the first grooves being located in the wall-like structure or at least partially located in the active pillar, and the openings of the first grooves facing the first sub-trench; Removing the remaining first dielectric layer above the first position in the first sub-trench; Filling a first conductive material in the space between the first position and the second position in the first sub-trench and in the first grooves, and performing an etching process on the first conductive material to form bit line contact portions, the bit line contact portions being at least partially located in the first grooves.

[0015] In some embodiments, after forming the first grooves and before forming the embedded bit line, the method further includes: Forming a doped layer in the active pillar or the wall-like structure, the doped layer surrounding the inner walls of the first grooves.

[0016] In some embodiments, forming the doped layer in the active pillar or the wall-like structure includes: Dope a first conductive material with a dopant; Before performing an etching process on the first conductive material to form bit line contacts, perform an annealing process on the first conductive material doped with the dopant, and part of the dopant diffuses into the active pillars or the wall-like structures to form a doped layer.

[0017] In some embodiments, after forming the buried bit lines, the method further includes: Form a plurality of word lines above the buried bit lines, the plurality of word lines are arranged along a second direction, each word line extends along a first direction, and each word line covers a part of the sidewalls of each active pillar in an active pillar row.

[0018] In the embodiments of the present disclosure, buried bit lines are formed only between two adjacent active pillar columns in an active pillar group. Two adjacent active pillar columns arranged adjacent to each other in the first direction in an active pillar group share a buried bit line, and no buried bit lines are formed between adjacent active pillar groups. In this way, the distance between adjacent buried bit lines is increased, thereby effectively reducing the coupling effect between the buried bit lines, reducing the contact resistance of the buried bit lines at the same time, and improving the performance of the semiconductor structure.

[0019] Details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the specification and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1 A top view schematic diagram of a semiconductor structure provided by some embodiments of the present disclosure; Figure 2 For some embodiments of the present disclosure along Figure 1 The cross-sectional structure schematic diagrams intercepted along line A1A2 and line B1B2 in; Figure 3 For some embodiments of the present disclosure along Figure 1 The cross-sectional structure schematic diagrams intercepted along line C1C2 and line D1D2 in; Figure 4 For some other embodiments of the present disclosure along Figure 1 The cross-sectional structure schematic diagrams intercepted along line A1A2 and line B1B2 in; Figure 5 For some other embodiments of the present disclosure along Figure 1Schematic cross-sectional structure diagram intercepted by line C1C2 and line D1D2 in Figure 6 For some other embodiments of the present disclosure along Figure 1 Schematic cross-sectional structure diagram intercepted by line A1A2 and line B1B2 in Figure 7 For some other embodiments of the present disclosure along Figure 1 Schematic cross-sectional structure diagram intercepted by line C1C2 and line D1D2 in Figure 8 Top view schematic diagram of a semiconductor structure provided by some other embodiments of the present disclosure; Figure 9 Top view schematic diagram of a semiconductor structure provided by some other embodiments of the present disclosure; Figure 10 Top view schematic diagram of a semiconductor structure provided by some further embodiments of the present disclosure; Figure 11 Top view schematic diagram of a semiconductor structure provided by some other embodiments of the present disclosure; Figure 12 Top view schematic diagram of a semiconductor structure provided by some other further embodiments of the present disclosure; Figure 13 Flow chart of a manufacturing method of a semiconductor structure provided by some embodiments of the present disclosure; Figure 14 For a semiconductor structure provided by some embodiments of the present disclosure during manufacturing along Figure 1 Schematic cross-sectional structure intercepted by line C1C2 in Figure 1 ; Figure 15 Top view schematic during the manufacturing process of a semiconductor structure provided by some embodiments of the present disclosure Figure 2 ; Figure 16 For a semiconductor structure provided by some embodiments of the present disclosure during manufacturing along Figure 1 Schematic cross-sectional structure intercepted by line C1C2 in Figure 3 ; Figure 17 For a semiconductor structure provided by some embodiments of the present disclosure during manufacturing along Figure 1 Schematic cross-sectional structure intercepted by line C1C2 in Figure 4 ; Figure 18 For a semiconductor structure provided by some embodiments of the present disclosure during manufacturing along Figure 1 Schematic cross-sectional structure intercepted by line C1C2 in Figure 5 ; Figure 19 For a semiconductor structure provided by some embodiments of the present disclosure during manufacturing along Figure 1Schematic of the cross-sectional structure intercepted by line C1C2 in Figure 6 ; Figure 20 Schematic of the cross-sectional structure intercepted by line C1C2 along the semiconductor structure provided by some embodiments of the present disclosure during the manufacturing process Figure 1 in Figure 7 ; Figure 21 Schematic of the cross-sectional structure intercepted by line C1C2 along the semiconductor structure provided by some embodiments of the present disclosure during the manufacturing process Figure 1 in Figure 8 ; Figure 22 Schematic of the cross-sectional structure intercepted by line C1C2 along the semiconductor structure provided by some embodiments of the present disclosure during the manufacturing process Figure 1 in Figure 9 ; Figure 23 Schematic of the cross-sectional structure intercepted by line C1C2 along the semiconductor structure provided by some embodiments of the present disclosure during the manufacturing process Figure 1 in Figure 10 ; Figure 24 Schematic of the cross-sectional structure intercepted by line C1C2 along the semiconductor structure provided by some embodiments of the present disclosure during the manufacturing process Figure 1 in Figure 10 One; Figure 25 Schematic of the cross-sectional structure intercepted by line C1C2 along the semiconductor structure provided by some embodiments of the present disclosure during the manufacturing process Figure 1 in Figure 10 Two; Figure 26 Schematic of the cross-sectional structure intercepted by line C1C2 along the semiconductor structure provided by some embodiments of the present disclosure during the manufacturing process Figure 1 in Figure 10 Three; Figure 27 Schematic of the cross-sectional structure intercepted by line C1C2 along the semiconductor structure provided by some embodiments of the present disclosure during the manufacturing process Figure 1 in Figure 10 Four; Figure 28 Top view schematic of the semiconductor structure provided by some embodiments of the present disclosure during the manufacturing process Figure 10 Five; Figure 29 Schematic of the cross-sectional structure intercepted by line A1A2 and line B1B2 along the semiconductor structure provided by some embodiments of the present disclosure during the manufacturing process Figure 1 in Figure 10 Six; Figure 30The cross-sectional structure diagrams of the semiconductor structures provided by some embodiments of the present disclosure during the manufacturing process, taken along the Figure 1 lines C1C2 and D1D2 in Figure 10 Seven; Figure 31 The top view diagrams of the semiconductor structures provided by some other embodiments of the present disclosure during the manufacturing process Figure 10 Eight; Figure 32 The cross-sectional structure diagrams of the semiconductor structures provided by some other embodiments of the present disclosure during the manufacturing process, taken along the Figure 1 lines A1A2 and B1B2 in Figure 10 Nine; Figure 33 The cross-sectional structure diagrams of the semiconductor structures provided by some other embodiments of the present disclosure during the manufacturing process, taken along the Figure 1 lines C1C2 and D1D2 in Figure 2 Ten; Figure 34 The cross-sectional structure diagrams of the semiconductor structures provided by some other embodiments of the present disclosure during the manufacturing process, taken along the Figure 1 lines A1A2 and B1B2 in Figure 2 Eleven; Figure 35 The cross-sectional structure diagrams of the semiconductor structures provided by some other embodiments of the present disclosure during the manufacturing process, taken along the Figure 1 lines C1C2 and D1D2 in Figure 2 Twelve; Figure 36 The cross-sectional structure diagrams of the semiconductor structures provided by some other embodiments of the present disclosure during the manufacturing process, taken along the Figure 1 lines A1A2 and B1B2 in Figure 2 Thirteen; Figure 37 The cross-sectional structure diagrams of the semiconductor structures provided by some other embodiments of the present disclosure during the manufacturing process, taken along the Figure 1 lines C1C2 and D1D2 in Figure 2 Fourteen; Figure 38 The cross-sectional structure diagrams of the semiconductor structures provided by some other embodiments of the present disclosure during the manufacturing process, taken along the Figure 1 lines A1A2 and B1B2 in Figure 2 Fifteen; Figure 39 The cross-sectional structure diagrams of the semiconductor structures provided by some other embodiments of the present disclosure during the manufacturing process, taken along the Figure 1 lines C1C2 and D1D2 in Figure 2 Sixteen; Figure 40The cross-sectional structure diagrams taken along line A1A2 and line B1B2 in Figure 1 during the manufacturing process of the semiconductor structure provided by some other embodiments of the present disclosure Figure 2 Seventeen; Figure 41 The cross-sectional structure diagrams taken along line C1C2 and line D1D2 in Figure 1 during the manufacturing process of the semiconductor structure provided by some other embodiments of the present disclosure Figure 2 Eighteen. Detailed implementation manners

[0022] The exemplary implementation manners disclosed in the present disclosure will be described in more detail with reference to the accompanying drawings. Although the exemplary implementation manners of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific implementation manners set forth herein. On the contrary, these implementation manners are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0023] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known to the art are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0024] In the drawings, for clarity, the dimensions of layers, regions, elements and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0025] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer or portion discussed below may be referred to as the second element, component, region, layer or portion. And when discussing the second element, component, region, layer or portion, it does not imply that a first element, component, region, layer or portion necessarily exists in the present disclosure.

[0026] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0027] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0028] As semiconductor structures continue to develop towards miniaturization and high integration, the density of bit lines increases and their size shrinks, leading to a series of problems. For example, due to the reduction in the distance between adjacent bit lines, the coupling effect between bit lines increases, resulting in an increase in signal crosstalk problems between adjacent bit lines; and due to the miniaturization of the sizes of bit lines and active pillars, problems such as a decrease in the contact area between bit lines and active pillars and an increase in contact resistance occur.

[0029] Based on this, the technical solutions of the embodiments of the present disclosure are proposed. In the embodiments of the present disclosure, buried bit lines are formed only between two adjacent active pillar columns in an active pillar group. Two adjacent active pillar columns arranged adjacent to each other in a first direction share a buried bit line, and no buried bit line is formed between adjacent active pillar groups. In this way, the distance between adjacent buried bit lines is increased, thereby effectively reducing the coupling effect between buried bit lines, while reducing the contact resistance of buried bit lines and improving the performance of semiconductor structures.

[0030] To make the above objects, features, and advantages of the present disclosure more obvious and understandable, the following detailed description of the specific embodiments of the present disclosure will be made in conjunction with the accompanying drawings. When detailing the embodiments of the present disclosure, for ease of explanation, the schematic diagrams will be enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples and should not limit the protection scope of the present disclosure herein.

[0031] The following further detailed description of the semiconductor structure provided by the embodiments of the present disclosure will be made in conjunction with the accompanying drawings.

[0032] As Figures 1 to 12 shown, the semiconductor structure provided by the embodiments of the present disclosure includes: a substrate 10, and a plurality of active pillars 11 located on the substrate 10. The plurality of active pillars 11 are arranged into a plurality of active pillar rows 111 extending in a first direction and a plurality of active pillar columns 112 extending in a second direction; wherein, the plurality of active pillar columns 112 include a plurality of active pillar groups 20 arranged at intervals in the first direction, and each active pillar group 20 includes two active pillar columns 112 arranged adjacent to each other in the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate 10; A plurality of buried bit lines 17, located between two adjacent active pillar columns 112 in the active pillar group 20, and electrically connected to each active pillar 11 in the two adjacent active pillar columns 112 adjacent thereto, and the two adjacent buried bit lines 17 are separated by two adjacent active pillar columns 112 belonging to different active pillar groups 20 in two adjacent active pillar groups 20.

[0033] In actual operation, the semiconductor structure provided by the embodiments of the present disclosure may be a dynamic random access memory (DRAM), such as a DRAM with vertical transistors. However, it is not limited thereto, and the semiconductor structure may also be any structure with vertical transistors.

[0034] In actual operation, the substrate 10 can be a semiconductor substrate and can include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate 10 is a silicon substrate, and the silicon substrate can be doped or undoped.

[0035] As Figure 1 and Figure 2 shown, in some embodiments, the semiconductor structure further includes a plurality of first trenches T1 and a plurality of second trenches T2. The plurality of first trenches T1 extend in a second direction in the substrate 10 and are arranged at intervals in a first direction. The plurality of second trenches T2 extend in the first direction in the substrate 10 and are arranged at intervals in the second direction. The first direction and the second direction are obliquely intersecting or perpendicular. The plurality of first trenches T1 and the plurality of second trenches T2 intersect with each other to define a plurality of active pillar rows 111 and a plurality of active pillar columns 112 in the substrate 10. Among them, the plurality of active pillar rows 111 are arranged in the second direction, and each active pillar row 111 includes a plurality of active pillars 11 arranged at intervals in the first direction. The plurality of active pillar columns 112 are arranged at intervals in the first direction, and each active pillar column 112 includes a plurality of active pillars 11 arranged in the second direction.

[0036] In some embodiments, the plurality of first trenches T1 include first sub-trenches T11 and second sub-trenches T12 arranged alternately in the first direction. The first sub-trenches T11 are located between two adjacent active pillar columns 112 in each active pillar group 20, and the second sub-trenches T12 are located between two adjacent active pillar groups 20.

[0037] As Figures 1 to 3 shown, in some embodiments, the buried bit line 17 is located below the first sub-trench T11 and extends in the second direction in the first sub-trench T11. Adjacent buried bit lines are separated by two active pillar columns 112 belonging to different active pillar groups 20 and the second sub-trench T12 located between the two active pillar columns 112.

[0038] In the embodiments of the present disclosure, the buried bit line 17 is only provided between two adjacent active pillar columns 112 in the active pillar group 20. Two adjacent active pillar columns 112 arranged adjacent to each other in the first direction in an active pillar group 20 share one buried bit line 17, and no buried bit line 17 is formed between adjacent active pillar groups 20. In this way, the distance between adjacent buried bit lines 17 is increased, the coupling effect between the buried bit lines 17 can be effectively reduced, and further the signal crosstalk between the plurality of buried bit lines 17 is reduced. At the same time, the contact resistance of the buried bit line 17 is reduced, and the performance of the semiconductor structure is improved.

[0039] The embedded bit line 17 can be a single-layer structure or a multi-layer structure. In some embodiments, the embedded bit line 17 includes a main body portion 172, and a barrier layer 171 covering the outer sidewall and the bottom surface of the main body portion 172, and the main body portion 172 is located within the space defined by the barrier layer 171.

[0040] In actual operation, the material of the barrier layer 171 can be a material that can conduct electricity and block metal diffusion, including but not limited to one or a combination of titanium nitride and tantalum nitride, for blocking the diffusion of the material of the main body portion 172 into the substrate 10 and the active pillar 11; the material of the main body portion 172 includes one or more of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum, such as tungsten.

[0041] As Figures 2 to 3 shown, in some embodiments, the semiconductor structure further includes: a first isolation structure 191, located below the embedded bit line 17 and extending along a second direction, and the embedded bit line 17 covers the first isolation structure 191; a second isolation structure 192, located between two adjacent active pillar groups 20 and extending along the second direction, and the upper surface of the second isolation structure 192 is higher than the upper surface of the embedded bit line 17.

[0042] Specifically, the first isolation structure 191 is located at the bottom of the first sub-groove T11, for electrically isolating the embedded bit line 17 and the substrate 10 to avoid leakage or short circuit; the second isolation structure 192 is located within the second sub-groove T12, and the upper surface is higher than the upper surface of the embedded bit line 17, for spacing adjacent active pillar groups 20 and adjacent embedded bit lines 17, and further reducing the coupling effect between the embedded bit lines 17.

[0043] In actual operation, both the first isolation structure 191 and the second isolation structure 192 include a first dielectric layer 12 and a first filling layer 13. The first dielectric layer 12 of the first isolation structure 191 covers a part of the sidewall and the bottom surface of the first sub-groove T11, the first dielectric layer 12 of the second isolation structure 192 covers a part of the sidewall and the bottom surface of the second sub-groove T12, and the first filling layer 13 is located within the space defined by the first dielectric layer 12.

[0044] In actual operation, the material of the first dielectric layer 12 includes but not limited to nitrides, such as silicon nitride; the material of the first filling layer 13 includes but not limited to oxides, such as silicon oxide.

[0045] In some embodiments, the semiconductor structure further includes a second filling layer 18, located within the first sub-groove T11, and the second filling layer 18 extends along the second direction and covers the embedded bit line 17.

[0046] In actual operation, the second filling layer 18 can be a single-layer structure or a multi-layer structure. The materials of the second filling layer 18 include one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), etc., for example, silicon oxide.

[0047] In some embodiments, the semiconductor structure further includes: a plurality of bit-line contact portions 15, which are respectively disposed on both sides of the buried bit-line 17 along a first direction and are electrically connected to the buried bit-line 17. At least a part of the bit-line contact portion 15 is laterally embedded in the active pillars 11 located on both sides of the buried bit-line 17 along the first direction. In this way, the buried bit-line 17 is electrically connected to the active pillars 11 through the bit-line contact portions 15. Between the buried bit-line 17 and the bit-line contact portions 15, there is a smaller contact resistance than between the buried bit-line 17 and the active pillars 11, thereby further reducing the contact resistance of the buried bit-line 17.

[0048] In actual operation, the materials of the bit-line contact portions 15 include but are not limited to polysilicon, and the bit-line contact portions 15 can be doped or undoped. In some specific embodiments, the bit-line contact portions 15 are doped with a dopant, and the dopant can be one or more of elements such as boron, phosphorus, arsenic, etc.

[0049] As Figures 2 to 5 shown, in some embodiments, the semiconductor structure further includes: a plurality of connection portions 21, which are located between the lower parts of two adjacent active pillars 11 arranged along a second direction, and the lower parts of the plurality of active pillars 11 arranged along the second direction are sequentially connected through the connection portions 21.

[0050] Among them, the bit-line contact portions 15 can be completely embedded in the active pillars 11 and the connection portions 21. For example, the side walls of the bit-line contact portions 15 can be substantially flush with the side walls of the active pillars 11 and the connection portions 21, or slightly indented inward relative to the side walls of the active pillars 11 and the connection portions 21; but not limited thereto, the side walls of the bit-line contact portions 15 can protrude slightly outward relative to the side walls of the active pillars 11 and the connection portions 21; the upper surface of the buried bit-line 17 is flush with or higher than the upper surface of the bit-line contact portions 15 to increase the scene applicability.

[0051] In actual operation, the depth of the second trench T2 can be less than the depth of the first trench T1, and the bottom surface of the second trench T2 can be higher than the upper surface of the buried bit-line 17. The part of the substrate 10 located below the second trench T2 is not etched to form the connection portion 21. The lower parts of the plurality of active pillars 11 arranged along the second direction and the connection portion 21 located between the lower parts of two adjacent active pillars 11 form a structure that continuously extends along the second direction.

[0052] In some embodiments, the bit line contact portion 15 is located within the plurality of active pillars 11 and the plurality of connection portions 21 and extends continuously in the second direction. The bit line contact portion 15 is a continuous structure extending in the second direction. There is a large contact area between the buried bit line 17 and the bit line contact portion 15, and between the bit line contact portion 15 and the active pillars 11 and the connection portions 21, further reducing the contact resistance between the bit line contact portion 15 and the active pillars 11, and the contact resistance between the buried bit line 17 and the bit line contact portion 15.

[0053] In some embodiments, the semiconductor structure further includes: a doped layer 16, at least a part of the doped layer 16 is located within the active pillar 11 and at least surrounds the contact surface between the bit line contact portion 15 and the active pillar 11. The presence of the doped layer 16 reduces the contact resistance between the bit line contact portion 15 and the active pillar 11, further improving the performance of the semiconductor structure.

[0054] In some embodiments, when the lower portions of the plurality of active pillars 11 arranged in the second direction are sequentially connected by the connection portions 21, the doped layer 16 is located within the plurality of active pillars 11 and the plurality of connection portions 21 and extends continuously in the second direction, and the doped layer 16 surrounds the contact surfaces between the bit line contact portion 15 and the active pillars 11 and the connection portions 21.

[0055] In actual operation, the dopant in the doped layer 16 can be one or more of elements such as boron, phosphorus, arsenic, etc., and the dopant in the doped layer 16 can be the same as the dopant in the bit line contact portion 15. In some specific embodiments, the dopant in the doped layer 16 is phosphorus, and the doping concentration of phosphorus is greater than 1*E 20 atom / cm 3 , for example, 2*E 20 atom / cm 3 , 3*E 20 atom / cm 3 , 5*E 20 atom / cm 3 , 1*E 21 atom / cm 3 and so on.

[0056] As Figures 1 to 3 shown, in some embodiments, the semiconductor structure further includes: a plurality of word lines 23 located above the buried bit line 17, the plurality of word lines 23 are arranged in the second direction, and each word line 23 extends in the first direction, and each word line 23 covers a part of the sidewalls of each active pillar 11 in an active pillar row 111. Further, each word line 23 extends in the first direction and surrounds each active pillar 11 in an active pillar row 111. In this way, it helps to increase the driving ability of the word line 23 for the active pillar row 111.

[0057] In some embodiments, the semiconductor structure further includes: a third isolation structure 193, filling the lower part of the second trench T2 and extending along a first direction, the third isolation structure 193 covering the connection portion 21, a part of the second filling layer 18, and a part of the second isolation structure 192 along the first direction, the word line 23 being located above the third isolation structure 193 and covering the third isolation structure 193, the third isolation structure 193 being configured to electrically isolate the word line 23 from the connection portion 21 and the word line 23 from the buried bit line 17.

[0058] However, it is not limited thereto. As Figures 4 to 5 shown, the third isolation structure 193 fills the lower part of a part of the second trench T2, the third isolation structure 193 is located between two adjacent first trenches T1 along the first direction and covers the connection portion 21, and the word line 23 covers the third isolation structure 193, a part of the second filling layer 18, and a part of the second isolation structure 192.

[0059] In actual operation, the third isolation structure 193 can be a single-layer structure or a multi-layer structure, and the material of the third isolation structure 193 includes one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), etc., such as silicon nitride.

[0060] As Figure 1 shown, in some embodiments, a second groove S2 is provided between two adjacent active pillars 11 of the active pillar row 111. In actual operation, the second groove S2 is formed by etching a part of the second filling layer 18 and a part of the second isolation structure 192, the second groove S2 communicates with the second trench T2, and the word line 23 extends along the first direction in the second groove S2 and the second trench T2 and surrounds a plurality of active pillars 11.

[0061] In some embodiments, the semiconductor structure further includes a gate dielectric layer 22, and the gate dielectric layer 22 is at least located between the word line 23 and the active pillar 11. In actual operation, the material of the gate dielectric layer 22 includes but is not limited to oxides, such as silicon oxide, and the gate dielectric layer 22 can be formed by performing an oxidation process on the sidewalls of the active pillars 11.

[0062] In some embodiments, the semiconductor structure further includes a fourth isolation structure 194, the fourth isolation structure 194 covering the word line 23 and filling the gaps between adjacent word lines 23, and the upper surface of the fourth isolation structure 194 being flush with the upper surface of the active pillar 11.

[0063] In actual operation, the fourth isolation structure 194 may include a third filling layer 24 and a fourth filling layer 25. The third filling layer 24 extends along a first direction in the second groove S2 and the second trench T2 and covers the upper surface of the word line 23, and the upper surface of the third filling layer 24 is flush with the upper surface of the active pillar 11. The fourth filling layer 25 extends along the first direction in the second trench T2 and extends downward from the upper surface of the third filling layer 24 to penetrate the word line 23, and is used to space adjacent word lines 23 and adjacent third filling layers 24.

[0064] In actual operation, the materials of the third filling layer 24 and the fourth filling layer 25 may be the same or different, and the materials of the third filling layer 24 and the fourth filling layer 25 include, but are not limited to, silicon nitride.

[0065] As Figures 2 to 3 shown, the semiconductor structure further includes: an insulating structure 26, located above the active pillar 11 and the fourth isolation structure 194, the insulating structure 26 has a plurality of discrete second openings K2 therein, and the second openings K2 expose the upper surface of the active pillar 11; a contact plug 27, located in the second opening K2 and electrically connected to the upper surface of the active pillar 11. In subsequent processes, a capacitor structure electrically connected thereto may be formed on the contact plug 27, and the capacitor structure is used to store data.

[0066] In actual operation, the insulating structure 26 may include a plurality of first sub-layers (not labeled) extending along the first direction and a plurality of second sub-layers (not labeled) extending along the second direction, and the plurality of first sub-layers and the plurality of second sub-layers cross each other to enclose a plurality of second openings K2.

[0067] In actual operation, the material of the insulating structure 26 includes, but is not limited to, nitrides, such as silicon nitride; the contact plug 27 may be a single-layer or multi-layer structure, and the materials of the word line 23 and the contact plug 27 include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy.

[0068] Figures 2 to 5 It is shown that the depth of the second trench T2 is less than the depth of the first trench T1, and the bottom surface of the second trench T2 is higher than the upper surface of the buried bit line 17. The lower portions of the plurality of active pillars 11 arranged along the second direction are sequentially connected through a connecting portion 21, and the bit line contact portion 15 and the doping layer 16 are located in the plurality of active pillars 11 and the plurality of connecting portions 21 and continuously extend along the second direction.

[0069] But not limited thereto, as Figures 6 to 7As shown, in some other embodiments of the present disclosure, a plurality of active pillars 11 in each active pillar column 112 are arranged at intervals in the second direction, a plurality of bit line contact portions 15 are arranged at intervals in the second direction and are correspondingly disposed in the plurality of active pillars 11 of the active pillar column 112, and a doped layer 16 is located in the active pillar 11 and surrounds the contact surface between the active pillar 11 and the bit line contact portion 15.

[0070] Specifically, the bottom surface of the second trench T2 is lower than the bottom surface of the buried bit line 17, and a third isolation structure 193 fills a lower part of the second trench T2. In the second direction, the lower parts of adjacent active pillars 11 are separated by the third isolation structure 193.

[0071] Among them, the bit line contact portion 15 can be completely embedded in the active pillar 11. For example, the side wall of the bit line contact portion 15 can be substantially flush with the side wall of the active pillar 11, or slightly indented inward relative to the side wall of the active pillar 11; however, this is not limited thereto, and the side wall of the bit line contact portion 15 can protrude slightly outward relative to the side wall of the active pillar 11 to increase the applicability of the scenario.

[0072] As Figures 6 to 7 shown, in some embodiments, the third isolation structure 193 fills a lower part of the second trench T2. The third isolation structure 193 is located between two first trenches T1 adjacent in the first direction and covers a part of the substrate 10, and the word line 23 covers the third isolation structure 193, a part of the second filling layer 18, and a part of the second isolation structure 192.

[0073] As Figure 8 shown, in some embodiments, the projection of the buried bit line 17 in the second direction can overlap with the projection of the active pillar 11 in the second direction. In this way, when the plurality of active pillars 11 in each active pillar column 112 are arranged at intervals in the second direction, the contact area between the buried bit line 17 and the active pillar 11 or the bit line contact portion 15 can be increased, and the contact resistance of the buried bit line 17 can be further reduced.

[0074] In actual operation, this can be achieved by increasing the width of the first trench T1 when forming the first trench T1, so that the first trench T1 exposes the ends of the active pillars 11 on both sides thereof. In this way, the area of the side wall of the active pillar 11 exposed by the first trench T1 is larger. For example, in addition to exposing the side wall of the active pillar 11 in the first direction, the first trench T1 can also expose a part of the side wall of the active pillar 11 in the second direction, so that the finally formed buried bit line 17 can contact not only the side wall of the active pillar 11 or the bit line contact portion 15 in the first direction, but also a part of the side wall of the active pillar 11 or the bit line contact portion 15 in the second direction.

[0075] As Figures 8 to 11As shown, in some embodiments, the positive projection of the active pillar 11 on the surface of the substrate 10 is symmetrically arranged along the first direction and the second direction. For example, the shape of the positive projection of the active pillar 11 on the surface of the substrate 10 can be a shape with arc edges such as a circle or an ellipse, or a polygon with straight edges such as a quadrilateral, a pentagon, or a hexagon, or a polygon composed of straight edges and arc edges.

[0076] However, it is not limited thereto. As Figure 12 shown, in some embodiments, the dimension of one end of the active pillar 11 close to the buried bit line 17 in the second direction is larger than the dimension of the other end of the active pillar 11 far from the buried bit line 17 in the second direction in the first direction. For example, the shape of the positive projection of the active pillar 11 on the surface of the substrate 10 can be a regular or irregular figure such as a triangle or a T shape. By increasing the dimension of one end of the active pillar 11 close to the buried bit line 17 in the second direction, the contact area between the bit line contact portion 15 and the active pillar 11 is increased, and at the same time, the dimension of the bit line contact portion 15 and the contact area between the buried bit line 17 and the bit line contact portion 15 are increased. Thus, the contact resistance between the bit line contact portion 15 and the active pillar 11 and the contact resistance between the buried bit line 17 and the bit line contact portion 15 are further reduced.

[0077] As Figures 9 to 12 shown, in some embodiments, the projection of the buried bit line 17 in the second direction can partially overlap with the projection of the active pillar 11 in the second direction, achieving the same technical effect as above, which will not be elaborated herein.

[0078] The embodiments of the present disclosure also provide a manufacturing method of a semiconductor structure. As Figure 13 shown, the manufacturing method includes: Step S101: Provide a substrate; Step S102: Form a plurality of active pillars on the substrate; form a plurality of buried bit lines; wherein, the plurality of active pillars are arranged into a plurality of active pillar rows extending in the first direction and a plurality of active pillar columns extending in the second direction; the plurality of active pillar columns include a plurality of active pillar groups arranged at intervals in the first direction, and each active pillar group includes two adjacent active pillar columns arranged adjacent to each other in the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate; the buried bit lines are located between two adjacent active pillar columns in the active pillar group and are electrically connected to each active pillar in the two adjacent active pillar columns, and two adjacent buried bit lines are separated by two adjacent active pillar columns belonging to different active pillar groups in the two adjacent active pillar groups.

[0079] The following further elaborates on the manufacturing method of the semiconductor structure provided by the embodiments of the present application in conjunction with the accompanying drawings. Among them, Figure 15 ForFigure 16 A top view schematic diagram of the semiconductor structure shown Figure 28 is Figures 29 to 30 a top view schematic diagram of the semiconductor structure shown; Figure 31 is Figures 32 to 33 and Figures 38 to 39 a top view schematic diagram of the semiconductor structure shown.

[0080] First, perform step S101. As shown in Figure 14 , provide a substrate 10.

[0081] The material of the substrate 10 is as described above and will not be elaborated here.

[0082] Next, perform step S102. As shown in Figures 15 to 16 , Figure 26 and Figures 28 to 30 , form a plurality of active pillars 11 on the substrate 10 and form a plurality of buried bit lines 17; wherein, the plurality of active pillars 11 are arranged into a plurality of active pillar rows 111 extending in a first direction and a plurality of active pillar columns 112 extending in a second direction; the plurality of active pillar columns 112 include a plurality of active pillar groups 20 arranged at intervals in the first direction, and each active pillar group 20 includes two adjacent active pillar columns 112 arranged in the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate 10; the buried bit lines 17 are located between two adjacent active pillar columns 112 in the active pillar group 20 and are electrically connected to each active pillar 11 in the two adjacent active pillar columns 112, and two adjacent buried bit lines 17 are separated by two adjacent active pillar columns 112 belonging to different active pillar groups 20 in two adjacent active pillar groups 20.

[0083] Referring again to Figures 15 to 16 and Figures 28 to 30 , in some embodiments, forming a plurality of active pillars 11 on the substrate 10 includes: etching the substrate 10 to form a plurality of first trenches T1 extending in the second direction on the substrate 10, and the first trenches T1 define the substrate 10 into a plurality of wall-like structures 11'; the plurality of first trenches T1 include first sub-trenches T11 and second sub-trenches T12 alternately arranged in sequence in the first direction (as shown in Figures 15 to 16 ); at least etching the wall-like structure 11' to form a plurality of second trenches T2 extending in the first direction in the substrate 10, and the first trenches T1 and the second trenches T2 intersect with each other to define a plurality of discrete active pillars 11 in the substrate 10 (as shown in Figures 28 to 30 ).

[0084] Referring again to Figure 26 , in some embodiments, forming a plurality of buried bit lines 17 includes: After forming the first trench T1 and before forming the second trench T2, an embedded bit line 17 is formed in the first sub-trench T11, and the second sub-trench T12 is located between two adjacent embedded bit lines 17.

[0085] Specifically, as Figure 15 and Figure 16 shown, a plurality of first trenches T1 are arranged along a first direction and extend along a second direction. The first trench T1 is located between two adjacent wall-like structures 11', and the first direction and the second direction can be perpendicular or obliquely intersecting.

[0086] As Figure 26 shown, in some embodiments, the embedded bit line 17 is located at the lower part of the first sub-trench T11 and extends along the second direction in the first sub-trench T11. Adjacent embedded bit lines 17 are separated by two wall-like structures 11' and a second sub-trench T12 located between the two wall-like structures 11', and the embedded bit line 17 is electrically connected to the two adjacent wall-like structures 11'.

[0087] In actual operation, the embedded bit line 17 can be a single-layer structure or a multi-layer structure. In some embodiments, the embedded bit line 17 includes a main body portion 172 and a barrier layer 171 covering the outer sidewall and bottom surface of the main body portion 172, and the main body portion 172 is located within the space defined by the barrier layer 171.

[0088] The materials of the main body portion 172 and the barrier layer 171 are as described above and will not be elaborated here.

[0089] As Figures 17 to 25 shown, in some embodiments, before forming the embedded bit line 17 in the first sub-trench T11, the method further includes: forming bit line contact portions 15 along the first direction on both sides of the first sub-trench T11, and at least part of the bit line contact portions 15 are laterally embedded in the wall-like structures 11' on both sides of the first sub-trench T11. In this way, the embedded bit line 17 can be electrically connected to the subsequent formed active pillar 11 through the bit line contact portions 15. The contact resistance between the embedded bit line 17 and the bit line contact portions 15 is smaller than that between the embedded bit line 17 and the active pillar 11, thereby reducing the contact resistance of the embedded bit line 17.

[0090] Specifically, forming the bit line contact portions 15 includes: forming a first dielectric layer 12 covering the inner walls of the first sub-trench T11 and the second sub-trench T12, and a first filling layer 13 covering the first dielectric layer 12 and filling the first sub-trench T11 and the second sub-trench T12 (as Figure 17 ); Remove a portion of the first filling layer 13 within the first sub-groove T11 to the first position P1 to expose the first dielectric layer 12 above the first position P1 (as Figure 18 ) Form a second dielectric layer 14, the second dielectric layer 14 covering the sidewalls of the exposed first dielectric layer 12 and the upper surface of the remaining first filling layer 13 (as Figure 19 ) Remove the second dielectric layer 14 covering the upper surface of the first filling layer 13 and retain the second dielectric layer 14 covering the sidewalls of the first dielectric layer 12 (as Figure 20 ) Remove a portion of the first filling layer 13 within the first sub-groove T11 to the second position P2 to expose the first dielectric layer 12 between the first position P1 and the second position P2 (as Figure 21 ) Remove the first dielectric layer 12 between the first position P1 and the second position P2 to expose a portion of the wall-like structure 11', and retain at least a portion of the first dielectric layer 12, the retained first dielectric layer 12 covering the sidewalls of the first sub-groove T11 above the first position P1 (as Figure 22 ) Perform a lateral etching process on the first sub-groove T11 between the first position P1 and the second position P2 to form first grooves S1 on both sides of the first sub-groove T11, the first grooves S1 being within the wall-like structure 11' and the openings of the first grooves S1 facing the first sub-groove T11 (as Figure 23 ) Remove the remaining first dielectric layer 12 above the first position P1 within the first sub-groove T11; fill the space within the first sub-groove T11 between the first position P1 and the second position P2 and within the first grooves S1 with a first conductive material 15' (as Figure 24 ) Perform an etching process on the first conductive material 15' to form a bit line contact portion 15, the bit line contact portion 15 being at least partially within the first grooves S1 (as Figure 25 )

[0091] In actual operation, the material of the first dielectric layer 12 includes but is not limited to nitrides, such as silicon nitride; the material of the first filling layer 13 includes but is not limited to oxides, such as silicon oxide.

[0092] In actual operation, the material of the second dielectric layer 14 may be the same as that of the first dielectric layer 12. It can be understood that since the side wall of the first sub-groove T11 above the first position P1 is covered by both the first dielectric layer 12 and the second dielectric layer 14, at least a part of the first dielectric layer 12 above the first position P1 will be retained after removing the first dielectric layer 12 between the first position P1 and the second position P2.

[0093] In some embodiments, the thickness of the second dielectric layer 14 may be set to be greater than that of the first dielectric layer 12. In this way, after removing the first dielectric layer 12 between the first position P1 and the second position P2, part of the second dielectric layer 14 may still be retained to improve the protection effect on the side wall of the first sub-groove T11 above the first position P1.

[0094] In some other embodiments of the present disclosure, the materials of the first dielectric layer 12 and the second dielectric layer 14 may also be different. For example, the material of the first dielectric layer 12 may include nitrides (such as silicon nitride), and the material of the second dielectric layer 14 may include oxides (such as silicon oxide). During the process of removing the first dielectric layer 12 between the first position P1 and the second position P2, the first dielectric layer 12 and the second dielectric layer 14 may have a large etching selectivity to reduce the consumption of the second dielectric layer 14 and further improve the protection effect on the side wall of the first sub-groove T11 above the first position P1.

[0095] In some embodiments, the first groove S1 continuously extends along the second direction within the wall-like structure 11'.

[0096] Refer to again Figure 24 , in actual operation, the remaining first dielectric layer 12 in the first sub-groove T11 at the first position P1 may be removed before or after forming the first conductive material 15'. Among them, when there is a residue of the second dielectric layer 14 after removing the first dielectric layer 12 between the first position P1 and the second position P2, the method further includes: removing the remaining second dielectric layer 14 in the first sub-groove T11 above the first position P1.

[0097] In actual operation, a first initial conductive material (not shown) may be filled in the space above the second position P2 of the first sub-groove T11 and in the first groove S1, and then a back-etching process is performed on the first initial conductive material (not shown) to form the first conductive material 15' between the first position P1 and the second position P2.

[0098] Continue to refer to Figure 24, in some embodiments, after forming the first groove S1 and before forming the buried bit line 17, the method further includes: forming a doped layer 16 within the wall-like structure 11'. The doped layer 16 extends continuously within the wall-like structure 11' in a second direction and surrounds the inner wall of the first groove S1. The presence of the doped layer 16 reduces the contact resistance between the bit line contact portion 15 and the active pillar 11, further improving the performance of the semiconductor structure.

[0099] In some embodiments, the dopant in the doped layer 16 can be one or more of elements such as boron, phosphorus, arsenic, etc., and the dopant in the doped layer 16 can be the same as the dopant in the bit line contact portion 15. In some specific embodiments, the dopant in the doped layer 16 is phosphorus, and the doping concentration of phosphorus is greater than 1*E 20 atom / cm 3 , for example 2*E 20 atom / cm 3 、3*E 20 atom / cm 3 、5*E 20 atom / cm 3 、1*E 21 atom / cm 3 etc.

[0100] In some embodiments, forming the doped layer 16 within the wall-like structure 11' includes: doping the first conductive material 15' with a dopant; before performing an etching process on the first conductive material 15' to form the bit line contact portion 15, performing an annealing process on the doped first conductive material 15', and part of the dopant diffuses into the wall-like structure 11' to form the doped layer 16.

[0101] In some embodiments, the first conductive material 15' includes but is not limited to polysilicon. The dopant doped into the first conductive material 15' can be one or more of elements such as boron, phosphorus, arsenic, etc., and processes such as in-situ doping, diffusion, ion implantation, etc. can be used to dope the first conductive material 15'.

[0102] However, it is not limited thereto. Before removing the first dielectric layer 12 or the first dielectric layer 12 and the second dielectric layer 14 located above the first position P1, before forming the first conductive material 15', a doping process can be performed on the inner wall of the first groove S1 to form the doped layer 16.

[0103] In some embodiments, the bit line contact portion 15 may completely fill the first groove S1 or partially fill the first groove S1, that is, the bit line contact portion 15 may be entirely located within the first groove S1. For example, the sidewall of the bit line contact portion 15 may be substantially flush with the sidewall of the wall-like structure 11' (or the active pillar 11 in other embodiments), or may be slightly indented inward relative to the sidewall of the wall-like structure 11' (or the active pillar 11 in other embodiments); however, this is not limited thereto. The sidewall of the bit line contact portion 15 may also protrude slightly outward relative to the sidewall of the wall-like structure 11' (or the active pillar 11 in other embodiments) to increase the applicability of the scenario.

[0104] In some embodiments, the upper surface of the buried bit line 17 is flush with or higher than the upper surface of the bit line contact portion 15 to increase the applicability of the scenario.

[0105] Refer again to Figure 26 , in some embodiments, the remaining first dielectric layer 12 and the first filling layer 13 in the first sub-groove T11 form the first isolation structure 191. The buried bit line 17 covers the first isolation structure 191. The first isolation structure 191 is used to electrically isolate the buried bit line 17 and the substrate 10 to avoid leakage or short circuit. The first dielectric layer 12 and the first filling layer 13 located in the second sub-groove T12 form the second isolation structure 192. The second isolation structure 192 is used to separate adjacent buried bit lines 17, which helps to reduce the coupling effect between the buried bit lines 17.

[0106] Next, as Figure 27 shown, the method further includes: forming a second filling layer 18, and the second filling layer 18 fills the remaining space of the first sub-groove T11.

[0107] In actual operation, the second filling layer 18 may be a single-layer structure or a multi-layer structure. The material of the second filling layer 18 includes one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), etc., such as silicon oxide.

[0108] Next, refer again to Figures 28 to 30 , in some embodiments, forming the second trench T2 includes: etching the wall-like structure 11', the second filling layer 18, and the second isolation structure 192 along the first direction to form the second trench T2.

[0109] In some embodiments, a plurality of second trenches T2 extend along a first direction and are arranged at intervals along a second direction; a plurality of first trenches T1 and a plurality of second trenches T2 intersect each other to define a plurality of active column rows 111 and a plurality of active column columns 112 in the substrate 10; wherein, the plurality of active column rows 111 are arranged along the second direction, and each active column row 111 includes a plurality of active columns 11 arranged at intervals along the first direction; the plurality of active column columns 112 are arranged at intervals along the first direction, and each active column column 112 includes a plurality of active columns 11 arranged along the second direction.

[0110] In some embodiments, the depth of the second trench T2 is less than the depth of the first trench T1, and the bottom surface of the second trench T2 is higher than the upper surface of the buried bit line 17. A part of the wall-like structure 11' located below the second trench T2 is not etched to form a connection part 21. The connection part 21 is located between the lower parts of two adjacent active columns 11 arranged along the second direction, and the lower parts of the plurality of active columns 11 arranged along the second direction are sequentially connected through the connection part 21.

[0111] In some embodiments, the bit line contact part 15 extends continuously along the second direction in the plurality of active columns 11 and the plurality of connection parts 21. In this way, there is a large contact area between the buried bit line 17 and the bit line contact part 15, and between the bit line contact part 15 and the active columns 11 and the connection parts 21, further reducing the contact resistance between the bit line contact part 15 and the active columns 11, and the contact resistance between the buried bit line 17 and the bit line contact part 15.

[0112] In some embodiments, the bit line contact part 15 can be completely embedded in the active columns 11 and the connection parts 21. For example, the side walls of the bit line contact part 15 can be substantially flush with the side walls of the active columns 11 and the connection parts 21, or slightly indented inward relative to the side walls of the active columns 11 and the connection parts 21; but not limited thereto, the side walls of the bit line contact part 15 can protrude slightly outward relative to the side walls of the active columns 11 and the connection parts 21 to increase the applicability of the scenario.

[0113] In some embodiments, when the lower parts of the plurality of active columns 11 arranged along the second direction are sequentially connected through the connection part 21, the doped layer 16 is located in the plurality of active columns 11 and the plurality of connection parts 21 and extends continuously along the second direction. The doped layer 16 surrounds the contact surface between the bit line contact part 15 and the active columns 11 and the connection parts 21.

[0114] Continue to refer to Figures 28 to 30, in some embodiments, after forming the second trench T2, the method further includes: forming a third isolation structure 193 in the second trench T2, the third isolation structure 193 extending along a first direction in the lower part of the second trench T2 and covering the connection part 21, a part of the second filling layer 18, and a part of the second isolation structure 192 along the first direction; removing a part of the second filling layer 18 and a part of the second isolation structure 192 between two adjacent active pillars 11 in the active pillar row 111 to form a second groove S2 between the two adjacent active pillars 11 in the active pillar row 111, and the second groove S2 communicates with the second trench T2.

[0115] Next, as Figure 1 and Figures 2 to 3 shown, after forming the buried bit line 17, the method further includes: forming a plurality of word lines 23 above the buried bit line 17, the plurality of word lines 23 being arranged along a second direction, each word line 23 extending along the first direction, and each word line 23 covering a part of the side walls of each active pillar 11 in an active pillar row 111.

[0116] In some embodiments, each word line 23 extends along the first direction and surrounds each active pillar 11 in an active pillar row 111. In this way, it helps to increase the driving ability of the word line 23 for the active pillar row 111.

[0117] Specifically, the word line 23 can be formed in the following manner: First, fill a second conductive material (not shown) in the second trench T2 and the second groove S2, and the second conductive material (not shown) covers the third isolation structure 193 and a part of the second filling layer 18 and a part of the second isolation structure 192 exposed by the second groove S2; then, perform a back-etching process to make the upper surface of the second conductive material (not shown) lower than the upper surface of the active pillar 11; then, form a third filling layer 24, and the third filling layer 24 covers the second conductive material (not shown) and fills the second trench T2 and the second groove S2; then, etch the second conductive material (not shown) to form a first opening K1 in the second trench T2, and the first opening K1 extends downward from the upper surface of the third filling layer 24 to penetrate through the second conductive material (not shown) to divide the second conductive material (not shown) into a plurality of word lines 23 arranged at intervals along the second direction, and each word line 23 surrounds each active pillar 11 in an active pillar row 111; then, fill a fourth filling layer 25 in the first opening K1, and the third filling layer 24 and the fourth filling layer 25 constitute a fourth isolation structure 194.

[0118] In some embodiments, before forming the word line 23, it further includes: forming a gate dielectric layer 22, and the gate dielectric layer 22 is at least located between the word line 23 and the active pillar 11. In actual operation, the material of the gate dielectric layer 22 includes but is not limited to oxides, such as silicon oxide, and the gate dielectric layer 22 can be formed by performing an oxidation process on the sidewalls of the active pillar 11. However, it is not limited thereto, and the gate dielectric layer 22 can also be formed by a thin film deposition process.

[0119] Continuing to refer to Figures 2 to 3 , in some embodiments, after forming the fourth isolation structure 194, the method further includes: forming an insulating structure 26 above the active pillar 11 and the fourth isolation structure 194, the insulating structure 26 having a plurality of discrete second openings K2 therein, and the second openings K2 exposing the upper surface of the active pillar 11; forming a contact plug 27 in the second openings K2, and the contact plug 27 is electrically connected to the upper surface of the active pillar 11. In subsequent processes, a capacitor structure electrically connected thereto can be formed on the contact plug 27, and the capacitor structure is used to store data.

[0120] In actual operation, the insulating structure 26 may include a plurality of first sub-layers (not labeled) extending in a first direction and a plurality of second sub-layers (not labeled) extending in a second direction, and the plurality of first sub-layers and the plurality of second sub-layers intersect each other to enclose a plurality of second openings K2.

[0121] The materials of the word line 23, the third isolation structure 193, the fourth isolation structure 194, the insulating structure 26, and the contact plug 27 are as described above and will not be elaborated herein.

[0122] Figures 17 to 30 and Figures 2 to 3 In the illustrated structure, after forming the first trench T1 and before forming the second trench T2, the buried bit line 17 is formed. However, it is not limited thereto. In some other embodiments of the present disclosure, the first trench T1 and the second trench T2 may also be formed before forming the buried bit line 17, so as to form a plurality of active pillars 11. After forming the first trench T1 and the second trench T2, the buried bit line 17 is formed.

[0123] Specifically, as Figure 31 , Figures 32 to 33 or Figures 38 to 39 shown, a plurality of second trenches T2 can be first formed in the substrate 10, and the third isolation structure 193 is filled in the second trenches T2; then, a plurality of first trenches T1 are formed in the substrate 10 and the third isolation structure 193, and the plurality of first trenches T1 and the plurality of second trenches T2 define a plurality of active pillars 11 in the substrate 10.

[0124] However, it is not limited thereto, and a mask plate process can also be used to form a plurality of active pillars 11 by etching the substrate 10 in one step.

[0125] As Figures 32 to 33 shown, in some embodiments, the depth of the second trench T2 is less than the depth of the first trench T1, and the bottom surface of the second trench T2 is higher than the upper surface of the buried bit line 17. The portion of the substrate 10 located below the second trench T2 is not etched to form the connection portion 21, and the remaining third isolation structure 193 is located between adjacent first trenches T1 and covers the connection portion 21.

[0126] Next, perform the steps as Figures 32 to 33 shown on the structure as Figures 17 to 27 shown to form the structure as Figures 34 to 35 shown.

[0127] In some embodiments, in the step of removing the first dielectric layer 12 between the first position P1 and the second position P2, part of the active pillar 11 and part of the connection portion 21 are exposed; in the step of forming the first groove S1, at least part of the first groove S1 is located within the active pillar 11. For example, the first groove S1 can be located within a plurality of active pillars 11 and a plurality of connection portions 21 arranged along the second direction and continuously extend along the second direction.

[0128] In some embodiments, the bit line contact portion 15 is at least partially laterally embedded within the active pillars 11 on both sides of the first sub-trench T11. For example, the bit line contact portion 15 can be laterally embedded within the active pillars 11 and the connection portion 21 on both sides of the first sub-trench T11 and continuously extend along the second direction, and the bit line contact portion 15 can be completely embedded within the active pillars 11 and the connection portion 21, and can also protrude partially outward relative to the side walls of the active pillars 11 and the connection portion 21; in the step of forming the doped layer 16, dopants diffuse into a plurality of active pillars 11 and a plurality of connection portions 21 arranged along the second direction to form a doped layer 16 that continuously extends along the second direction.

[0129] Next, as Figures 36 to 37 shown, remove part of the second filling layer 18 and part of the second isolation structure 192 between two adjacent active pillars 11 of the active pillar row 111 to form a second groove S2 between two adjacent active pillars 11 of the active pillar row 111, and remove part of the third isolation structure 193, part of the second filling layer 18, and part of the second isolation structure 192 along the first direction to reopen part of the second trench T2, and the second groove S2 communicates with the second trench T2.

[0130] Next, perform the steps as Figures 36 to 37 shown on the structure as Figures 2 to 3 shown to form the structure as Figures 4 to 5 shown.

[0131] Figures 2 to 3 And Figures 4 to 5The depth of the second trench T2 shown is less than that of the first trench T1, and the bottom surface of the second trench T2 is higher than the upper surface of the buried bit line 17. The lower parts of the plurality of active pillars 11 arranged along the second direction are sequentially connected through the connection parts 21. The bit line contact parts 15 and the doping layer 16 are located within the plurality of active pillars 11 and the plurality of connection parts 21 and continuously extend along the second direction.

[0132] However, it is not limited thereto. As Figures 38 to 39 shown, in some other embodiments of the present disclosure, the second trench T2 may have a greater depth, and the bottom surface of the second trench T2 may be lower than the bottom surface of the subsequently formed buried bit line 17. The plurality of active pillars 11 of each active pillar column 112 are arranged at intervals along the second direction. The remaining third isolation structure 193 is located between adjacent first trenches T1 and covers a part of the substrate 10. Adjacent two active pillars 11 in the second direction are spaced apart by the third isolation structure 193.

[0133] Next, perform the steps as Figures 38 to 39 shown on the structure as Figures 17 to 27 shown to form the structure as Figures 40 to 41 shown.

[0134] In some embodiments, in the step of removing the first dielectric layer 12 between the first position P1 and the second position P2, part of the active pillar 11 and part of the third isolation structure 193 are exposed; in the step of forming the first groove S1, the first groove S1 is located within the plurality of active pillars 11 arranged along the second direction.

[0135] In some embodiments, the bit line contact part 15 is at least partially laterally embedded in the active pillars 11 on both sides of the first sub-trench T11. For example, the plurality of bit line contact parts 15 are arranged at intervals along the second direction and correspondingly laterally embedded in the plurality of active pillars 11 of the active pillar columns 112 on both sides of the first sub-trench T11, and the bit line contact part 15 may be completely embedded in the active pillar 11 or may partially protrude outward relative to the side wall of the active pillar 11; in the step of forming the doping layer 16, the dopant diffuses into the plurality of active pillars 11 arranged at intervals along the second direction to form the doping layer 16 within the plurality of active pillars 11, and the doping layer 16 surrounds the contact surface of the active pillar 11 and the bit line contact part 15.

[0136] Next, perform the steps as Figures 38 to 39 shown on the structure as Figures 36 to 37 and Figures 4 to 5 shown to form the structure as Figures 6 to 7 shown.

[0137] As Figure 8As shown, in some embodiments, when the multiple active pillars 11 in each active pillar column 112 are arranged at intervals in the second direction, the projection of the buried bit line 17 in the second direction may partially overlap with the projection of the active pillars 11 in the second direction, thereby increasing the contact area between the buried bit line 17 and the active pillars 11 or the bit line contact part 15 located within the active pillars 11, and further reducing the contact resistance of the buried bit line 17.

[0138] In actual operation, this can be achieved by increasing the width of the first trench T1 when forming the first trench T1, so that the first trench T1 exposes the ends of the active pillars 11 on both sides thereof. In this way, the area of the side walls of the active pillars 11 exposed by the first trench T1 is larger. For example, in addition to exposing the side walls of the active pillars 11 in the first direction, the first trench T1 can also expose part of the side walls of the active pillars 11 in the second direction, so that the finally formed buried bit line 17 can contact not only the side walls of the active pillars 11 or the bit line contact part 15 in the first direction, but also part of the side walls of the active pillars 11 or the bit line contact part 15 in the second direction.

[0139] As Figures 8 to 11 shown, in some embodiments, the orthographic projection of the active pillars 11 on the surface of the substrate 10 is symmetrically arranged in the first direction and the second direction. For example, the shape of the orthographic projection of the active pillars 11 on the surface of the substrate 10 can be a shape with rounded edges such as a circle or an ellipse, or a polygon with straight edges such as a quadrilateral, a pentagon, or a hexagon, or a polygon composed of straight edges and rounded edges.

[0140] However, it is not limited thereto. As Figure 12 shown, in some embodiments, the dimension of one end of the active pillar 11 close to the buried bit line 17 in the second direction is larger than the dimension of the other end of the active pillar 11 far from the buried bit line 17 in the second direction. For example, the shape of the orthographic projection of the active pillars 11 on the surface of the substrate 10 can be a regular or irregular figure such as a triangle or a T shape. By increasing the dimension of the end of the active pillar 11 close to the buried bit line 17 in the second direction, the contact area between the bit line contact part 15 and the active pillar 11 is increased, and at the same time, the dimension of the bit line contact part 15 and the contact area between the buried bit line 17 and the bit line contact part 15 are increased. In this way, the contact resistance between the bit line contact part 15 and the active pillar 11, and the contact resistance between the buried bit line 17 and the bit line contact part 15 are further reduced.

[0141] As Figures 8 to 11As shown, in some embodiments, the orthographic projection of the active pillar 11 on the surface of the substrate 10 is symmetrically arranged along the first direction and the second direction. For example, the shape of the orthographic projection of the active pillar 11 on the surface of the substrate 10 can be a shape with an arc edge such as a circle or an ellipse, or a polygon with straight edges such as a quadrilateral, a pentagon, or a hexagon, or a polygon composed of straight edges and arc edges.

[0142] However, it is not limited thereto. As Figure 12 shown, in some embodiments, the dimension of the end of the active pillar 11 close to the buried bit line 17 in the second direction in the first direction is greater than the dimension of the end of the active pillar 11 far from the buried bit line 17 in the first direction in the second direction. For example, the shape of the orthographic projection of the active pillar 11 on the surface of the substrate 10 can be a regular or irregular figure such as a triangle or a T shape. By increasing the dimension of the end of the active pillar 11 close to the buried bit line 17 in the second direction, the contact area between the bit line contact portion 15 and the active pillar 11 is increased, and at the same time, the dimension of the bit line contact portion 15 and the contact area between the buried bit line 17 and the bit line contact portion 15 are increased. In this way, the contact resistance between the bit line contact portion 15 and the active pillar 11 and the contact resistance between the buried bit line 17 and the bit line contact portion 15 are further reduced.

[0143] As Figures 9 to 12 shown, in some embodiments, when the multiple active pillars 11 in each active pillar column 112 are arranged at intervals along the second direction, the projection of the buried bit line 17 in the second direction can partially overlap the projection of the active pillar 11 in the second direction, achieving the same technical effect as above, which will not be elaborated here.

[0144] It can be seen that in the embodiments of the present disclosure, the buried bit line 17 is only formed in the first sub-groove T11, and not in the second sub-groove T12, that is, two adjacent active pillar columns 112 arranged along the first direction in an active pillar group 20 share one buried bit line 17, and no buried bit line 17 is formed between adjacent active pillar groups 20. In this way, the distance between adjacent buried bit lines 17 is increased, the coupling effect between the buried bit lines 17 can be effectively reduced, and further the signal crosstalk between the multiple buried bit lines 17 is reduced. At the same time, the contact resistance of the buried bit line 17 is reduced, and the performance of the semiconductor structure is improved.

[0145] Among the technical features in the technical solutions described in the above embodiments, they can be arbitrarily combined without conflict. Those skilled in the art can change the order of the above formation method steps without departing from the protection scope of the present disclosure. In the embodiments of the present disclosure, without conflict, some steps can be executed simultaneously or in a sequential order.

[0146] The above are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, and a plurality of active pillars located on the substrate, wherein the plurality of active pillars are arranged into a plurality of active pillar rows extending along a first direction and a plurality of active pillar columns extending along a second direction; wherein the plurality of active pillar columns include a plurality of active pillar groups arranged at intervals along the first direction, and each of the active pillar groups includes two active pillar columns arranged adjacently along the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate; A plurality of buried bit lines are located between two adjacent active column columns in the active column group and are electrically connected to each active column in the two adjacent active column columns, and two adjacent buried bit lines are separated by two adjacent active column columns in the two adjacent active column groups that belong to different active column groups.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes: a plurality of bit line contacts, which are respectively arranged on both sides of the buried bit line along the first direction and electrically connected to the buried bit line, and the bit line contacts are at least partially laterally embedded in the active pillars located on both sides of the buried bit line along the first direction.

3. The semiconductor structure according to claim 2, characterized in that: The multiple active pillars of each active pillar column are arranged at intervals along the second direction, and the multiple bit line contacts are arranged at intervals along the second direction and are correspondingly disposed in the multiple active pillars of the active pillar column.

4. The semiconductor structure according to claim 1, characterized in that The orthographic projections of the active pillars on the surface of the substrate are symmetrically arranged along the first direction and the second direction; or, The dimension of one end of the active pillar in the first direction close to the buried bit line in the second direction is greater than the dimension of one end of the active pillar in the first direction far from the buried bit line in the second direction.

5. The semiconductor structure according to claim 2, characterized in that: The semiconductor structure further includes: a plurality of connection parts, located between the lower parts of two active pillars arranged adjacent to each other along the second direction, and the lower parts of the plurality of active pillars arranged along the second direction are sequentially connected through the connection parts; The bit line contact portion is located within the plurality of active pillars and the plurality of connection portions and extends continuously along the second direction.

6. The semiconductor structure according to claim 2, characterized in that: The semiconductor structure further includes: a doping layer, which is at least partially located in the active pillar and at least surrounds a contact surface between the bit line contact portion and the active pillar.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The semiconductor structure further comprises: a first isolation structure, located below the buried bit line and extending along the second direction, wherein the buried bit line covers the first isolation structure; The second isolation structure is located between two adjacent active pillar groups and extends along the second direction, and the upper surface of the second isolation structure is higher than the upper surface of the buried bit line.

8. The semiconductor structure according to any one of claims 1 to 6, characterized in that: A plurality of active pillar rows are arranged along the second direction; and the semiconductor structure further comprises: A plurality of word lines are located above the buried bit lines, the plurality of word lines are arranged along the second direction, each of the word lines extends along the first direction, and each of the word lines covers a portion of a side wall of each of the active pillars in one active pillar row.

9. A method for manufacturing a semiconductor structure, characterized in that: include; providing a substrate; forming a plurality of active pillars on the substrate; A plurality of buried bit lines are formed; wherein, The plurality of active pillars are arranged into a plurality of active pillar rows extending along a first direction and a plurality of active pillar columns extending along a second direction; the plurality of active pillar columns include a plurality of active pillar groups arranged at intervals along the first direction, and each of the active pillar groups includes two active pillar columns arranged adjacently along the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate; The buried bit line is located between two adjacent active column columns in the active column group and is electrically connected to each active column in the two adjacent active column columns, and two adjacent buried bit lines are separated by two adjacent active column columns in the two adjacent active column groups that belong to different active column groups.

10. The manufacturing method according to claim 9, characterized in that: The forming of a plurality of active pillars on the substrate comprises: Etching the substrate to form a plurality of first grooves extending along the second direction on the substrate, wherein the first grooves define the substrate as a plurality of wall-like structures extending along the second direction; the plurality of first grooves include first sub-grooves and second sub-grooves alternately arranged in sequence along the first direction; At least etching the wall-like structure to form a plurality of second trenches extending along the first direction in the substrate, wherein the first trenches and the second trenches intersect each other to define a plurality of discrete active pillars in the substrate; The forming of a plurality of buried bit lines comprises: After forming the first trench and before or after forming the second trench, the buried bit line is formed in the first sub-trench, and the second sub-trench is located between two adjacent buried bit lines.

11. The manufacturing method according to claim 10, characterized in that: Before forming the buried bit line in the first sub-trench, the method further includes: Bit line contacts are formed on both sides of the first sub-trench along the first direction, and the bit line contacts are at least partially laterally embedded in the active pillars or the wall-like structures located on both sides of the first sub-trench.

12. The manufacturing method according to claim 11, characterized in that: The forming of the bit line contact portion comprises: forming a first dielectric layer covering inner walls of the first sub-groove and the second sub-groove, and a first filling layer covering the first dielectric layer and filling the first sub-groove and the second sub-groove; removing a portion of the first filling layer located in the first sub-groove to a first position to expose the first dielectric layer located above the first position; forming a second dielectric layer, wherein the second dielectric layer covers the exposed sidewalls of the first dielectric layer and the remaining upper surface of the first filling layer; removing the second dielectric layer covering the upper surface of the first filling layer, and retaining the second dielectric layer covering the side wall of the first dielectric layer; removing a portion of the first filling layer located in the first sub-groove to a second position to expose the first dielectric layer located between the first position and the second position; removing the first dielectric layer between the first position and the second position to expose a portion of the active pillar or a portion of the wall-like structure, and retaining at least a portion of the first dielectric layer, wherein the retained first dielectric layer covers a sidewall of the first sub-trench above the first position; Performing a lateral etching process on the first sub-groove located between the first position and the second position to form a first groove on both sides of the first sub-groove, wherein the first groove is located in the wall-like structure or at least partially in the active pillar, and an opening of the first groove faces the first sub-groove; removing the remaining first dielectric layer above the first position in the first sub-groove; A first conductive material is filled in the space between the first position and the second position of the first sub-trench and in the first groove, and an etching process is performed on the first conductive material to form the bit line contact portion, wherein the bit line contact portion is at least partially located in the first groove.

13. The manufacturing method according to claim 12, characterized in that: After forming the first groove and before forming the buried bit line, the method further includes: A doping layer is formed in the active pillar or the wall-shaped structure, and the doping layer surrounds an inner wall of the first groove.

14. The manufacturing method according to claim 13, characterized in that: Forming a doping layer in the active pillar or the wall-shaped structure, comprising: adding a dopant into the first conductive material; Before performing an etching process on the first conductive material to form the bit line contact portion, an annealing process is performed on the first conductive material doped with dopants, and a portion of the dopants diffuses into the active pillar or the wall-shaped structure to form the doping layer.

15. The manufacturing method according to any one of claims 9 to 14, characterized in that: After forming the buried bit line, the method further comprises: A plurality of word lines are formed above the buried bit lines. The plurality of word lines are arranged along the second direction. Each of the word lines extends along the first direction, and each of the word lines covers a portion of a side wall of each of the active pillars in one active pillar row.

Images