Floating gate memory based on two-dimensional material and preparation method thereof

Abstract

The embodiment of the invention provides a floating gate memory based on a two-dimensional material and a preparation method thereof. The floating gate memory comprises a control gate layer, a barrier layer, a floating gate layer, a tunneling insulating layer, a channel layer and a source and drain electrode buffer layer which are stacked from bottom to top, each layer is prepared from a two-dimensional material, adjacent interfaces between the layers are atomic-scale sharp interfaces, the control gate layer is prepared from a two-dimensional conductive material, and the barrier layer is prepared from a two-dimensional insulating material; the floating gate layer is prepared from a two-dimensional material with high state density, and the tunneling insulating layer is prepared from a two-dimensional insulating material; the channel layer is made of a two-dimensional semiconductor material with high carrier mobility; and the source and drain electrode buffer layer is prepared from a two-dimensional material with high conductivity. The functional layers of the floating gate memory are designed and are all constructed by adopting different two-dimensional materials with excellent characteristics, so that adjacent interfaces between the different functional layers are atomic-scale sharp interfaces, the high-speed nonvolatile memory is obtained, and the required power consumption is extremely low.

Description

Technical Field

[0001] The present invention relates to the technical field of memories, and particularly to a floating-gate memory based on two-dimensional materials and a preparation method thereof. Background Art

[0002] With the advent of the digital age, the generation of data has grown exponentially, posing higher requirements for data processing and storage technologies. Currently, silicon-based flash memory technology, as the mainstream data storage solution, is widely used in devices such as USB memories, flash cards, and solid-state drives, supporting the data storage and transmission of digital devices such as computers, mobile phones, and digital cameras. However, as semiconductor devices enter the nanoscale process node, silicon-based memory technology faces serious challenges. Specifically, silicon-based floating-gate memories expose many problems when scaled down in size. For example, its gate coupling ratio is relatively low, and the Si / SiO2 tunneling barrier is as high as 3 - 4 eV. Further, in traditional silicon-based devices, there are a large number of dangling bonds on the silicon surface, which causes unwanted interface effects such as Fermi level pinning, thus restricting carrier injection. These factors result in slow device operation speed and high energy consumption. In addition, in application scenarios where high-speed storage computing devices are required, the erase / write speed of silicon-based floating-gate memories is only in the millisecond level, showing a large gap compared with on-chip high-speed memories such as SRAM (static random access memory) and DRAM (dynamic random access memory). Especially when the thickness of the gate oxide layer of silicon-based devices is further reduced to break through the 10 nm technology node, it is restricted by process bottlenecks and physical limits.

[0003] In contrast, floating-gate memories based on two-dimensional materials exhibit significant advantages. Two-dimensional materials and their van der Waals heterostructures show excellent charge transport efficiency due to their atomic-scale thickness and flat, dangling-bond-free interface characteristics. For example, in a floating-gate device with boron nitride as the tunneling insulating layer, the tunneling barrier is as low as 1.7 - 2.2 eV, significantly reducing the difficulty of electron tunneling and improving the charge transport efficiency. In addition, the gate coupling ratio of floating-gate devices based on two-dimensional materials far exceeds that of traditional silicon-based devices, enabling a more precise degree of charge regulation. Therefore, in the context of the rapid growth of high-density storage requirements and the continuous shrinking of semiconductor technology nodes, two-dimensional materials have become potential materials to solve the bottleneck of Moore's Law.

[0004] In view of this, there is a need in the art for a new floating-gate memory based on two-dimensional materials and a preparation method thereof. Summary of the Invention

[0005] To address at least one of the above problems and defects in the prior art, embodiments of the present invention provide a floating-gate memory based on two-dimensional materials and a method for preparing the same. By designing the functional layers of the floating-gate memory, all of which are constructed using different two-dimensional materials with excellent properties and ensuring that the adjacent interfaces between different functional layers are atomically sharp interfaces, the performance of the floating-gate memory is significantly improved, a high-speed non-volatile memory is obtained, and the required power consumption is extremely low.

[0006] The technical solution is as follows:

[0007] According to one aspect of the present invention, there is provided a floating-gate memory based on two-dimensional materials, which includes a control gate layer, a blocking layer, a floating gate layer, a tunneling insulating layer, a channel layer, and a source / drain electrode buffer layer stacked from bottom to top. Each layer is prepared from two-dimensional materials, and the adjacent interfaces between the layers are atomically sharp interfaces. Among them, the control gate layer is prepared from two-dimensional conductive materials, and the blocking layer is prepared from two-dimensional insulating materials; the floating gate layer is prepared from two-dimensional materials with a high density of states, and the tunneling insulating layer is prepared from two-dimensional insulating materials; the channel layer is prepared from two-dimensional semiconductor materials with a high carrier mobility; the source / drain electrode buffer layer is prepared from two-dimensional materials with a high electrical conductivity.

[0008] Further, in some embodiments, the two-dimensional conductive material of the control gate layer can be multilayer graphene with more than four layers.

[0009] Further, in some embodiments, the two-dimensional insulating material of the blocking layer can be boron nitride or copper indium phosphorus sulfur, and can have a thickness of 30-50 nanometers.

[0010] Further, in some embodiments, the two-dimensional material with a high density of states of the floating gate layer can be any one of graphene, black phosphorus, or indium selenide.

[0011] Further, in some embodiments, the tunneling insulating layer can be the two-dimensional insulating material boron nitride and can have a thickness of 10-20 nanometers.

[0012] Further, in some embodiments, the two-dimensional semiconductor material with a high carrier mobility of the channel layer can be any one of molybdenum disulfide, indium selenide, tungsten diselenide, molybdenum ditelluride, tungsten disulfide, rhenium disulfide, or black phosphorus.

[0013] Further, in some embodiments, the two-dimensional material with a high electrical conductivity of the source / drain electrode buffer layer can be any one of graphene, vanadium disulfide, vanadium diselenide, or platinum diselenide, and forms a good van der Waals contact with the channel layer.

[0014] According to another aspect of the present invention, there is provided a method for fabricating a floating gate memory based on two-dimensional materials, wherein the control gate layer, the blocking layer, the floating gate layer, the tunneling insulating layer, the channel layer, and the source-drain electrode buffer layer are formed by bottom-up layer-by-layer stacking using semiconductor micro-nano processing techniques.

[0015] Further, in some embodiments, the control gate layer, the blocking layer, the floating gate layer, the tunneling insulating layer, the channel layer, and the source-drain electrode buffer layer can all be fabricated using mechanical exfoliation methods or chemical vapor deposition growth methods.

[0016] Further, in some embodiments, the layer-by-layer stacking can be performed using dry or wet transfer techniques for van der Waals heterojunction stacking.

[0017] Further, in some embodiments, source-drain electrodes can be fabricated above the source-drain electrode buffer layer using interface engineering means, electron beam lithography, and thermal evaporation deposition techniques, or metal electrodes can be directly transferred above the source-drain electrode buffer layer as source-drain electrodes.

[0018] Preferably, in some embodiments, when source-drain electrodes are fabricated above the source-drain electrode buffer layer using interface engineering means, electron beam lithography, and thermal evaporation deposition techniques, the interface engineering means can employ one or a combination of surface charge transfer doping, plasma treatment, optical modification, or annealing.

[0019] The floating gate memory based on two-dimensional materials and its fabrication method provided by the embodiments of the present invention have at least one or a part of at least one of the following advantages:

[0020] First, according to the floating gate memory based on two-dimensional materials and its fabrication method of the embodiments of the present invention, by constructing each functional layer of the floating gate memory using different two-dimensional materials, the following benefits can be obtained: First, since the channel layer is fabricated from a two-dimensional semiconductor material with high carrier mobility, and two-dimensional materials have the characteristic of high carrier mobility, which enables faster charge injection and extraction, thereby improving the operation speed; Second, two-dimensional materials have the characteristics of atomic-level thickness and gate-tunable band structure, making them have excellent nano-scale gate coupling, thus achieving enhanced electrostatic control; Third, the adjacent interfaces between different functional layers are atomic-level sharp interfaces, without dangling bonds, few interface defects, and low tunneling barriers, allowing for more efficient tunneling, reducing the operation voltage, and decreasing energy consumption; Fourth, the present invention can further optimize the device structure by adding a source-drain electrode buffer layer fabricated from a two-dimensional material with high conductivity between the source-drain electrodes and the channel layer; Therefore, the selection and combination of materials for each layer can synergistically optimize the performance of the floating gate memory, thereby enabling the acquisition of a high-speed non-volatile memory.

[0021] Furthermore, the present invention can achieve an efficient erasing operation of the floating-gate memory by applying voltage pulses to the control gate, and the power consumption required is extremely low.

[0022] In addition, the present invention can further optimize the contact interface between the two-dimensional material and the metal electrode by means of interface engineering, effectively suppressing the interface Fermi level pinning effect caused by the traditional metal deposition process, reducing the contact resistance, further improving the operation speed, and reducing the energy consumption at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] These and / or other aspects and advantages of the present invention will become apparent and be readily understood from the following description of the preferred embodiments in conjunction with the accompanying drawings, in which:

[0024] Figure 1 FIG. is a schematic structural diagram of a floating-gate memory based on two-dimensional materials according to an embodiment of the present invention;

[0025] Figure 2 FIG. is a schematic structural diagram of a floating-gate memory based on two-dimensional materials according to another embodiment of the present invention;

[0026] Figure 3 FIG. is a schematic structural diagram of a floating-gate memory based on two-dimensional materials according to still another embodiment of the present invention;

[0027] Figure 4 Exemplarily shown Figure 1 is a graph of the erasing operation test of the floating-gate memory based on two-dimensional materials in, in which the inset shows the waveform of the corresponding gate voltage pulse. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] Hereinafter, through embodiments and in conjunction with the accompanying drawings, the technical solutions of the present invention will be further specifically described. In the specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation of the present invention.

[0029] At present, in the context of the rapid growth of high-density storage requirements and the continuous shrinking of semiconductor technology nodes, two-dimensional materials have become potential materials for solving the bottleneck of Moore's Law due to their atomic-level thickness, tunable band structure, high carrier mobility, etc. Therefore, it is of positive significance to develop floating-gate memories based on two-dimensional materials to meet the development needs of high-speed, low-power non-volatile memories. Two-dimensional materials have a rich material gene pool, including conductive materials such as graphene, semiconductor materials such as transition metal chalcogenides, black phosphorus, IIIA-VIA group compounds, and insulating materials such as boron nitride. More particularly, among the examples of two-dimensional materials, graphene has good conductivity and can be used as an electrode or a floating gate; boron nitride is a good insulator and is suitable as a tunneling insulating layer or a blocking layer; molybdenum disulfide has a high carrier mobility and can be used as a channel material.

[0030] Therefore, the present invention provides a new two-dimensional material-based floating-gate memory and a preparation method thereof. By designing that each functional layer of the floating-gate memory is constructed with two-dimensional materials having excellent properties, and the adjacent interfaces between different functional layers are atomically sharp interfaces, the materials of each layer can synergistically optimize the performance of the floating-gate memory. And by adding a source-drain electrode buffer layer to optimize the device structure, a non-volatile memory with an extremely fast operation speed and extremely low power consumption can be obtained. Among them, the functional layers of the above device include a control gate layer, a blocking layer, a floating gate layer, a tunneling insulating layer, a channel layer, and a source-drain electrode buffer layer.

[0031] Furthermore, the present invention can further optimize the contact interface between the two-dimensional material and the metal electrode through interface engineering means, effectively suppress the interface Fermi level pinning effect caused by the traditional metal deposition process, reduce the contact resistance, and enable the above non-volatile memory to further improve the operation speed and reduce the power consumption.

[0032] The two-dimensional material-based floating-gate memory of the present invention can achieve the effects of extremely fast operation speed and extremely low power consumption. First, it benefits from the high carrier mobility of two-dimensional materials, which makes the charge injection and extraction faster, thus improving the operation speed. Second, two-dimensional materials have the characteristics of atomic-level thickness and gate-tunable band structure, enabling them to have excellent nanoscale gate coupling, thereby realizing enhanced electrostatic control. Third, there are atomically sharp interfaces between different functional layers, no dangling bonds, few interface defects, and low tunneling barriers, allowing for more efficient tunneling, reducing the operation voltage, and reducing energy consumption. Fourth, the device structure is optimized by adding a source-drain electrode buffer layer. Therefore, the selection and combination of the materials of each layer can synergistically optimize the performance of the floating-gate memory.

[0033] For example, boron nitride can be used as a tunneling insulating layer, which is thinner and has a smaller tunneling barrier than the traditional material silicon dioxide, allowing tunneling at a lower operating voltage and shortening the operating time. For example, graphene can be used as a floating gate layer, and due to its high density of states, it can achieve efficient charge injection and stable storage, avoiding the charge leakage problem of traditional polysilicon floating gates. For example, molybdenum disulfide can be used as a channel layer, which has a high carrier mobility and can improve the operating speed, thereby reducing power consumption.

[0034] Furthermore, the interface quality is improved by adopting interface engineering means. The source-drain electrode buffer layer is prepared from a two-dimensional material with high conductivity. By forming a van der Waals contact interface with the channel layer, the contact interface between the two-dimensional material and the metal electrode is further optimized by interface engineering means, reducing the interface Fermi level pinning effect caused by the traditional metal deposition process, thereby reducing the interface defect density and reducing the interface scattering problem, reducing the contact resistance, making it easier for carriers to be injected from the source-drain electrodes into the channel material, and significantly improving the operating speed of the memory and reducing power consumption.

[0035] According to an embodiment of the present invention, a floating gate memory based on two-dimensional materials is provided, which includes a control gate layer, a blocking layer, a floating gate layer, a tunneling insulating layer, a channel layer, and a source-drain electrode buffer layer stacked from bottom to top. Each layer is prepared from a two-dimensional material, and the adjacent interfaces between the layers are atomically sharp interfaces. Among them, the control gate layer is prepared from a two-dimensional conductive material, and the blocking layer is prepared from a two-dimensional insulating material; the floating gate layer is prepared from a two-dimensional material with a high density of states, and the tunneling insulating layer is prepared from a two-dimensional insulating material; the channel layer is prepared from a two-dimensional semiconductor material with a high carrier mobility; the source-drain electrode buffer layer is prepared from a two-dimensional material with high conductivity.

[0036] Generally speaking, for two-dimensional materials, a "high density of states"> 10 12 states / eV / cm 2 can be regarded as a high density of states. A high density of states means that the number of quantum states available for electrons to occupy within a unit energy range in the material is relatively large, which means that the material has a strong ability to store charges.

[0037] Generally speaking, for two-dimensional materials, a "high carrier mobility"> 10 2 cm 2 / (V·s) can be regarded as a high mobility. A high carrier mobility means that carriers can move quickly in the material, thereby improving the response speed of the device and reducing power consumption.

[0038] Generally speaking, for two-dimensional materials, a "high conductivity"> 10 3 S / m can be regarded as a high conductivity.

[0039] Further, in some embodiments, the two-dimensional conductive material of the control gate layer may be a multi-layer graphene with more than four layers.

[0040] Further, in some embodiments, the two-dimensional insulating material of the blocking layer may be boron nitride or copper indium phosphosulfide, and may have a thickness of 30 - 50 nanometers.

[0041] Further, in some embodiments, the two-dimensional material with a high density of states of the floating gate layer may be any one of graphene, black phosphorus, or indium selenide.

[0042] Further, in some embodiments, the two-dimensional insulating material of the tunneling insulating layer may be boron nitride, and may have a thickness of 10 - 20 nanometers.

[0043] Further, in some embodiments, the two-dimensional semiconductor material with a high carrier mobility of the channel layer may be any one of molybdenum disulfide, indium selenide, tungsten diselenide, molybdenum ditelluride, tungsten disulfide, rhenium disulfide, or black phosphorus.

[0044] Further, in some embodiments, the two-dimensional material with a high conductivity of the source / drain electrode buffer layer may be any one of graphene, vanadium disulfide, vanadium diselenide, or platinum diselenide, and forms a good van der Waals contact with the channel layer, thereby reducing the contact resistance. Preferably, the source / drain electrode buffer layer may be graphene. The excellent conductivity of graphene can accelerate the transfer of charges from the electrode to the channel, thereby improving the carrier injection efficiency. It forms a van der Waals contact interface with the semiconductor channel layer, reducing interface defects and scattering, and lowering the contact resistance, thus increasing the operation speed and reducing the power consumption.

[0045] According to another embodiment of the present invention, a method for fabricating a floating gate memory based on two-dimensional materials is provided, wherein the control gate layer, the blocking layer, the floating gate layer, the tunneling insulating layer, the channel layer, and the source / drain electrode buffer layer are formed by stacking layer by layer from bottom to top using semiconductor micro-nano processing technology.

[0046] Further, in some embodiments, the control gate layer, the blocking layer, the floating gate layer, the tunneling insulating layer, the channel layer, and the source / drain electrode buffer layer can all be fabricated by mechanical exfoliation method or chemical vapor deposition growth method.

[0047] Further, in some embodiments, the layer-by-layer stacking can be performed by van der Waals heterojunction stacking using dry or wet transfer techniques.

[0048] Further, in some embodiments, source / drain electrodes can be fabricated above the source / drain electrode buffer layer through interface engineering means, electron beam lithography, and thermal evaporation deposition techniques, or metal electrodes can be directly transferred above the source / drain electrode buffer layer as source / drain electrodes.

[0049] Preferably, in some embodiments, when the source-drain electrodes are prepared above the source-drain electrode buffer layer by means of interface engineering and electron beam lithography and thermal evaporation deposition techniques, the interface engineering means may employ one or a combination of surface charge transfer doping, plasma treatment, optical modification, or annealing.

[0050] As one of the interface engineering means, surface charge transfer doping can achieve the doping of materials to change their electrical properties by surface adsorption or charge exchange processes with the surface, rather than by replacing atoms in the lattice or interstitial doping. Therefore, surface charge transfer doping is an effective and non-destructive two-dimensional material doping technique, and its doping process is driven by the spontaneous charge transfer aligned by the energy levels at the dopant / two-dimensional material interface. For example, AuCl3 can be used as a surface dopant, and Au in AuCl3 3+ can extract electrons from the material, resulting in holes as the majority carriers, thus achieving p-type doping. After doping, a higher hole concentration will be provided at the contact interface, causing its Fermi level to shift downward and reducing the Schottky barrier height of the holes, thereby reducing the contact resistance.

[0051] The following will further exemplify and detail the preparation method of the floating gate memory based on two-dimensional materials according to the embodiments of the present invention with reference to the accompanying drawings.

[0052] Embodiment 1:

[0053] Figure 1 is a schematic structural diagram of a floating gate memory based on two-dimensional materials according to an embodiment of the present invention. As Figure 1 shown, on a silicon-based (Si / SiO2) substrate 101, five-layer graphene can be prepared as the control gate layer 102 by mechanical exfoliation; the barrier layer 103 can be selected as 30-nanometer-thick boron nitride by mechanical exfoliation; the floating gate layer 104 can be selected as graphene by mechanical exfoliation; the tunneling insulating layer 105 can be selected as 13-nanometer-thick boron nitride by mechanical exfoliation; the channel layer 106 can be selected as molybdenum disulfide by mechanical exfoliation; the source-drain electrode buffer layer 107 can be selected as graphene by mechanical exfoliation. The above functional layers can be stacked in sequence by a dry transfer technique assisted by polydimethylsiloxane (PDMS) to prepare a van der Waals heterojunction. The source-drain metal electrodes 108 can be selected as chromium-gold source-drain electrodes prepared by electron beam lithography and thermal evaporation deposition techniques, and the entire device can be annealed at a temperature of 200 °C for 30 min in an H2 / Ar atmosphere.

[0054] Embodiment 2:

[0055] Figure 2 is a schematic structural diagram of a floating gate memory based on two-dimensional materials according to another embodiment of the present invention. As Figure 2As shown in the figure, the control gate layer 202 can be more than four layers of graphene grown on a silicon-based substrate 201 by chemical vapor deposition; the blocking layer 203 can be 32-nanometer-thick copper indium phosphorus sulfide obtained by mechanical exfoliation; the floating gate layer 204 can be indium selenide obtained by mechanical exfoliation; the tunneling insulation layer 205 can be 15-nanometer-thick boron nitride obtained by mechanical exfoliation; the channel layer 206 can be molybdenum disulfide obtained by mechanical exfoliation; the source-drain electrode buffer layer 207 can be graphene obtained by mechanical exfoliation. The above functional layers are sequentially stacked by PDMS-assisted dry transfer technology to prepare a van der Waals heterojunction. The source-drain metal electrodes 208 can be palladium-gold electrodes prepared by electron beam lithography and thermal evaporation deposition technology. The floating gate device can be optimized by two interface engineering means, such as surface charge transfer doping and annealing. The AuCl3 dopant can be spin-coated on the device at 5500 rpm for 1 min, then baked at 50 °C for 5 min, and the whole device can be annealed at 100 °C for 10 min in an H2 / Ar atmosphere to obtain an optimized floating gate device.

[0056] Example 3:

[0057] Figure 3 It is a schematic structural diagram of a floating gate memory based on two-dimensional materials according to another embodiment of the present invention. As Figure 3 shown, on a silicon-based or sapphire or quartz substrate 301, more than four layers of graphene can be grown as the control gate layer 302 by mechanical exfoliation or chemical vapor deposition technology; the blocking layer 303 can be multilayer boron nitride or copper indium phosphorus sulfide obtained by mechanical exfoliation or chemical vapor deposition growth; the floating gate layer 304 can be two-dimensional materials with a high density of states obtained by mechanical exfoliation or chemical vapor deposition growth, such as graphene, black phosphorus, indium selenide, etc.; the tunneling insulation layer 305 can be multilayer boron nitride obtained by mechanical exfoliation or chemical vapor deposition growth; the channel layer 306 can be two-dimensional semiconductor materials with a high carrier mobility obtained by mechanical exfoliation or chemical vapor deposition growth, such as molybdenum disulfide, indium selenide, tungsten diselenide, molybdenum ditelluride, tungsten disulfide, rhenium disulfide, or black phosphorus, etc.; the source-drain electrode buffer layer 307 can be two-dimensional materials with a high conductivity obtained by mechanical exfoliation or chemical vapor deposition growth, such as graphene, vanadium disulfide, vanadium diselenide, or platinum diselenide, etc. The above functional layers can be sequentially stacked by dry / wet / mixed transfer technology to prepare a van der Waals heterojunction. The source-drain metal electrodes 308 can be chromium-gold electrodes / titanium-gold electrodes / palladium-gold electrodes prepared by interface engineering means and electron beam lithography and thermal evaporation deposition technology, or metal electrodes can be directly transferred above the source-drain electrode buffer layer as the source-drain electrodes. The interface engineering means can be one or a combination of surface charge transfer doping, plasma treatment, optical modification, or annealing.

[0058] For Figures 1-3The floating - gate memory embodiments in [reference] are tested. Then, the present inventors found that when applying a voltage pulse to the control gate to achieve the erase operation of the floating - gate memory, it is efficient and requires extremely low power consumption.

[0059] Take the embodiments in Figure 1 as an example. Figure 4 Exemplarily shown is Figure 1 a graph of the erase operation test of the two - dimensional - material - based floating - gate memory in [reference], where the inset in the graph shows the corresponding gate voltage pulse waveform. As Figure 4 shown, by applying an operating voltage of - 10V to the control gate, an erase operation of 500 ns can be achieved. This result shows the advantageous technical effect of an extremely fast operation speed. Further, according to the formula E = V ds ×t×I peak the single - pulse energy consumption corresponding to the gate voltage pulse with a pulse width of 500 ns is calculated to be 20 aJ, where V ds is the operating voltage for reading the source - drain current, I peak is the peak value of the source - drain current, and t is the pulse width. This result shows the advantageous technical effect of extremely low power consumption. After testing and calculation, Figure 2 and Figure 3 's floating - gate memory embodiments also show similar performance to Figure 1 's, and similar advantageous technical effects of extremely fast operation speed and extremely low power consumption can be obtained.

[0060] Therefore, the two - dimensional - material - based floating - gate memory according to the embodiments of the present invention can have high - speed tunneling efficiency. The characteristics such as the atomic - level thickness, absence of dangling bonds, and high carrier mobility of the two - dimensional material can significantly reduce the tunneling barrier, reduce interface scattering, enabling charges to complete tunneling in only 500 ns at, for example, - 10V voltage, which is 2 - 3 orders of magnitude faster than traditional memories, while reducing the power consumption of the memory.

[0061] In summary, for the two - dimensional - material - based floating - gate memory and its manufacturing method provided according to the embodiments of the present invention, by designing the functional layer of the floating - gate memory, all different two - dimensional materials with excellent characteristics are used to construct it, and an atomic - level sharp interface is ensured between different functional layers. And by adding a buffer layer between the source - drain electrodes and the channel layer to optimize the device structure, the performance of the floating - gate memory can be significantly improved, obtaining a high - speed non - volatile memory with extremely low power consumption. Further, the present invention can achieve an efficient erase operation of the floating - gate memory by applying a voltage pulse to the control gate, and the required power consumption is extremely low. Further, the present invention can also further optimize the contact interface between the two - dimensional material and the metal electrode through interface engineering means, effectively suppressing the interface Fermi - level pinning effect caused by the traditional metal deposition process, reducing the contact resistance, thereby improving the operation speed and further reducing the power consumption.

[0062] While some embodiments of the present general inventive concept have been shown and described, those of ordinary skill in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, and the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A floating gate memory based on two-dimensional materials, characterized in that: It includes a control gate layer, a barrier layer, a floating gate layer, a tunneling insulating layer, a channel layer and a source-drain electrode buffer layer stacked from bottom to top, each layer is made of a two-dimensional material, and the adjacent interfaces between the layers are atomic-level sharp interfaces, wherein the control gate layer is made of a two-dimensional conductive material, and the barrier layer is made of a two-dimensional insulating material; the floating gate layer is made of a two-dimensional material with a high state density, and the tunneling insulating layer is made of a two-dimensional insulating material; the channel layer is made of a two-dimensional semiconductor material with a high carrier mobility; and the source-drain electrode buffer layer is made of a two-dimensional material with a high electrical conductivity.

2. The floating gate memory according to claim 1, wherein: The two-dimensional conductive material of the control gate layer is multilayer graphene with more than four layers.

3. The floating gate memory according to claim 1, wherein: The two-dimensional insulating material of the barrier layer is made of boron nitride or copper indium phosphide and has a thickness of 30-50 nanometers.

4. The floating gate memory according to claim 1, wherein: The two-dimensional material with high state density of the floating gate layer is any one of graphene, black phosphorus, or indium selenide.

5. The floating gate memory according to claim 1, wherein: The two-dimensional insulating material of the tunnel insulating layer is boron nitride and has a thickness of 10-20 nanometers.

6. The floating gate memory according to claim 1, wherein: The two-dimensional semiconductor material with high carrier mobility of the channel layer is any one of molybdenum disulfide, indium selenide, tungsten diselenide, molybdenum ditelluride, tungsten disulfide, rhenium disulfide, or black phosphorus.

7. The floating gate memory according to claim 1, wherein: The two-dimensional material with high conductivity of the source-drain electrode buffer layer is any one of graphene, vanadium disulfide, vanadium diselenide or platinum diselenide, and forms a good van der Waals contact with the channel layer.

8. A method for preparing a floating gate memory based on a two-dimensional material as claimed in any one of claims 1 to 7, characterized in that: The control gate layer, the barrier layer, the floating gate layer, the tunneling insulating layer, the channel layer and the source-drain electrode buffer layer are formed by stacking them layer by layer from bottom to top using semiconductor micro-nano processing technology.

9. The preparation method according to claim 8, characterized in that: The layer-by-layer stacking utilizes dry or wet transfer technology to perform van der Waals heterojunction stacking; The control gate layer, the barrier layer, the floating gate layer, the tunneling insulating layer, the channel layer and the source-drain electrode buffer layer are all manufactured by a mechanical stripping method or a chemical vapor deposition growth method.

10. The preparation method according to claim 8, characterized in that: Prepare source-drain electrodes on the source-drain electrode buffer layer by using interface engineering means, electron beam exposure and thermal evaporation deposition technology, or directly transfer metal electrodes to the source-drain electrode buffer layer as source-drain electrodes; Preferably, when the source-drain electrode is prepared above the source-drain electrode buffer layer by using interface engineering means and electron beam exposure and thermal evaporation deposition technology, the interface engineering means adopts one or more combinations of surface charge transfer doping, plasma treatment, optical modification, or annealing.

Images