Memory, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the invention provides a memory and a manufacturing method thereof. According to the manufacturing method of the memory provided by some embodiments of the invention, after a storage structure is formed on one side of a substrate, a first field effect transistor is directly formed on one side, far away from the substrate, of the storage structure, so that a first electrode of the first field effect transistor is connected with a word line of the storage structure, and the first field effect transistor is electrically connected with the storage structure. Compared with a manufacturing method of a related memory, by forming the storage structure and the first field effect transistor on the same substrate, the manufacturing cost and the manufacturing difficulty of the memory can be reduced, and the manufacturing efficiency and the yield of the memory can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a memory and its manufacturing method, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, the industry has proposed various semiconductor structure designs and process optimizations to meet the requirements of current products. Summary of the Invention

[0004] In view of the shortcomings of the existing methods, this application provides a memory and its manufacturing method, and an electronic device.

[0005] In a first aspect, some embodiments of this application provide a method for manufacturing a memory, including:

[0006] Forming a storage structure on one side of a substrate; the storage structure includes at least one layer of a storage array, word lines, and bit lines; the storage array includes at least one storage unit;

[0007] Forming at least one first stacked structure on a side of the storage structure away from the substrate; the first stacked structure includes at least one stacked layer of a first sacrificial structure and at least one layer of a first semiconductor structure;

[0008] Forming a first electrode such that the first electrode is connected to the word line and the first semiconductor structure;

[0009] Removing part of the first sacrificial structure such that part of the first semiconductor structure is exposed;

[0010] Sequentially forming a first dielectric structure and a first gate on the exposed surface of the first semiconductor structure;

[0011] Forming a second electrode such that the second electrode is connected to the first semiconductor structure to form a first field-effect transistor;

[0012] Exemplarily, forming at least one first stacked structure includes: forming a first planar structure covering the storage structure and at least two first stacked structures embedded in the first planar structure, and the orthographic projection of the first stacked structure on the substrate at least partially overlaps with the orthographic projection of the corresponding storage unit on the substrate.

[0013] Exemplarily, the bit line extends along a first direction parallel to the substrate and is connected to a column of memory cells arranged along the first direction in the memory array in the same layer; the word line extends along a second direction perpendicular to the substrate and is connected to a group of the memory cells stacked along the second direction.

[0014] Exemplarily, at least one first stacked structure is formed on a side of the memory structure away from the substrate, including:

[0015] At least two of the first stacked structures are formed on a side of the memory structure away from the substrate;

[0016] The first flat structure is formed in an area of the memory structure not covered by the first stacked structure, such that a surface of the first flat structure away from the substrate is flush with a surface of the first stacked structure away from the substrate.

[0017] Exemplarily, at least two of the first stacked structures are formed on a side of the memory structure away from the substrate, including:

[0018] Based on an epitaxial process, a first composite film layer is formed on a side of the memory structure away from the substrate; the first composite film layer includes at least two first sacrificial layers and at least one first semiconductor layer, and the first semiconductor layer is located between two adjacent first sacrificial layers;

[0019] The first composite film layer is patterned to form at least two of the first stacked structures; the first stacked structure includes the first sacrificial structure formed after patterning the first sacrificial layer and the first semiconductor structure formed after patterning the first semiconductor layer.

[0020] Exemplarily, a first electrode is formed such that the first electrode is connected to the word line and the first semiconductor structure, including:

[0021] A first via hole penetrating the first stacked structure and at least one second via hole penetrating the first flat structure are formed; the first via hole exposes at least a surface of the word line away from the substrate, and the second via hole exposes a surface of a shared word line of the memory structure extending along the second direction away from the substrate; the shared word line is connected to a group of second field effect transistors stacked along the second direction, and the bit line and the shared bit line in the same layer are electrically connected through the second field effect transistors in the same layer; the second direction is perpendicular to the substrate;

[0022] The first electrode filling the first via hole and a first connection electrode filling the second via hole are formed, such that the first connection electrode is connected to the shared word line.

[0023] Exemplarily, removing a part of the first sacrificial structure to expose a part of the first semiconductor structure includes:

[0024] Forming at least two third vias penetrating the first flat structure and at least one first trench; a part of the first connection electrode is exposed in the first trench;

[0025] Etching back the inner sidewall of the third via to remove the exposed part of the first sacrificial structure, so that the outer peripheral wall of a part of the first semiconductor structure is exposed, and so that a column of the third vias arranged along a first direction are all communicated with the same first trench; the first direction is parallel to the substrate.

[0026] Exemplarily, forming a first dielectric structure and a first gate on the exposed surface of the first semiconductor structure in sequence includes:

[0027] Forming the first dielectric structure surrounding the outer peripheral wall of a part of the first semiconductor structure;

[0028] Forming the first gate and a second connection electrode filling the third via and the first trench based on a deposition process, so that the first gate surrounds the outer peripheral wall of the first dielectric structure; the first gates of the first field effect transistors in the same column are electrically connected to each other through the second connection electrode and the first connection electrode.

[0029] Exemplarily, forming a second electrode to connect the second electrode to the first semiconductor structure to form a first field effect transistor includes:

[0030] Forming a second flat structure covering the first flat structure and the first stacked structure;

[0031] Forming at least two fourth vias penetrating the second flat structure and at least a part of the first stacked structure, and at least one fifth via penetrating the second flat structure; the fourth via exposes a part of the first semiconductor structure, and the fifth via exposes a part of the first connection electrode;

[0032] Forming the second electrode in the fourth via, a third connection electrode in the fifth via, and a fourth connection electrode connecting the second electrodes of the first field effect transistors in the same row; the third connection electrode is connected to the first connection electrode; the fourth connection electrode is disposed on a side of the second flat structure away from the substrate and extends along a third direction; the third direction is parallel to the substrate and intersects with the first direction.

[0033] Exemplarily, forming a storage structure on one side of the substrate includes:

[0034] Based on an epitaxial process, a second composite film layer is formed on one side of the substrate; the second composite film layer includes multiple layers of the first sacrificial layer and the first semiconductor layer stacked alternately;

[0035] Pattern the second composite film layer to form at least two second stacked structures, at least one third stacked structure, and at least one fourth stacked structure; both the second stacked structure and the fourth stacked structure extend along a third direction, and the third stacked structure extends along the first direction; along the third direction, a column of the second stacked structures connected to the third stacked structure is provided on both sides of the third stacked structure; along the first direction, the fourth stacked structure is connected to one end of the third stacked structure;

[0036] Based on the second stacked structure and the third stacked structure, form at least two stacked memory cells, a word line connected to the memory cells, and at least two stacked and mutually insulated bit lines.

[0037] Exemplarily, forming at least two stacked memory cells, a word line connected to the memory cells, and at least two stacked and mutually insulated bit lines based on the second stacked structure and the third stacked structure includes:

[0038] Form at least two stacked capacitors based on the second stacked structure;

[0039] Form at least two spaced-apart sub-stacked structures based on the third stacked structure, the sub-stacked structure including a bit line group, and the bit line group including at least two stacked and mutually insulated bit lines;

[0040] Form a shared bit line group based on the fourth stacked structure, the shared bit line group including at least two stacked and mutually insulated shared bit lines;

[0041] Form a third field-effect transistor and a word line connected to the third field-effect transistor based on the second stacked structure formed with the capacitor; along the third direction, one end of the third field-effect transistor is connected to the capacitor, and the other end is connected to the bit line arranged on the same layer;

[0042] Form at least two stacked second field-effect transistors and a shared word line connected to the second field-effect transistors based on the sub-stacked structure. In a second aspect, some embodiments of the present application provide a memory, including:

[0043] A substrate, and a memory structure, a first field-effect transistor, and a second field-effect transistor provided on the same substrate;

[0044] The memory structure includes at least one layer of a memory array, a word line, and a bit line;

[0045] The first field-effect transistor is disposed on a side of the storage structure away from the substrate, and the second field-effect transistor is configured to control the gating of the bit line; the first field-effect transistor is electrically connected to the word line and the second field-effect transistor respectively.

[0046] Exemplarily, the first field-effect transistor includes a first gate, a first electrode, and a second electrode, and the first electrode of the first field-effect transistor is connected to the word line.

[0047] Exemplarily, the first gate of the first field-effect transistor is electrically connected to the second gate of the second field-effect transistor.

[0048] Exemplarily, the bit line extends along a first direction parallel to the substrate and is connected to a third field-effect transistor of a column of storage units arranged along the first direction in the storage array of the same layer;

[0049] The word line extends along a second direction perpendicular to the substrate and is connected to a third field-effect transistor of a group of the storage units stacked along the second direction.

[0050] Exemplarily, at least two stacked and mutually insulated shared bit lines are disposed on one side of the storage structure along the first direction;

[0051] At least two stacked second field-effect transistors and at least one shared word line connected to the second field-effect transistors.

[0052] Exemplarily, along the first direction, both the second field-effect transistor and the shared word line are disposed between the shared bit line and the storage structure.

[0053] Exemplarily, the bit line and the shared bit line disposed in the same layer are electrically connected through the second field-effect transistor disposed in the same layer.

[0054] Exemplarily, the word line is electrically connected to the third gate of a third field-effect transistor of a group of storage units stacked along the second direction.

[0055] Exemplarily, the second electrodes of a row of first field-effect transistors arranged along a third direction are electrically connected to each other through a fourth connection electrode; the third direction is parallel to the substrate and intersects with the first direction.

[0056] Exemplarily, the first gates of a column of first field-effect transistors arranged along the first direction are electrically connected to each other through a second connection electrode.

[0057] Exemplarily, the second connection electrode is electrically connected to the shared word line through the first connection electrode. In a third aspect, some embodiments of the present application provide an electronic device, including: the memory as described above.

[0058] The beneficial technical effects brought by the technical solutions provided in some embodiments of the present application include:

[0059] In the manufacturing method of the memory provided in some embodiments of the present application, after forming a storage structure on one side of the substrate, a first field-effect transistor is directly formed on the side of the storage structure away from the substrate; compared with the manufacturing method of related three-dimensional stacked memories, by forming the storage structure and the first field-effect transistor on the same substrate, the manufacturing cost and difficulty of the memory can be reduced, which helps to improve the manufacturing efficiency and yield of the memory.

[0060] In the memory provided in some embodiments of the present application, by arranging the first field-effect transistor and the storage structure on the same substrate, the manufacturing cost and difficulty of the memory can be reduced, which helps to improve the manufacturing efficiency and yield of the memory; by electrically connecting the first field-effect transistor to the word line and the second field-effect transistor, the electrical function of the first field-effect transistor can be realized, so that the operation of the word line and the operation of the bit line can be effectively coordinated, simplifying the circuit and improving the working efficiency of the circuit.

[0061] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or can be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The above and / or additional aspects and advantages of the present application will become apparent and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0063] Figure 1 is a schematic flowchart of a manufacturing method of a memory provided in some embodiments of the present application;

[0064] Figure 2 is a cross-sectional view perpendicular to the substrate after forming a second composite film layer in the manufacturing method of a memory provided in some embodiments of the present application;

[0065] Figure 3 is a top view of the film layer structure after forming a second stacked structure, a third stacked structure, and a fourth stacked structure in the manufacturing method of a memory provided in some embodiments of the present application;

[0066] Figure 4 is a top view of the film layer structure after forming a third planar structure in the manufacturing method of a memory provided in some embodiments of the present application;

[0067] Figure 5 is a top view of the film layer structure after forming a support structure in the manufacturing method of a memory provided in some embodiments of the present application;

[0068] Figure 6In a manufacturing method of a memory provided by some embodiments of the present application, a top view schematic diagram of a film layer structure after forming a sixth via;

[0069] Figure 7 For Figure 6 A cross-sectional schematic diagram perpendicular to the substrate at AA in the shown film layer structure;

[0070] Figure 8 For Figure 6 A cross-sectional schematic diagram perpendicular to the substrate at BB in the shown film layer structure;

[0071] Figure 9 In a manufacturing method of a memory provided by some embodiments of the present application, a cross-sectional schematic diagram perpendicular to the substrate at AA after laterally etching a part of the sidewall of the sixth via;

[0072] Figure 10 In a manufacturing method of a memory provided by some embodiments of the present application, a cross-sectional schematic diagram perpendicular to the substrate at BB after forming a first electrode structure;

[0073] Figure 11 In a manufacturing method of a memory provided by some embodiments of the present application, a cross-sectional schematic diagram perpendicular to the substrate at BB after forming a capacitor;

[0074] Figure 12 In a manufacturing method of a memory provided by some embodiments of the present application, a top view schematic diagram of a film layer structure after forming a second trench and a third trench;

[0075] Figure 13 For Figure 12 A cross-sectional schematic diagram perpendicular to the substrate at BB in the shown film layer structure;

[0076] Figure 14 For Figure 12 A cross-sectional schematic diagram perpendicular to the substrate at CC in the shown film layer structure;

[0077] Figure 15 In a manufacturing method of a memory provided by some embodiments of the present application, a cross-sectional schematic diagram perpendicular to the substrate at BB after forming a bit line;

[0078] Figure 16 In a manufacturing method of a memory provided by some embodiments of the present application, a cross-sectional schematic diagram perpendicular to the substrate at CC after forming a bit line and a shared bit line;

[0079] Figure 17 In a manufacturing method of a memory provided by some embodiments of the present application, a top view schematic diagram of a film layer structure after forming a fourth planar structure;

[0080] Figure 18In a method for manufacturing a memory provided in some embodiments of the present application, a schematic cross-sectional view perpendicular to the substrate at BB after forming the third field-effect transistor and the word line;

[0081] Figure 19 In a method for manufacturing a memory provided in some embodiments of the present application, a schematic cross-sectional view perpendicular to the substrate at CC after forming the second field-effect transistor and the shared word line;

[0082] Figure 20 In a method for manufacturing a memory provided in some embodiments of the present application, a top view schematic of the film layer structure after forming the first stacked structure;

[0083] Figure 21 For Figure 20 A schematic cross-sectional view perpendicular to the substrate at BB in the shown film layer structure;

[0084] Figure 22 In a method for manufacturing a memory provided in some embodiments of the present application, a top view schematic of the film layer structure after forming the first electrode and the first connection electrode;

[0085] Figure 23 For Figure 22 A schematic cross-sectional view perpendicular to the substrate at BB in the shown film layer structure;

[0086] Figure 24 For Figure 22 A schematic cross-sectional view perpendicular to the substrate at CC in the shown film layer structure;

[0087] Figure 25 In a method for manufacturing a memory provided in some embodiments of the present application, a schematic cross-sectional view perpendicular to the substrate at BB after etching back the inner sidewall of the third via;

[0088] Figure 26 In a method for manufacturing a memory provided in some embodiments of the present application, a top view schematic of the film layer structure after forming the second connection electrode;

[0089] Figure 27 For Figure 26 A schematic cross-sectional view perpendicular to the substrate at BB in the shown film layer structure;

[0090] Figure 28 In a method for manufacturing a memory provided in some embodiments of the present application, a top view schematic of the film layer structure after forming the fourth via and the fifth via;

[0091] Figure 29 In a method for manufacturing a memory provided in some embodiments of the present application, a top view schematic of the film layer structure after forming the second electrode, the third connection electrode, and the fourth connection electrode;

[0092] Figure 30 For Figure 29 The cross-sectional schematic view perpendicular to the substrate at BB in the shown film layer structure.

[0093] Explanation of the reference numerals:

[0094] 100 - Substrate; 101 - First sacrificial layer; 1011 - First sacrificial structure; 102 - First semiconductor layer; 1021 - First semiconductor structure; 103 - First protective layer; 1031 - First protective structure; 104 - Second stacked structure; 105 - Third stacked structure; 1051 - Initial sub-stacked structure; 1052 - Sub-stacked structure; 106 - Fourth stacked structure; 1061 - Fourth sub-stacked structure; 107 - Third planar structure; 1071 - Sixth via; 108 - Support structure; 109 - Capacitor; 1091 - First electrode structure; 1092 - First dielectric structure; 1093 - Second electrode structure.

[0095] 110 - Second trench; 111 - Third trench; 112 - Third field-effect transistor; 1121 - Third dielectric structure; 1122 - Third gate; 113 - Second field-effect transistor; 1131 - Second dielectric structure; 1132 - Second gate; 114 - Fourth planar structure; 115 - Seventh via; 116 - Eighth via; 117 - First stacked structure; 118 - First planar structure; 119 - First electrode.

[0096] 120 - First connection electrode; 121 - First field-effect transistor; 1211 - First dielectric structure; 1212 - First gate; 1213 - Second electrode; 122 - Second connection electrode; 123 - Second planar structure; 124 - Fourth via; 125 - Fifth via; 126 - Third connection electrode; 127 - Fourth connection electrode.

[0097] 200 - Storage structure; 201 - Bit line; 202 - Shared bit line; 203 - Word line; 204 - Shared word line. Detailed implementation manners

[0098] The embodiments of the present application will be described below with reference to the accompanying drawings in the present application. It should be understood that the embodiments described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of some embodiments of the present application, and do not constitute limitations on the technical solutions of some embodiments of the present application.

[0099] Those skilled in the art can understand that, unless specifically stated, the singular forms "a", "an", "the" and "said" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present application means the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the art. The term "and / or" used herein means at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0100] To make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

[0101] The technical solutions of the present application will be described in detail below with specific embodiments. It should be noted that the following embodiments can be referred to, learned from or combined with each other. For the same terms, similar features and similar implementation steps in different embodiments, they will not be described repeatedly.

[0102] Some embodiments of the present application provide a method for manufacturing a memory. The flow schematic diagram of the manufacturing method is as Figure 1 shown, and the method includes steps S101 to S106.

[0103] S101, forming a storage structure on one side of the substrate; the storage structure includes at least one layer of a storage array, word lines and bit lines; the storage array includes at least one storage cell.

[0104] S102, forming at least one first stacked structure on the side of the storage structure away from the substrate; the first stacked structure includes at least one layer of a first sacrificial structure and at least one layer of a first semiconductor structure stacked.

[0105] S103, forming a first electrode such that the first electrode is connected to the word line and the first semiconductor structure.

[0106] S104, removing part of the first sacrificial structure such that part of the first semiconductor structure is exposed.

[0107] S105, sequentially forming a first dielectric structure and a first gate on the exposed surface of the first semiconductor structure.

[0108] S106, forming a second electrode such that the second electrode is connected to the first semiconductor structure to form a first field-effect transistor.

[0109] In the manufacturing method of the memory provided in some embodiments of the present application, after forming a storage structure on one side of a substrate, a first field-effect transistor is directly formed on the side of the storage structure away from the substrate, so that the first electrode of the first field-effect transistor is connected to the word line of the storage structure, thereby realizing the electrical connection between the first field-effect transistor and the storage structure. Compared with the manufacturing method of related three-dimensional stacked memories, by forming the storage structure and the first field-effect transistor on the same substrate, the manufacturing cost and difficulty of the memory can be reduced, which helps to improve the manufacturing efficiency and yield of the memory.

[0110] To facilitate the reader's intuitive understanding of the memory manufacturing method provided in some embodiments of the present application and the advantages of this manufacturing method, the following will be combined with Figures 2 - 30 to describe the memory manufacturing method in detail.

[0111] In practical applications, the storage structure can be a single-layer storage array or a multi-layer storage array stack.

[0112] Optionally, in some embodiments of the present application, forming at least one first stacked structure includes: forming a first flat structure covering the storage structure and at least two first stacked structures embedded in the first flat structure, and the orthographic projection of the first stacked structure on the substrate at least partially overlaps with the orthographic projection of the corresponding storage unit on the substrate.

[0113] Optionally, in some embodiments of the present application, the bit line extends along a first direction parallel to the substrate and is connected to a column of storage units arranged along the first direction in the storage array of the same layer; the word line extends along a second direction perpendicular to the substrate and is connected to a group of storage units stacked along the second direction.

[0114] Optionally, in some embodiments of the present application, the orthographic projection of each first stacked structure on the substrate at least partially overlaps with the orthographic projection range of the corresponding storage unit on the substrate.

[0115] Optionally, in some embodiments of the present application, forming a storage structure on one side of the substrate 100 in the above step S101 includes: forming a second composite film layer on one side of the substrate 100 based on an epitaxial process; the second composite film layer includes a plurality of alternately stacked first sacrificial layers 101 and first semiconductor layers 102; patterning the second composite film layer to form at least two second stacked structures, at least one third stacked structure, and at least one fourth stacked structure; both the second stacked structure and the fourth stacked structure extend along a third direction, and the third stacked structure extends along a first direction; along the third direction, a column of second stacked structures connected to the third stacked structure is disposed on both sides of the third stacked structure; along the first direction, the fourth stacked structure is connected to one end of the third stacked structure; forming at least two stacked storage units, word lines connected to the storage units, and at least two stacked and mutually insulated bit lines based on the second stacked structure and the third stacked structure.

[0116] Optionally, in some embodiments of the present application, forming a second composite film layer on one side of the substrate 100 based on an epitaxial process in the above step; the second composite film layer includes a plurality of alternately stacked first sacrificial layers 101 and first semiconductor layers 102, including: forming alternately stacked first sacrificial layers 101 and first semiconductor layers 102 on one side of the substrate 100 based on an epitaxial process.

[0117] Optionally, as Figure 2 shown, a first protective layer 103 may be deposited on the side of the topmost first sacrificial layer 101 away from the substrate 100 to protect the first sacrificial layer 101. The second composite film layer includes stacked first sacrificial layers 101, first semiconductor layers 102, and a first protective layer 103.

[0118] Optionally, as Figure 2 shown, the second composite film layer includes four first sacrificial layers 101, three first semiconductor layers 102, and one first protective layer 103.

[0119] Optionally, in some embodiments of the present application, the substrate 100 is a silicon substrate, the material of the first sacrificial layer 101 includes SiGe (germanium silicon), the material of the first semiconductor layer 101 includes Si (silicon), and the material of the first protective layer includes silicon nitride. Optionally, the material of the first semiconductor layer 101 includes single crystal silicon.

[0120] Optionally, in some embodiments of the present application, in the above step of patterning the second composite film layer to form at least two second stacked structures, at least one third stacked structure, and at least one fourth stacked structure, it includes: processing the second composite film layer based on a patterning process including exposure, development, and etching to form at least two second stacked structures 104 extending in the third direction, at least one third stacked structure 105 extending in the first direction, and at least one fourth stacked structure 106 extending in the third direction.

[0121] Optionally, as Figure 3 shown, on both sides of the third stacked structure 105, there is a column of second stacked structures 104 connected to the third stacked structure 105; the fourth stacked structure 106 is connected to one end of the third stacked structure 105 in the first direction.

[0122] Optionally, as Figure 3 shown, after patterning the second composite film layer, six second stacked structures 104 extending in the third direction, one third stacked structure 105 extending in the first direction, and one fourth stacked structure 106 extending in the third direction are formed. In the first direction, the fourth stacked structure 106 is disposed at one end of the third stacked structure 105 and is connected to the third stacked structure 105; in a plane parallel to the substrate 100, three second stacked structures 104 are connected to each of the left and right sides of the third stacked structure 105, and the three second stacked structures 104 arranged at intervals on each side form a column arranged in the first direction.

[0123] Optionally, in some embodiments of the present application, the second stacked structure 104, the third stacked structure 105, and the fourth stacked structure 106 are integrally formed structures. To facilitate an intuitive understanding of the second stacked structure 104, the third stacked structure 105, and the fourth stacked structure 106, Figure 3 the dividing lines between the structures are represented by dashed lines.

[0124] Optionally, in some embodiments of the present application, after the above step of patterning the second composite film layer to form at least two second stacked structures, at least one third stacked structure, and at least one fourth stacked structure, it further includes: based on a deposition process, filling the trenches between adjacent two second stacked structures 104 and the trenches between the second stacked structure 104 and the fourth stacked structure 106 to form a third planar structure 107.

[0125] Optionally, as Figure 4As shown, based on the deposition process, the trenches between two adjacent second stacked structures 104 and the trenches between the second stacked structure 104 and the fourth stacked structure 106 are filled with silicon oxide, and the silicon oxide is processed based on the CMP (Chemical Mechanical Polishing) process, so that the surfaces of the second stacked structure 104, the third stacked structure 105, and the fourth stacked structure 106 away from the substrate are exposed, forming a third planar structure 107.

[0126] Optionally, the surfaces of the third planar structure 107, the second stacked structure 104, the third stacked structure 105, and the fourth stacked structure 106 away from the substrate are coplanar.

[0127] Optionally, in some embodiments of the present application, after forming the third planar structure 107, it further includes: processing the third planar structure 107 based on a patterning process, so that one side of each second stacked structure 104 away from the third stacked structure 105 is exposed; based on the deposition process, a support structure 108 connected to one side of the second stacked structure 104 away from the third stacked structure 105 is formed.

[0128] Optionally, the two side surfaces of the third planar structure 107 along the third direction are etched away until one side of each second stacked structure 104 away from the third stacked structure 105 is exposed.

[0129] Optionally, as Figure 5 shown, a support structure 108 is connected to one side of each second stacked structure 104 away from the third stacked structure 105. During subsequent process steps, the support structure 108 serves to support the second stacked structure 104, thereby reducing the probability of the second stacked structure 104 breaking.

[0130] Optionally, in some embodiments of the present application, the material of the support structure 108 includes silicon nitride. Silicon nitride has relatively high strength, which helps to ensure the structural strength of the support structure 108. During subsequent process steps, it can further reduce the probability of the second stacked structure 104 breaking, thereby helping to improve the yield of the memory.

[0131] Optionally, in some embodiments of the present application, the surfaces of the support structure 108, the third planar structure 107, the second stacked structure 104, the third stacked structure 105, and the fourth stacked structure 106 away from the substrate are coplanar.

[0132] Optionally, in some embodiments of the present application, in the above steps, forming at least two stacked memory cells, a word line connected to the memory cells, and at least two stacked and mutually insulated bit lines based on the second stacked structure 104 and the third stacked structure 105 includes: forming at least two stacked capacitors based on the second stacked structure 104; forming at least two spaced sub-stacked structures based on the third stacked structure 105, the sub-stacked structure including a bit line group, the bit line group including at least two stacked and mutually insulated bit lines; forming a shared bit line group based on the fourth stacked structure 106, the shared bit line group including at least two stacked and mutually insulated shared bit lines; forming a third field effect transistor and a word line connected to the third field effect transistor based on the second stacked structure 104 formed with capacitors; along the third direction, one end of the third field effect transistor is connected to the capacitor, and the other end is connected to the bit line arranged on the same layer; forming at least two stacked second field effect transistors and a shared word line connected to the second field effect transistors based on the sub-stacked structure.

[0133] Optionally, in some embodiments of the present application, in the above steps, forming at least two stacked and mutually insulated capacitors based on the second stacked structure 104 includes: forming a photoresist structure covering the support structure 108, the third flat structure 107, the second stacked structure 104, the third stacked structure 105, and the fourth stacked structure 106; forming at least two vias in the photoresist structure, along the third direction, such that part of the third flat structure 107 on both sides of any second stacked structure 104 is exposed; using the photoresist structure as a mask to etch the exposed part of the third flat structure 107 to form at least two sixth vias 1071 penetrating the third flat structure 107, the side walls of the sixth vias 1071 including the side walls of part of the second stacked structure 104; laterally etching the part of the second stacked structure 104 exposed in the sixth vias 1071 to remove part of the first sacrificial structure 1011 of the second stacked structure 104 until any two adjacent sixth vias 1071 are connected along the first direction.

[0134] Optionally, in some embodiments of the present application, using the photoresist structure formed with vias as a mask to etch the exposed part of the third flat structure 107 to form a plurality of sixth vias 1071 penetrating the third flat structure 107, as Figure 6 and Figure 7 shown. Optionally, as Figure 6 and Figure 7 shown, along the first direction, a second stacked structure 104 is arranged between any two adjacent sixth vias 1071, so that two opposite partial side walls of the second stacked structure 104 are exposed.

[0135] Optionally, as Figure 7 shown, along the first direction, two opposite side walls in the sixth vias 1071 both include the side walls of part of the second stacked structure 104.

[0136] Optionally, in some embodiments of the present application, such as Figure 7 and Figure 8 shown, the second stacked structure 104, the third stacked structure 105, and the fourth stacked structure 106 all include alternately stacked first sacrificial structures 1011, first semiconductor structures 1021, and first protection structures 1031. Among them, the first sacrificial structure 1011 is formed by patterning the first sacrificial layer 101, the first semiconductor structure 1021 is formed by patterning the first semiconductor layer 102, and the first protection structure 1031 is formed by patterning the first protection layer 103.

[0137] Optionally, after forming the sixth via 1071, it further includes: laterally etching a part of the sidewall of the sixth via 1071. Optionally, etching exposes a part of the first sacrificial structure 1011 of a part of the second stacked structure 104 within the sixth via 1071 until any two adjacent sixth vias 1071 in the first direction are connected, such as Figure 9 shown, the outer peripheral wall of a part of the first semiconductor structure 1021 is exposed.

[0138] Optionally, such as Figure 7 and Figure 9 shown, due to the protection of the third planar structure 107, the fourth stacked structure 106 can be avoided from being etched, that is, the third planar structure 107 also plays a role in protecting the fourth stacked structure 106. Optionally, the third planar structure 107 also plays a role in protecting the third stacked structure 105.

[0139] Optionally, in the above steps of forming at least two stacked and insulated capacitors based on the second stacked structure 104, it further includes: processing a part of the exposed first semiconductor structure 1021 based on a metal silicide process, so that a part of the exposed first semiconductor structure 1021 forms a metal silicide, thereby obtaining a first electrode structure 1091, such as Figure 10 shown.

[0140] Optionally, in the above steps of forming at least two stacked capacitors 109 based on the second stacked structure 104, it further includes: sequentially forming a first dielectric structure 1092 and a second electrode structure 1093 around the exposed outer sidewall of the first electrode structure 1091 based on a deposition process, to obtain a capacitor 109 including the first electrode structure 1091, the first dielectric structure 1092, and the second electrode structure 1093.

[0141] Optionally, such as Figure 11 shown, along the second direction, a plurality of capacitors 109 are stacked on one side of the substrate 100.

[0142] Optionally, in some embodiments of the present application, the material of the second electrode structure 1093 includes polysilicon.

[0143] Optionally, in some embodiments of the present application, in the above steps, at least two spaced-apart sub-superimposed structures 1052 are formed based on the third superimposed structure 105. The sub-superimposed structure 1052 includes a bit line group, and the bit line group includes at least two superimposed and mutually insulated bit lines 201; a shared bit line group is formed based on the fourth superimposed structure 106, and the shared bit line group includes at least two superimposed and mutually insulated shared bit lines 202. Specifically, the following steps are included:

[0144] First, pattern the third superimposed structure 105 and the third planar structure 107 to respectively form a second trench 110 penetrating the third superimposed structure 105 and a third trench 111 penetrating the third planar structure. The second trench 110 extends along a first direction; the third trench 111 extends along a third direction. Along the first direction, the third trench 111 is disposed at one end of the fourth superimposed structure 106, such that the fourth superimposed structure 106 is exposed within the third trench 111, as Figure 12 、 Figure 13 and Figure 14 shown.

[0145] Then, laterally etch partial sidewalls of the second trench 110 and partial sidewalls of the third trench 111 to respectively remove partial first semiconductor structures 1021 of partial initial sub-superimposed structures 1051 and partial first semiconductor structures 1021 of the fourth superimposed structure 106.

[0146] Optionally, laterally etching partial sidewalls of the second trench 110 includes: laterally etching the first semiconductor structure 1021 of the initial sub-superimposed structure 1051 exposed within the second trench 110 until partial first semiconductor structures 1021 within the second superimposed structure 104 are exposed, such that a first lateral groove is formed between any two adjacent first sacrificial structures 1011. As Figure 13 shown, the dashed line represents the boundary line between the second superimposed structure 104 and the initial sub-superimposed structure 1051, and the dashed line does not exist in the actual product.

[0147] Optionally, laterally etching partial sidewalls of the third trench 111 includes: laterally etching the first semiconductor structure 1021 of the fourth superimposed structure 106 exposed within the third trench 111 until the first semiconductor structure 1021 is completely removed, such that a second lateral groove is formed between any two adjacent first sacrificial structures 1011.

[0148] Next, deposit a conductive material within the second trench 110 and the third trench 111 based on a deposition process, such that both the first lateral groove and the second lateral groove are filled with the conductive material, and remove the conductive material within the second trench 110 and the third trench 111 to respectively form a bit line 201 located within the first lateral groove and a shared bit line 202 located within the second lateral groove.

[0149] Optionally, as Figure 15 and Figure 16 shown, the sub-stack structure 1052 includes a plurality of stacked and mutually insulated bit lines 201 that extend in a first direction; the fourth sub-stack structure 1061 includes a plurality of stacked and mutually insulated shared bit lines 202 that extend in a third direction, and a partial first semiconductor structure 1021 is provided between the bit line 201 and the shared bit line 202 arranged in the same layer.

[0150] Optionally, in some embodiments of the present application, in the above steps, a third field effect transistor 112 and a word line 203 connected to the same group of third field effect transistors 112 are formed based on the second stack structure 104 formed with the capacitor 109; along the third direction, one end of the third field effect transistor 112 is connected to the capacitor 109, and the other end is connected to the bit line 201 arranged in the same layer; at least two stacked second field effect transistors 113 and a shared word line 204 connected to the second field effect transistor 113 are formed based on the sub-stack structure 1052, and the specific steps include the following:

[0151] First, based on a deposition process, a dielectric material is deposited in the second trench 110 and the third trench 111, and based on a CMP process, a fourth planar structure 114 coplanar with the surface of the second stack structure 104, the sub-stack structure 1052, and the fourth sub-stack structure 1061 that is away from the substrate is formed, as Figure 17 shown.

[0152] Then, a photoresist structure covering the second stack structure 104, the sub-stack structure 1052, the fourth sub-stack structure 1061, and the fourth planar structure 114 is formed. The photoresist structure includes a plurality of vias, such that one end of the sub-stack structure 1052 close to the fourth sub-stack structure 1061 is exposed, and a part of the second stack structure 104 is exposed.

[0153] Next, using the photoresist structure as a mask, the second stack structure 104 and the sub-stack structure 1052 are etched to respectively form a seventh via 115 penetrating the second stack structure 104 and an eighth via 116 penetrating the sub-stack structure 1052, as Figure 17 shown.

[0154] Then, the second stack structure 104 is laterally etched to expose a part of the first sacrificial structure 1011 in the seventh via 115 until a part of the first dielectric structure 1092 of the capacitor 109 is exposed; the sub-stack structure 1052 is laterally etched to expose a part of the first sacrificial structure 1011 in the eighth via 116.

[0155] Next, based on the deposition process, a dielectric material and a conductive material are sequentially filled in the seventh via 115 and the eighth via 116 to form a third dielectric structure 1121 and a third gate 1122 surrounding a part of the first semiconductor structure 1021 in the second stacked structure 104, and a second dielectric structure 1131 and a second gate 1132 surrounding a part of the first semiconductor structure 1021 in the sub-stacked structure 1052.

[0156] Optionally, as Figure 18 shown, along the second direction, multiple stacked third field-effect transistors 112 are the same group of third field-effect transistors 112, and each group of third field-effect transistors 112 is connected to a word line 203, and the word line 203 extends along the second direction. The third field-effect transistor 112 includes a third dielectric structure 1121, a third gate 1122, and a first semiconductor structure 1021 surrounded by the third dielectric structure 1121.

[0157] Optionally, as Figure 18 shown, along the third direction, one end of the third field-effect transistor 112 is connected to the capacitor 109, and the other end is connected to the bit line 201 arranged in the same layer, so that the first electrode structure 1091 of the capacitor 109 and a part of the bit line 201 serve as the source and drain electrodes of the third field-effect transistor 112.

[0158] Optionally, as Figure 19 shown, along the second direction, multiple stacked second field-effect transistors 113 are the same group of second field-effect transistors 113, and each group of second field-effect transistors 113 is connected to a shared word line 204, and the shared word line 204 extends along the second direction. The second field-effect transistor 113 includes a second dielectric structure 1131, a second gate 1132, and a first semiconductor structure 1021 surrounded by the second dielectric structure 1131.

[0159] Optionally, as Figure 19 shown, one end of the second field-effect transistor 113 is connected to the bit line 201, and the other end is connected to the shared bit line 202, so that a part of the bit line 201 and a part of the shared bit line 202 serve as the source and drain electrodes of the second field-effect transistor 113. That is, through the second field-effect transistor 113, the electrical connection relationship between the bit line 201 and the shared bit line 202 arranged in the same layer can be realized.

[0160] Optionally, in the embodiments of the present application, based on Figures 2 - 19The process shown obtains a storage structure 200 on one side of the substrate 100. The storage structure 200 includes at least two stacked storage arrays, at least two word lines 203, and at least two bit lines 201. The bit lines 201 extend along a first direction parallel to the substrate 100 and are connected to a column of storage cells arranged along the first direction in the storage array of the same layer. The word lines 203 extend along a second direction perpendicular to the substrate and are connected to a group of storage cells stacked along the second direction. Optionally, the storage cell includes a capacitor 109 and a third field effect transistor 112 that are electrically connected.

[0161] Optionally, in some embodiments of the present application, forming at least one first stacked structure on the side of the storage structure away from the substrate in the above step S102 includes: forming at least two first stacked structures 117 on the side of the storage structure 200 away from the substrate 100; forming a first flat structure 118 in the area of the storage structure 200 not covered by the first stacked structures 117, such that the surface of the first flat structure 118 away from the substrate is flush with the surface of the first stacked structures 117 away from the substrate.

[0162] Optionally, in some embodiments of the present application, first stacked structures 117 matching the number of word lines 203 are formed on the side of the storage structure 200 away from the substrate 100, and a first field effect transistor for site selection is formed based on the first stacked structures 117.

[0163] Optionally, in some embodiments of the present application, forming at least two first stacked structures 117 on the side of the storage structure 200 away from the substrate 100 in the above step includes: forming a first composite film layer on the side of the storage structure 200 away from the substrate 100 based on an epitaxial process; the first composite film layer includes at least two first sacrificial layers 101 and at least one first semiconductor layer 102, and the first semiconductor layer 102 is located between two adjacent first sacrificial layers 101; patterning the first composite film layer to form at least two first stacked structures 117; the first stacked structures 117 include a first sacrificial structure 1011 formed after patterning the first sacrificial layer 101 and a first semiconductor structure 1021 formed after patterning the first semiconductor layer 102.

[0164] Optionally, in some embodiments of the present application, in order to facilitate the epitaxial process, before forming the first composite film layer, it further includes: removing at least part of the first protection structure 1031 such that at least part of the first sacrificial structure 1011 at the top layer in the storage structure 200 is exposed.

[0165] Optionally, based on the epitaxial process, a first sacrificial layer 101 and a first semiconductor layer 102 are alternately formed on the side of the exposed first sacrificial structure 1011 of the storage structure 200. Optionally, in some embodiments of the present application, two first sacrificial layers 101 and one first semiconductor layer 102 are formed.

[0166] Optionally, at least two first stacked structures 117 are formed by processing the first composite film layer based on a patterning process, as Figure 20 shown. Optionally, the orthographic projection of each first stacked structure 117 on the substrate 100 at least partially overlaps with the orthographic projection range of the corresponding memory cell on the substrate 100, so as to facilitate the subsequent electrical connection between the first field-effect transistor formed based on the first stacked structure 117 and the word line 203.

[0167] Optionally, as Figure 21 shown, the first stacked structure 117 includes stacked first sacrificial structures 1011, first semiconductor structures 1021, first sacrificial structures 1011, and first protective structures 1031.

[0168] Optionally, in some embodiments of the present application, after forming the first stacked structure 117, it further includes: forming a first planar structure 118 flush with the surface of the first stacked structure 117 away from the substrate based on a deposition process and a CMP process.

[0169] Optionally, in some embodiments of the present application, forming the first electrode 119 penetrating the first stacked structure 117 in the above step S103 such that the first electrode 119 is connected to the word line 203 includes: forming a first via penetrating the first stacked structure 117 and at least one second via penetrating the first planar structure 118; the first via exposes at least a part of the surface of the word line 203 away from the substrate, and the second via exposes the surface of the shared word line 204 extending in the second direction of the memory structure 200 away from the substrate; the shared word line 204 is connected to a group of second field-effect transistors 113 stacked in the second direction, and the bit line 201 and the shared bit line 202 arranged in the same layer are electrically connected through the second field-effect transistors 113 arranged in the same layer; forming a first electrode 119 filling the first via and a first connection electrode 120 filling the second via such that the first connection electrode 120 is connected to the shared word line 204.

[0170] Optionally, in some embodiments of the present application, based on a patterning process, the first stacked structure 117 is patterned to form at least one first via penetrating the first stacked structure 117, so as to expose at least a part of the surface of the word line 203 away from the substrate.

[0171] At the same time, based on the same patterning process, the first planar structure 118 is patterned to form at least one second via penetrating the first planar structure 118, so as to expose the surface of the shared word line 204 away from the substrate.

[0172] Optionally, based on a deposition process, a conductive material is filled in the first via and the second via to form a first electrode 119 in the first via and a first connection electrode 120 in the second via, asFigure 22 as shown

[0173] Optionally, as Figure 23 shown, the first electrode 119 extends along the second direction, and one end of the first electrode 119 is connected to the word line 203, that is, the first electrode 119 is electrically connected to the word line 203.

[0174] Optionally, as Figure 24 shown, the first connection electrode 120 extends along the second direction, and one end of the first connection electrode 120 is connected to the shared word line 204, that is, the first connection electrode 120 is electrically connected to the shared word line 204.

[0175] Optionally, in some embodiments of the present application, the above step S104 removes part of the first sacrificial structure 1011 to expose part of the first semiconductor structure 1021, including: forming at least two third vias penetrating the first flat structure 118 and at least one first trench; part of the first connection electrode 120 is exposed in the first trench; etching back the inner sidewall of the third via to remove the exposed part of the first sacrificial structure 1011, so that the outer peripheral wall of part of the first semiconductor structure 1021 is exposed, and a column of third vias arranged along the first direction are all communicated with the same first trench.

[0176] Optionally, a plurality of third vias penetrating the first flat structure 118 are formed based on a patterning process. Optionally, along the first direction, one third via is formed between any two adjacent first stacked structures 117, so that part of the sidewalls of the adjacent two first stacked structures 117 are exposed in the third via.

[0177] Optionally, at the same time of forming the third via, based on the same patterning process, a first trench penetrating the first flat structure 118 is formed, so that part of the sidewall of the first connection electrode 120 is exposed in the first trench, and part of the sidewall of the first stacked structure 117 closest to the first connection electrode 120 is exposed in the first trench.

[0178] Optionally, after forming the third via and the first trench based on the same patterning process, it further includes: laterally etching part of the first sacrificial structure 1011 of the first stacked structure 117 exposed in the third via, so that the outer peripheral wall of part of the first semiconductor structure 1021 in the first stacked structure 117 is exposed, as Figure 25 shown, so that a column of third vias arranged along the first direction are all communicated with the same first trench.

[0179] Optionally, as Figure 25 shown, part of the first sacrificial structure 1011 is reserved to prevent the capacitor 109 from being exposed and prevent the device formed subsequently from being short-circuited with the capacitor 109.

[0180] Optionally, in some embodiments of the present application, forming the first dielectric structure 1211 and the first gate 1212 on the exposed surface of the first semiconductor structure 1021 in the above step S105 includes: forming the first dielectric structure 1211 surrounding the outer peripheral wall of a part of the first semiconductor structure 1021; forming the first gate 1212 and the second connection electrode 122 filling the third via and the first trench based on a deposition process, so that the first gate 1212 surrounds the outer peripheral wall of the first dielectric structure 1211; the first gates 1212 of each first field-effect transistor 121 in the same column are electrically connected to the first connection electrode 120 through the second connection electrode 122.

[0181] Optionally, based on a deposition process, form the first dielectric structure 1211 surrounding the outer peripheral wall of a part of the first semiconductor structure 1021; based on a deposition process, form the first gate 1212 surrounding the outer peripheral wall of the first dielectric structure 1211, as Figure 27 shown.

[0182] Optionally, while forming the first gate 1212, based on the same deposition process, form the second connection electrode 122 in each of the third via and the first trench, so that the third via and the first trench are filled with the second connection electrode 122, as Figure 26 shown.

[0183] Optionally, as Figure 26 shown, along the first direction, a second connection electrode 122 is provided between any two adjacent first stacked structures 117, so that the first gates 1212 arranged in a column along the first direction are connected to each other through the second connection electrode 122, and the first gates 1212 in the same column are connected to the first connection electrode through one second connection electrode 122.

[0184] Optionally, in some embodiments of the present application, forming the second electrode 1213 in the above step S106 such that the second electrode 1213 is connected to the first semiconductor structure 1021 to form the first field-effect transistor 121 includes: forming a second flat structure 123 covering the first flat structure 118 and the first stacked structure 117; forming at least two fourth vias 124 penetrating through the second flat structure 123 and at least part of the first stacked structure 117, and at least one fifth via 125 penetrating through the second flat structure 123; the fourth vias 124 expose part of the first semiconductor structure 1021, and the fifth vias 125 expose part of the first connection electrode 120; forming the second electrode 1213 located in the fourth vias 124, the third connection electrode 126 located in the fifth vias 125, and the fourth connection electrode 127 connecting the second electrodes 1213 of the same row of the first field-effect transistors 121; the third connection electrode 126 is connected to the first connection electrode 120; the fourth connection electrode 127 is disposed on a side of the second flat structure away from the substrate 100 and extends in a third direction; the third direction is parallel to the substrate 100 and intersects the first direction.

[0185] Optionally, forming the second flat structure 123 covering the first flat structure 118 and the first stacked structure 117 includes: forming the second flat structure 123 based on a deposition process and a CMP process. Optionally, the material of the second flat structure 123 includes silicon oxide.

[0186] Optionally, forming at least two fourth vias 124 penetrating through the second flat structure 123 and at least part of the first stacked structure 117, and at least one fifth via 125 penetrating through the second flat structure 123 includes: processing the second flat structure 123 based on a patterning process to form at least two fourth vias 124 and at least one fifth via 125.

[0187] Optionally, as Figure 28 shown, six fourth vias 124 and two fifth vias 125 are formed.

[0188] Optionally, as Figure 28 shown, part of the first semiconductor structure 1021 of the first stacked structure 117 is exposed to form the bottom wall of the fourth via 124. Optionally, the peripheral wall of the fourth via 124 includes part of the first sacrificial structure 1011 of the first stacked structure 117, so that the subsequently formed second electrode 1213 is insulated from the first gate 1212.

[0189] Optionally, as Figure 28 shown, part of the first connection electrode 120 is exposed to form the bottom wall of the fifth via 125.

[0190] Optionally, after forming the fourth viaduct 124 and the fifth viaduct 125, it further includes: based on a deposition process, depositing a conductive material inside the fourth viaduct 124, inside the fifth viaduct 125, and on the side of the second flat structure 123 away from the substrate 100 to form a conductive layer; processing the conductive layer based on a patterning process to form a second electrode 1213, a third connection electrode 126, and a fourth connection electrode 127, as Figure 29 and Figure 30 shown.

[0191] Optionally, as Figure 29 shown, the third connection electrode 126 is located inside the fifth viaduct 125, the third connection electrode 126 extends along the second direction, and one end of the third connection electrode 126 is connected to the first connection electrode 120.

[0192] Optionally, as Figure 29 shown, the fourth connection electrode 127 extends along the third direction.

[0193] Optionally, combining Figure 29 and Figure 30 it can be known that the second electrode 1213 is located inside the fourth viaduct 124, the second electrode 1213 extends along the second direction, one end of the second electrode 1213 is connected to the first semiconductor structure 1021, and the other end is connected to the fourth connection electrode 127. Along the third direction, the second electrodes 1213 of the first field-effect transistors 121 in the same row are connected to the same fourth connection electrode 127.

[0194] Optionally, as Figure 30 shown, the first field-effect transistor 121 includes: a first dielectric structure 1211, a part of the first semiconductor structure 1021 surrounded by the first dielectric structure 1211, a first gate 1212, a second electrode 1213, and a first electrode 119.

[0195] Based on the same inventive concept, some embodiments of the present application provide a memory, see Figure 29 and Figure 30 , the memory includes: a substrate 100, and a storage structure 200, a first field-effect transistor 121, and a second field-effect transistor 113 provided on the same substrate 100; the storage structure 200 includes at least one layer of a storage array, a word line 203, and a bit line 201; the first field-effect transistor 121 is disposed on the side of the storage structure 200 away from the substrate 100, and the second field-effect transistor 113 is used to control the gating of the bit line; the first field-effect transistor 121 is electrically connected to the word line 203 and the second field-effect transistor 113 respectively.

[0196] By disposing the storage structure 200 and the first field-effect transistor 121 on the same substrate 100, the manufacturing cost and difficulty of the three-dimensional stacked memory can be reduced, which helps to improve the manufacturing efficiency and yield of the three-dimensional stacked memory; by electrically connecting the first field-effect transistor to the word line and the second field-effect transistor, the electrical function of the first field-effect transistor can be realized, enabling the operations of the word line and the bit line to effectively cooperate, simplifying the circuit, and improving the circuit working efficiency.

[0197] The first field-effect transistor 121 includes a first gate 1212, a first electrode 119, and a second electrode 1213. The first electrode 119 of the first field-effect transistor 121 is connected to the word line 203; the second electrodes 1213 of a row of the first field-effect transistors 121 arranged along a third direction parallel to the substrate 100 are electrically connected to each other; the first gates 1212 of a column of the first field-effect transistors 121 arranged along a first direction are electrically connected to each other; both the first direction and the third direction are parallel to the substrate 100 and intersect; the electrical connection of the second electrodes 1213 of a row of the first field-effect transistors 121 to each other and the electrical connection of the first gates 1212 of a column of the first field-effect transistors 121 to each other can simplify the circuit connection relationship and save space.

[0198] Optionally, the first gate 1212 of the first field-effect transistor 121 is electrically connected to the second gate 1132 of the second field-effect transistor 113.

[0199] Optionally, in some embodiments of the present application, the bit line 201 extends along a first direction parallel to the substrate 100 and is electrically connected to the third field-effect transistors 112 of a column of storage units arranged along the first direction in the storage array of the same layer; the word line 203 extends along a second direction perpendicular to the substrate 100 and is electrically connected to the third field-effect transistors 112 of a group of storage units stacked along the second direction.

[0200] In some embodiments of the present application, the memory includes multiple layers of storage arrays stacked along a second direction perpendicular to the substrate 100. Each storage array parallel to the substrate 100 includes multiple storage units arranged in an array. Each storage unit includes a third field-effect transistor 112 and a capacitor 109 arranged horizontally. The internal structure of the third field-effect transistor 112 is horizontally arranged and includes a horizontally arranged channel region; horizontally refers to the direction parallel to the substrate 100, such as the third direction. This (vertical) stacking and (horizontal) arrangement manner of the storage units including the horizontal third field-effect transistors in the embodiments of the present application can greatly increase the unit area density of the storage units.

[0201] In some embodiments of the present application, the bit line 201 is horizontally arranged and the word line 203 is vertically arranged, which can be adapted to the stacking and arrangement manner of the above-mentioned high-density memory cells, and is beneficial to improving the density of the memory cells. Specifically, the word line 203 is electrically connected to the gate of the third field effect transistor 112 of a group of memory cells stacked along the second direction. The word line is a longitudinal connection in the memory and is used to select the row of the memory cells; the bit line 201 is electrically connected to one source / drain of the third field effect transistor 112 of a column of memory cells arranged along the first direction in the memory array of the same layer. The bit line is a horizontal connection in the memory and is used to read or write the state of the memory cells. The bit line is selected by the input address and intersects with a specific word line, and the intersection is the selected memory cell. The word line 203 extends along the second direction perpendicular to the substrate 100, occupying a smaller area of the substrate 100, and from a top view, the dimension of the word line 203 along the third direction does not exceed the dimension of the third gate 1122 of the third field effect transistor 112 along the third direction (or the two dimensions are not much different), which is beneficial to improving the density of the memory cells. Moreover, the extending direction of the bit line 201 is orthogonal to the extending direction of the word line 203, which is beneficial to reducing the signal interference between the two and is beneficial to improving the stability and reliability of the signal.

[0202] Optionally, in some embodiments of the present application, the word line 203 is electrically connected to the third gate 1122 of the third field effect transistor 112 of a group of memory cells stacked along the second direction; the second electrodes 1213 of a row of the first field effect transistors 121 arranged along the third direction parallel to the substrate 100 are electrically connected to each other through the fourth connection electrode 127. The first gates 1212 of a column of the first field effect transistors 121 arranged along the first direction are electrically connected to each other through the second connection electrode 122.

[0203] By electrically connecting the second electrodes 1213 of a row of the first field effect transistors 121 to each other and electrically connecting the first gates 1212 of a column of the first field effect transistors 121 to each other, the circuit connection relationship can be simplified and space can be saved.

[0204] Optionally, in some embodiments of the present application, the memory further includes: at least two stacked and mutually insulated shared bit lines 202, arranged on one side of the storage structure 200 along the first direction; at least two stacked second field effect transistors 113 and at least one shared word line 204 connected to the second field effect transistors 113.

[0205] Since at least one shared word line 204 is connected to at least two stacked second field effect transistors 113, the at least two stacked second field effect transistors 113 connected to the shared word line 204 can be controlled by controlling the shared word line 204.

[0206] Optionally, in some embodiments of the present application, along the first direction, both the second field-effect transistor 113 and the shared word line 204 are disposed between the shared bit line 202 and the storage structure 200.

[0207] For example, as Figure 17 and Figure 19 shown, along the first direction, the bit line 201, the second field-effect transistor 113, and the shared bit line 202 in the storage structure 200 are arranged in sequence; the bit line 201 is connected to the shared bit line 202 through the first semiconductor structure 1021 of the second field-effect transistor 113. Along the second direction, the shared word line 204 needs to be electrically connected to the second gate 1132 of the second field-effect transistor 113. Then, setting the shared word line 204 between the shared bit line 202 and the storage structure 200 is actually to set the shared word line 204 and the second gate 1132 as close as possible from a top view angle, so that the orthographic projection of the shared word line 204 on the substrate 100 and the orthographic projection of the second gate 1132 on the substrate 100 at least partially overlap, which is beneficial to reducing or eliminating the exclusive area of the shared word line 204 and is beneficial to improving the density of the storage unit.

[0208] Optionally, the orthographic projection of the shared word line 204 on the substrate 100 is all within the orthographic projection range of the second gate 1132 on the substrate 100. Optionally, the orthographic projection of the second gate 1132 on the substrate 100 is within the orthographic projection range of the shared word line 204 on the substrate 100. Optionally, the orthographic projections of the shared word line 204 and the second gate 1132 on the substrate 100 completely overlap.

[0209] Optionally, in some embodiments of the present application, the bit line 201 and the shared bit line 202 arranged in the same layer are electrically connected through the second field-effect transistor 113 arranged in the same layer. With such a setting, part of the bit line 201 and part of the shared bit line 202 serve as the source and drain electrodes of the second field-effect transistor 113, that is, the electrical connection relationship between the bit line 201 and the shared bit line 202 arranged in the same layer can be realized through the second field-effect transistor 113.

[0210] Based on the same inventive concept, some embodiments of the present application provide an electronic device, which includes: any memory provided in the above-mentioned various embodiments.

[0211] In some embodiments of the present application, since the electronic device adopts any one of the memories provided in the foregoing embodiments, the principles and technical effects are referred to the foregoing embodiments and will not be elaborated herein.

[0212] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0213] It should be noted that the electronic device is not limited to the above several types. Those skilled in the art can, according to actual application requirements, set any one of the memories provided in the above various embodiments of the present application in different devices, so as to obtain the electronic devices provided in some embodiments of the present application.

[0214] Those skilled in the art of the present technology can understand that the electronic devices provided in some embodiments of the present application can be specially designed and manufactured for the required purposes, or can also include known devices in general-purpose computers. These devices have any one of the memories provided in the above various embodiments.

[0215] Applying some embodiments of the present application can at least achieve the following beneficial effects:

[0216] In the manufacturing method of the memory provided in some embodiments of the present application, after forming a storage structure on one side of the substrate, a first field-effect transistor is directly formed on the side of the storage structure away from the substrate; compared with the manufacturing method of related three-dimensional stacked memories, by forming the storage structure and the first field-effect transistor on the same substrate, the manufacturing cost and difficulty of the memory can be reduced, which helps to improve the manufacturing efficiency and yield of the memory.

[0217] In the memory provided in some embodiments of the present application, by arranging the first field-effect transistor and the storage structure on the same substrate, the manufacturing cost and difficulty of the memory can be reduced, which helps to improve the manufacturing efficiency and yield of the memory; by electrically connecting the first field-effect transistor to the word line and the second field-effect transistor, the electrical function of the first field-effect transistor can be realized, so that the operation of the word line and the operation of the bit line can be effectively coordinated, simplifying the circuit and improving the working efficiency of the circuit.

[0218] Those skilled in the art of the present technology can understand that the steps, measures, and solutions in various operations, methods, and processes discussed in the present application can be alternated, changed, combined, or deleted. Further, the other steps, measures, and solutions in various operations, methods, and processes discussed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and solutions in the prior art that are the same as those disclosed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0219] In the description of the present application, the directions or positional relationships indicated by terms such as "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the exemplary directions or positional relationships shown in the drawings, and are for the convenience of describing or simplifying the embodiments of the present application, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present application.

[0220] The terms "first" and "second" are used only for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0221] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "mounted", "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a direct connection, or an indirect connection through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0222] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0223] The above are only some embodiments of the present application. It should be noted that for those of ordinary skill in the art, without departing from the technical concept of the present application, other similar implementation means based on the technical idea of the present application also belong to the protection scope of some embodiments of the present application.

Claims

1. A method for manufacturing a memory, characterized in that, Comprising: Forming a storage structure on one side of a substrate; the storage structure includes at least one layer of a storage array, word lines, and bit lines; The storage array includes at least one storage cell; Forming at least one first stacked structure on the side of the storage structure away from the substrate; the first stacked structure includes at least one stacked first sacrificial structure and at least one first semiconductor structure; Forming a first electrode such that the first electrode is connected to the word line and the first semiconductor structure; Removing part of the first sacrificial structure such that part of the first semiconductor structure is exposed; Sequentially forming a first dielectric structure and a first gate on the exposed surface of the first semiconductor structure; Forming a second electrode such that the second electrode is connected to the first semiconductor structure to form a first field-effect transistor.

2. The method for manufacturing a memory according to claim 1, characterized in that, Forming at least one first stacked structure includes: forming a first planar structure covering the storage structure and at least two first stacked structures embedded in the first planar structure, and the orthographic projection of the first stacked structure on the substrate at least partially overlaps with the orthographic projection of the corresponding storage cell on the substrate.

3. The method for manufacturing a memory according to claim 1, characterized in that, The bit line extends along a first direction parallel to the substrate and is connected to a column of storage cells arranged along the first direction in the storage array of the same layer; the word line extends along a second direction perpendicular to the substrate and is connected to a group of the storage cells stacked along the second direction.

4. The method for manufacturing a memory according to claim 2, characterized in that, Forming at least one first stacked structure on the side of the storage structure away from the substrate includes: Forming at least two of the first stacked structures on the side of the storage structure away from the substrate; Forming the first planar structure in the area of the storage structure not covered by the first stacked structure such that the surface of the first planar structure away from the substrate is flush with the surface of the first stacked structure away from the substrate.

5. The method for manufacturing a memory according to claim 4, characterized in that, Forming at least two of the first stacked structures on the side of the storage structure away from the substrate includes: Based on an epitaxial process, forming a first composite film layer on the side of the storage structure away from the substrate; the first composite film layer includes at least two first sacrificial layers and at least one first semiconductor layer, and the first semiconductor layer is located between two adjacent first sacrificial layers; Patterning the first composite film layer to form at least two of the first stacked structures; the first stacked structure includes the first sacrificial structure formed after patterning the first sacrificial layer and the first semiconductor structure formed after patterning the first semiconductor layer.

6. The method for manufacturing a memory according to claim 2, characterized in that, Forming a first electrode such that the first electrode is connected to the word line and the first semiconductor structure includes: Forming a first via hole penetrating the first stacked structure and at least one second via hole penetrating the first planar structure; the first via hole exposes at least part of the surface of the word line away from the substrate, and the second via hole exposes the surface of the shared word line extending along the second direction of the storage structure away from the substrate; the shared word line is connected to a group of second field-effect transistors stacked along the second direction, and the bit line and the shared bit line of the same layer are electrically connected through the second field-effect transistors of the same layer; the second direction is perpendicular to the substrate; Form the first electrode filling the first via and the first connection electrode filling the second via, such that the first connection electrode is connected to the shared word line.

7. The method for manufacturing a memory according to claim 6, characterized in that, Remove part of the first sacrificial structure, such that part of the first semiconductor structure is exposed, including: Form at least two third vias penetrating the first flat structure and at least one first trench; part of the first connection electrode is exposed in the first trench; Etch back the inner sidewalls of the third vias, removing the exposed part of the first sacrificial structure, such that the outer peripheral walls of part of the first semiconductor structure are exposed, and such that a column of the third vias arranged in a first direction are all communicated with the same first trench; the first direction is parallel to the substrate.

8. The method for manufacturing a memory according to claim 7, characterized in that, Form a first dielectric structure and a first gate electrode in sequence on the exposed surface of the first semiconductor structure, including: Form the first dielectric structure surrounding the outer peripheral walls of part of the first semiconductor structure; Based on a deposition process, form the first gate electrode and the second connection electrode filling the third vias and the first trench, such that the first gate electrode surrounds the outer peripheral wall of the first dielectric structure; the first gate electrodes of the first field effect transistors in the same column are electrically connected to each other through the second connection electrode and the first connection electrode.

9. The method for manufacturing a memory according to claim 7, characterized in that, Form a second electrode, such that the second electrode is connected to the first semiconductor structure, forming a first field effect transistor, including: Form a second flat structure covering the first flat structure and the first stacked structure; Form at least two fourth vias penetrating the second flat structure and at least part of the first stacked structure, and at least one fifth via penetrating the second flat structure; the fourth vias expose part of the first semiconductor structure, and the fifth vias expose part of the first connection electrode; Form the second electrode located in the fourth vias, the third connection electrode located in the fifth vias, and the fourth connection electrode connecting the second electrodes of the first field effect transistors in the same row; the third connection electrode is connected to the first connection electrode; the fourth connection electrode is disposed on a side of the second flat structure away from the substrate and extends in a third direction; the third direction is parallel to the substrate and intersects the first direction.

10. The method for manufacturing a memory according to claim 9, characterized in that,Form a storage structure on one side of the substrate, including: Based on an epitaxial process, form a second composite film layer on one side of the substrate; the second composite film layer includes multiple layers of the first sacrificial layer and the first semiconductor layer stacked alternately; Pattern the second composite film layer to form at least two second stacked structures, at least one third stacked structure, and at least one fourth stacked structure; both the second stacked structure and the fourth stacked structure extend in the third direction, and the third stacked structure extends in the first direction; along the third direction, a column of the second stacked structures connected to the third stacked structure are disposed on both sides of the third stacked structure; along the first direction, the fourth stacked structure is connected to one end of the third stacked structure; At least two stacked memory cells, a word line connected to the memory cells, and at least two stacked and mutually insulated bit lines are formed based on the second stacked structure and the third stacked structure.

11. The manufacturing method of the memory according to claim 10, wherein, Forming at least two stacked memory cells, a word line connected to the memory cells, and at least two stacked and mutually insulated bit lines based on the second stacked structure and the third stacked structure includes: Forming at least two stacked capacitors based on the second stacked structure; Forming at least two spaced-apart sub-stacked structures based on the third stacked structure, the sub-stacked structure including a bit line group, the bit line group including at least two stacked and mutually insulated bit lines; Forming a shared bit line group based on the fourth stacked structure, the shared bit line group including at least two stacked and mutually insulated shared bit lines; Forming a third field-effect transistor and the word line connected to the third field-effect transistor based on the second stacked structure having the capacitor formed thereon; along the third direction, one end of the third field-effect transistor is connected to the capacitor, and the other end is connected to the bit line disposed on the same layer; Forming at least two stacked second field-effect transistors and a shared word line connected to the second field-effect transistors based on the sub-stacked structure.

12. A memory, wherein, Including: A substrate, and a memory structure, a first field-effect transistor, and a second field-effect transistor disposed on the same substrate; The memory structure includes at least one layer of memory array, word lines, and bit lines; One layer of memory array includes at least one memory cell; The first field-effect transistor is disposed on a side of the memory structure away from the substrate, and the second field-effect transistor is used to control the gating of the bit line; the first field-effect transistor is electrically connected to the word line and the second field-effect transistor respectively.

13. The memory according to claim 12, wherein, The first field-effect transistor includes a first gate, a first electrode, and a second electrode, and the first electrode of the first field-effect transistor is connected to the word line.

14. The memory according to claim 13, wherein, The first gate of the first field-effect transistor is electrically connected to the second gate of the second field-effect transistor.

15. The memory according to claim 13, wherein, The bit line extends along a first direction parallel to the substrate and is connected to a third field-effect transistor of a column of the memory cells arranged along the first direction in the memory array on the same layer; The word line extends along a second direction perpendicular to the substrate and is connected to a third field-effect transistor of a group of the memory cells stacked along the second direction.

16. The memory according to claim 15, wherein, Further including: At least two stacked and mutually insulated shared bit lines, disposed on one side of the memory structure along the first direction; At least two stacked second field-effect transistors and at least one shared word line connected to the second field-effect transistors.

17. The memory according to claim 16, wherein, Along the first direction, the second field-effect transistors and the shared word line are both disposed between the shared bit lines and the memory structure.

18. The memory according to claim 16, wherein, The bit line and the shared bit line disposed on the same layer are electrically connected through the second field-effect transistor disposed on the same layer.

19. The memory according to claim 16, wherein, The word line is electrically connected to a third gate of a third field-effect transistor of a group of memory cells stacked along the second direction.

20. The memory according to claim 16, wherein, The second electrodes of a row of the first field-effect transistors arranged along the third direction are electrically connected to each other through a fourth connection electrode, and the third direction is parallel to the substrate and intersects the first direction.

21. The memory according to claim 16, wherein, The first gates of a column of first field effect transistors arranged along the first direction are electrically connected to each other through a second connection electrode.

22. The memory according to claim 21, wherein, The second connection electrode is electrically connected to the shared word line via a first connection electrode.

23. An electronic device, wherein, Comprising: The memory according to any one of claims 12 to 22.

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