Semiconductor device structure and preparation method thereof

Abstract

The invention provides a semiconductor device structure and a preparation method thereof, and belongs to the technical field of semiconductor device production. The semiconductor device structure comprises a substrate, a drift region and a plurality of protection layers which are sequentially arranged along a first direction, and scribing channels are arranged between adjacent cell regions corresponding to a semiconductor device in the protection layers. The scribing channel is provided with opposite side walls and a bottom face in the width direction, a ridge part is arranged on the bottom face in a protruding mode in the length direction, and containing structures are symmetrically arranged on the two sides of the center line, in the length direction of the scribing channel, of the ridge part. The section of the containing structure is step-shaped, and the width of the section is gradually increased in the first direction. The first direction is a direction from the back surface to the front surface of the semiconductor device. According to the semiconductor device structure, the cells can be protected through the side walls, the hot melt generated in the scribing process is contained through the containing structure, the hot melt is prevented from overflowing out of the scribing channel, pollution and damage to the cell area caused by the hot melt are further prevented, and the yield of products can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of SIC device production, and particularly to a semiconductor device structure and a preparation method thereof. Background Art

[0002] Silicon-based IGBTs (Insulated Gate Bipolar Transistors) are widely used in new energy vehicles, photovoltaic inverters and other scenarios due to their high voltage and high current characteristics. However, with the development of technology and the improvement of application requirements, the limitations of silicon-based IGBTs have become increasingly prominent. Specifically, silicon-based IGBTs cannot withstand high-frequency working conditions and have poor performance when operating in a high-frequency environment; at the same time, they have a large power consumption, which not only increases the energy consumption cost but also limits their application in fields with high energy efficiency requirements. With the rise of silicon carbide (SiC) materials, the excellent physical properties of SiC (such as high breakdown field strength, high thermal conductivity and high temperature resistance) have made SiC MOSFET devices gradually become an alternative to silicon-based IGBTs. Research shows that under the same specifications, the switching loss of SiC MOSFETs is reduced by about 66% compared with silicon-based IGBTs, significantly improving the system efficiency.

[0003] However, the manufacturing process of SiC MOSFET devices still faces technical challenges. To improve the wafer utilization rate, alignment marks (Mark) are usually placed in the dicing lane area during the manufacturing process of SiC MOSFET devices, which results in multiple layers of dielectrics (such as SiO2, Si3N4) and metal structures in the dicing lane. During the laser dicing process, the reflection of the laser by the metal layer and the thickness non-uniformity problem caused by the difference in the deposition and etching rates of the dielectric layers will lead to inconsistent laser energy distribution, and then generate high-temperature molten materials. These molten materials are easily sputtered onto the wafer pattern area during the dicing process, causing damage to the device structure and seriously reducing the yield. Although existing processes have tried to alleviate this problem by adjusting laser parameters or improving etching methods, the core contradiction of molten material splashing has not been effectively solved.

[0004] Therefore, it is urgent to improve the existing structure and preparation method of SiC MOSFET devices to overcome the defects of the prior art. Summary of the Invention

[0005] To overcome the problems existing in the related art, one of the objectives of the present invention is to provide a semiconductor device structure that can protect the cells through the sidewalls and accommodate the molten materials generated during the dicing process through an accommodating structure, preventing the molten materials from overflowing the dicing lane, and thus preventing the molten materials from contaminating and damaging the cell area, which helps to improve the product yield.

[0006] A semiconductor device structure includes a substrate, a drift region, and a plurality of protective layers sequentially arranged in a first direction. A dicing lane is provided between adjacent cell areas of the semiconductor device corresponding to the protective layers.

[0007] The scribing lane has opposite side walls and a bottom surface in the width direction, and a rib portion is protruded from the bottom surface in the length direction. The rib portion is symmetrically provided with receiving structures on both sides of the center line in the length direction of the scribing lane; the cross section of the receiving structure is stepped, and the cross-sectional width gradually increases in the first direction;

[0008] The first direction is the direction from the back surface to the front surface of the semiconductor device.

[0009] In a preferred technical solution of the present invention, the protective layer includes a first protective layer, a second protective layer, a third protective layer, and a fourth protective layer arranged in sequence along the first direction; the receiving structure is correspondingly divided into a first receiving area, a second receiving area, a third receiving area, and a fourth receiving area for the above-mentioned respective protective layers, and the widths of the respective receiving areas are d7, d8, d9, and d10;

[0010] Wherein, d8 / d7 = 1.8 - 2.2; d9 / d7 = 1.8 - 2.2; d10 / d7 = 1.8 - 2.2.

[0011] In a preferred technical solution of the present invention, the first protective layer includes a field oxide layer, and the field oxide layer includes multiple SiO2 layers arranged in sequence along the first direction;

[0012] The second protective layer includes a gate oxide layer and a polysilicon layer arranged in sequence along the first direction. The gate oxide layer grows on the top of the field oxide layer, and the polysilicon layer grows on the top of the gate oxide layer; wherein the thickness of the gate oxide layer: the thickness of the polysilicon layer = 1:6 - 1:12; the thickness of the second protective layer: the thickness of the first protective layer = 15:4 - 15:6;

[0013] The third protective layer includes an LPTEOS layer and a PETEOS layer arranged in sequence along the first direction. Wherein, the LPTEOS layer grows on the top of the polysilicon layer, and the PETEOS layer grows on the top of the LPTEOS layer;

[0014] The thickness of the LPTEOS layer: the thickness of the PETEOS layer = 1:2 - 1:5, wherein the thickness of the second protective layer: the thickness of the third protective layer = 1:1.5 - 1:3;

[0015] The fourth protective layer includes a metal MT layer; the metal MT layer includes a TI layer, a TiN layer, and an AlCu layer arranged in sequence along the first direction. Wherein the thickness of the TI layer is 500 - 2000 Å, the thickness of the TiN layer is 500 - 2000 Å, and the thickness of the AlCu layer is 2 - 6 μm; or,

[0016] The thickness of the Ti layer: the thickness of the TiN layer: the thickness of the AlCu layer = 1:0.8:20 - 1:1.2:60; the thickness of the second protective layer: the thickness of the fourth protective layer = 1:7.5 - 1:15.

[0017] In a preferred technical solution of the present invention, along the first direction, the height of the upper surface of the cell region is greater than the height of the upper surface of the rib portion.

[0018] In a preferred technical solution of the present invention, in the cell region, a passivation layer is further grown on the top of the metal MT layer. The passivation layer includes a fourth SiO2 layer and a Si3N4 layer arranged in sequence along the first direction. Among them, the fourth SiO2 layer is grown on the top of the metal MT layer, and the Si3N4 layer is grown on the top of the fourth SiO2 layer. The thickness ratio of the fourth SiO2 layer to the Si3N4 layer is 6:1 - 1:1; the thickness of the second protective layer: the thickness of the passivation layer = 3:12 - 5:12.

[0019] In a preferred technical solution of the present invention, a polyimide layer is further coated on the top of the passivation layer. The thickness d6 of the polyimide layer is 5 - 12 um, and the thickness of the second protective layer: the thickness of the polyimide layer = 4:50 - 1:30.

[0020] In a preferred technical solution of the present invention, a laser groove is provided on the upper surface of the rib portion along the center line in the length direction of the scribing lane. The depth of the laser groove extends in the thickness direction of the accommodation structure from the upper surface of the rib portion to the bottom of the scribing lane;

[0021] The width of the cross-section of the laser groove is d11, and the depth of the laser groove is d12; where d11 is 8 - 16 um and d12 is 5 - 20 um; the width of the scribing lane is d, where d11 / d = 20% - 25%.

[0022] The second object of the present invention is to provide a method for manufacturing a semiconductor device structure for manufacturing the semiconductor device structure as described above. The method includes:

[0023] Generating a plurality of protective layers in sequence on the drift region of the semiconductor device;

[0024] After each protective layer is formed, a barrier layer is provided at a preset position on the center line in the length direction of the scribing lane, and grooves are etched on both sides of the barrier layer; and along the first direction, the cross-sectional width of each groove gradually increases to form an accommodation structure with a stepped cross-section on one side; the opposite side of the accommodation structure forms the side wall of the scribing lane and is connected to the cell region;

[0025] The first direction is from the back surface to the front surface of the semiconductor device.

[0026] In a preferred technical solution of the present invention, the protective layer includes a first protective layer, a second protective layer, a third protective layer, and a fourth protective layer arranged in sequence along the first direction;

[0027] In the cell region, a passivation layer is further grown on the top of the fourth protective layer, and a polyimide layer is coated on the top of the passivation layer, so that the height of the upper surface of the cell region is greater than the height of the upper surface where the rib portion is located;

[0028] After the polyimide layer is fabricated, a laser groove is formed in the middle of the upper surface of the rib portion.

[0029] In a preferred technical solution of the present invention, the first protective layer includes a field oxide layer, the second protective layer includes a gate oxide layer and a polysilicon layer arranged in sequence along the first direction, the third protective layer includes an LPTEOS layer and a PETEOS layer, and the fourth protective layer includes a metal MT layer; wherein,

[0030] The preparation method of the field oxide layer includes: using a thermal oxidation process, introducing N2 and O2 to generate a first SiO2 layer on the drift region; using a low-pressure chemical vapor deposition process to generate a second SiO2 layer on the first SiO2 layer; using a plasma-enhanced chemical vapor deposition process to generate a second SiO2 layer on the second SiO2 layer; densifying the generated SiO2 layers at 1000°C - 1200°C;

[0031] The preparation method of the second protective layer includes: growing a gate oxide layer on the field oxide layer using a chemical vapor deposition process or an atomic layer deposition process, and growing a polysilicon layer on the gate oxide layer using a low-pressure chemical vapor deposition process;

[0032] The preparation method of the third protective layer includes: growing the LPTEOS layer on the polysilicon layer using a low-pressure chemical vapor deposition process, and growing the PETEOS layer on the LPTEOS layer using a plasma-enhanced chemical vapor deposition process;

[0033] The fabrication method of the fourth protective layer includes: sequentially growing a TI layer, a TiN layer, and an AlCu layer on the PETEOS layer;

[0034] After the fourth protective layer is fabricated, it further includes:

[0035] Growing a passivation layer on the fourth protective layer in the cell region: first growing a fourth SiO2 layer on the fourth protective layer, and then growing a Si3N4 layer on the fourth SiO2 layer;

[0036] Apply and cure polyimide on the passivation layer.

[0037] The beneficial effects of the present invention are as follows:

[0038] A semiconductor device structure provided by the present invention includes a substrate, a drift region, and a plurality of protective layers arranged in sequence along a first direction. A dicing channel is provided between adjacent cell regions corresponding to the semiconductor device in the protective layer. The dicing channel has opposite side walls and a bottom surface in the width direction, and a rib portion protrudes from the bottom surface in the length direction. The rib portion is symmetrically provided with accommodating structures on both sides of the center line of the dicing channel in the length direction of the dicing channel; the cross-section of the accommodating structure is stepped, and the cross-sectional width gradually increases along the first direction; the first direction is the direction from the back surface to the front surface of the semiconductor device. The side walls of the dicing channel of the semiconductor device structure can form a physical barrier during the dicing process, which can block the diffusion of mechanical stress, heat, and hot melt generated by dicing to adjacent cell regions, avoiding damage to the structure and electrical performance of the cell regions, thereby improving the reliability and stability of the product. During the dicing process, the generated hot melt will fall into the dicing channel due to gravity and splashing. Due to the stepped design of the accommodating structure, the hot melt will be blocked and dispersed by each step during the falling process, so as to better collect and discharge the hot melt, avoid excessive accumulation of the hot melt and overflow of the dicing channel, and further prevent the hot melt from contaminating and damaging the cell regions. This not only reduces problems such as device short circuits and leakage caused by hot melt, but also improves the yield rate of the product and reduces production costs.

[0039] This application also provides a preparation method of the above semiconductor device structure. By forming the side walls and the accommodating structure of the dicing channel in the dicing channel of the device, the side walls of the dicing channel can be used to block the splashing of hot melt, and the accommodating structure can be used to collect the hot melt, reducing the risk of hot melt contaminating the cell regions, thereby improving the yield rate of the semiconductor device. Brief Description of the Drawings

[0040] Figure 1 is a schematic diagram of the semiconductor device structure provided in the embodiment of the present invention;

[0041] Figure 2 is a flowchart of the preparation method of the semiconductor device structure provided in the embodiment of the present invention.

[0042] Reference Signs:

[0043] 1. Substrate; 2. Drift region; 3. First protective layer; 4. Second protective layer; 41. Gate oxide layer; 42. Polysilicon layer; 5. Third protective layer; 51. LPTEOS layer; 52. PETEOS layer; 6. Fourth protective layer; 61. TI layer; 62. TiN layer; 63. AlCu layer; 7. Passivation layer; 71. Fourth SiO2 layer; 72. Si3N4 layer; 8. Polyimide layer; 100. Scribing lane; 110. Ridge portion; 1101. Laser groove; 120. Sidewall; 200. Cell region. Detailed implementation manners

[0044] The preferred implementation manners of the present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred implementation manners of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation manners set forth herein. On the contrary, these implementation manners are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0045] The manufacturing process of existing SiC MOSFET devices still faces technical challenges. To improve the wafer utilization rate, alignment marks (Marks) are usually placed in the scribing lane area during the manufacturing process of SiC MOSFET devices, which results in the presence of multiple dielectric layers (such as SiO2, Si3N4) and metal structures in the scribing lane. During the laser scribing process, the reflection of the metal layer on the laser and the thickness non-uniformity problem caused by the difference in the deposition and etching rates of the dielectric layers will lead to inconsistent laser energy distribution, and then generate high-temperature molten materials. These molten materials are easily sputtered onto the wafer pattern area during the scribing process, causing damage to the device structure and seriously reducing the yield. Although the existing process attempts to alleviate this problem by adjusting the laser parameters or improving the etching method, the core contradiction of the molten material splashing has not been effectively solved.

[0046] Based on this, the present application provides a semiconductor device structure.

[0047] Embodiment 1

[0048] As Figure 1 shown, a semiconductor device structure provided in this embodiment includes a substrate 1, a drift region 2, and a plurality of protective layers arranged in sequence along a first direction. A scribing lane is provided between adjacent cell regions 200 corresponding to the semiconductor device in the protective layer;

[0049] The scribing lane has opposite sidewalls 120 and a bottom surface in the width direction, and a ridge portion 110 protrudes from the bottom surface in the length direction. Accommodating structures are symmetrically arranged on both sides of the center line of the ridge portion 110 along the length direction of the scribing lane; the cross section of the accommodating structure is stepped, and the cross-sectional width gradually increases along the first direction;

[0050] The first direction is from the back to the front of the semiconductor device.

[0051] Specifically, the substrate 1 of the present application can be an N+ SIC substrate 1 with a resistivity of 0.02 ± 20% Ω*cm. During the manufacturing process, the substrate 1 needs to be strictly cleaned. For example, the standard RCA cleaning process can be used to remove organic substances, metal impurities, and particulate contaminants on the surface to ensure the cleanliness of the substrate 1 surface.

[0052] Then, an EPI layer is grown on the substrate 1 to form the drift region 2, which bears the main breakdown layer, and its doping concentration is 1E+15 - 1E1+16 cm -3 , and the thickness is determined according to product requirements. For example, the thickness of the drift region 2 can be 5um - 11um. Specifically, CVD technology can be used to grow the EPI layer on the N+ SIC substrate 1. In a high-temperature environment, gaseous source substances containing specific elements undergo chemical reactions to deposit a semiconductor layer that matches the lattice of the substrate 1 on the surface of the substrate 1. For example, when growing a silicon carbide epitaxial layer, common gaseous source substances include silane (SiH4) and propane (C3H8), etc. At a high temperature of 1500 - 1700 °C, these gases decompose, react, and deposit on the surface of the substrate 1 to gradually form a high-quality silicon carbide epitaxial layer. When the device withstands a reverse voltage, the EPI layer can block current leakage and play an insulating and voltage-resistant effect. By precisely controlling the thickness and doping concentration of the EPI layer, key electrical performance parameters such as the breakdown voltage and on-resistance of the device can be adjusted. By precisely controlling the thickness and doping concentration of the EPI layer, key electrical performance parameters such as the breakdown voltage and on-resistance of the device can be adjusted. For example, the EPI layer thickness of 1200V MOS is 9 - 11μm, and the EPI layer thickness of 650V MOS is 5 - 7μm. Different thicknesses correspond to different voltage withstand levels to meet the requirements of different application scenarios for the voltage withstand ability of the device.

[0053] In this embodiment, after the drift region 2 is formed, multiple protective layers are sequentially deposited on the drift region 2. For example, a layer of silicon dioxide (SiO2) can be grown as a buffer layer using the thermal oxidation process, with the temperature set at 900 °C - 1100 °C, the time being 3 - 5 hours, and the thickness being approximately 50 - 100nm. This buffer layer can effectively alleviate the impact of subsequent processes on the drift region 2 and improve the stability of the device. Then, a silicon nitride (Si3N4) layer is deposited using plasma-enhanced chemical vapor deposition (PECVD) technology, with silane and ammonia (NH3) as raw materials, reacting at a relatively low temperature (300 - 400 °C), and the thickness is controlled within 200 - 300nm. The silicon nitride layer has good insulation and moisture resistance and can further protect the internal structure of the device.

[0054] After each layer of the protective layer is formed, lithography and etching processes are used to fabricate the accommodation structures for each layer in the protective layer, thereby forming an overall accommodation structure in the scribing lane. The lithography and etching processes are as follows: A photoresist is evenly coated on the surface of the protective layer, and the thickness of the photoresist is controlled to be 1 - 1.5 μm. Through a photomask, deep ultraviolet lithography technology (DUV) is used for exposure, and the exposure energy and time are precisely controlled to ensure the accuracy of the lithography pattern. After development, reactive ion etching technology is used, with chlorine and fluorine gases as the etching gases, to etch the protective layer. During the etching process, the flow rate, power, and time of the etching gas are precisely controlled to make the sidewall 120 of the scribing lane vertical and the bottom surface flat. After etching is completed, the photoresist is removed to obtain the accommodation structure of the protective layer.

[0055] In this semiconductor device structure, when the scribing tool operates within the scribing lane, the sidewall 120 can block the diffusion of mechanical stress, heat, and fine particles generated during scribing to the adjacent cell region 200. For example, during laser scribing, the laser energy causes the materials within the scribing lane to instantaneously vaporize and melt, and the generated shock waves and sputtered materials will spread in all directions. The vertical sidewall 120 can effectively block these sputtered materials from entering the cell region 200, preventing the structure and electrical properties of the cell region 200 from being damaged, thereby improving the reliability and stability of the product. Also, during the scribing process, the generated molten materials (such as molten silicon, silicon dioxide, and silicon nitride, etc.) will fall into the scribing lane due to gravity and splashing. Due to the stepped design of the accommodation structure, the molten materials will be blocked and dispersed by each step during the falling process and will not directly accumulate at the bottom, avoiding excessive accumulation of molten materials and overflowing from the scribing lane, and further preventing the molten materials from contaminating and damaging the cell region 200. This not only reduces problems such as device short - circuit and leakage caused by molten materials but also improves the yield rate of the product and reduces production costs. The accommodation structure can also play a role in discharging the molten materials more quickly.

[0056] Embodiment 2

[0057] This embodiment is an improvement based on Embodiment 1.

[0058] In this embodiment, the detailed structure of each protective layer is provided. Specifically as follows:

[0059] In this embodiment, the protective layer includes a first protective layer 3, a second protective layer 4, a third protective layer 5, and a fourth protective layer 6 arranged in sequence along the first direction; the accommodation structure is correspondingly divided into a first receiving area, a second receiving area, a third receiving area, and a fourth receiving area for the above - mentioned protective layers, and the widths of each receiving area are d7, d8, d9, and d10 respectively;

[0060] Wherein, d8 / d7 = 1.8 - 2.2; d9 / d7 = 1.8 - 2.2; d10 / d7 = 1.8 - 2.2.

[0061] In this embodiment, by strictly defining the proportional relationship of each receiving area, it can be ensured that the receiving area can accommodate more hot melt materials, form a good hot melt material collection system, and prevent the hot melt materials from damaging the cell area 200. And the accommodating structure will not affect the stability of the overall device structure.

[0062] Specifically, the first protective layer 3 includes a field oxide layer, and the field oxide layer includes multiple SiO2 layers arranged in sequence along the first direction;

[0063] The second protective layer 4 includes a gate oxide layer 41 and a polysilicon layer 42 arranged in sequence along the first direction. The gate oxide layer 41 is grown on the top of the field oxide layer, and the polysilicon layer 42 is grown on the top of the gate oxide layer 41; wherein the thickness of the gate oxide layer 41: the thickness of the polysilicon layer 42 = 1:6 - 1:12; the thickness of the second protective layer 4: the thickness of the first protective layer 3 = 15:4 - 15:6;

[0064] The gate oxide layer 41 serves as an insulating medium. The relatively thin gate oxide layer 41 can effectively reduce the distance between the gate and the channel, enhance the control ability of the gate over the carriers in the channel, and improve the switching speed of the device. The polysilicon layer 42 serves as the gate electrode, and its appropriate thickness can ensure good conductivity, ensure the uniform distribution and rapid transmission of charges on the gate. When the gate oxide layer 41 and the polysilicon layer 42 are set in a suitable proportion, the key electrical parameters such as the threshold voltage and transconductance of the device can be optimized, enabling the device to operate efficiently under low power consumption. The design of the thickness ratio of the second protective layer 4 to the first protective layer 3 helps to stabilize the electric field distribution inside the device. Different thicknesses of the protective layer will affect the penetration and distribution of the electric field among the layers of the device. A reasonable thickness ratio can avoid the concentration of the electric field in certain areas, prevent breakdown phenomena caused by too strong an electric field, improve the breakdown voltage ability of the device, and ensure the stable operation of the device in a high-voltage environment.

[0065] The third protective layer 5 includes an LPTEOS layer 51 and a PETEOS layer 52 arranged in sequence along the first direction. Among them, the LPTEOS layer 51 is grown on the top of the polysilicon layer 42, and the PETEOS layer 52 is grown on the top of the LPTEOS layer 51;

[0066] The thickness of the LPTEOS layer 51: the thickness of the PETEOS layer 52 = 1:2 - 1:5, wherein the thickness of the second protective layer 4: the thickness of the third protective layer 5 = 1:1.5 - 1:3;

[0067] Both the LPTEOS layer and the PETEOS layer 52 are insulating materials. A suitable thickness combination can effectively block current leakage and improve the breakdown voltage level of the device. A thicker PETEOS layer 52 can provide stronger insulation protection. When the LPTEOS layer 51 and the PETEOS layer 52 are combined in a suitable ratio, it can reduce the increase in parasitic capacitance caused by an overly thick insulating layer while ensuring the insulation effect, and maintain good electrical performance.

[0068] The thickness ratio (1:1.5 - 1:3) of the second protective layer 4 to the third protective layer 5 ensures the electrical performance matching between the two layers, further optimizing the electric field distribution and charge transport characteristics inside the device. For example, a suitable thickness ratio can reduce the charge accumulation at the layer interface, lower the leakage risk, and improve the overall electrical performance of the device.

[0069] During the deposition process of the LPTEOS layer 51 and the PETEOS layer 52, controlling the thickness according to a specific ratio can make the process more stable and repeatable. For example, in the chemical vapor deposition (CVD) process, by precisely controlling parameters such as the flow rate of reaction gases and deposition time, two layers of materials with the desired thickness ratio can be accurately obtained, improving the precision and consistency of the manufacturing process. In addition, a reasonable thickness ratio helps to reduce the cost of the manufacturing process.

[0070] The fourth protective layer 6 includes a metal MT layer; the metal MT layer includes a TI layer 61, a TiN layer 62, and an AlCu layer 63 arranged in sequence along the first direction, where the thickness of the TI layer 61 is 500 - 2000 Å, the thickness of the TiN layer 62 is 500 - 2000 Å, and the thickness of the AlCu layer 63 is 2 - 6 μm; or,

[0071] The thickness of the Ti layer : the thickness of the TiN layer 62 : the thickness of the AlCu layer 63 = 1:0.8:20 - 1:1.2:60; the thickness of the second protective layer 4 : the thickness of the fourth protective layer 6 = 1:7.5 - 1:15.

[0072] The thickness settings of the TI layer 61, the TiN layer 62, and the AlCu layer 63 ensure that the overall metal MT layer has good electrical conductivity. The TI layer 61 has certain electrical conductivity and good adhesion. A thickness of 500 - 2000 Å can not only ensure tight bonding with the underlying material but also provide a path for current conduction. The TiN layer 62 not only has good electrical conductivity but also has corrosion resistance and electromigration resistance. Its thickness of 500 - 2000 Å, while ensuring its own functions, cooperates with the TI layer 61 and the AlCu layer 63 to optimize the overall electrical conductivity. The AlCu layer 63 is the main conductive layer, and a thickness of 2 - 6 μm provides a low - resistance path for large - current transmission, ensuring that the device can stably transmit current during operation.

[0073] The reasonable setting of the thickness ratios of each layer (the thickness of the Ti layer: the thickness of the TiN layer 62: the thickness of the AlCu layer 63 = 1:0.8:20 - 1:1.2:60) ensures the conductivity matching between layers, reduces the contact resistance, and maintains a stable electrical connection. The thickness ratio between the second protective layer 4 and the fourth protective layer 6 ensures the compatibility between the two layers. The thickness setting of the metal MT layer needs to be adapted to the structure of the entire semiconductor device. A reasonable thickness can not only meet its own functional requirements but also have no negative impact on the performance of other layers, ensuring the stability and reliability of the entire device structure.

[0074] In this embodiment, more specifically, d7 is 2 - 5 μm, the width of the dicing lane is d, and d7 / d = 5% - 8%. d8 / d7 = 0.8 - 1.2. If d8 is too small, the boundary between the second protective layer 4 and the first protective layer 3 is close, reducing the deposition channel of the laser dicing melt. In addition, the sputtered material impacts the boundary, resulting in large stress, so that the second protective layer 4 is easily damaged, affecting the overall effect. If d8 is too large, the size of the alignment Mark area of the dicing lane is sacrificed. And d9 / d7 = 0.8 - 1.2. If d9 is too small, it is close to the second protective layer 4, reducing the deposition channel of the laser dicing melt. In addition, the sputtered material impacts the boundary, resulting in large stress, so that the third protective layer 5 is easily damaged, affecting the overall effect. If d9 is too large, the size of the alignment Mark area of the dicing lane is sacrificed. d10 / d7 = 0.8 - 1.2. Similarly, if d10 is too small, it is close to the boundary of the third protective layer 5, reducing the deposition channel of the laser dicing melt. In addition, the sputtered material impacts the boundary, resulting in large stress, so that the metal MT layer is easily damaged, affecting the overall effect. If d10 is too large, the size of the alignment Mark area of the dicing lane is sacrificed.

[0075] Embodiment 3

[0076] This embodiment is an improvement based on Embodiment 2.

[0077] In this embodiment, along the first direction, the height of the upper surface of the cell region 200 is greater than the height of the upper surface of the rib portion 110. A height difference is formed between the upper surface of the cell region 200 and the upper surface of the rib portion 110. This setting reduces the influence of the melt on the wafer of the cell region 200 during dicing and subsequent laser grooving 1101, which helps to improve the yield of the product.

[0078] More specifically, the design that the height of the upper surface of the cell region 200 is greater than the height of the upper surface of the rib portion 110 is because in the cell region 200, a passivation layer 7 is further grown on the top of the metal MT layer. The passivation layer 7 includes a fourth SiO2 layer 71 and a Si3N4 layer 72 arranged in sequence along a first direction. Among them, the fourth SiO2 layer 71 is grown on the top of the metal MT layer, the Si3N4 layer 72 is grown on the top of the fourth SiO2 layer 71, and the thickness ratio of the fourth SiO2 layer 71 to the Si3N4 layer 72 is 6:1 - 1:1; the thickness of the second protective layer 4: the thickness of the passivation layer 7 = 3:12 - 5:12.

[0079] In this embodiment, the passivation layer 7 is composed of a fourth SiO2 layer and a Si3N4 layer, and the thickness ratio is 6:1 - 1:1. This structure can effectively protect the underlying metal MT layer and other internal structures. The fourth SiO2 layer can block the intrusion of external substances such as water vapor and impurity ions, prevent the metal MT layer from being corroded, and avoid problems such as performance degradation and short - circuit of the metal layer caused by corrosion. The Si3N4 layer has good chemical stability and mechanical strength, which can enhance the overall protection ability of the passivation layer 7, and further improve the stability and service life of the device. The existence of the passivation layer 7 can improve the electrical performance of the device. The fourth SiO2 layer and the Si3N4 layer can reduce the charge exchange between the metal MT layer and the external environment, reduce the surface state density, and inhibit the surface leakage phenomenon, thereby improving the insulation performance and reliability of the device.

[0080] Furthermore, a polyimide layer 8 is coated on the top of the passivation layer 7. The thickness d6 of the polyimide layer 8 is 5 - 12 um, and the thickness of the second protective layer 4: the thickness of the polyimide layer 8 = 4:50 - 1:30.

[0081] The polyimide layer 8 is coated on the top of the passivation layer 7 with a thickness d6 of 5 - 12 um, which can further improve the protection performance of the device. The polyimide material has excellent insulation, chemical corrosion resistance and high temperature resistance, can effectively resist the erosion of the harsh environment on the device, reduce the influence of external factors on the internal structure, and ensure the stable operation of the device in various complex environments.

[0082] Further, a laser groove 1101 is provided along the center line in the length direction of the dicing channel on the upper surface of the rib portion 110. The depth of the laser groove 1101 extends in the thickness direction of the accommodation structure from the upper surface of the rib portion 110 to the bottom of the dicing channel;

[0083] The width of the cross-section of the laser groove 1101 is d11, and the depth of the laser groove 1101 is d12; where d11 is 8 - 16 um and d12 is 5 - 20 um; the width of the scribing lane is d, where d11 / d = 20% - 25%.

[0084] Example 4

[0085] As Figure 1 - Figure 2 shown, this embodiment provides a method for manufacturing a semiconductor device structure for manufacturing the semiconductor device structure as described in the claims. The method includes:

[0086] S100. Sequentially form a plurality of layers of protective layers on the drift region 2 of the semiconductor device;

[0087] S200. After each protective layer is formed, set a barrier layer at a preset position on the center line along the length direction of the scribing lane, and etch to form grooves on both sides of the barrier layer; and along the first direction, the cross-sectional width of each groove gradually increases, constituting a receiving structure with a stepped cross-section on one side; the opposite side of the receiving structure constitutes the side wall 120 of the scribing lane and is connected to the cell region 200;

[0088] The first direction is the direction from the back surface to the front surface of the semiconductor device.

[0089] Specifically, the protective layers include a first protective layer 3, a second protective layer 4, a third protective layer 5, and a fourth protective layer 6 sequentially arranged along the first direction;

[0090] In the cell region 200, a passivation layer 7 also grows on the top of the fourth protective layer 6, and a polyimide layer 8 is coated on the top of the passivation layer 7, so that the height of the upper surface of the cell region 200 is greater than the height of the upper surface where the ridge portion 110 is located;

[0091] After the polyimide layer 8 is manufactured, a laser groove 1101 is opened in the middle of the upper surface of the ridge portion 110.

[0092] Furthermore, the first protective layer 3 includes a field oxide layer, the second protective layer 4 includes a gate oxide layer 41 and a polysilicon layer 42 sequentially arranged along the first direction, the third protective layer 5 includes an LPTEOS layer 51 and a PETEOS layer 52, and the fourth protective layer 6 includes a metal MT layer; where

[0093] The preparation method of the field oxide layer includes: using a thermal oxidation process, introducing N2 and O2 to form a first SiO2 layer on the drift region 2; using a low-pressure chemical vapor deposition process to form a second SiO2 layer on the first SiO2 layer; using a plasma-enhanced chemical vapor deposition process to form a second SiO2 layer on the second SiO2 layer; densifying the formed SiO2 layers at 1000°C - 1200°C;

[0094] The preparation method of the second protective layer 4 includes: growing a gate oxide layer 41 on the field oxide layer using a chemical vapor deposition process or an atomic layer deposition process, and growing a polysilicon layer 42 on the gate oxide layer 41 using a low-pressure chemical vapor deposition process;

[0095] The preparation method of the third protective layer 5 includes: growing the LPTEOS layer 51 on the polysilicon layer 42 using a low-pressure chemical vapor deposition process, and growing the PETEOS layer 52 on the LPTEOS layer 51 using a plasma-enhanced chemical vapor deposition process;

[0096] The manufacturing method of the fourth protective layer 6 includes: sequentially growing a TI layer 61, a TiN layer 62, and an AlCu layer 63 on the PETEOS layer 52;

[0097] After the manufacturing of the fourth protective layer 6 is completed, it further includes:

[0098] Growing a passivation layer 7 on the fourth protective layer 6 in the cell region 200: first growing a fourth SiO2 layer 71 on the fourth protective layer 6, and then growing a Si3N4 layer 72 on the fourth SiO2 layer 71;

[0099] Coating and curing polyimide on the passivation layer 7.

[0100] The preparation method of this semiconductor device structure is as follows:

[0101] Growing multiple protective layers sequentially on the drift region 2 of the semiconductor device. The drift region 2 is formed by growing an EPI layer based on an N+ SIC substrate 1 and serves as the main breakdown layer, with a doping concentration of 1E+15 - 1E+16 cm -3 , and the thickness depends on product requirements. For example, the thickness of the 1200V MOS EPI layer is 9 - 11 um, and the thickness of the 650V MOS EPI layer is 5 - 7 um.

[0102] The first protective layer 3 (field oxide layer, i.e., FOX layer): First, perform RCA cleaning on the drift region 2, then use the thermal oxidation process, introduce N2 and O2, and grow a first SiO2 layer with a thickness of 100 - 500 Å on the drift region 2 SIC at 1000 - 1200 °C; then after taking it out of the furnace and cleaning, adopt the low-pressure chemical vapor deposition process, use tetraethyl orthosilicate (TEOS) and O2 as raw materials, and grow a second SiO2 layer with a thickness of 1000 - 5000 Å at 600 - 900 °C; then use the plasma-enhanced chemical vapor deposition process, use TEOS and O2 as raw materials, and grow a third SiO2 layer with a thickness of 10000 - 20000 Å at 600 - 900 °C; finally, densify the generated SiO2 layers at 1000 - 1200 °C.

[0103] Apply PR glue on the surface of the first protective layer 3 with a glue thickness of 1 - 1.5 μm, expose and develop it with an i-line lithography machine. The width d7 after development is 2 - 5 μm, and the width of the scribe lane 100 is d, where d7 / d = 5% - 8%. Then adopt the wet process, use BOE chemical solution to etch away the pattern in the opening area, and form a first receiving area in the first protective layer 3. Specifically, the BOE chemical solution in this application is composed of hydrofluoric acid and ammonium fluoride mixed in a certain proportion, and the ratio of hydrofluoric acid to ammonium fluoride is 1:6 - 1:10. During the etching process, the temperature of the BOE solution in the etching tank is 20 - 30 °C. The temperature of the BOE solution in the etching tank is controlled by a temperature control device during the etching process to control the etching rate. During the etching process, use a magnetic stirrer to stir the BOE solution, and the stirring speed is controlled between 100 - 300 rpm, which can be appropriately adjusted according to the size of the etching tank and the volume of the solution. The etching duration is about 5 - 10 minutes.

[0104] On the first protective layer 3 (field oxide layer), grow a gate oxide layer 41 with a thickness of 200 Å - 1000 Å using the chemical vapor deposition process or atomic layer deposition process. Subsequently, grow a polysilicon layer 42 with a thickness of 2000 Å - 6000 Å on the gate oxide layer 41 using the low-pressure chemical vapor deposition process, and then etch away the excess gate oxide and polysilicon.

[0105] On the second protective layer 4 (polysilicon layer 42), first grow a LPTEOS layer 51 with a thickness of 1000 Å - 4000 Å using the low-pressure chemical vapor deposition process, and then grow a PETEOS layer 52 with a thickness of 5000 Å - 8000 Å on the LPTEOS layer 51 using the plasma-enhanced chemical vapor deposition process. Finally, the thickness of the SiO2 deposited by the two processes is 6000 - 12000 Å, and finally etch away the excess third protective layer 5.

[0106] On the third protective layer 5 (PETEOS layer 52), a TI layer 61 (with a thickness of 500 - 2000 Å), a TiN layer 62 (with a thickness of 500 Å - 2000 Å), and an AlCu layer 63 (with a thickness of 2 - 6 μm) are sequentially grown, where Ti:TiN:AlCu = 1:0.8:20 - 1:1.2:60. Finally, the excess metal MT layer is etched away.

[0107] After each protective layer is formed, a barrier layer is set at a preset position on the center line along the length direction of the scribing lane, and grooves are etched on both sides of the barrier layer. Along the first direction from the back surface to the front surface of the semiconductor device, the cross-sectional width of each groove gradually increases, forming a receiving structure with a stepped cross-section on one side. The other side opposite to the receiving structure forms the side wall 120 of the scribing lane, which is connected to the cell region 200. During the etching process, relevant dimensional ratios need to be strictly controlled. For example, after applying PR glue (with a glue thickness of 1 - 1.5 μm), exposing and developing with an i-line lithography machine, the developed width d7 is 2 - 5 μm, and the ratio of d7 to the scribing lane width d, d7 / d = 5% - 8%.

[0108] A passivation layer 7 is grown on the fourth protective layer 6 in the cell region 200. First, a fourth SiO2 layer with a thickness of 4000 - 10000 Å is grown on the fourth protective layer 6, and then a Si3N4 layer with a thickness of 4000 - 10000 Å is grown on the fourth SiO2 layer. Polyimide is coated and cured on the passivation layer 7 so that the height of the upper surface of the cell region 200 is greater than the height of the upper surface of the ridge portion 110 of the receiving structure. The finally cured thickness d6 of the polyimide is 5 - 12 μm.

[0109] After the polyimide layer 8 is fabricated, a laser groove 1101 is opened in the middle of the upper surface of the ridge portion 110 of the slide lane 100. The grooving width d11 of the laser groove 1101 is 8 - 16 μm, d12 / d = 20% - 25%, and the grooving depth d12 is 5 - 20 μm. If d11 is too small, it will affect the subsequent stealth dicing effect; if it is too large, too much molten material will be generated, increasing the risk of the molten material splashing onto the wafer pattern area. Similar problems of affecting the stealth dicing effect and increasing the risk of molten material splashing will also occur if d12 is too small or too large.

[0110] Unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for the sake of convenience in description, the dimensions of the various parts shown in the drawings are not drawn in actual proportional relationships. Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be regarded as part of the authorization specification. In all the examples shown and discussed here, any specific value should be construed as merely exemplary, rather than as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings. In the description of the present application, it should be understood that the orientation terms such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal", and "top, bottom", etc. generally indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Without contrary description, these orientation terms do not indicate and imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and thus should not be construed as limiting the scope of protection of the present application; the orientation terms "inside, outside" refer to the inside and outside relative to the contour of each component itself.

[0111] For the sake of convenience in description, spatial relative terms such as "above", "over", "on the upper surface", "upper", etc. may be used here to describe the spatial positional relationship of one device or feature to other devices or features as shown in the drawings. It should be understood that the spatial relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the drawings of the device. For example, if the device in the drawing is inverted, the device described as "above" or "over" other devices or structures will then be positioned "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both the orientations of "above" and "below". The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and corresponding interpretations should be made for the spatial relative descriptions used here.

[0112] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Without additional statements, the above terms have no special meanings. Therefore, it should not be construed as a limitation on the protection scope of this application. The above description is only the preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor device structure, comprising a substrate, a drift region and a plurality of protective layers arranged in sequence along a first direction, wherein a scribe line is provided between adjacent cell regions corresponding to the semiconductor device in the protective layer; characterized in that: The scribe line has opposite side walls and a bottom surface along the width direction, and an edge portion is protruding from the bottom surface along the length direction, and the edge portion is symmetrically provided with a receiving structure on both sides of the center line along the length direction of the scribe line; the cross section of the receiving structure is step-shaped, and the width of the cross section gradually increases along the first direction; The first direction is a direction from the back side to the front side of the semiconductor device.

2. The semiconductor device structure according to claim 1, characterized in that: The protective layer comprises a first protective layer, a second protective layer, a third protective layer and a fourth protective layer arranged in sequence along the first direction; the containing structure is divided into a first receiving area, a second receiving area, a third receiving area and a fourth receiving area corresponding to the above protective layers, and the widths of the receiving areas are d7, d8, d9 and d10 respectively; Among them, d8 / d7=1.8-2.2; d9 / d7=1.8-2.2; d10 / d7=1.8-2.

2.

3. The semiconductor device structure according to claim 2, characterized in that: The first protection layer includes a field oxide layer, and the field oxide layer includes a plurality of SiO2 layers sequentially arranged along a first direction; The second protective layer comprises a gate oxide layer and a polysilicon layer arranged in sequence along a first direction, the gate oxide layer is grown on top of the field oxide layer, and the polysilicon layer is grown on top of the gate oxide layer; wherein the thickness of the gate oxide layer: the thickness of the polysilicon layer = 1:6-1:12; the thickness of the second protective layer: the thickness of the first protective layer = 15:4-15:6; The third protective layer comprises an LPTEOS layer and a PETEOS layer sequentially arranged along the first direction, wherein the LPTEOS layer is grown on top of the polysilicon layer, and the PETEOS layer is grown on top of the LPTEOS layer; The thickness of the LPTEOS layer: the thickness of the PETEOS layer = 1:2-1:5, wherein the thickness of the second protective layer: the thickness of the third protective layer = 1:1.5-1:3; The fourth protective layer includes a metal MT layer; the metal MT layer includes a TI layer, a TiN layer and an AlCu layer sequentially arranged along the first direction, wherein the thickness of the TI layer is 500-2000A, the thickness of the TiN layer is 500-2000A, and the thickness of the AlCu layer is 2-6um; or, The thickness of the Ti layer: the thickness of the TiN layer: the thickness of the AlCu layer = 1:0.8:20-1:1.2:60; the thickness of the second protective layer: the thickness of the fourth protective layer = 1:7.5-1:

15.

4. The semiconductor device structure according to any one of claims 1 to 3, characterized in that: Along the first direction, the height of the upper surface of the cell region is greater than the height of the upper surface of the edge portion.

5. The semiconductor device structure according to claim 3, characterized in that: In the cell region, a passivation layer is also grown on the top of the metal MT layer, and the passivation layer includes a fourth SiO2 layer and a Si3N4 layer arranged in sequence along the first direction, wherein the fourth SiO2 layer is grown on the top of the metal MT layer, and the Si3N4 layer is grown on the top of the fourth SiO2 layer, and the ratio of the thickness of the fourth SiO2 layer to the Si3N4 layer is 6:1-1:1; the thickness of the second protective layer: the thickness of the passivation layer = 3:12-5:

12.

6. The semiconductor device structure according to claim 5, characterized in that: The top of the passivation layer is also coated with a polyimide layer, the thickness d6 of the polyimide layer is 5-12 um, and the thickness of the second protective layer: the thickness of the polyimide layer = 4:50-1:

30.

7. The semiconductor device structure according to any one of claims 1 to 3, characterized in that: A laser groove is provided on the upper surface of the edge portion and along the center line of the length direction of the scribing road, and the depth of the laser groove extends from the upper surface of the edge portion to the bottom of the scribing road in the thickness direction of the containing structure; The width of the cross section of the laser groove is d11, and the depth of the laser groove is d12; wherein d11 is 8-16um, and d12 is 5-20um; the width of the scribe line is d, wherein d11 / d=20%-25%.

8. A method for preparing a semiconductor device structure, used for preparing the semiconductor device structure as claimed in any one of claims 1 to 7, characterized in that: The method comprises: sequentially generating a plurality of protective layers on the drift region of the semiconductor device; After each protective layer is formed, a barrier layer is arranged at a preset position on the center line along the length direction of the scribe line, and grooves are etched on both sides of the barrier layer; and along the first direction, the cross-sectional width of each groove gradually increases to form a containment structure with a step-shaped cross-section on one side; the other side of the containment structure forms the side wall of the scribe line and is connected to the cell area; The first direction is a direction from the back side to the front side of the semiconductor device.

9. The method for preparing a semiconductor device structure according to claim 8, characterized in that: The protective layer comprises a first protective layer, a second protective layer, a third protective layer and a fourth protective layer arranged in sequence along a first direction; In the cell region, a passivation layer is further grown on the top of the fourth protective layer, and a polyimide layer is coated on the top of the passivation layer, so that the height of the upper surface of the cell region is greater than the height of the upper surface of the edge portion; After the polyimide layer is manufactured, a laser groove is opened in the middle of the upper surface of the edge portion.

10. The method for preparing a semiconductor device structure according to claim 9, characterized in that: The first protection layer includes a field oxide layer, the second protection layer includes a gate oxide layer and a polysilicon layer arranged in sequence along a first direction, the third protection layer includes an LPTEOS layer and a PETEOS layer, and the fourth protection layer includes a metal MT layer; wherein, The method for preparing the field oxide layer comprises: using a thermal oxidation process, introducing N2 and O2, to form a first SiO2 layer on the drift region; using a low-pressure chemical vapor deposition process, to form a second SiO2 layer on the first SiO2 layer; using a plasma enhanced chemical vapor deposition process, to form a second SiO2 layer on the second SiO2 layer; and densifying the generated SiO2 layers at 1000° C.-1200° C.; The preparation method of the second protective layer comprises: growing a gate oxide layer on the field oxide layer by using a chemical vapor deposition process or an atomic layer deposition process, and growing a polysilicon layer on the gate oxide layer by using a low pressure chemical vapor deposition process; The preparation method of the third protective layer comprises: growing the LPTEOS layer on the polysilicon layer using a low pressure chemical vapor deposition process, and growing the PETEOS layer on the LPTEOS layer using a plasma enhanced chemical vapor deposition process; The method for manufacturing the fourth protective layer comprises: sequentially growing a TI layer, a TiN layer and an Al Cu layer on the PETEOS layer; After the fourth protective layer is manufactured, the method further comprises: Growing a passivation layer on the fourth protective layer in the cell region: firstly growing a fourth SiO2 layer on the fourth protective layer, and then growing a Si3N4 layer on the fourth SiO2 layer; Polyimide is coated on the passivation layer and cured.

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